	ident     'TASKING CHC C compiler v99.9r9 Build 210.1.1'
	; TASKING CHC C compiler v99.9r9 Build 210.1.1
	; Options: -o Output\ChcOutputs\NB3000_CHC_Graphics.src --dep-file=Output\ChcOutputs\NB3000_CHC_Graphics.d --make-target=Output\ChcOutputs\NB3000_CHC_Graphics.src -f Output\ChcOutputs\NB3000_CHC_Graphics.src.opt -D__ALTIUM_BUILD_MAJOR__=10 -D__ALTIUM_BUILD_MINOR__=0 -D__SWPLATFORM__ -IOutput\ChcOutputs\..\framecfg -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\platform\fpga\processors\c3000\include -D__UNIFIED_HANDLES__=1 -D__POSIX_DEVIO__ -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\services\posix\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\system\ifconfig\include -D__FRAMEWORK__ -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\system\sysutils\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\platform\fpga\drivers\terminal\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\platform\fpga\drivers\vga_ili9320\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\platform\fpga\peripherals\terminal\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\platform\fpga\peripherals\vga32_ili9320\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\services\platform\graphics\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\services\platform\interrupts\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\services\platform\timing\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\services\posix\devio\include -IC:\Users\Public\Documents\Altium\AD\Library\Software Platform\services\posix\devio\serial\include --qualifier-file=Output\ChcOutputs\..\NB3000_CHC_Graphics.qua -IP:\Hardware\Elektronik-Module_und_Bausätze\Altium Nanoboard 3000\NB3000_CHC_Graphics\Embedded --iso=99 --only-rtl-qualified --integer-enumeration --align-composites=n --core-compatibility=c3000 --endianness=big --target-device=chc_default_device --resource-definition=Output\ChcOutputs\..\default_resources.prd -O2 --tradeoff=0 --lsl-include-directory=Output\ChcOutputs\.. --lsl-include-directory=C:\PROGRAM FILES\ALTIUM\AD\System\Tasking\c3000\include.lsl --lsl-file=NB3000_CHC_Graphics_mem.lsl
	; Module start
	endianness	big
    function	MULADD18_v2, local
	port    	"in0":in:in:9, "in1":in:in:10, "in2":in:in:10, :retval:out:18
	setuptime  	62
	area       	11
	operation	muladd
    endfunc		; MULADD18_v2
    function	ALU32_v3, local
	port    	"in0":in:in:32, "in1":in:in:19, :retval:out:32, :oper:in:1
	setuptime  	38
	area       	10
	operation	add, sub
    endfunc		; ALU32_v3
    function	ltui, local
	port    	:in:in:16, "in1":in:in:16:generic, :retval:out:1
	setuptime  	27
	area       	9
	operation	ltu
    endfunc		; ltui
    function	vst_me_16, local
	port    	:in:in:16, :address:in:32, :start:in:1, :done:out:1
	port    	:clock:global_in:1, :reset:global_in:1
	cycles     	-1
	operation	vst
	component	__me_0, __me, import
	mau		16
    endfunc		; vst_me_16
    function	__me, import
	port    	"EN":start:in:1, "DONE":done:out:1, :clock:global_in:1, :reset:global_in:1
	port    	"DOUT":retval:out:32, "DIN":in:in:32, "WE":we:in:1, "ADR":address:in:30
	port    	"SEL":byte_select:in:4
	cycles     	-1
	operation	ld, st, ld2, st2
	cc		wishbone
	is_memory
	mau		8
	used_maus	0
	total_maus	-1
	space		1
    endfunc		; __me
    function	ALU32_v2, local
	port    	"in0":in:in:16, "in1":in:in:16, :retval:out:16, :oper:in:1
	setuptime  	38
	area       	10
	operation	add, sub
    endfunc		; ALU32_v2
    function	CMPU16, local
	port    	"in0":in:in:16, "in1":in:in:16, :retval:out:1, "retval1":retval:out:1
	setuptime  	30
	area       	10
	operation	equ, ltu
    endfunc		; CMPU16
    function	mux_v3, local
	port    	:retval:out:16, :in:in:16, "sel0":sel:in:1, "in1":in:in:16
	operation	mux
    endfunc		; mux_v3
    function	CMP16_v2, local
	port    	"in0":in:in:16, "in1":in:in:16, "retval1":retval:out:1
	setuptime  	30
	area       	10
	operation	lt
    endfunc		; CMP16_v2
    function	ALU16, local
	port    	"in0":in:in:16, "in1":in:in:16, :retval:out:16, :oper:in:1
	setuptime  	31
	area       	10
	operation	add, sub
    endfunc		; ALU16
    function	CMP32_v3, local
	port    	"in0":in:in:16, "in1":in:in:17, :retval:out:1, "retval1":retval:out:1
	setuptime  	35
	area       	10
	operation	eq, lt
    endfunc		; CMP32_v3
    function	subi0_v4, local
	port    	:in:in:17:generic, "in1":in:in:16, :retval:out:17
	setuptime  	18
	area       	4
	operation	sub
    endfunc		; subi0_v4
    function	addi_v4, local
	port    	:in:in:17, "in1":in:in:17:generic, :retval:out:17
	setuptime  	18
	area       	4
	operation	add
    endfunc		; addi_v4
    function	mux_v2, local
	port    	:retval:out:17, :in:in:17, "sel0":sel:in:1, "in1":in:in:17
	operation	mux
    endfunc		; mux_v2
    function	addi_v5, local
	port    	:in:in:2, "in1":in:in:2:generic, :retval:out:2
	setuptime  	4
	area       	2
	operation	add
    endfunc		; addi_v5
    function	ALU16_v2, local
	port    	"in0":in:in:16, "in1":in:in:2, :retval:out:16, :oper:in:1
	setuptime  	31
	area       	10
	operation	add, sub
    endfunc		; ALU16_v2
    function	addi_v3, local
	port    	:in:in:16, "in1":in:in:16:generic, :retval:out:16
	setuptime  	27
	area       	9
	operation	add
    endfunc		; addi_v3
    function	gti, local
	port    	:in:in:16, "in1":in:in:16:generic, :retval:out:1
	setuptime  	27
	area       	9
	operation	gt
    endfunc		; gti
    function	subi0_v3, local
	port    	:in:in:18:generic, "in1":in:in:18, :retval:out:18
	setuptime  	19
	area       	5
	operation	sub
    endfunc		; subi0_v3
    function	ALU32, local
	port    	"in0":in:in:32, "in1":in:in:32, :retval:out:32, :oper:in:1
	setuptime  	38
	area       	10
	operation	add, sub
    endfunc		; ALU32
    function	addi_v2, local
	port    	:in:in:32, "in1":in:in:32:generic, :retval:out:32
	setuptime  	34
	area       	9
	operation	add
    endfunc		; addi_v2
    function	gei, local
	port    	:in:in:32, "in1":in:in:32:generic, :retval:out:1
	setuptime  	31
	area       	9
	operation	ge
    endfunc		; gei
    function	subi, local
	port    	:in:in:32, "in1":in:in:32:generic, :retval:out:32
	setuptime  	34
	area       	9
	operation	sub
    endfunc		; subi
    function	mux, local
	port    	:retval:out:32, :in:in:32, "sel0":sel:in:1, "in1":in:in:32
	operation	mux
    endfunc		; mux
    function	CMP32_v2, local
	port    	"in0":in:in:32, "in1":in:in:32, :retval:out:1
	setuptime  	35
	area       	10
	operation	le
    endfunc		; CMP32_v2
	source 'main.c'

; Function hw_plot
    function	hw_plot, export
	port    	"vgamem":in:in:32, "x":in:in:16, "y":in:in:16, "color":in:in:16
	port    	:start:in:1, :done:out:1, :clock:global_in:1, :reset:global_in:1
	cycles     	-2
	setuptime  	70
	holdtime   	10
	component	__me_0, __me, import
	cc		wishbone, 2
    implementation  
	component	vst_me_16_0, vst_me_16 ( __me_0 )
	component	ltui_1, ltui, generics ( "in1"=#240:16 )
	component	ltui_0, ltui, generics ( "in1"=#320:16 )
	component	ALU32_v3_0, ALU32_v3
	component	MULADD18_v2_2, MULADD18_v2
	wire		w1:16, w2:16, w3:9, w4:10, w5:19, w6:32, w7:1, w8:1, w9:1
	register	r1:32, r2:16, r3:16, r4:16, r5:18, r6:1
    begin           
S0:  [ 
	                    input           #0:1, r1:32
	                    input           #1:1, w1:16
	                    input           #2:2, w2:16
	                    input           #3:2, r2:16
	                    mov             w1:16, r3:16
	                    mov             w2:16, r4:16
	                    zext            w2:8, w3:9
	                    zext            w1:9, w4:10
	@MULADD18_v2_2      muladd          w3:9, #320:10, w4:10, r5:18
     ]
S1:  [ 
	                    concat          r5:18, #0:1, w5:19
	@ALU32_v3_0         add             r1:32, w5:19, w6:32
	@ltui_0             ltu             r3:16, #320:9, w7:1
	@ltui_1             ltu             r4:16, #240:8, w8:1
	                    and             w8:1, w7:1, w9:1
	                    mov             w9:1, r6:1
	@vst_me_16_0        vst             r2:16, w6:32	if w9
     ]
S2:  [ 
	@vst_me_16_0        jsr_ret_wait    	if r6
	                    ret             
     ]
    endfunc         

	; End of function
; Function hw_line
    function	hw_line, export
	port    	"vgamem":in:in:32, "x0":in:in:16, "y0":in:in:16, "x1":in:in:16
	port    	"y1":in:in:16, "color":in:in:16, :start:in:1, :done:out:1
	port    	:clock:global_in:1, :reset:global_in:1
	cycles     	-3
	setuptime  	75
	holdtime   	5
	component	__me_0, __me, import
	cc		wishbone, 1
    implementation  
	component	mux_v3_14, mux_v3
	component	mux_v3_13, mux_v3
	component	gti_0, gti, generics ( "in1"=#0:16 )
	component	ALU16_2, ALU16
	component	addi_v3_0, addi_v3, generics ( "in1"=#1:16 )
	component	ALU16_v2_0, ALU16_v2
	component	vst_me_16_1, vst_me_16 ( __me_0 )
	component	ltui_3, ltui, generics ( "in1"=#240:16 )
	component	ltui_2, ltui, generics ( "in1"=#320:16 )
	component	MULADD18_v2_0, MULADD18_v2
	component	mux_v3_12, mux_v3
	component	mux_v3_11, mux_v3
	component	mux_v3_10, mux_v3
	component	addi_v5_0, addi_v5, generics ( "in1"=#-1:2 )
	component	mux_v2_0, mux_v2
	component	addi_v4_0, addi_v4, generics ( "in1"=#1:17 )
	component	subi0_v4_0, subi0_v4, generics ( "in"=#0:17 )
	component	ALU32_v2_1, ALU32_v2
	component	ALU32_v2_4, ALU32_v2
	component	CMP32_v3_0, CMP32_v3
	component	ALU16_0, ALU16
	component	CMPU16_2, CMPU16
	component	mux_v3_9, mux_v3
	component	mux_v3_8, mux_v3
	component	mux_v3_7, mux_v3
	component	mux_v3_6, mux_v3
	component	mux_v3_5, mux_v3
	component	mux_v3_4, mux_v3
	component	mux_v3_3, mux_v3
	component	mux_v3_2, mux_v3
	component	CMP16_v2_0, CMP16_v2
	component	mux_v3_1, mux_v3
	component	mux_v3_0, mux_v3
	component	CMPU16_1, CMPU16
	component	ALU32_v2_2, ALU32_v2
	component	ALU32_v2_3, ALU32_v2
	component	CMPU16_0, CMPU16
	component	ALU32_v2_0, ALU32_v2
	component	ALU32_v3_1, ALU32_v3
	register	r7:32, r8:16, r9:16, r10:16, r11:16, r12:16, r13:16, r14:16, r15:1, r16:1
	wire		w10:16, w11:16, w12:16, w13:16, w14:1, w15:1, w16:16, w17:16, w18:1, w19:1
	wire		w20:16, w21:16, w22:1, w23:16, w24:16, w25:1, w26:16, w27:16, w28:16, w29:16
	wire		w30:1, w31:1, w32:16, w33:17, w34:1, w35:1, w36:1, w37:16, w38:16, w39:17
	register	r17:16, r18:16, r19:1, r20:1, r21:1, r22:1, r23:16, r24:16, r25:16, r26:2
	wire		w40:17, w41:32, w42:1, w43:17, w44:1, w45:2, w46:1, w47:1, w48:16, w49:16
	wire		w50:16, w51:16, w52:9, w53:10, w54:19, w55:32, w56:1, w57:1, w58:1, w59:16
	wire		w60:16, w61:16, w62:17, w63:1, w64:1, w65:16, w66:1, w67:1
	register	r27:16, r28:16, r29:16, r30:16, r31:16, r32:16, r33:16, r34:18
    begin           
S0:  [ 
	                    input           #0:1, r7:32
	                    input           #1:1, w10:16
	                    input           #2:2, w11:16
	                    input           #3:2, w12:16
	                    input           #4:3, w13:16
	                    input           #5:3, r8:16
	                    mov             w10:16, r9:16
	                    mov             w11:16, r10:16
	                    mov             w12:16, r11:16
	                    mov             w13:16, r12:16
	@ALU32_v3_1         sub             w10:16, w12:16, r13:16
	@ALU32_v2_0         sub             w12:16, w10:16, r14:16
	@CMPU16_0           cmpu            w10:16, w12:16, r15:1, r16:1
	@ALU32_v2_3         sub             w11:16, w13:16, r17:16
	@ALU32_v2_2         sub             w13:16, w11:16, r18:16
	@CMPU16_1           cmpu            w11:16, w13:16, r19:1, r20:1
     ]
S1:  [ 
	                    or              r15:1, r16:1, w14:1
	                    or              r19:1, r20:1, w15:1
	@mux_v3_0           mux             w16:16, w14:1?r14:16, r13:16
	@mux_v3_1           mux             w17:16, w15:1?r18:16, r17:16
	@CMP16_v2_0         lt              w16:16, w17:16, w18:1
	                    mov             w18:1, r21:1
	                    mov             w18:1, w19:1
	                    mov             w19:1, r22:1
	@mux_v3_2           mux             w20:16, w19:1?r10:16, r9:16
	                    mov             w20:16, r23:16
	@mux_v3_3           mux             w21:16, w19:1?r12:16, r11:16
	                    mov             w21:16, r24:16
	@CMPU16_1           cmpu            w20:16, w21:16, r19:1, r20:1
     ]
S2:  [ 
	                    or              r19:1, r20:1, w22:1
	@mux_v3_4           mux             w23:16, r22:1?r9:16, r10:16
	@mux_v3_5           mux             w24:16, r22:1?r11:16, r12:16
	                    not             w22:1, w25:1
	@mux_v3_6           mux             w26:16, w25:1?r24:16, r23:16
	@mux_v3_7           mux             w27:16, w25:1?r23:16, r24:16
	@mux_v3_8           mux             w28:16, w25:1?w23:16, w24:16
	@mux_v3_9           mux             w29:16, w25:1?w24:16, w23:16
	@CMPU16_2           cmpu            w28:16, w29:16, w30:1, w31:1
	@ALU16_0            sub             w27:16, w26:16, w32:16
	                    mov             w32:16, r25:16
	                    zext            w27:16, w33:17
	@CMP32_v3_0         cmp             w26:16, w33:17, w34:1, w35:1
	@CMPU16_1           ltu             w29:16, w28:16, w36:1
	@ALU32_v2_4         sub             w28:16, w29:16, w37:16
	@ALU32_v2_1         sub             w29:16, w28:16, w38:16
	@subi0_v4_0         sub             #0:1, w32:16, w39:17
	@addi_v4_0          add             w39:17, #1:2, w40:17
	                    sext            w39:17, w41:32
	                    extract         w41:32, #31:5, w42:1
	@mux_v2_0           mux             w43:17, w42:1?w40:17, w41:17
	                    or              w30:1, w31:1, w44:1
	                    concat          w36:1, #0:1, w45:2
	                    nor             w34:1, w35:1, w46:1
	@addi_v5_0          add             w45:2, #-1:1, r26:2
	@mux_v3_10          mux             r27:16, w44:1?w38:16, w37:16
	                    mov             w29:16, r28:16
	                    mov             w27:16, r29:16
	                    mov             w26:16, r30:16
	                    extract         w43:17, #16:5, r31:16
	                    jmp             .L12:32 if w46
     ]
.L13:
S3:  [ 
	                    not             r21:1, w47:1
	                    mov             r28:16, w48:16
	                    mov             r30:16, w49:16
	@mux_v3_11          mux             w50:16, w47:1?w49:16, w48:16
	                    mov             w50:16, r32:16
	@mux_v3_12          mux             w51:16, w47:1?w48:16, w49:16
	                    mov             w51:16, r33:16
	                    zext            w51:8, w52:9
	                    zext            w50:9, w53:10
	@MULADD18_v2_0      muladd          w52:9, #320:10, w53:10, r34:18
     ]
S4:  [ 
	                    concat          r34:18, #0:1, w54:19
	@ALU32_v3_1         add             r7:32, w54:19, w55:32
	@ltui_2             ltu             r32:16, #320:9, w56:1
	@ltui_3             ltu             r33:16, #240:8, w57:1
	                    and             w57:1, w56:1, w58:1
	                    mov             w58:1, r19:1
	@vst_me_16_1        vst             r8:16, w55:32	if w58
     ]
S5:  [ 
	@vst_me_16_1        jsr_ret_wait    	if r19
	@ALU16_v2_0         add             r28:16, r26:2, w59:16
	@addi_v3_0          add             r30:16, #1:2, w60:16
	@ALU16_0            add             r31:16, r27:16, w61:16
	                    zext            r29:16, w62:17
	@CMP32_v3_0         cmp             w60:16, w62:17, w63:1, w64:1
	@ALU16_2            sub             w61:16, r25:16, w65:16
	@gti_0              gt              w61:16, #0:1, w66:1
	@mux_v3_13          mux             r28:16, w66:1?w59:16, r28:16
	@mux_v3_14          mux             r31:16, w66:1?w65:16, w61:16
	                    or              w63:1, w64:1, w67:1
	                    mov             w60:16, r30:16
	                    jmp             .L13:32 if w67
     ]
.L12:
S6:  [ 
	                    ret             
     ]
    endfunc         

	; End of function
; Function hw_circle
    function	hw_circle, export
	port    	"vgamem":in:in:32, "x0":in:in:16, "y0":in:in:16, "radius":in:in:16
	port    	"color":in:in:16, :start:in:1, :done:out:1, :clock:global_in:1
	port    	:reset:global_in:1
	cycles     	-11
	setuptime  	35
	holdtime   	5
	component	__me_0, __me, import
	cc		wishbone, 0
    implementation  
	component	mux_1, mux
	component	CMP32_v2_0, CMP32_v2
	component	mux_0, mux
	component	addi_v2_2, addi_v2, generics ( "in1"=#1:32 )
	component	addi_v2_1, addi_v2, generics ( "in1"=#10:32 )
	component	subi_0, subi, generics ( "in1"=#1:32 )
	component	gei_0, gei, generics ( "in1"=#0:32 )
	component	vst_me_16_9, vst_me_16 ( __me_0 )
	component	addi_v2_0, addi_v2, generics ( "in1"=#6:32 )
	component	ALU32_8, ALU32
	component	vst_me_16_8, vst_me_16 ( __me_0 )
	component	ltui_11, ltui, generics ( "in1"=#240:16 )
	component	vst_me_16_7, vst_me_16 ( __me_0 )
	component	ltui_10, ltui, generics ( "in1"=#320:16 )
	component	vst_me_16_6, vst_me_16 ( __me_0 )
	component	ltui_9, ltui, generics ( "in1"=#320:16 )
	component	ltui_8, ltui, generics ( "in1"=#240:16 )
	component	vst_me_16_5, vst_me_16 ( __me_0 )
	component	vst_me_16_4, vst_me_16 ( __me_0 )
	component	ltui_7, ltui, generics ( "in1"=#240:16 )
	component	vst_me_16_3, vst_me_16 ( __me_0 )
	component	ltui_6, ltui, generics ( "in1"=#320:16 )
	component	vst_me_16_2, vst_me_16 ( __me_0 )
	component	ltui_5, ltui, generics ( "in1"=#320:16 )
	component	ltui_4, ltui, generics ( "in1"=#240:16 )
	component	ALU32_7, ALU32
	component	MULADD18_v2_1, MULADD18_v2
	component	ALU16_4, ALU16
	component	ALU16_3, ALU16
	component	subi0_v3_0, subi0_v3, generics ( "in"=#3:18 )
	register	r35:32, r36:16, r37:16, r38:16, r39:32, r40:32, r41:32, r42:16, r43:16, r44:9
	wire		w68:16, w69:17, w70:18, w71:18, w72:16, w73:16, w74:9, w75:10, w76:16, w77:10
	wire		w78:19, w79:32, w80:1, w81:1, w82:1, w83:16, w84:9, w85:19, w86:32, w87:1
	register	r45:10, r46:18, r47:16, r48:10, r49:18, r50:1, r51:1, r52:1, r53:16, r54:1
	wire		w88:1, w89:19, w90:32, w91:1, w92:1, w93:16, w94:16, w95:9, w96:10, w97:19
	register	r55:1, r56:1, r57:1, r58:16, r59:16, r60:1, r61:16, r62:1, r63:1, r64:1
	wire		w98:32, w99:1, w100:16, w101:10, w102:19, w103:32, w104:1, w105:1, w106:1, w107:16
	wire		w108:9, w109:19, w110:32, w111:1, w112:1, w113:19, w114:32, w115:1, w116:1, w117:19
	wire		w118:32, w119:1, w120:32, w121:1, w122:32, w123:32, w124:32, w125:32, w126:32, w127:32
	wire		w128:1, w129:32, w130:1
	register	r65:16, r66:1, r67:1, r68:1, r69:1, r70:30, r71:32, r72:1
    begin           
S0:  [ 
	                    input           #0:1, r35:32
	                    input           #1:1, r36:16
	                    input           #2:2, r37:16
	                    input           #3:2, w68:16
	                    input           #4:3, r38:16
	                    concat          w68:16, #0:1, w69:17
	                    zext            w69:17, w70:18
	@subi0_v3_0         sub             #3:3, w70:18, w71:18
	                    mov             #0:1, r39:32
	                    zext            w68:16, r40:32
	                    sext            w71:18, r41:32
     ]
.L19:			; loop start
S1:  [ 
	@ALU16_3            add             r36:16, r39:16, w72:16
	                    mov             w72:16, r42:16
	@ALU16_4            add             r37:16, r40:16, w73:16
	                    mov             w73:16, r43:16
	                    zext            w73:8, w74:9
	                    mov             w74:9, r44:9
	                    zext            w72:9, w75:10
	                    mov             w75:10, r45:10
	@MULADD18_v2_1      muladd          w74:9, #320:10, w75:10, r46:18
     ]
S2:  [ 
	@ALU16_3            sub             r36:16, r39:16, w76:16
	                    mov             w76:16, r47:16
	                    zext            w76:9, w77:10
	                    mov             w77:10, r48:10
	@MULADD18_v2_1      muladd          r44:9, #320:10, w77:10, r49:18
	                    concat          r46:18, #0:1, w78:19
	@ALU32_7            add             r35:32, w78:19, w79:32
	@ltui_4             ltu             r43:16, #240:8, w80:1
	                    mov             w80:1, r50:1
	@ltui_5             ltu             r42:16, #320:9, w81:1
	                    mov             w81:1, r51:1
	                    and             w80:1, w81:1, w82:1
	                    mov             w82:1, r52:1
	@vst_me_16_2        vst             r38:16, w79:32	if w82
     ]
S3:  [ 
	@vst_me_16_2        jsr_ret_wait    	if r52
	@ALU16_4            sub             r37:16, r40:16, w83:16
	                    mov             w83:16, r53:16
	                    zext            w83:8, w84:9
	                    mov             w84:9, r44:9
	@MULADD18_v2_1      muladd          w84:9, #320:10, r45:10, r46:18
	                    concat          r49:18, #0:1, w85:19
	@ALU32_7            add             r35:32, w85:19, w86:32
	@ltui_6             ltu             r47:16, #320:9, w87:1
	                    mov             w87:1, r54:1
	                    and             r50:1, w87:1, w88:1
	                    mov             w88:1, r55:1
	@vst_me_16_3        vst             r38:16, w86:32	if w88
     ]
S4:  [ 
	@vst_me_16_3        jsr_ret_wait    	if r55
	@MULADD18_v2_1      muladd          r44:9, #320:10, r48:10, r49:18
	                    concat          r46:18, #0:1, w89:19
	@ALU32_7            add             r35:32, w89:19, w90:32
	@ltui_7             ltu             r53:16, #240:8, w91:1
	                    mov             w91:1, r56:1
	                    and             w91:1, r51:1, w92:1
	                    mov             w92:1, r57:1
	@vst_me_16_4        vst             r38:16, w90:32	if w92
     ]
S5:  [ 
	@vst_me_16_4        jsr_ret_wait    	if r57
	@ALU16_3            add             r36:16, r40:16, w93:16
	                    mov             w93:16, r58:16
	@ALU16_4            add             r37:16, r39:16, w94:16
	                    mov             w94:16, r59:16
	                    zext            w94:8, w95:9
	                    mov             w95:9, r44:9
	                    zext            w93:9, w96:10
	                    mov             w96:10, r45:10
	@MULADD18_v2_1      muladd          w95:9, #320:10, w96:10, r46:18
	                    concat          r49:18, #0:1, w97:19
	@ALU32_7            add             r35:32, w97:19, w98:32
	                    and             r56:1, r54:1, w99:1
	                    mov             w99:1, r60:1
	@vst_me_16_5        vst             r38:16, w98:32	if w99
     ]
S6:  [ 
	@vst_me_16_5        jsr_ret_wait    	if r60
	@ALU16_3            sub             r36:16, r40:16, w100:16
	                    mov             w100:16, r61:16
	                    zext            w100:9, w101:10
	                    mov             w101:10, r48:10
	@MULADD18_v2_1      muladd          r44:9, #320:10, w101:10, r49:18
	                    concat          r46:18, #0:1, w102:19
	@ALU32_7            add             r35:32, w102:19, w103:32
	@ltui_8             ltu             r59:16, #240:8, w104:1
	                    mov             w104:1, r62:1
	@ltui_9             ltu             r58:16, #320:9, w105:1
	                    mov             w105:1, r63:1
	                    and             w104:1, w105:1, w106:1
	                    mov             w106:1, r64:1
	@vst_me_16_6        vst             r38:16, w103:32	if w106
     ]
S7:  [ 
	@vst_me_16_6        jsr_ret_wait    	if r64
	@ALU16_4            sub             r37:16, r39:16, w107:16
	                    mov             w107:16, r65:16
	                    zext            w107:8, w108:9
	                    mov             w108:9, r44:9
	@MULADD18_v2_1      muladd          w108:9, #320:10, r45:10, r46:18
	                    concat          r49:18, #0:1, w109:19
	@ALU32_7            add             r35:32, w109:19, w110:32
	@ltui_10            ltu             r61:16, #320:9, w111:1
	                    mov             w111:1, r66:1
	                    and             r62:1, w111:1, w112:1
	                    mov             w112:1, r67:1
	@vst_me_16_7        vst             r38:16, w110:32	if w112
     ]
S8:  [ 
	@vst_me_16_7        jsr_ret_wait    	if r67
	@MULADD18_v2_1      muladd          r44:9, #320:10, r48:10, r49:18
	                    concat          r46:18, #0:1, w113:19
	@ALU32_7            add             r35:32, w113:19, w114:32
	@ltui_11            ltu             r65:16, #240:8, w115:1
	                    mov             w115:1, r68:1
	                    and             w115:1, r63:1, w116:1
	                    mov             w116:1, r69:1
	@vst_me_16_8        vst             r38:16, w114:32	if w116
     ]
S9:  [ 
	@vst_me_16_8        jsr_ret_wait    	if r69
	                    concat          r49:18, #0:1, w117:19
	@ALU32_7            add             r35:32, w117:19, w118:32
	@ALU32_8            sub             r39:30, r40:30, r70:30
	@addi_v2_0          add             r41:32, #6:4, r71:32
	                    and             r68:1, r66:1, w119:1
	                    mov             w119:1, r72:1
	@vst_me_16_9        vst             r38:16, w118:32	if w119
     ]
S10:  [ 
	@vst_me_16_9        jsr_ret_wait    	if r72
	                    concat          r39:30, #0:2, w120:32
	@gei_0              ge              r41:32, #0:1, w121:1
	@subi_0             sub             r40:32, #1:2, w122:32
	@ALU32_7            add             r71:32, w120:32, w123:32
	@addi_v2_1          add             r41:32, #10:5, w124:32
	@addi_v2_2          add             r39:32, #1:2, w125:32
	@mux_0              mux             w126:32, w121:1?w122:32, r40:32
	                    concat          r70:30, #0:2, w127:32
	@CMP32_v2_0         le              w125:32, w126:32, w128:1
	@ALU32_8            add             w124:32, w127:32, w129:32
	@mux_1              mux             r41:32, w121:1?w129:32, w123:32
	                    mov             w128:1, w130:1
	                    mov             w125:32, r39:32
	                    mov             w126:32, r40:32
	                    jmp             .L19:0 if w130:1			; loop end; __Nil:64
     ]
S11:  [ 
	                    ret             
     ]
    endfunc         

	; End of function
	; Module end
	component	hw_plot_0, hw_plot ( __me_0 ), export
	component	__me_0, __me, import
	component	hw_line_0, hw_line ( __me_0 ), export
	component	hw_circle_0, hw_circle ( __me_0 ), export
    end
