Classic Timing Analyzer report for NB3000_Unique_MAC
Wed Mar 06 21:28:53 2013
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'CLK_REF'
  7. Clock Setup: 'CLK_BRD'
  8. Clock Setup: 'JTAG_NEXUS_TCK'
  9. Clock Setup: 'ETH_TXC'
 10. Clock Setup: 'ETH_RXC'
 11. tsu
 12. tco
 13. tpd
 14. th
 15. Minimum tco
 16. Minimum tpd
 17. Board Trace Model Assignments
 18. Input Transition Times
 19. Slow Corner Signal Integrity Metrics
 20. Fast Corner Signal Integrity Metrics
 21. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+
; Type                          ; Slack ; Required Time ; Actual Time                                    ; From                                                                                                                                                                                       ; To                                                                                                                                                                         ; From Clock     ; To Clock       ; Failed Paths ;
+-------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+
; Worst-case tsu                ; N/A   ; None          ; 13.438 ns                                      ; SRAM0_D[1]                                                                                                                                                                                 ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]                                                                                                                 ; --             ; CLK_BRD        ; 0            ;
; Worst-case tco                ; N/A   ; None          ; 20.875 ns                                      ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                                                                                        ; SRAM0_E                                                                                                                                                                    ; CLK_BRD        ; --             ; 0            ;
; Worst-case tpd                ; N/A   ; None          ; 16.212 ns                                      ; TEST_BUTTON                                                                                                                                                                                ; ETH_RESETB_E                                                                                                                                                               ; --             ; --             ; 0            ;
; Worst-case th                 ; N/A   ; None          ; 0.777 ns                                       ; ETH_MDIO                                                                                                                                                                                   ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[0]                                                                                                           ; --             ; CLK_REF        ; 0            ;
; Worst-case Minimum tco        ; N/A   ; None          ; 8.069 ns                                       ; WB_SPI32:U_Unique_MAC_System_SPI_SubPart_Port|spi32:U_spi|SPI_CLK                                                                                                                          ; SPI_CLK                                                                                                                                                                    ; CLK_BRD        ; --             ; 0            ;
; Worst-case Minimum tpd        ; N/A   ; None          ; 16.212 ns                                      ; TEST_BUTTON                                                                                                                                                                                ; ETH_RESETB_E                                                                                                                                                               ; --             ; --             ; 0            ;
; Clock Setup: 'CLK_BRD'        ; N/A   ; None          ; 49.69 MHz ( period = 20.124 ns )               ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD        ; CLK_BRD        ; 0            ;
; Clock Setup: 'ETH_TXC'        ; N/A   ; None          ; 86.72 MHz ( period = 11.532 ns )               ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]                                                                                                                          ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14]                                                                                                         ; ETH_TXC        ; ETH_TXC        ; 0            ;
; Clock Setup: 'ETH_RXC'        ; N/A   ; None          ; 117.70 MHz ( period = 8.496 ns )               ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]                                                                                                                          ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok                                                                                                                 ; ETH_RXC        ; ETH_RXC        ; 0            ;
; Clock Setup: 'JTAG_NEXUS_TCK' ; N/A   ; None          ; 162.00 MHz ( period = 6.173 ns )               ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z             ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0            ;
; Clock Setup: 'CLK_REF'        ; N/A   ; None          ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]                                                                                                                           ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[2]                                                                                                           ; CLK_REF        ; CLK_REF        ; 0            ;
; Total number of failed paths  ;       ;               ;                                                ;                                                                                                                                                                                            ;                                                                                                                                                                            ;                ;                ; 0            ;
+-------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP3C40F780C8       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; On                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; On                 ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK_REF         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLK_BRD         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; JTAG_NEXUS_TCK  ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ETH_TXC         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ETH_RXC         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_REF'                                                                                                                                                                                                                                                                                                                           ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                             ; To                                                                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_9   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_8   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_11  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_7   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_15  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_10  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[1]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_6   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_12  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_5   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_13  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_14  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[4]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[3]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[2]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.504 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[1] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.395 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[0] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.395 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[1] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.382 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[0] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.382 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_9   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_8   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_11  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_7   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_15  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_10  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[1]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_6   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_12  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_5   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_13  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_14  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[4]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[3]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[2]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[1] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.298 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[0] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.298 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[15]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[14]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[13]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[12]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[11]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[10]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[9]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[8]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[7]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[6]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[5]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[4]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[3]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[2]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[1]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|op[1]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|op[0]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[4]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[3]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[2]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[1]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[0]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[4]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[3]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[2]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[1]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[0]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.211 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[1] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.118 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[0] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.118 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[15]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[14]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[13]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[12]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[11]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[10]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[9]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[8]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[7]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[6]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[5]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[4]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[3]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[2]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[1]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 3.014 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[1] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.962 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[0] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.962 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|op[1]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|op[0]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[4]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[3]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[2]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[1]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[0]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[4]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[3]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[2]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[1]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[0]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.954 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|stop_comm   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.842 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[1] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.835 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[0] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.835 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|stop_comm   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.829 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|stop_comm   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.745 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[0]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.583 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|stop_comm   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.565 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[0]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.411 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|stop_comm   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.409 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|mdoe        ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.322 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|stop_comm   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.282 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[1] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.262 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|last_cmd[0] ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.262 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|mdoe        ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.195 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[1]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.185 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|mdo         ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.113 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.076 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|mdoe        ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.041 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.017 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 2.003 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.947 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.944 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.930 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.874 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.871 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.869 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.857 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|mdo         ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.856 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_2__Z                                             ; CDIV20DC50:U4|OutState_Z                                          ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.850 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_1__Z                                             ; CDIV20DC50:U4|OutState_Z                                          ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.806 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.801 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.799 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.798 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.796 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.784 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.747 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.728 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.726 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.725 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.723 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.711 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|stop_comm   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.709 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|st[0]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.652 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|ta[1]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.648 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|st[1]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.586 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|ta[0]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.520 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_0__Z                                             ; CDIV20DC50:U4|OutState_Z                                          ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.511 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_2__Z                                             ; CDIV20DC50:U4|i_2__Z                                              ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.488 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|mdoe        ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.463 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_3__Z                                             ; CDIV20DC50:U4|OutState_Z                                          ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.460 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_1__Z                                             ; CDIV20DC50:U4|i_2__Z                                              ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.444 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|ta[0]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.427 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|st[1]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.426 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|ta[1]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.392 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|st[0]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.391 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[0]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.341 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|mdoe        ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.282 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[0]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.242 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_9  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_10  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.238 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[15] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|ta[0]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.176 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_0__Z                                             ; CDIV20DC50:U4|i_2__Z                                              ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.149 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[9]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.093 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.069 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[5]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.063 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[8]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.058 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[6]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.058 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[2]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.055 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[4]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.053 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[3]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.053 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[1]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.053 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_0__Z                                             ; CDIV20DC50:U4|i_1__Z                                              ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.043 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[1]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.040 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_5  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_6   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.040 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[3]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.038 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[2]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.029 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|ta[1]      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[0]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.027 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[4]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.027 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[0]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.024 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_1__Z                                             ; CDIV20DC50:U4|i_3__Z                                              ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.019 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[4] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_5   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.013 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|st[0]      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|st[1]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.012 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_2__Z                                             ; CDIV20DC50:U4|i_3__Z                                              ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.011 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_8  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_9   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.005 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_13 ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_14  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.005 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_11 ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_12  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.004 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|st[1]      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|mdo         ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.004 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|ta[0]      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|ta[1]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.003 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[2]   ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[3]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.001 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_12 ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_13  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.000 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[7]   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 1.000 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; CDIV20DC50:U4|i_3__Z                                             ; CDIV20DC50:U4|i_1__Z                                              ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.999 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_10 ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_11  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.999 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[1]   ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[2]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.999 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[0]   ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[1]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.998 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[4]   ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[0]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.997 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_6  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_7   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.996 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[3]   ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reg_a[4]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.996 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[1] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[2]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.868 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[3] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[4]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.866 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[2] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[3]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.866 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|op[1]      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|st[0]       ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.854 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_7  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_8   ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.852 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[1]   ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[2]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.842 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[11] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_o[12]  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.842 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_14 ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_15  ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.841 ns                ;
; N/A                                     ; Restricted to 250.00 MHz ( period = 4.000 ns )      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[2]   ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|phy_a[3]    ; CLK_REF    ; CLK_REF  ; None                        ; None                      ; 0.841 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                  ;                                                                   ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                       ; To                                                                                                                                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 49.69 MHz ( period = 20.124 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.747 ns                ;
; N/A                                     ; 50.06 MHz ( period = 19.976 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.697 ns                ;
; N/A                                     ; 51.35 MHz ( period = 19.474 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.430 ns                ;
; N/A                                     ; 51.45 MHz ( period = 19.438 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.432 ns                ;
; N/A                                     ; 51.60 MHz ( period = 19.380 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.395 ns                ;
; N/A                                     ; 51.78 MHz ( period = 19.314 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.340 ns                ;
; N/A                                     ; 51.98 MHz ( period = 19.240 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.313 ns                ;
; N/A                                     ; 52.07 MHz ( period = 19.206 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.293 ns                ;
; N/A                                     ; 52.32 MHz ( period = 19.114 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.252 ns                ;
; N/A                                     ; 52.83 MHz ( period = 18.928 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.163 ns                ;
; N/A                                     ; 53.38 MHz ( period = 18.734 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.122 ns                ;
; N/A                                     ; 53.41 MHz ( period = 18.722 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.145 ns                ;
; N/A                                     ; 53.57 MHz ( period = 18.668 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.017 ns                ;
; N/A                                     ; 53.57 MHz ( period = 18.666 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2                                                                                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.596 ns                ;
; N/A                                     ; 53.70 MHz ( period = 18.622 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5                                                                                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.574 ns                ;
; N/A                                     ; 53.84 MHz ( period = 18.574 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.095 ns                ;
; N/A                                     ; 54.09 MHz ( period = 18.486 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.998 ns                ;
; N/A                                     ; 54.24 MHz ( period = 18.436 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.973 ns                ;
; N/A                                     ; 54.26 MHz ( period = 18.430 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.970 ns                ;
; N/A                                     ; 54.27 MHz ( period = 18.425 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 18.280 ns               ;
; N/A                                     ; 54.29 MHz ( period = 18.418 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.963 ns                ;
; N/A                                     ; 54.45 MHz ( period = 18.367 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 18.235 ns               ;
; N/A                                     ; 54.47 MHz ( period = 18.360 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1                                                                                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.933 ns                ;
; N/A                                     ; 54.56 MHz ( period = 18.328 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.916 ns                ;
; N/A                                     ; 54.64 MHz ( period = 18.303 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 18.143 ns               ;
; N/A                                     ; 54.67 MHz ( period = 18.292 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.918 ns                ;
; N/A                                     ; 54.78 MHz ( period = 18.254 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.830 ns                ;
; N/A                                     ; 54.88 MHz ( period = 18.220 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.886 ns                ;
; N/A                                     ; 54.91 MHz ( period = 18.212 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.813 ns                ;
; N/A                                     ; 55.11 MHz ( period = 18.144 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.868 ns                ;
; N/A                                     ; 55.14 MHz ( period = 18.137 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.972 ns               ;
; N/A                                     ; 55.31 MHz ( period = 18.080 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.728 ns                ;
; N/A                                     ; 55.31 MHz ( period = 18.079 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.927 ns               ;
; N/A                                     ; 55.48 MHz ( period = 18.024 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.824 ns                ;
; N/A                                     ; 55.53 MHz ( period = 18.009 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.392 ns               ;
; N/A                                     ; 55.54 MHz ( period = 18.006 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.869 ns               ;
; N/A                                     ; 55.55 MHz ( period = 18.002 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.909 ns               ;
; N/A                                     ; 55.56 MHz ( period = 17.999 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.911 ns               ;
; N/A                                     ; 55.57 MHz ( period = 17.994 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3                                                                                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.750 ns                ;
; N/A                                     ; 55.64 MHz ( period = 17.974 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.763 ns                ;
; N/A                                     ; 55.67 MHz ( period = 17.962 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.794 ns               ;
; N/A                                     ; 55.68 MHz ( period = 17.960 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.732 ns                ;
; N/A                                     ; 55.69 MHz ( period = 17.956 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.730 ns                ;
; N/A                                     ; 55.72 MHz ( period = 17.948 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0                                                                                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.237 ns                ;
; N/A                                     ; 55.73 MHz ( period = 17.944 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.864 ns               ;
; N/A                                     ; 55.76 MHz ( period = 17.933 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.329 ns               ;
; N/A                                     ; 55.77 MHz ( period = 17.932 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.753 ns               ;
; N/A                                     ; 55.79 MHz ( period = 17.924 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.305 ns               ;
; N/A                                     ; 55.83 MHz ( period = 17.912 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.738 ns                ;
; N/A                                     ; 55.83 MHz ( period = 17.910 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[0]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.731 ns                ;
; N/A                                     ; 55.85 MHz ( period = 17.904 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.749 ns               ;
; N/A                                     ; 55.87 MHz ( period = 17.900 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_29                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.281 ns               ;
; N/A                                     ; 55.88 MHz ( period = 17.896 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.277 ns               ;
; N/A                                     ; 55.89 MHz ( period = 17.891 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.737 ns               ;
; N/A                                     ; 55.90 MHz ( period = 17.889 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.270 ns               ;
; N/A                                     ; 55.91 MHz ( period = 17.886 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.272 ns               ;
; N/A                                     ; 56.01 MHz ( period = 17.854 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.242 ns               ;
; N/A                                     ; 56.03 MHz ( period = 17.848 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.242 ns               ;
; N/A                                     ; 56.03 MHz ( period = 17.846 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.634 ns                ;
; N/A                                     ; 56.08 MHz ( period = 17.832 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.209 ns               ;
; N/A                                     ; 56.08 MHz ( period = 17.831 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.225 ns               ;
; N/A                                     ; 56.10 MHz ( period = 17.824 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_29                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.218 ns               ;
; N/A                                     ; 56.10 MHz ( period = 17.824 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.619 ns                ;
; N/A                                     ; 56.11 MHz ( period = 17.823 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.206 ns               ;
; N/A                                     ; 56.11 MHz ( period = 17.822 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.205 ns               ;
; N/A                                     ; 56.11 MHz ( period = 17.821 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.204 ns               ;
; N/A                                     ; 56.12 MHz ( period = 17.820 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.214 ns               ;
; N/A                                     ; 56.12 MHz ( period = 17.820 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.203 ns               ;
; N/A                                     ; 56.12 MHz ( period = 17.819 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.202 ns               ;
; N/A                                     ; 56.14 MHz ( period = 17.812 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.698 ns                ;
; N/A                                     ; 56.28 MHz ( period = 17.769 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.155 ns               ;
; N/A                                     ; 56.30 MHz ( period = 17.762 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.142 ns               ;
; N/A                                     ; 56.31 MHz ( period = 17.758 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.570 ns                ;
; N/A                                     ; 56.35 MHz ( period = 17.747 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.122 ns               ;
; N/A                                     ; 56.35 MHz ( period = 17.747 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.143 ns               ;
; N/A                                     ; 56.35 MHz ( period = 17.746 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.142 ns               ;
; N/A                                     ; 56.35 MHz ( period = 17.745 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_29                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.131 ns               ;
; N/A                                     ; 56.35 MHz ( period = 17.745 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.141 ns               ;
; N/A                                     ; 56.36 MHz ( period = 17.744 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.140 ns               ;
; N/A                                     ; 56.36 MHz ( period = 17.743 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.139 ns               ;
; N/A                                     ; 56.36 MHz ( period = 17.742 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.626 ns                ;
; N/A                                     ; 56.37 MHz ( period = 17.741 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.127 ns               ;
; N/A                                     ; 56.37 MHz ( period = 17.740 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.630 ns                ;
; N/A                                     ; 56.40 MHz ( period = 17.729 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.548 ns               ;
; N/A                                     ; 56.41 MHz ( period = 17.727 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.547 ns               ;
; N/A                                     ; 56.42 MHz ( period = 17.723 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_29                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.098 ns               ;
; N/A                                     ; 56.44 MHz ( period = 17.719 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.094 ns               ;
; N/A                                     ; 56.44 MHz ( period = 17.718 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.561 ns               ;
; N/A                                     ; 56.44 MHz ( period = 17.717 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.114 ns               ;
; N/A                                     ; 56.45 MHz ( period = 17.716 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.553 ns               ;
; N/A                                     ; 56.45 MHz ( period = 17.714 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.095 ns               ;
; N/A                                     ; 56.45 MHz ( period = 17.714 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.095 ns               ;
; N/A                                     ; 56.45 MHz ( period = 17.714 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10                                                                                       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.611 ns                ;
; N/A                                     ; 56.46 MHz ( period = 17.711 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.092 ns               ;
; N/A                                     ; 56.47 MHz ( period = 17.707 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.567 ns               ;
; N/A                                     ; 56.48 MHz ( period = 17.706 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.608 ns                ;
; N/A                                     ; 56.48 MHz ( period = 17.706 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.522 ns               ;
; N/A                                     ; 56.48 MHz ( period = 17.704 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.097 ns               ;
; N/A                                     ; 56.50 MHz ( period = 17.698 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4                                                                                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.602 ns                ;
; N/A                                     ; 56.60 MHz ( period = 17.668 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.056 ns               ;
; N/A                                     ; 56.60 MHz ( period = 17.667 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.055 ns               ;
; N/A                                     ; 56.61 MHz ( period = 17.666 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.054 ns               ;
; N/A                                     ; 56.61 MHz ( period = 17.665 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.053 ns               ;
; N/A                                     ; 56.61 MHz ( period = 17.664 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.052 ns               ;
; N/A                                     ; 56.63 MHz ( period = 17.658 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.601 ns                ;
; N/A                                     ; 56.64 MHz ( period = 17.656 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.472 ns               ;
; N/A                                     ; 56.67 MHz ( period = 17.646 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.023 ns               ;
; N/A                                     ; 56.67 MHz ( period = 17.645 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.022 ns               ;
; N/A                                     ; 56.68 MHz ( period = 17.644 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.021 ns               ;
; N/A                                     ; 56.68 MHz ( period = 17.643 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.020 ns               ;
; N/A                                     ; 56.68 MHz ( period = 17.642 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.019 ns               ;
; N/A                                     ; 56.69 MHz ( period = 17.639 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.024 ns               ;
; N/A                                     ; 56.70 MHz ( period = 17.638 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.032 ns               ;
; N/A                                     ; 56.70 MHz ( period = 17.638 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.032 ns               ;
; N/A                                     ; 56.71 MHz ( period = 17.635 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.029 ns               ;
; N/A                                     ; 56.72 MHz ( period = 17.632 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.027 ns               ;
; N/A                                     ; 56.72 MHz ( period = 17.630 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.459 ns               ;
; N/A                                     ; 56.73 MHz ( period = 17.628 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.618 ns                ;
; N/A                                     ; 56.73 MHz ( period = 17.628 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.521 ns               ;
; N/A                                     ; 56.77 MHz ( period = 17.616 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.467 ns               ;
; N/A                                     ; 56.77 MHz ( period = 17.615 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.461 ns               ;
; N/A                                     ; 56.77 MHz ( period = 17.614 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.440 ns               ;
; N/A                                     ; 56.78 MHz ( period = 17.612 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[0]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.586 ns                ;
; N/A                                     ; 56.79 MHz ( period = 17.608 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_29                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.003 ns               ;
; N/A                                     ; 56.81 MHz ( period = 17.604 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.999 ns               ;
; N/A                                     ; 56.81 MHz ( period = 17.604 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.978 ns               ;
; N/A                                     ; 56.84 MHz ( period = 17.594 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.597 ns                ;
; N/A                                     ; 56.84 MHz ( period = 17.592 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_0                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.569 ns                ;
; N/A                                     ; 56.85 MHz ( period = 17.589 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.435 ns               ;
; N/A                                     ; 56.86 MHz ( period = 17.588 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_35                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.708 ns                ;
; N/A                                     ; 56.86 MHz ( period = 17.588 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_3                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.567 ns                ;
; N/A                                     ; 56.86 MHz ( period = 17.586 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_1                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.566 ns                ;
; N/A                                     ; 56.86 MHz ( period = 17.586 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0[4]                                                                 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.566 ns                ;
; N/A                                     ; 56.87 MHz ( period = 17.584 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.981 ns               ;
; N/A                                     ; 56.87 MHz ( period = 17.583 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.498 ns               ;
; N/A                                     ; 56.88 MHz ( period = 17.580 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.409 ns               ;
; N/A                                     ; 56.89 MHz ( period = 17.579 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.400 ns               ;
; N/A                                     ; 56.91 MHz ( period = 17.572 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_2                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.559 ns                ;
; N/A                                     ; 56.93 MHz ( period = 17.564 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.393 ns               ;
; N/A                                     ; 56.95 MHz ( period = 17.559 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.945 ns               ;
; N/A                                     ; 56.95 MHz ( period = 17.559 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.945 ns               ;
; N/A                                     ; 56.96 MHz ( period = 17.556 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.942 ns               ;
; N/A                                     ; 56.98 MHz ( period = 17.551 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.372 ns               ;
; N/A                                     ; 57.00 MHz ( period = 17.544 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.430 ns               ;
; N/A                                     ; 57.00 MHz ( period = 17.543 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.383 ns               ;
; N/A                                     ; 57.01 MHz ( period = 17.541 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.432 ns               ;
; N/A                                     ; 57.02 MHz ( period = 17.537 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.912 ns               ;
; N/A                                     ; 57.02 MHz ( period = 17.537 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.912 ns               ;
; N/A                                     ; 57.03 MHz ( period = 17.534 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.909 ns               ;
; N/A                                     ; 57.04 MHz ( period = 17.531 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.928 ns               ;
; N/A                                     ; 57.05 MHz ( period = 17.530 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.927 ns               ;
; N/A                                     ; 57.05 MHz ( period = 17.529 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.926 ns               ;
; N/A                                     ; 57.05 MHz ( period = 17.529 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.339 ns               ;
; N/A                                     ; 57.05 MHz ( period = 17.528 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.925 ns               ;
; N/A                                     ; 57.05 MHz ( period = 17.527 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.924 ns               ;
; N/A                                     ; 57.05 MHz ( period = 17.527 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.419 ns               ;
; N/A                                     ; 57.06 MHz ( period = 17.524 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_21                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.340 ns               ;
; N/A                                     ; 57.07 MHz ( period = 17.523 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.909 ns               ;
; N/A                                     ; 57.07 MHz ( period = 17.523 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.339 ns               ;
; N/A                                     ; 57.07 MHz ( period = 17.521 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_22                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.337 ns               ;
; N/A                                     ; 57.08 MHz ( period = 17.520 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.336 ns               ;
; N/A                                     ; 57.08 MHz ( period = 17.519 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.891 ns               ;
; N/A                                     ; 57.08 MHz ( period = 17.518 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.519 ns                ;
; N/A                                     ; 57.08 MHz ( period = 17.518 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.904 ns               ;
; N/A                                     ; 57.09 MHz ( period = 17.515 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.882 ns               ;
; N/A                                     ; 57.10 MHz ( period = 17.513 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.372 ns               ;
; N/A                                     ; 57.13 MHz ( period = 17.503 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.337 ns               ;
; N/A                                     ; 57.13 MHz ( period = 17.503 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.894 ns               ;
; N/A                                     ; 57.14 MHz ( period = 17.501 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.322 ns               ;
; N/A                                     ; 57.15 MHz ( period = 17.499 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.894 ns               ;
; N/A                                     ; 57.16 MHz ( period = 17.495 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_29                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.867 ns               ;
; N/A                                     ; 57.17 MHz ( period = 17.491 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.863 ns               ;
; N/A                                     ; 57.18 MHz ( period = 17.488 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.524 ns                ;
; N/A                                     ; 57.19 MHz ( period = 17.486 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.385 ns               ;
; N/A                                     ; 57.20 MHz ( period = 17.484 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.499 ns                ;
; N/A                                     ; 57.20 MHz ( period = 17.483 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.852 ns               ;
; N/A                                     ; 57.20 MHz ( period = 17.482 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.511 ns                ;
; N/A                                     ; 57.21 MHz ( period = 17.480 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[0]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.512 ns                ;
; N/A                                     ; 57.21 MHz ( period = 17.479 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.289 ns               ;
; N/A                                     ; 57.22 MHz ( period = 17.475 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_29                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.870 ns               ;
; N/A                                     ; 57.23 MHz ( period = 17.473 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.841 ns               ;
; N/A                                     ; 57.24 MHz ( period = 17.471 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.866 ns               ;
; N/A                                     ; 57.24 MHz ( period = 17.470 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.859 ns               ;
; N/A                                     ; 57.25 MHz ( period = 17.468 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.366 ns               ;
; N/A                                     ; 57.26 MHz ( period = 17.464 ns )                    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                                                                                        ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.486 ns                ;
; N/A                                     ; 57.29 MHz ( period = 17.454 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.516 ns                ;
; N/A                                     ; 57.31 MHz ( period = 17.449 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.298 ns               ;
; N/A                                     ; 57.31 MHz ( period = 17.448 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_21                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.277 ns               ;
; N/A                                     ; 57.32 MHz ( period = 17.447 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.846 ns               ;
; N/A                                     ; 57.32 MHz ( period = 17.447 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.276 ns               ;
; N/A                                     ; 57.32 MHz ( period = 17.445 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_22                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.274 ns               ;
; N/A                                     ; 57.33 MHz ( period = 17.444 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.273 ns               ;
; N/A                                     ; 57.33 MHz ( period = 17.442 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.841 ns               ;
; N/A                                     ; 57.36 MHz ( period = 17.435 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_a1h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.809 ns               ;
; N/A                                     ; 57.38 MHz ( period = 17.428 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.251 ns               ;
; N/A                                     ; 57.39 MHz ( period = 17.425 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_b1h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.316 ns               ;
; N/A                                     ; 57.39 MHz ( period = 17.424 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.250 ns               ;
; N/A                                     ; 57.40 MHz ( period = 17.422 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.817 ns               ;
; N/A                                     ; 57.40 MHz ( period = 17.422 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.817 ns               ;
; N/A                                     ; 57.41 MHz ( period = 17.419 ns )                    ; Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_91h2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.814 ns               ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                                            ;                                                                                                                                                                            ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                           ; To                                                                                                                                                                      ; From Clock     ; To Clock       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 162.00 MHz ( period = 6.173 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.916 ns                ;
; N/A                                     ; 162.10 MHz ( period = 6.169 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.913 ns                ;
; N/A                                     ; 162.15 MHz ( period = 6.167 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.911 ns                ;
; N/A                                     ; 162.47 MHz ( period = 6.155 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.901 ns                ;
; N/A                                     ; 162.52 MHz ( period = 6.153 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.894 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.48 MHz ( period = 6.043 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 166.39 MHz ( period = 6.010 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.797 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 170.56 MHz ( period = 5.863 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.650 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.518 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.64 MHz ( period = 5.726 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.513 ns                ;
; N/A                                     ; 174.73 MHz ( period = 5.723 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.469 ns                ;
; N/A                                     ; 175.56 MHz ( period = 5.696 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.457 ns                ;
; N/A                                     ; 175.59 MHz ( period = 5.695 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.437 ns                ;
; N/A                                     ; 175.69 MHz ( period = 5.692 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.454 ns                ;
; N/A                                     ; 175.75 MHz ( period = 5.690 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.452 ns                ;
; N/A                                     ; 176.12 MHz ( period = 5.678 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.442 ns                ;
; N/A                                     ; 176.18 MHz ( period = 5.676 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.435 ns                ;
; N/A                                     ; 176.62 MHz ( period = 5.662 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z              ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.428 ns                ;
; N/A                                     ; 176.74 MHz ( period = 5.658 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z              ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.425 ns                ;
; N/A                                     ; 176.80 MHz ( period = 5.656 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z              ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.423 ns                ;
; N/A                                     ; 177.18 MHz ( period = 5.644 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z              ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.413 ns                ;
; N/A                                     ; 177.24 MHz ( period = 5.642 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z              ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.406 ns                ;
; N/A                                     ; 178.95 MHz ( period = 5.588 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.378 ns                ;
; N/A                                     ; 178.95 MHz ( period = 5.588 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.378 ns                ;
; N/A                                     ; 178.95 MHz ( period = 5.588 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.378 ns                ;
; N/A                                     ; 178.95 MHz ( period = 5.588 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.378 ns                ;
; N/A                                     ; 178.95 MHz ( period = 5.588 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.378 ns                ;
; N/A                                     ; 178.95 MHz ( period = 5.588 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_11__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.378 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 179.28 MHz ( period = 5.578 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.368 ns                ;
; N/A                                     ; 180.02 MHz ( period = 5.555 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.345 ns                ;
; N/A                                     ; 180.02 MHz ( period = 5.555 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.345 ns                ;
; N/A                                     ; 180.02 MHz ( period = 5.555 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.345 ns                ;
; N/A                                     ; 180.02 MHz ( period = 5.555 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.345 ns                ;
; N/A                                     ; 180.02 MHz ( period = 5.555 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.345 ns                ;
; N/A                                     ; 180.02 MHz ( period = 5.555 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_11__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.345 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.08 MHz ( period = 5.553 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 180.18 MHz ( period = 5.550 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.313 ns                ;
; N/A                                     ; 180.31 MHz ( period = 5.546 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.310 ns                ;
; N/A                                     ; 180.38 MHz ( period = 5.544 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.308 ns                ;
; N/A                                     ; 180.77 MHz ( period = 5.532 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.298 ns                ;
; N/A                                     ; 180.83 MHz ( period = 5.530 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.291 ns                ;
; N/A                                     ; 181.26 MHz ( period = 5.517 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.274 ns                ;
; N/A                                     ; 181.26 MHz ( period = 5.517 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[1]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.274 ns                ;
; N/A                                     ; 181.26 MHz ( period = 5.517 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[3]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.274 ns                ;
; N/A                                     ; 181.26 MHz ( period = 5.517 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[5]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.274 ns                ;
; N/A                                     ; 181.26 MHz ( period = 5.517 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.274 ns                ;
; N/A                                     ; 181.42 MHz ( period = 5.512 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.278 ns                ;
; N/A                                     ; 181.55 MHz ( period = 5.508 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.275 ns                ;
; N/A                                     ; 181.62 MHz ( period = 5.506 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.273 ns                ;
; N/A                                     ; 182.02 MHz ( period = 5.494 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.263 ns                ;
; N/A                                     ; 182.05 MHz ( period = 5.493 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.259 ns                ;
; N/A                                     ; 182.08 MHz ( period = 5.492 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.256 ns                ;
; N/A                                     ; 182.18 MHz ( period = 5.489 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.256 ns                ;
; N/A                                     ; 182.25 MHz ( period = 5.487 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.254 ns                ;
; N/A                                     ; 182.65 MHz ( period = 5.475 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.244 ns                ;
; N/A                                     ; 182.72 MHz ( period = 5.473 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.237 ns                ;
; N/A                                     ; 183.55 MHz ( period = 5.448 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.212 ns                ;
; N/A                                     ; 183.69 MHz ( period = 5.444 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.209 ns                ;
; N/A                                     ; 183.76 MHz ( period = 5.442 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.207 ns                ;
; N/A                                     ; 184.13 MHz ( period = 5.431 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.172 ns                ;
; N/A                                     ; 184.16 MHz ( period = 5.430 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.197 ns                ;
; N/A                                     ; 184.23 MHz ( period = 5.428 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.190 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.30 MHz ( period = 5.426 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.216 ns                ;
; N/A                                     ; 184.91 MHz ( period = 5.408 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.198 ns                ;
; N/A                                     ; 184.91 MHz ( period = 5.408 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.198 ns                ;
; N/A                                     ; 184.91 MHz ( period = 5.408 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.198 ns                ;
; N/A                                     ; 184.91 MHz ( period = 5.408 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.198 ns                ;
; N/A                                     ; 184.91 MHz ( period = 5.408 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.198 ns                ;
; N/A                                     ; 184.91 MHz ( period = 5.408 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_11__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.198 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_19__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_18__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_20__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_16__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_14__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_13__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_24__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_22__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_25__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_21__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_9__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.178 ns                ;
; N/A                                     ; 185.87 MHz ( period = 5.380 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.146 ns                ;
; N/A                                     ; 186.01 MHz ( period = 5.376 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.143 ns                ;
; N/A                                     ; 186.08 MHz ( period = 5.374 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.141 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.39 MHz ( period = 5.365 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.155 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_19__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_18__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_20__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_16__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_14__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_13__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_24__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_22__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_25__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_21__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.46 MHz ( period = 5.363 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_9__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.50 MHz ( period = 5.362 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.131 ns                ;
; N/A                                     ; 186.57 MHz ( period = 5.360 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.124 ns                ;
; N/A                                     ; 188.79 MHz ( period = 5.297 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.059 ns                ;
; N/A                                     ; 189.72 MHz ( period = 5.271 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.061 ns                ;
; N/A                                     ; 189.72 MHz ( period = 5.271 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.061 ns                ;
; N/A                                     ; 189.72 MHz ( period = 5.271 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.061 ns                ;
; N/A                                     ; 189.72 MHz ( period = 5.271 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.061 ns                ;
; N/A                                     ; 189.72 MHz ( period = 5.271 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.061 ns                ;
; N/A                                     ; 189.72 MHz ( period = 5.271 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_11__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.061 ns                ;
; N/A                                     ; 189.75 MHz ( period = 5.270 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.060 ns                ;
; N/A                                     ; 189.75 MHz ( period = 5.270 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.060 ns                ;
; N/A                                     ; 189.75 MHz ( period = 5.270 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.060 ns                ;
; N/A                                     ; 189.75 MHz ( period = 5.270 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.060 ns                ;
; N/A                                     ; 189.79 MHz ( period = 5.269 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[12]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.031 ns                ;
; N/A                                     ; 189.79 MHz ( period = 5.269 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[13]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.031 ns                ;
; N/A                                     ; 189.79 MHz ( period = 5.269 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[14]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.031 ns                ;
; N/A                                     ; 189.79 MHz ( period = 5.269 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[15]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.031 ns                ;
; N/A                                     ; 189.79 MHz ( period = 5.269 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[16]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.031 ns                ;
; N/A                                     ; 189.79 MHz ( period = 5.269 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[17]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.031 ns                ;
; N/A                                     ; 189.79 MHz ( period = 5.269 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[18]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.031 ns                ;
; N/A                                     ; 189.79 MHz ( period = 5.269 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[19]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.031 ns                ;
; N/A                                     ; 189.90 MHz ( period = 5.266 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 189.90 MHz ( period = 5.266 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[20]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 189.90 MHz ( period = 5.266 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[21]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 189.90 MHz ( period = 5.266 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[30]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 190.01 MHz ( period = 5.263 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z              ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.030 ns                ;
; N/A                                     ; 190.51 MHz ( period = 5.249 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg_0                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.007 ns                ;
; N/A                                     ; 190.51 MHz ( period = 5.249 ns )                    ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                 ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[1]                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.007 ns                ;
; N/A                                     ; 190.62 MHz ( period = 5.246 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.010 ns                ;
; N/A                                     ; 190.95 MHz ( period = 5.237 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 190.95 MHz ( period = 5.237 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 190.95 MHz ( period = 5.237 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 190.95 MHz ( period = 5.237 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 5.027 ns                ;
; N/A                                     ; 191.64 MHz ( period = 5.218 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 4.978 ns                ;
; N/A                                     ; 191.72 MHz ( period = 5.216 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_25__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 4.998 ns                ;
; N/A                                     ; 191.72 MHz ( period = 5.216 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_21__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 4.998 ns                ;
; N/A                                     ; 191.72 MHz ( period = 5.216 ns )                    ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 4.998 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                                ;                                                                                                                                                                         ;                ;                ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'ETH_TXC'                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                               ; To                                                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 86.72 MHz ( period = 11.532 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 11.293 ns               ;
; N/A                                     ; 86.84 MHz ( period = 11.516 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 11.277 ns               ;
; N/A                                     ; 87.63 MHz ( period = 11.412 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 11.173 ns               ;
; N/A                                     ; 87.65 MHz ( period = 11.409 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 11.166 ns               ;
; N/A                                     ; 87.75 MHz ( period = 11.396 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 11.157 ns               ;
; N/A                                     ; 88.58 MHz ( period = 11.289 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 11.046 ns               ;
; N/A                                     ; 89.12 MHz ( period = 11.221 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.982 ns               ;
; N/A                                     ; 89.49 MHz ( period = 11.175 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.932 ns               ;
; N/A                                     ; 89.61 MHz ( period = 11.160 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.920 ns               ;
; N/A                                     ; 89.73 MHz ( period = 11.144 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.904 ns               ;
; N/A                                     ; 89.94 MHz ( period = 11.119 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.879 ns               ;
; N/A                                     ; 90.07 MHz ( period = 11.103 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.863 ns               ;
; N/A                                     ; 90.08 MHz ( period = 11.101 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.862 ns               ;
; N/A                                     ; 90.45 MHz ( period = 11.056 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.813 ns               ;
; N/A                                     ; 90.46 MHz ( period = 11.055 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.812 ns               ;
; N/A                                     ; 90.60 MHz ( period = 11.037 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.793 ns               ;
; N/A                                     ; 90.79 MHz ( period = 11.015 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.775 ns               ;
; N/A                                     ; 90.92 MHz ( period = 10.999 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.759 ns               ;
; N/A                                     ; 90.94 MHz ( period = 10.996 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.752 ns               ;
; N/A                                     ; 90.95 MHz ( period = 10.995 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.751 ns               ;
; N/A                                     ; 91.44 MHz ( period = 10.936 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.693 ns               ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.660 ns               ;
; N/A                                     ; 91.81 MHz ( period = 10.892 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.648 ns               ;
; N/A                                     ; 91.84 MHz ( period = 10.889 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.646 ns               ;
; N/A                                     ; 91.88 MHz ( period = 10.884 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.644 ns               ;
; N/A                                     ; 91.95 MHz ( period = 10.875 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.631 ns               ;
; N/A                                     ; 92.00 MHz ( period = 10.870 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.630 ns               ;
; N/A                                     ; 92.13 MHz ( period = 10.854 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.614 ns               ;
; N/A                                     ; 92.16 MHz ( period = 10.851 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.608 ns               ;
; N/A                                     ; 92.17 MHz ( period = 10.849 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.609 ns               ;
; N/A                                     ; 92.22 MHz ( period = 10.844 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.604 ns               ;
; N/A                                     ; 92.32 MHz ( period = 10.832 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.592 ns               ;
; N/A                                     ; 92.46 MHz ( period = 10.816 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.576 ns               ;
; N/A                                     ; 92.52 MHz ( period = 10.808 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.568 ns               ;
; N/A                                     ; 92.57 MHz ( period = 10.803 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.559 ns               ;
; N/A                                     ; 92.58 MHz ( period = 10.802 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.562 ns               ;
; N/A                                     ; 92.79 MHz ( period = 10.777 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.533 ns               ;
; N/A                                     ; 92.86 MHz ( period = 10.769 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.526 ns               ;
; N/A                                     ; 92.92 MHz ( period = 10.762 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.518 ns               ;
; N/A                                     ; 92.99 MHz ( period = 10.754 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.514 ns               ;
; N/A                                     ; 93.05 MHz ( period = 10.747 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.503 ns               ;
; N/A                                     ; 93.13 MHz ( period = 10.738 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.498 ns               ;
; N/A                                     ; 93.18 MHz ( period = 10.732 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.493 ns               ;
; N/A                                     ; 93.19 MHz ( period = 10.731 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.488 ns               ;
; N/A                                     ; 93.25 MHz ( period = 10.724 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.484 ns               ;
; N/A                                     ; 93.38 MHz ( period = 10.709 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.465 ns               ;
; N/A                                     ; 93.42 MHz ( period = 10.704 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.464 ns               ;
; N/A                                     ; 93.60 MHz ( period = 10.684 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.440 ns               ;
; N/A                                     ; 93.62 MHz ( period = 10.682 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.442 ns               ;
; N/A                                     ; 93.77 MHz ( period = 10.664 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.425 ns               ;
; N/A                                     ; 93.83 MHz ( period = 10.658 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.414 ns               ;
; N/A                                     ; 93.96 MHz ( period = 10.643 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.399 ns               ;
; N/A                                     ; 94.06 MHz ( period = 10.631 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.387 ns               ;
; N/A                                     ; 94.08 MHz ( period = 10.629 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.389 ns               ;
; N/A                                     ; 94.14 MHz ( period = 10.623 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.378 ns               ;
; N/A                                     ; 94.23 MHz ( period = 10.612 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.373 ns               ;
; N/A                                     ; 94.33 MHz ( period = 10.601 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.365 ns               ;
; N/A                                     ; 94.44 MHz ( period = 10.589 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.349 ns               ;
; N/A                                     ; 94.47 MHz ( period = 10.585 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.349 ns               ;
; N/A                                     ; 94.50 MHz ( period = 10.582 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.337 ns               ;
; N/A                                     ; 94.52 MHz ( period = 10.580 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.337 ns               ;
; N/A                                     ; 94.60 MHz ( period = 10.571 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.328 ns               ;
; N/A                                     ; 94.71 MHz ( period = 10.559 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.319 ns               ;
; N/A                                     ; 94.76 MHz ( period = 10.553 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.317 ns               ;
; N/A                                     ; 94.84 MHz ( period = 10.544 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.305 ns               ;
; N/A                                     ; 94.85 MHz ( period = 10.543 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.299 ns               ;
; N/A                                     ; 94.89 MHz ( period = 10.539 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.295 ns               ;
; N/A                                     ; 94.90 MHz ( period = 10.537 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.301 ns               ;
; N/A                                     ; 94.96 MHz ( period = 10.531 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.295 ns               ;
; N/A                                     ; 95.05 MHz ( period = 10.521 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.281 ns               ;
; N/A                                     ; 95.08 MHz ( period = 10.517 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.273 ns               ;
; N/A                                     ; 95.10 MHz ( period = 10.515 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.279 ns               ;
; N/A                                     ; 95.12 MHz ( period = 10.513 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.269 ns               ;
; N/A                                     ; 95.16 MHz ( period = 10.509 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.269 ns               ;
; N/A                                     ; 95.24 MHz ( period = 10.500 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.261 ns               ;
; N/A                                     ; 95.39 MHz ( period = 10.483 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[7] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.239 ns               ;
; N/A                                     ; 95.43 MHz ( period = 10.479 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.235 ns               ;
; N/A                                     ; 95.44 MHz ( period = 10.478 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.238 ns               ;
; N/A                                     ; 95.44 MHz ( period = 10.478 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.233 ns               ;
; N/A                                     ; 95.46 MHz ( period = 10.476 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.232 ns               ;
; N/A                                     ; 95.47 MHz ( period = 10.475 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.231 ns               ;
; N/A                                     ; 95.49 MHz ( period = 10.472 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.231 ns               ;
; N/A                                     ; 95.60 MHz ( period = 10.460 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.217 ns               ;
; N/A                                     ; 95.68 MHz ( period = 10.452 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.216 ns               ;
; N/A                                     ; 95.68 MHz ( period = 10.451 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.208 ns               ;
; N/A                                     ; 95.76 MHz ( period = 10.443 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.203 ns               ;
; N/A                                     ; 95.80 MHz ( period = 10.438 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.194 ns               ;
; N/A                                     ; 95.82 MHz ( period = 10.436 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.200 ns               ;
; N/A                                     ; 95.87 MHz ( period = 10.431 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.190 ns               ;
; N/A                                     ; 95.88 MHz ( period = 10.430 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.190 ns               ;
; N/A                                     ; 95.88 MHz ( period = 10.430 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.189 ns               ;
; N/A                                     ; 95.93 MHz ( period = 10.424 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.180 ns               ;
; N/A                                     ; 96.08 MHz ( period = 10.408 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.168 ns               ;
; N/A                                     ; 96.09 MHz ( period = 10.407 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.171 ns               ;
; N/A                                     ; 96.18 MHz ( period = 10.397 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.153 ns               ;
; N/A                                     ; 96.21 MHz ( period = 10.394 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.150 ns               ;
; N/A                                     ; 96.24 MHz ( period = 10.391 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.155 ns               ;
; N/A                                     ; 96.26 MHz ( period = 10.389 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.148 ns               ;
; N/A                                     ; 96.26 MHz ( period = 10.388 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.149 ns               ;
; N/A                                     ; 96.34 MHz ( period = 10.380 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.141 ns               ;
; N/A                                     ; 96.41 MHz ( period = 10.372 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.128 ns               ;
; N/A                                     ; 96.50 MHz ( period = 10.363 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[7] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.119 ns               ;
; N/A                                     ; 96.50 MHz ( period = 10.363 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.118 ns               ;
; N/A                                     ; 96.53 MHz ( period = 10.360 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.120 ns               ;
; N/A                                     ; 96.56 MHz ( period = 10.356 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.112 ns               ;
; N/A                                     ; 96.77 MHz ( period = 10.334 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.090 ns               ;
; N/A                                     ; 96.78 MHz ( period = 10.333 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.088 ns               ;
; N/A                                     ; 96.81 MHz ( period = 10.329 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.089 ns               ;
; N/A                                     ; 96.83 MHz ( period = 10.327 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.086 ns               ;
; N/A                                     ; 96.91 MHz ( period = 10.319 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.079 ns               ;
; N/A                                     ; 97.03 MHz ( period = 10.306 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.070 ns               ;
; N/A                                     ; 97.13 MHz ( period = 10.295 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.050 ns               ;
; N/A                                     ; 97.16 MHz ( period = 10.292 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.052 ns               ;
; N/A                                     ; 97.18 MHz ( period = 10.290 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.054 ns               ;
; N/A                                     ; 97.18 MHz ( period = 10.290 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.054 ns               ;
; N/A                                     ; 97.23 MHz ( period = 10.285 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.044 ns               ;
; N/A                                     ; 97.24 MHz ( period = 10.284 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.044 ns               ;
; N/A                                     ; 97.30 MHz ( period = 10.278 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.034 ns               ;
; N/A                                     ; 97.39 MHz ( period = 10.268 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.029 ns               ;
; N/A                                     ; 97.49 MHz ( period = 10.257 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.013 ns               ;
; N/A                                     ; 97.49 MHz ( period = 10.257 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.016 ns               ;
; N/A                                     ; 97.55 MHz ( period = 10.251 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.011 ns               ;
; N/A                                     ; 97.62 MHz ( period = 10.244 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.004 ns               ;
; N/A                                     ; 97.64 MHz ( period = 10.242 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 10.006 ns               ;
; N/A                                     ; 97.78 MHz ( period = 10.227 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.983 ns                ;
; N/A                                     ; 97.85 MHz ( period = 10.220 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.984 ns                ;
; N/A                                     ; 97.86 MHz ( period = 10.219 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.975 ns                ;
; N/A                                     ; 97.88 MHz ( period = 10.217 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.972 ns                ;
; N/A                                     ; 97.89 MHz ( period = 10.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.975 ns                ;
; N/A                                     ; 97.90 MHz ( period = 10.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.975 ns                ;
; N/A                                     ; 97.92 MHz ( period = 10.212 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.971 ns                ;
; N/A                                     ; 97.96 MHz ( period = 10.208 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.964 ns                ;
; N/A                                     ; 98.05 MHz ( period = 10.199 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.955 ns                ;
; N/A                                     ; 98.08 MHz ( period = 10.196 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.956 ns                ;
; N/A                                     ; 98.15 MHz ( period = 10.189 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.945 ns                ;
; N/A                                     ; 98.15 MHz ( period = 10.189 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.945 ns                ;
; N/A                                     ; 98.20 MHz ( period = 10.183 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.943 ns                ;
; N/A                                     ; 98.21 MHz ( period = 10.182 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.941 ns                ;
; N/A                                     ; 98.29 MHz ( period = 10.174 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.934 ns                ;
; N/A                                     ; 98.33 MHz ( period = 10.170 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.929 ns                ;
; N/A                                     ; 98.36 MHz ( period = 10.167 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.923 ns                ;
; N/A                                     ; 98.44 MHz ( period = 10.158 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.914 ns                ;
; N/A                                     ; 98.51 MHz ( period = 10.151 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.907 ns                ;
; N/A                                     ; 98.55 MHz ( period = 10.147 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.907 ns                ;
; N/A                                     ; 98.58 MHz ( period = 10.144 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.903 ns                ;
; N/A                                     ; 98.61 MHz ( period = 10.141 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.905 ns                ;
; N/A                                     ; 98.62 MHz ( period = 10.140 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.899 ns                ;
; N/A                                     ; 98.74 MHz ( period = 10.128 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.888 ns                ;
; N/A                                     ; 98.77 MHz ( period = 10.125 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.885 ns                ;
; N/A                                     ; 98.89 MHz ( period = 10.112 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.871 ns                ;
; N/A                                     ; 98.90 MHz ( period = 10.111 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.867 ns                ;
; N/A                                     ; 98.90 MHz ( period = 10.111 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[7] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.866 ns                ;
; N/A                                     ; 98.99 MHz ( period = 10.102 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.861 ns                ;
; N/A                                     ; 99.01 MHz ( period = 10.100 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.860 ns                ;
; N/A                                     ; 99.05 MHz ( period = 10.096 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.860 ns                ;
; N/A                                     ; 99.06 MHz ( period = 10.095 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.855 ns                ;
; N/A                                     ; 99.14 MHz ( period = 10.087 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.847 ns                ;
; N/A                                     ; 99.24 MHz ( period = 10.077 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.837 ns                ;
; N/A                                     ; 99.28 MHz ( period = 10.073 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.829 ns                ;
; N/A                                     ; 99.30 MHz ( period = 10.070 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.830 ns                ;
; N/A                                     ; 99.30 MHz ( period = 10.070 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[7] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.825 ns                ;
; N/A                                     ; 99.34 MHz ( period = 10.066 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.825 ns                ;
; N/A                                     ; 99.36 MHz ( period = 10.064 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.823 ns                ;
; N/A                                     ; 99.37 MHz ( period = 10.063 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.819 ns                ;
; N/A                                     ; 99.37 MHz ( period = 10.063 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.819 ns                ;
; N/A                                     ; 99.45 MHz ( period = 10.055 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.815 ns                ;
; N/A                                     ; 99.46 MHz ( period = 10.054 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.810 ns                ;
; N/A                                     ; 99.50 MHz ( period = 10.050 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.810 ns                ;
; N/A                                     ; 99.68 MHz ( period = 10.032 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.792 ns                ;
; N/A                                     ; 99.68 MHz ( period = 10.032 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.792 ns                ;
; N/A                                     ; 99.76 MHz ( period = 10.024 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.783 ns                ;
; N/A                                     ; 99.84 MHz ( period = 10.016 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.775 ns                ;
; N/A                                     ; 99.84 MHz ( period = 10.016 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.776 ns                ;
; N/A                                     ; 99.98 MHz ( period = 10.002 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.762 ns                ;
; N/A                                     ; 100.03 MHz ( period = 9.997 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.756 ns                ;
; N/A                                     ; 100.05 MHz ( period = 9.995 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[13] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.759 ns                ;
; N/A                                     ; 100.06 MHz ( period = 9.994 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.753 ns                ;
; N/A                                     ; 100.17 MHz ( period = 9.983 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.743 ns                ;
; N/A                                     ; 100.24 MHz ( period = 9.976 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.736 ns                ;
; N/A                                     ; 100.25 MHz ( period = 9.975 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[15] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.735 ns                ;
; N/A                                     ; 100.33 MHz ( period = 9.967 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.726 ns                ;
; N/A                                     ; 100.34 MHz ( period = 9.966 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[7] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[11] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.721 ns                ;
; N/A                                     ; 100.36 MHz ( period = 9.964 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.724 ns                ;
; N/A                                     ; 100.42 MHz ( period = 9.958 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.718 ns                ;
; N/A                                     ; 100.46 MHz ( period = 9.954 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.714 ns                ;
; N/A                                     ; 100.51 MHz ( period = 9.949 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[2]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.709 ns                ;
; N/A                                     ; 100.52 MHz ( period = 9.948 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.704 ns                ;
; N/A                                     ; 100.57 MHz ( period = 9.943 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.699 ns                ;
; N/A                                     ; 100.61 MHz ( period = 9.939 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.695 ns                ;
; N/A                                     ; 100.69 MHz ( period = 9.931 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.691 ns                ;
; N/A                                     ; 100.72 MHz ( period = 9.929 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.688 ns                ;
; N/A                                     ; 100.81 MHz ( period = 9.920 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.680 ns                ;
; N/A                                     ; 100.83 MHz ( period = 9.918 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.674 ns                ;
; N/A                                     ; 100.86 MHz ( period = 9.915 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[5] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[4]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.674 ns                ;
; N/A                                     ; 100.88 MHz ( period = 9.913 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[16] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.676 ns                ;
; N/A                                     ; 100.91 MHz ( period = 9.910 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.670 ns                ;
; N/A                                     ; 100.92 MHz ( period = 9.909 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.665 ns                ;
; N/A                                     ; 101.13 MHz ( period = 9.888 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[7]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.648 ns                ;
; N/A                                     ; 101.15 MHz ( period = 9.886 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[12] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[10] ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.646 ns                ;
; N/A                                     ; 101.21 MHz ( period = 9.880 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[8]  ; ETH_TXC    ; ETH_TXC  ; None                        ; None                      ; 9.636 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                    ;                                                                    ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'ETH_RXC'                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                               ; To                                                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 117.70 MHz ( period = 8.496 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok         ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 8.246 ns                ;
; N/A                                     ; 121.39 MHz ( period = 8.238 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 7.988 ns                ;
; N/A                                     ; 127.50 MHz ( period = 7.843 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 7.593 ns                ;
; N/A                                     ; 132.91 MHz ( period = 7.524 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 7.274 ns                ;
; N/A                                     ; 135.81 MHz ( period = 7.363 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 7.113 ns                ;
; N/A                                     ; 136.31 MHz ( period = 7.336 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 7.086 ns                ;
; N/A                                     ; 136.86 MHz ( period = 7.307 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok         ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 7.057 ns                ;
; N/A                                     ; 137.74 MHz ( period = 7.260 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 7.010 ns                ;
; N/A                                     ; 139.31 MHz ( period = 7.178 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.928 ns                ;
; N/A                                     ; 140.27 MHz ( period = 7.129 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.879 ns                ;
; N/A                                     ; 140.29 MHz ( period = 7.128 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok         ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.878 ns                ;
; N/A                                     ; 140.71 MHz ( period = 7.107 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.857 ns                ;
; N/A                                     ; 142.01 MHz ( period = 7.042 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.792 ns                ;
; N/A                                     ; 142.11 MHz ( period = 7.037 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.787 ns                ;
; N/A                                     ; 142.35 MHz ( period = 7.025 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[11] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.775 ns                ;
; N/A                                     ; 144.32 MHz ( period = 6.929 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok         ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.689 ns                ;
; N/A                                     ; 145.26 MHz ( period = 6.884 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.634 ns                ;
; N/A                                     ; 146.24 MHz ( period = 6.838 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.588 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[9]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[11] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[1]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[0]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[8]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[10] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[7]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[15] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[3]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[12] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[5]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[13] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[6]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[14] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[4]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 146.58 MHz ( period = 6.822 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[2]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.585 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[24] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[31] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[17] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[25] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[28] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[29] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[30] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[26] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[16] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[27] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[20] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[22] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[23] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[21] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[18] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.12 MHz ( period = 6.797 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[19] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 147.75 MHz ( period = 6.768 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.518 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.399 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.408 ns                ;
; N/A                                     ; 151.01 MHz ( period = 6.622 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.372 ns                ;
; N/A                                     ; 152.11 MHz ( period = 6.574 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.324 ns                ;
; N/A                                     ; 152.46 MHz ( period = 6.559 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.309 ns                ;
; N/A                                     ; 154.34 MHz ( period = 6.479 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok         ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.229 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[9]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[11] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[1]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[0]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[8]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[10] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[7]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[15] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[3]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[12] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[5]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[13] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[6]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[14] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[4]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[2]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.214 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[9]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[11] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[1]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[0]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[8]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[10] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[7]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[15] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[3]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[12] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[5]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[13] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[6]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[14] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[4]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.18 MHz ( period = 6.444 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[2]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.211 ns                ;
; N/A                                     ; 155.33 MHz ( period = 6.438 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.188 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[24] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[31] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[17] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[25] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[28] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[29] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[30] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[26] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[16] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[27] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[20] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[22] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[23] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[21] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[18] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.71 MHz ( period = 6.422 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[19] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.185 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[24] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[31] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[17] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[25] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[28] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[29] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[30] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[26] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[16] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[27] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[20] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[22] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[23] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[21] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[18] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 155.79 MHz ( period = 6.419 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[19] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.182 ns                ;
; N/A                                     ; 157.18 MHz ( period = 6.362 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error       ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.112 ns                ;
; N/A                                     ; 158.03 MHz ( period = 6.328 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[10] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.078 ns                ;
; N/A                                     ; 158.45 MHz ( period = 6.311 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[11] ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.061 ns                ;
; N/A                                     ; 159.39 MHz ( period = 6.274 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 159.46 MHz ( period = 6.271 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.034 ns                ;
; N/A                                     ; 159.80 MHz ( period = 6.258 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[0]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.012 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[9]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[11] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[1]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[0]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[8]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[10] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[7]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[15] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[3]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[12] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[5]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[13] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[6]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[14] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[4]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.23 MHz ( period = 6.241 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[2]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.008 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[9]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[11] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[1]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[0]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[8]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[10] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[7]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[15] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[3]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[12] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[5]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[13] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[6]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[14] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[4]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.26 MHz ( period = 6.240 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[2]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 6.007 ns                ;
; N/A                                     ; 160.72 MHz ( period = 6.222 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|broadcast_ok   ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[24] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[31] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[17] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[25] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[28] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[29] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[30] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[26] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[16] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[27] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[20] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[22] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[23] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[21] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[18] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.88 MHz ( period = 6.216 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[19] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.979 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[24] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[31] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[17] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[25] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[28] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[29] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[30] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[26] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[16] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok         ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]    ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.975 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[27] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[20] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[22] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[23] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[21] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[18] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 160.90 MHz ( period = 6.215 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[19] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.978 ns                ;
; N/A                                     ; 161.55 MHz ( period = 6.190 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[12] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.944 ns                ;
; N/A                                     ; 161.55 MHz ( period = 6.190 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[5]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.944 ns                ;
; N/A                                     ; 161.55 MHz ( period = 6.190 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[13] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.944 ns                ;
; N/A                                     ; 161.55 MHz ( period = 6.190 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[6]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.944 ns                ;
; N/A                                     ; 161.55 MHz ( period = 6.190 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[14] ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.944 ns                ;
; N/A                                     ; 161.55 MHz ( period = 6.190 ns )                    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_errors[4]  ; ETH_RXC    ; ETH_RXC  ; None                        ; None                      ; 5.944 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                    ;                                                                    ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+-------------------------------------------------------------------+----------+
; Slack                                   ; Required tsu                                        ; Actual tsu ; From        ; To                                                                ; To Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+-------------------------------------------------------------------+----------+
; N/A                                     ; None                                                ; 13.438 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 13.365 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 13.292 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 13.219 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 13.146 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 13.073 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 13.000 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.927 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.623 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.550 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.477 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.462 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.437 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.404 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.389 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.364 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.331 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.331 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.322 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.316 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.291 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.258 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.258 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.249 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.243 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.240 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[0]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_10 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_9  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_12 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_11 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_15 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_13 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_14 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.226 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_17 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.218 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.185 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.185 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.176 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.170 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.145 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.112 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.112 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.103 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.097 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.072 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.057 ns  ; SRAM0_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.039 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.030 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 12.024 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.999 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.984 ns  ; SRAM0_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.966 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.957 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.951 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.926 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.911 ns  ; SRAM0_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.905 ns  ; SRAM0_D[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.893 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.884 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.861 ns  ; SRAM0_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.838 ns  ; SRAM0_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.832 ns  ; SRAM0_D[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.820 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.811 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.790 ns  ; SRAM0_D[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.788 ns  ; SRAM0_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.765 ns  ; SRAM0_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.759 ns  ; SRAM0_D[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.746 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[4]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.746 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[3]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.736 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[1]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.736 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[10] ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.736 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[9]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.736 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[5]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.736 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[6]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.736 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[2]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.733 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[8]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.733 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[7]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.733 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[0]  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.717 ns  ; SRAM0_D[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.715 ns  ; SRAM0_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.714 ns  ; SRAM1_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.692 ns  ; SRAM0_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.686 ns  ; SRAM0_D[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_8  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_7  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_0  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_2  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_6  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_5  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_4  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_1  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.670 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_3  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.644 ns  ; SRAM0_D[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.642 ns  ; SRAM0_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.641 ns  ; SRAM1_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.619 ns  ; SRAM0_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.613 ns  ; SRAM0_D[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_10 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_9  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_12 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_11 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_15 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_13 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_14 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.596 ns  ; TEST_BUTTON ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_17 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.588 ns  ; SRAM1_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.571 ns  ; SRAM0_D[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.569 ns  ; SRAM0_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.568 ns  ; SRAM1_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.546 ns  ; SRAM0_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.540 ns  ; SRAM0_D[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.528 ns  ; SRAM1_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.515 ns  ; SRAM1_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.498 ns  ; SRAM0_D[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.496 ns  ; SRAM0_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.495 ns  ; SRAM1_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.467 ns  ; SRAM0_D[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.455 ns  ; SRAM1_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.442 ns  ; SRAM1_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.425 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[0]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.425 ns  ; SRAM0_D[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.423 ns  ; SRAM0_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.422 ns  ; SRAM1_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_10 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_9  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_12 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_11 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_15 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_13 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_14 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.411 ns  ; SRAM0_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_17 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.394 ns  ; SRAM0_D[8]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.382 ns  ; SRAM1_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.369 ns  ; SRAM1_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.352 ns  ; SRAM0_D[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.350 ns  ; SRAM0_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.349 ns  ; SRAM1_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.348 ns  ; SRAM1_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.309 ns  ; SRAM1_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.296 ns  ; SRAM1_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.285 ns  ; SRAM1_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.279 ns  ; SRAM0_D[9]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.276 ns  ; SRAM1_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.275 ns  ; SRAM1_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.264 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[0]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.260 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_in_6      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.260 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_in_5      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.260 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_in_4      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.260 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_in_0      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.260 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_in_3      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.260 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_in_1      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.260 ns  ; SRAM0_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_in_2      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_10 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_9  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_12 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_11 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_15 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_13 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_14 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.250 ns  ; SRAM0_D[3]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_17 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.239 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[0]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.236 ns  ; SRAM1_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[4]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_10 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_9  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_12 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_11 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_15 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_13 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_14 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.225 ns  ; SRAM0_D[0]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_17 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.223 ns  ; SRAM1_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.212 ns  ; SRAM1_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[7]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.203 ns  ; SRAM1_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.202 ns  ; SRAM1_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.163 ns  ; SRAM1_D[5]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[3]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.150 ns  ; SRAM1_D[6]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[2]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.139 ns  ; SRAM1_D[7]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[6]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.133 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[0]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.129 ns  ; SRAM1_D[1]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[5]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.124 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[0]        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_10 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_9  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_12 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_11 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_15 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_13 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_14 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.119 ns  ; SRAM0_D[2]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_17 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.110 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_10 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.110 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_9  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.110 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_12 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.110 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 11.110 ns  ; SRAM0_D[4]  ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_11 ; CLK_BRD  ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;             ;                                                                   ;          ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+-------------------------------------------------------------------+----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------+-------------+------------+
; Slack                                   ; Required tco                                        ; Actual tco ; From                                                                                                    ; To          ; From Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------+-------------+------------+
; N/A                                     ; None                                                ; 20.875 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.841 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.819 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.754 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.751 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.726 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.723 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.720 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.717 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.698 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.688 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.630 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.618 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.605 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.602 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.596 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.584 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.567 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.562 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.561 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.527 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.505 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.505 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.494 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.486 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.482 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.469 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.466 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.460 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.437 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.431 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.412 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.409 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.403 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.384 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.379 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.374 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.374 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.365 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.365 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.361 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.361 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.357 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.340 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.318 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.258 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.250 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.248 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.244 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.240 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.240 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.236 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.229 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.225 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.225 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.222 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.216 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.216 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2     ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.201 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.191 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.187 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.172 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.168 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.167 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead  ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.122 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.119 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.108 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.108 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.104 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.100 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.095 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2     ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.080 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.074 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.065 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.052 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.051 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.047 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.046 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead  ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.043 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.006 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.004 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.003 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.986 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.985 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.984 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.983 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.981 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.980 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.972 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.969 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.959 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.959 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.956 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.952 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.950 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.950 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.947 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.946 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.944 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.930 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.926 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.924 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.921 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.910 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead  ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.902 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2     ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.887 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.882 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.879 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.878 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.864 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.862 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.860 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.857 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.856 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.856 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.854 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.854 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.853 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead  ; SRAM0_A[14] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.851 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.848 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.845 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.837 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.834 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.831 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.828 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.828 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.822 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.819 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.816 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.813 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.799 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.793 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.779 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.757 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.739 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.738 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.737 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.719 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.715 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.715 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.703 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.700 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.689 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.681 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.666 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead  ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.664 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.661 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.655 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.636 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.633 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.626 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.617 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.616 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.614 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.613 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.613 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.612 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.610 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.610 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.598 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.597 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.594 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.593 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.591 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.590 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.588 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8     ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.587 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0 ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.585 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6     ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.579 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7     ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.550 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1 ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.548 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.514 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.510 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.507 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.506 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM1_A[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.496 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.493 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.492 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.492 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.490 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.489 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.488 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.485 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM1_A[13] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.484 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1     ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.476 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.473 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.472 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM1_A[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.472 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.470 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10    ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.468 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM0_A[0]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.466 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9     ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.462 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4 ; SRAM0_OE    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.456 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3     ; SRAM1_A[1]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.450 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5 ; SRAM1_A[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.449 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2     ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.443 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3 ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.434 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.424 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5     ; SRAM0_D[12] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.424 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0     ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.422 ns  ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2 ; SRAM1_A[1]  ; CLK_BRD    ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                                         ;             ;            ;
+-----------------------------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------+-------------+------------+


+--------------------------------------------------------------------------+
; tpd                                                                      ;
+-------+-------------------+-----------------+-------------+--------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From        ; To           ;
+-------+-------------------+-----------------+-------------+--------------+
; N/A   ; None              ; 16.212 ns       ; TEST_BUTTON ; ETH_RESETB_E ;
+-------+-------------------+-----------------+-------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Minimum Slack                           ; Required th                                         ; Actual th ; From           ; To                                                                                                                                                                              ; To Clock       ;
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; N/A                                     ; None                                                ; 0.777 ns  ; ETH_MDIO       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[0]                                                                                                                ; CLK_REF        ;
; N/A                                     ; None                                                ; -0.183 ns ; ETH_RXD[1]     ; EMAC32:U_Unique_MAC_System_EMAC|Memory_M2_EMAC:M2_EMAC|altsyncram:altsyncram_component|altsyncram_9q22:auto_generated|ram_block1a0~porta_datain_reg0                            ; ETH_RXC        ;
; N/A                                     ; None                                                ; -0.436 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|Memory_M2_EMAC:M2_EMAC|altsyncram:altsyncram_component|altsyncram_9q22:auto_generated|ram_block1a0~porta_datain_reg0                            ; ETH_RXC        ;
; N/A                                     ; None                                                ; -0.819 ns ; ETH_RXD[3]     ; EMAC32:U_Unique_MAC_System_EMAC|Memory_M2_EMAC:M2_EMAC|altsyncram:altsyncram_component|altsyncram_9q22:auto_generated|ram_block1a2~porta_datain_reg0                            ; ETH_RXC        ;
; N/A                                     ; None                                                ; -0.935 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|Memory_M2_EMAC:M2_EMAC|altsyncram:altsyncram_component|altsyncram_9q22:auto_generated|ram_block1a2~porta_datain_reg0                            ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.089 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[0]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.496 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[6]                                                                                                              ; ETH_TXC        ;
; N/A                                     ; None                                                ; -1.512 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|last_rxdv                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.615 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_overflow                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.651 ns ; ETH_RXD[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[0]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.753 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.765 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[2]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.826 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[3]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.830 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[2]                                                                                                              ; ETH_TXC        ;
; N/A                                     ; None                                                ; -1.838 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[4]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.887 ns ; ETH_RXD[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.889 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|broadcast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.899 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[5]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.911 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[6]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.916 ns ; ETH_RXD[1]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|broadcast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.972 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[7]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.979 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[19]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.984 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -1.987 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[25]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.000 ns ; SRAM1_D[0]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[16]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.020 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[3]                                                                                                              ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.045 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[9]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.057 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[10]                                                                                                              ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.073 ns ; ETH_RXD[1]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[28]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.087 ns ; ETH_RXD[1]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[18]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.093 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.097 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|multicast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.097 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|broadcast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.112 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[11]                                                                                                              ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.112 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[9]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.112 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[7]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.112 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[5]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.112 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[3]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.112 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.118 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[11]                                                                                                              ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.194 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.199 ns ; ETH_RXD[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|broadcast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.243 ns ; ETH_RXD[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[16]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.245 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_error                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.267 ns ; SRAM0_D[13]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[13]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.286 ns ; SRAM1_D[12]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[28]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.288 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[9]                                                                                                                  ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.312 ns ; SRAM1_D[12]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[28]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.314 ns ; ETH_RXD[1]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[12]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.319 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[2]                                                                                                                  ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.320 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[0]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.320 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[6]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.321 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[3]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.321 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[4]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.323 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[10]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.363 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[11]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.378 ns ; SRAM1_D[0]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[16]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.385 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[10]                                                                                                              ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.385 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[8]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.385 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[6]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.385 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[4]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.385 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[2]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.385 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[0]                                                                                                               ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.407 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[16]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.411 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_9                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_8                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_7                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_3                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_6                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_4                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_5                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_2                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_1                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.415 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|buf_out_0                                                                                                                   ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_8                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_9                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_7                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_6                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_5                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_4                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_3                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_2                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_1                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_0                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.418 ns ; SRAM1_D[11]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[27]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.420 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[31]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.422 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.441 ns ; ETH_RXD[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[0]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.442 ns ; SRAM0_D[0]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[0]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.457 ns ; SRAM1_D[11]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[27]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.458 ns ; SRAM0_D[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[3]                                                                                                                ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.466 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|broadcast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.466 ns ; SRAM0_D[3]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[3]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.471 ns ; ETH_COL        ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ip[7]                                                                                                              ; ETH_TXC        ;
; N/A                                     ; None                                                ; -2.471 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[2]                                                                                                                  ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.472 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[0]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.472 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[6]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.473 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[5]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.473 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[3]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.473 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[4]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.475 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[10]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.480 ns ; SRAM1_D[1]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[17]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.481 ns ; SRAM1_D[2]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[18]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.502 ns ; SRAM1_D[14]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[30]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.527 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|multicast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.550 ns ; SRAM1_D[13]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[29]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.559 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[16]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.563 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[20]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.568 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[26]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.570 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[17]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_8                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_9                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_7                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_6                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_5                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_4                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_3                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_2                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_1                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.571 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|buf_in_0                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.572 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[31]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.574 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[21]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.577 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[14]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.582 ns ; ETH_RXD[1]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|multicast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.605 ns ; JTAG_NEXUS_TMS ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[1]                                                                  ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.606 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[6]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.607 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[2]                                                                                                                  ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.607 ns ; JTAG_NEXUS_TMS ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                                  ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.609 ns ; JTAG_NEXUS_TMS ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[2]                                                                  ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.611 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[30]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.611 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[7]                                                                                                                  ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.611 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[13]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.611 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[22]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.611 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[26]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.611 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[14]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.614 ns ; SRAM1_D[10]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[26]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.623 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[29]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.625 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.638 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[0]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.641 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[3]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.656 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[29]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.657 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[11]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.658 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[1]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.659 ns ; SRAM0_D[13]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[13]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.671 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[23]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.672 ns ; JTAG_NEXUS_TDI ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.680 ns ; ETH_RXD[1]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|rx_state[1]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.687 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[18]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.687 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[24]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.687 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[12]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.687 ns ; SRAM0_D[7]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[7]                                                                                                                ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.689 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[5]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.690 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[28]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.694 ns ; SRAM0_D[7]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[7]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.695 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[8]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.698 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[15]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.707 ns ; SRAM1_D[4]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[20]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.723 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[30]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.723 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[7]                                                                                                                  ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.726 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[14]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.737 ns ; JTAG_NEXUS_TDI ; TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.744 ns ; SRAM0_D[14]    ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[14]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.747 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[25]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.752 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[27]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.755 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[19]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.760 ns ; ETH_RXER       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[9]                                                                                                                  ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.771 ns ; SRAM0_D[1]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[1]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.780 ns ; SRAM0_D[10]    ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]                                                                                                                      ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.785 ns ; SRAM0_D[6]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[6]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.794 ns ; SRAM0_D[3]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[3]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.798 ns ; SRAM0_D[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[0]                                                                                                                ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.799 ns ; ETH_RXD[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[1]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.802 ns ; JTAG_NEXUS_TMS ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[0]                                                                  ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.808 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[29]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.808 ns ; SRAM0_D[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[1]                                                                                                                      ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.809 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[11]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.810 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[1]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.810 ns ; SRAM0_D[2]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[2]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.821 ns ; SRAM1_D[2]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[18]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.823 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[23]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.831 ns ; SRAM0_D[5]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[5]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.836 ns ; ETH_RXD[3]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|multicast_ok                                                                                                                ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.839 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[18]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.839 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[24]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.839 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[12]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.841 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[5]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.842 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i_0[28]                                                                                                                 ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.842 ns ; SRAM0_D[1]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[1]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.842 ns ; SRAM1_D[8]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[24]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.847 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[8]                                                                                                                    ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.847 ns ; SRAM0_D[9]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|frame_len[9]                                                                                                                ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.850 ns ; ETH_RXDV       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[15]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.856 ns ; ETH_RXD[0]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[15]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.856 ns ; ETH_RXD[2]     ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|crc_i[24]                                                                                                                   ; ETH_RXC        ;
; N/A                                     ; None                                                ; -2.856 ns ; SRAM1_D[8]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[24]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.861 ns ; SRAM1_D[1]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[17]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.863 ns ; SRAM1_D[10]    ; EMAC32:U_Unique_MAC_System_EMAC|Memory_M1_EMAC:M1_EMAC|altsyncram:altsyncram_component|altsyncram_9q22:auto_generated|ram_block1a2~portb_datain_reg0                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.878 ns ; SRAM1_D[6]     ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[22]                                                          ; CLK_BRD        ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;                ;                                                                                                                                                                                 ;                ;
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum tco                                                                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+
; Minimum Slack                           ; Required Min tco                                    ; Actual Min tco ; From                                                                                                                                         ; To             ; From Clock     ;
+-----------------------------------------+-----------------------------------------------------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+
; N/A                                     ; None                                                ; 8.069 ns       ; WB_SPI32:U_Unique_MAC_System_SPI_SubPart_Port|spi32:U_spi|SPI_CLK                                                                            ; SPI_CLK        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.126 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_W        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.288 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.513 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.523 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.598 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.599 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.650 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.683 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.696 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.706 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.747 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.785 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.797 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.827 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.847 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.865 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.868 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.868 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.878 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.888 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.888 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.931 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.954 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.035 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.094 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[31]                                                                          ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.117 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.120 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.133 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.136 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.136 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.142 ns       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                     ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 9.151 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_1                                                                             ; SRAM0_A[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.156 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.162 ns       ; WB_SPI32:U_Unique_MAC_System_SPI_SubPart_Port|spi32:U_spi|ctrl_2                                                                             ; SPI_MODE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.166 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.175 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.177 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.188 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.188 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.197 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[19]                                                                          ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.198 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.204 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16                                                                            ; SRAM1_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.215 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_A[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.231 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.237 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.241 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.244 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_2                                                                             ; SRAM0_A[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.260 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[17]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.282 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.286 ns       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                    ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 9.286 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.289 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[5]                                                                           ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.293 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.301 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_A[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.314 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[3]                                                                           ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.317 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.326 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.331 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.339 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.349 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.358 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_WBM:U_MAC32_WBM|tx_select                                                                              ; SRAM1_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.381 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.390 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.393 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.424 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[15]                                                                          ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.428 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.431 ns       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                     ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 9.432 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.436 ns       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                  ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 9.436 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[14]                                                                          ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.439 ns       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                               ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 9.440 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.446 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.448 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.470 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.480 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_A[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.483 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.487 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.489 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_2                                                                             ; SRAM1_A[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.490 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.494 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.508 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.511 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.511 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.511 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.512 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_A[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.517 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.517 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.518 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM1_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.521 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.521 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.523 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.526 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.528 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.531 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.531 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.533 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[20]                                                                          ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.545 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[9]                                                                           ; SRAM0_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.546 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.549 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.551 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_W        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.552 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.556 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.559 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.560 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.560 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.563 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.580 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_A[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.591 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[17]                                                                          ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.594 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_A[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.596 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.602 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_A[17]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.613 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[29]                                                                          ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.625 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[3]                                                                           ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.627 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.627 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[26]                                                                          ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.640 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.648 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.673 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[16]                                                                          ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.681 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.694 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.700 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.704 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.710 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[22]                                                                          ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.725 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.726 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[25]                                                                          ; SRAM1_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.727 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.743 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_A[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.745 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.755 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_8                                                                             ; SRAM1_A[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.760 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_WBM:U_MAC32_WBM|tx_select                                                                              ; SRAM0_A[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.769 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[11]                                                                          ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.772 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.774 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|txd_1                                                                                    ; ETH_TXD[1]     ; ETH_TXC        ;
; N/A                                     ; None                                                ; 9.779 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.779 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]           ; SRAM0_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.783 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.791 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.795 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_LB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.795 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.821 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_16                                                                            ; SRAM0_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.825 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_A[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.825 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.836 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.837 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.845 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.845 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.845 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.847 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_A[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.851 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[30]                                                                          ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.853 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_3                                                                             ; SRAM0_A[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.857 ns       ; WB_SPI32:U_Unique_MAC_System_SPI_SubPart_Port|spi32:U_spi|SPI_DOUT                                                                           ; SPI_DOUT       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.863 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.864 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[28]                                                                          ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.864 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|data_buffer[23]                                                                          ; SRAM1_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.866 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.866 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.869 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.871 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_A[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.876 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.886 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.886 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]         ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.912 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.917 ns       ; WB_SPI32:U_Unique_MAC_System_SPI_SubPart_Port|spi32:U_spi|ctrl_1                                                                             ; SPI_SEL        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.918 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.920 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.921 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.925 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.930 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_4                                                                             ; SRAM1_A[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.932 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|wbm_output_4                                                                             ; SRAM0_A[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.936 ns       ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_4                                               ; SRAM0_A[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.939 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.939 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[2]                                                                           ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.939 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.945 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.947 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.948 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.954 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.959 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_A[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.961 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.963 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|txd_2                                                                                    ; ETH_TXD[2]     ; ETH_TXC        ;
; N/A                                     ; None                                                ; 9.965 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.966 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.967 ns       ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                       ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 9.967 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.971 ns       ; Configurable_SRAM:U_Unique_MAC_System_SRAM|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]        ; SRAM0_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.975 ns       ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_WBM:U_MAC32_WBM|tx_select                                                                              ; SRAM0_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.996 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_A[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.998 ns       ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM0_A[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.008 ns      ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.032 ns      ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.035 ns      ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_A[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.040 ns      ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.050 ns      ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_1|lpm_ff:ff1|dffs[0] ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.062 ns      ; EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|store_state[4]                                                                           ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.062 ns      ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_2                                    ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.063 ns      ; TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg_0     ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 10.070 ns      ; Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|NB3000_Unique_MAC__AltSyn_AltiumAlteraDffAsync:State_0|lpm_ff:ff1|dffs[0] ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.072 ns      ; TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_3                                    ; SRAM0_D[3]     ; CLK_BRD        ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                ;                                                                                                                                              ;                ;                ;
+-----------------------------------------+-----------------------------------------------------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+


+----------------------------------------------------------------------------------+
; Minimum tpd                                                                      ;
+---------------+-------------------+-----------------+-------------+--------------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From        ; To           ;
+---------------+-------------------+-----------------+-------------+--------------+
; N/A           ; None              ; 16.212 ns       ; TEST_BUTTON ; ETH_RESETB_E ;
+---------------+-------------------+-----------------+-------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; ETH_MDC        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ETH_RESETB_E   ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ETH_TXD[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ETH_TXD[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ETH_TXD[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ETH_TXD[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ETH_TXEN       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SPI_CLK        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SPI_DOUT       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SPI_MODE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SPI_SEL        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[16]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[17]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_E        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_LB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_OE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_UB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_W        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[16]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[17]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_E        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_LB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_OE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_UB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_W        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ETH_MDIO       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; ETH_MDIO                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; TEST_BUTTON             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK_REF                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK_BRD                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_TXC                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_COL                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TCK          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TMS          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TDI          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_RXC                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_CRS                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_RXER                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_RXDV                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_RXD[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_RXD[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_RXD[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ETH_RXD[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SPI_DIN                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DCLK~           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; ETH_MDC        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; ETH_RESETB_E   ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; ETH_TXD[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; ETH_TXD[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; ETH_TXD[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; ETH_TXD[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; ETH_TXEN       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SPI_CLK        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SPI_DOUT       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SPI_MODE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00566 V          ; 0.066 V                              ; 0.016 V                              ; 6.89e-010 s                 ; 6.77e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00566 V         ; 0.066 V                             ; 0.016 V                             ; 6.89e-010 s                ; 6.77e-010 s                ; Yes                       ; Yes                       ;
; SPI_SEL        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM0_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00566 V          ; 0.066 V                              ; 0.016 V                              ; 6.89e-010 s                 ; 6.77e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00566 V         ; 0.066 V                             ; 0.016 V                             ; 6.89e-010 s                ; 6.77e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM0_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.33 V              ; -0.00201 V          ; 0.092 V                              ; 0.05 V                               ; 3.78e-009 s                 ; 3.59e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.33 V             ; -0.00201 V         ; 0.092 V                             ; 0.05 V                              ; 3.78e-009 s                ; 3.59e-009 s                ; Yes                       ; Yes                       ;
; SRAM1_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM1_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM1_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; ETH_MDIO       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00566 V          ; 0.066 V                              ; 0.016 V                              ; 6.89e-010 s                 ; 6.77e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00566 V         ; 0.066 V                             ; 0.016 V                             ; 6.89e-010 s                ; 6.77e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; ETH_MDC        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; ETH_RESETB_E   ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; ETH_TXD[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; ETH_TXD[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; ETH_TXD[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; ETH_TXD[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; ETH_TXEN       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SPI_CLK        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SPI_DOUT       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SPI_MODE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.72 V              ; -0.0405 V           ; 0.163 V                              ; 0.077 V                              ; 4.51e-010 s                 ; 4.33e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.72 V             ; -0.0405 V          ; 0.163 V                             ; 0.077 V                             ; 4.51e-010 s                ; 4.33e-010 s                ; No                        ; Yes                       ;
; SPI_SEL        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM0_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.72 V              ; -0.0405 V           ; 0.163 V                              ; 0.077 V                              ; 4.51e-010 s                 ; 4.33e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.72 V             ; -0.0405 V          ; 0.163 V                             ; 0.077 V                             ; 4.51e-010 s                ; 4.33e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM0_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.64 V              ; -0.011 V            ; 0.212 V                              ; 0.198 V                              ; 2.38e-009 s                 ; 2.29e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.64 V             ; -0.011 V           ; 0.212 V                             ; 0.198 V                             ; 2.38e-009 s                ; 2.29e-009 s                ; No                        ; Yes                       ;
; SRAM1_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM1_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM1_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; ETH_MDIO       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.72 V              ; -0.0405 V           ; 0.163 V                              ; 0.077 V                              ; 4.51e-010 s                 ; 4.33e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.72 V             ; -0.0405 V          ; 0.163 V                             ; 0.077 V                             ; 4.51e-010 s                ; 4.33e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Copyright (C) 1991-2009 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Wed Mar 06 21:28:40 2013
Info: Command: quartus_tan NB3000_Unique_MAC
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found USE_TIMEQUEST_TIMING_ANALYZER=ON. The Classic Timing Analyzer is not the default timing analysis tool during full compilation
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK_REF" is an undefined clock
    Info: Assuming node "CLK_BRD" is an undefined clock
    Info: Assuming node "JTAG_NEXUS_TCK" is an undefined clock
    Info: Assuming node "ETH_TXC" is an undefined clock
    Info: Assuming node "ETH_RXC" is an undefined clock
Warning: Clock Setting "CLK_BRD" is unassigned
Warning: Clock Setting "CLK_REF" is unassigned
Warning: Clock Setting "ETH_RXC" is unassigned
Warning: Clock Setting "ETH_TXC" is unassigned
Warning: Clock Setting "JTAG_NEXUS_TCK" is unassigned
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CDIV20DC50:U4|OutState_Z" as buffer
Info: Clock "CLK_REF" Internal fmax is restricted to 250.0 MHz between source register "EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]" and destination register "EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_9"
    Info: fmax restricted to clock pin edge rate 4.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.504 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y39_N23; Fanout = 11; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]'
            Info: 2: + IC(1.048 ns) + CELL(0.398 ns) = 1.446 ns; Loc. = LCCOMB_X37_Y38_N6; Fanout = 16; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_2_0_15__g0_i_o4_i'
            Info: 3: + IC(1.263 ns) + CELL(0.795 ns) = 3.504 ns; Loc. = FF_X41_Y39_N13; Fanout = 2; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_9'
            Info: Total cell delay = 1.193 ns ( 34.05 % )
            Info: Total interconnect delay = 2.311 ns ( 65.95 % )
        Info: - Smallest clock skew is -0.002 ns
            Info: + Shortest clock path from clock "CLK_REF" to destination register is 6.323 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AH14; Fanout = 1; CLK Node = 'CLK_REF'
                Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X36_Y0_N15; Fanout = 1; COMB Node = 'CLK_REF~input'
                Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G19; Fanout = 5; COMB Node = 'CLK_REF~inputclkctrl'
                Info: 4: + IC(1.341 ns) + CELL(0.941 ns) = 3.443 ns; Loc. = FF_X66_Y22_N19; Fanout = 3; REG Node = 'CDIV20DC50:U4|OutState_Z'
                Info: 5: + IC(0.835 ns) + CELL(0.000 ns) = 4.278 ns; Loc. = CLKCTRL_G7; Fanout = 61; COMB Node = 'CDIV20DC50:U4|OutState_Z~clkctrl'
                Info: 6: + IC(1.365 ns) + CELL(0.680 ns) = 6.323 ns; Loc. = FF_X41_Y39_N13; Fanout = 2; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_9'
                Info: Total cell delay = 2.585 ns ( 40.88 % )
                Info: Total interconnect delay = 3.738 ns ( 59.12 % )
            Info: - Longest clock path from clock "CLK_REF" to source register is 6.325 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AH14; Fanout = 1; CLK Node = 'CLK_REF'
                Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X36_Y0_N15; Fanout = 1; COMB Node = 'CLK_REF~input'
                Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G19; Fanout = 5; COMB Node = 'CLK_REF~inputclkctrl'
                Info: 4: + IC(1.341 ns) + CELL(0.941 ns) = 3.443 ns; Loc. = FF_X66_Y22_N19; Fanout = 3; REG Node = 'CDIV20DC50:U4|OutState_Z'
                Info: 5: + IC(0.835 ns) + CELL(0.000 ns) = 4.278 ns; Loc. = CLKCTRL_G7; Fanout = 61; COMB Node = 'CDIV20DC50:U4|OutState_Z~clkctrl'
                Info: 6: + IC(1.367 ns) + CELL(0.680 ns) = 6.325 ns; Loc. = FF_X37_Y39_N23; Fanout = 11; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|counter[5]'
                Info: Total cell delay = 2.585 ns ( 40.87 % )
                Info: Total interconnect delay = 3.740 ns ( 59.13 % )
        Info: + Micro clock to output delay of source is 0.261 ns
        Info: + Micro setup delay of destination is -0.021 ns
Info: Clock "CLK_BRD" has Internal fmax of 49.69 MHz between source memory "Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0" and destination memory "TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0" (period= 20.124 ns)
    Info: + Longest memory to memory delay is 9.747 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y26_N0; Fanout = 2; MEM Node = 'Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(3.204 ns) = 3.204 ns; Loc. = M9K_X40_Y26_N0; Fanout = 1; MEM Node = 'Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|q_a[7]'
        Info: 3: + IC(1.262 ns) + CELL(0.177 ns) = 4.643 ns; Loc. = LCCOMB_X41_Y29_N2; Fanout = 1; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|IMem_DataOut_2_0_0_x[31]'
        Info: 4: + IC(0.464 ns) + CELL(0.177 ns) = 5.284 ns; Loc. = LCCOMB_X42_Y29_N4; Fanout = 18; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|IMem_DataOut_3_0_0_31'
        Info: 5: + IC(0.355 ns) + CELL(0.472 ns) = 6.111 ns; Loc. = LCCOMB_X42_Y29_N28; Fanout = 26; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Decode:U_PipeStage_Decode|local_rd_0_sqmuxa_1_1_o2'
        Info: 6: + IC(0.879 ns) + CELL(0.177 ns) = 7.167 ns; Loc. = LCCOMB_X42_Y28_N12; Fanout = 1; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rt_Index_Local_0_0_0_1_4_m1_e_0'
        Info: 7: + IC(0.256 ns) + CELL(0.177 ns) = 7.600 ns; Loc. = LCCOMB_X42_Y28_N26; Fanout = 2; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rt_Index_Local_0_0_0_1_4_m1_e'
        Info: 8: + IC(0.288 ns) + CELL(0.324 ns) = 8.212 ns; Loc. = LCCOMB_X42_Y28_N4; Fanout = 1; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rt_Index_Local_0_0_0_1_3_m6_i_a3'
        Info: 9: + IC(0.264 ns) + CELL(0.327 ns) = 8.803 ns; Loc. = LCCOMB_X42_Y28_N30; Fanout = 38; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rt_Index_Local_0_0_0_1_3_m6_i'
        Info: 10: + IC(0.856 ns) + CELL(0.088 ns) = 9.747 ns; Loc. = M9K_X40_Y27_N0; Fanout = 32; MEM Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0'
        Info: Total cell delay = 5.123 ns ( 52.56 % )
        Info: Total interconnect delay = 4.624 ns ( 47.44 % )
    Info: - Smallest clock skew is -0.089 ns
        Info: + Shortest clock path from clock "CLK_BRD" to destination memory is 3.544 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
            Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
            Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 2322; COMB Node = 'CLK_BRD~inputclkctrl'
            Info: 4: + IC(1.352 ns) + CELL(1.031 ns) = 3.544 ns; Loc. = M9K_X40_Y27_N0; Fanout = 32; MEM Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0'
            Info: Total cell delay = 1.995 ns ( 56.29 % )
            Info: Total interconnect delay = 1.549 ns ( 43.71 % )
        Info: - Longest clock path from clock "CLK_BRD" to source memory is 3.633 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
            Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
            Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 2322; COMB Node = 'CLK_BRD~inputclkctrl'
            Info: 4: + IC(1.366 ns) + CELL(1.106 ns) = 3.633 ns; Loc. = M9K_X40_Y26_N0; Fanout = 2; MEM Node = 'Memory_MCU:U_Unique_MAC_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_c1h2:auto_generated|ram_block1a4~porta_address_reg0'
            Info: Total cell delay = 2.070 ns ( 56.98 % )
            Info: Total interconnect delay = 1.563 ns ( 43.02 % )
    Info: + Micro clock to output delay of source is 0.294 ns
    Info: + Micro setup delay of destination is -0.068 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "JTAG_NEXUS_TCK" has Internal fmax of 162.0 MHz between source register "TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z" and destination register "TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]" (period= 6.173 ns)
    Info: + Longest register to register delay is 5.916 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X44_Y30_N5; Fanout = 2; REG Node = 'TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z'
        Info: 2: + IC(1.804 ns) + CELL(0.324 ns) = 2.128 ns; Loc. = LCCOMB_X53_Y27_N10; Fanout = 2; COMB Node = 'TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|G_8'
        Info: 3: + IC(0.327 ns) + CELL(0.398 ns) = 2.853 ns; Loc. = LCCOMB_X53_Y27_N0; Fanout = 1; COMB Node = 'TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tdo_u_0_a2_3'
        Info: 4: + IC(0.258 ns) + CELL(0.177 ns) = 3.288 ns; Loc. = LCCOMB_X53_Y27_N26; Fanout = 1; COMB Node = 'TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tdo_u_0_2'
        Info: 5: + IC(0.264 ns) + CELL(0.327 ns) = 3.879 ns; Loc. = LCCOMB_X53_Y27_N12; Fanout = 8; COMB Node = 'TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tdo_u_0'
        Info: 6: + IC(1.572 ns) + CELL(0.465 ns) = 5.916 ns; Loc. = FF_X56_Y25_N5; Fanout = 2; REG Node = 'TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]'
        Info: Total cell delay = 1.691 ns ( 28.58 % )
        Info: Total interconnect delay = 4.225 ns ( 71.42 % )
    Info: - Smallest clock skew is -0.017 ns
        Info: + Shortest clock path from clock "JTAG_NEXUS_TCK" to destination register is 3.255 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_Y27; Fanout = 1; CLK Node = 'JTAG_NEXUS_TCK'
            Info: 2: + IC(0.000 ns) + CELL(1.048 ns) = 1.048 ns; Loc. = IOIBUF_X67_Y22_N15; Fanout = 1; COMB Node = 'JTAG_NEXUS_TCK~input'
            Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.245 ns; Loc. = CLKCTRL_G9; Fanout = 350; COMB Node = 'JTAG_NEXUS_TCK~inputclkctrl'
            Info: 4: + IC(1.330 ns) + CELL(0.680 ns) = 3.255 ns; Loc. = FF_X56_Y25_N5; Fanout = 2; REG Node = 'TERMINAL:U_Unique_MAC_System_SOFT_TERM|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]'
            Info: Total cell delay = 1.728 ns ( 53.09 % )
            Info: Total interconnect delay = 1.527 ns ( 46.91 % )
        Info: - Longest clock path from clock "JTAG_NEXUS_TCK" to source register is 3.272 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_Y27; Fanout = 1; CLK Node = 'JTAG_NEXUS_TCK'
            Info: 2: + IC(0.000 ns) + CELL(1.048 ns) = 1.048 ns; Loc. = IOIBUF_X67_Y22_N15; Fanout = 1; COMB Node = 'JTAG_NEXUS_TCK~input'
            Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.245 ns; Loc. = CLKCTRL_G9; Fanout = 350; COMB Node = 'JTAG_NEXUS_TCK~inputclkctrl'
            Info: 4: + IC(1.347 ns) + CELL(0.680 ns) = 3.272 ns; Loc. = FF_X44_Y30_N5; Fanout = 2; REG Node = 'TSK3000A_OCDS:U_Unique_MAC_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z'
            Info: Total cell delay = 1.728 ns ( 52.81 % )
            Info: Total interconnect delay = 1.544 ns ( 47.19 % )
    Info: + Micro clock to output delay of source is 0.261 ns
    Info: + Micro setup delay of destination is -0.021 ns
Info: Clock "ETH_TXC" has Internal fmax of 86.72 MHz between source register "EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]" and destination register "EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14]" (period= 11.532 ns)
    Info: + Longest register to register delay is 11.293 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X26_Y34_N19; Fanout = 12; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]'
        Info: 2: + IC(1.555 ns) + CELL(0.489 ns) = 2.044 ns; Loc. = LCCOMB_X34_Y35_N26; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un20_counter_tx_i_i_0_a2_0_a2_1_1'
        Info: 3: + IC(1.173 ns) + CELL(0.408 ns) = 3.625 ns; Loc. = LCCOMB_X30_Y34_N14; Fanout = 3; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un20_counter_tx_i_i_0_a2_0_a2_1_8'
        Info: 4: + IC(0.289 ns) + CELL(0.327 ns) = 4.241 ns; Loc. = LCCOMB_X30_Y34_N20; Fanout = 4; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|tx_state_ns_5_1_1_a2_2_3_0_a2'
        Info: 5: + IC(0.800 ns) + CELL(0.324 ns) = 5.365 ns; Loc. = LCCOMB_X30_Y34_N12; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_buf_out_0_sqmuxa_1_0_a2_1'
        Info: 6: + IC(0.493 ns) + CELL(0.324 ns) = 6.182 ns; Loc. = LCCOMB_X29_Y34_N26; Fanout = 12; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_buf_out_0_sqmuxa_1_0'
        Info: 7: + IC(1.170 ns) + CELL(0.177 ns) = 7.529 ns; Loc. = LCCOMB_X26_Y35_N2; Fanout = 37; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_tx_state_12_293'
        Info: 8: + IC(0.498 ns) + CELL(0.565 ns) = 8.592 ns; Loc. = LCCOMB_X26_Y35_N18; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_1'
        Info: 9: + IC(0.000 ns) + CELL(0.073 ns) = 8.665 ns; Loc. = LCCOMB_X26_Y35_N20; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_2'
        Info: 10: + IC(0.000 ns) + CELL(0.073 ns) = 8.738 ns; Loc. = LCCOMB_X26_Y35_N22; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_3'
        Info: 11: + IC(0.000 ns) + CELL(0.073 ns) = 8.811 ns; Loc. = LCCOMB_X26_Y35_N24; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_4'
        Info: 12: + IC(0.000 ns) + CELL(0.073 ns) = 8.884 ns; Loc. = LCCOMB_X26_Y35_N26; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_5'
        Info: 13: + IC(0.000 ns) + CELL(0.073 ns) = 8.957 ns; Loc. = LCCOMB_X26_Y35_N28; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_6'
        Info: 14: + IC(0.000 ns) + CELL(0.073 ns) = 9.030 ns; Loc. = LCCOMB_X26_Y35_N30; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_7'
        Info: 15: + IC(0.000 ns) + CELL(0.073 ns) = 9.103 ns; Loc. = LCCOMB_X26_Y34_N0; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_8'
        Info: 16: + IC(0.000 ns) + CELL(0.073 ns) = 9.176 ns; Loc. = LCCOMB_X26_Y34_N2; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_9'
        Info: 17: + IC(0.000 ns) + CELL(0.073 ns) = 9.249 ns; Loc. = LCCOMB_X26_Y34_N4; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_10'
        Info: 18: + IC(0.000 ns) + CELL(0.073 ns) = 9.322 ns; Loc. = LCCOMB_X26_Y34_N6; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_11'
        Info: 19: + IC(0.000 ns) + CELL(0.073 ns) = 9.395 ns; Loc. = LCCOMB_X26_Y34_N8; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_12'
        Info: 20: + IC(0.000 ns) + CELL(0.073 ns) = 9.468 ns; Loc. = LCCOMB_X26_Y34_N10; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_carry_13'
        Info: 21: + IC(0.000 ns) + CELL(0.607 ns) = 10.075 ns; Loc. = LCCOMB_X26_Y34_N12; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_counter_tx_1_add14'
        Info: 22: + IC(0.753 ns) + CELL(0.465 ns) = 11.293 ns; Loc. = FF_X27_Y34_N31; Fanout = 11; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14]'
        Info: Total cell delay = 4.562 ns ( 40.40 % )
        Info: Total interconnect delay = 6.731 ns ( 59.60 % )
    Info: - Smallest clock skew is 0.001 ns
        Info: + Shortest clock path from clock "ETH_TXC" to destination register is 5.136 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_J5; Fanout = 1; CLK Node = 'ETH_TXC'
            Info: 2: + IC(0.000 ns) + CELL(1.008 ns) = 1.008 ns; Loc. = IOIBUF_X0_Y38_N1; Fanout = 1; COMB Node = 'ETH_TXC~input'
            Info: 3: + IC(2.102 ns) + CELL(0.000 ns) = 3.110 ns; Loc. = CLKCTRL_G3; Fanout = 113; COMB Node = 'ETH_TXC~inputclkctrl'
            Info: 4: + IC(1.346 ns) + CELL(0.680 ns) = 5.136 ns; Loc. = FF_X27_Y34_N31; Fanout = 11; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[14]'
            Info: Total cell delay = 1.688 ns ( 32.87 % )
            Info: Total interconnect delay = 3.448 ns ( 67.13 % )
        Info: - Longest clock path from clock "ETH_TXC" to source register is 5.135 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_J5; Fanout = 1; CLK Node = 'ETH_TXC'
            Info: 2: + IC(0.000 ns) + CELL(1.008 ns) = 1.008 ns; Loc. = IOIBUF_X0_Y38_N1; Fanout = 1; COMB Node = 'ETH_TXC~input'
            Info: 3: + IC(2.102 ns) + CELL(0.000 ns) = 3.110 ns; Loc. = CLKCTRL_G3; Fanout = 113; COMB Node = 'ETH_TXC~inputclkctrl'
            Info: 4: + IC(1.345 ns) + CELL(0.680 ns) = 5.135 ns; Loc. = FF_X26_Y34_N19; Fanout = 12; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|counter_tx[9]'
            Info: Total cell delay = 1.688 ns ( 32.87 % )
            Info: Total interconnect delay = 3.447 ns ( 67.13 % )
    Info: + Micro clock to output delay of source is 0.261 ns
    Info: + Micro setup delay of destination is -0.021 ns
Info: Clock "ETH_RXC" has Internal fmax of 117.7 MHz between source register "EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]" and destination register "EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok" (period= 8.496 ns)
    Info: + Longest register to register delay is 8.246 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X54_Y37_N21; Fanout = 12; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]'
        Info: 2: + IC(1.692 ns) + CELL(0.472 ns) = 2.164 ns; Loc. = LCCOMB_X53_Y32_N2; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|un157_phy_rxdv_i_m2_5'
        Info: 3: + IC(0.304 ns) + CELL(0.473 ns) = 2.941 ns; Loc. = LCCOMB_X53_Y32_N28; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|un157_phy_rxdv_i_m2_2'
        Info: 4: + IC(0.477 ns) + CELL(0.177 ns) = 3.595 ns; Loc. = LCCOMB_X52_Y32_N30; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok_0_0_g2_0_i_m3_0'
        Info: 5: + IC(0.311 ns) + CELL(0.472 ns) = 4.378 ns; Loc. = LCCOMB_X52_Y32_N4; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok_0_0_g2_0_373_i_o3'
        Info: 6: + IC(1.107 ns) + CELL(0.472 ns) = 5.957 ns; Loc. = LCCOMB_X51_Y34_N18; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok_0_0_g2_0_373_i_a3'
        Info: 7: + IC(0.301 ns) + CELL(0.487 ns) = 6.745 ns; Loc. = LCCOMB_X51_Y34_N16; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok_0_0_g2_0_373_i'
        Info: 8: + IC(1.036 ns) + CELL(0.465 ns) = 8.246 ns; Loc. = FF_X52_Y32_N29; Fanout = 4; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok'
        Info: Total cell delay = 3.018 ns ( 36.60 % )
        Info: Total interconnect delay = 5.228 ns ( 63.40 % )
    Info: - Smallest clock skew is -0.010 ns
        Info: + Shortest clock path from clock "ETH_RXC" to destination register is 5.126 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G15; Fanout = 1; CLK Node = 'ETH_RXC'
            Info: 2: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = IOIBUF_X41_Y43_N8; Fanout = 1; COMB Node = 'ETH_RXC~input'
            Info: 3: + IC(2.210 ns) + CELL(0.000 ns) = 3.134 ns; Loc. = CLKCTRL_G10; Fanout = 124; COMB Node = 'ETH_RXC~inputclkctrl'
            Info: 4: + IC(1.312 ns) + CELL(0.680 ns) = 5.126 ns; Loc. = FF_X52_Y32_N29; Fanout = 4; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|mac_ok'
            Info: Total cell delay = 1.604 ns ( 31.29 % )
            Info: Total interconnect delay = 3.522 ns ( 68.71 % )
        Info: - Longest clock path from clock "ETH_RXC" to source register is 5.136 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G15; Fanout = 1; CLK Node = 'ETH_RXC'
            Info: 2: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = IOIBUF_X41_Y43_N8; Fanout = 1; COMB Node = 'ETH_RXC~input'
            Info: 3: + IC(2.210 ns) + CELL(0.000 ns) = 3.134 ns; Loc. = CLKCTRL_G10; Fanout = 124; COMB Node = 'ETH_RXC~inputclkctrl'
            Info: 4: + IC(1.322 ns) + CELL(0.680 ns) = 5.136 ns; Loc. = FF_X54_Y37_N21; Fanout = 12; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_RX:U_MAC32_RX|counter_rx[1]'
            Info: Total cell delay = 1.604 ns ( 31.23 % )
            Info: Total interconnect delay = 3.532 ns ( 68.77 % )
    Info: + Micro clock to output delay of source is 0.261 ns
    Info: + Micro setup delay of destination is -0.021 ns
Info: tsu for register "EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]" (data pin = "SRAM0_D[1]", clock pin = "CLK_BRD") is 13.438 ns
    Info: + Longest pin to register delay is 16.640 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_E22; Fanout = 1; PIN Node = 'SRAM0_D[1]'
        Info: 2: + IC(0.000 ns) + CELL(0.954 ns) = 0.954 ns; Loc. = IOIBUF_X65_Y43_N22; Fanout = 10; COMB Node = 'SRAM0_D[1]~input'
        Info: 3: + IC(5.487 ns) + CELL(0.398 ns) = 6.839 ns; Loc. = LCCOMB_X34_Y35_N18; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un13_m_acklto3'
        Info: 4: + IC(0.258 ns) + CELL(0.177 ns) = 7.274 ns; Loc. = LCCOMB_X34_Y35_N24; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un13_m_acklto8_2'
        Info: 5: + IC(0.261 ns) + CELL(0.177 ns) = 7.712 ns; Loc. = LCCOMB_X34_Y35_N2; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un13_m_acklto9'
        Info: 6: + IC(1.208 ns) + CELL(0.327 ns) = 9.247 ns; Loc. = LCCOMB_X36_Y38_N20; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un13_m_acklto31_12'
        Info: 7: + IC(0.910 ns) + CELL(0.472 ns) = 10.629 ns; Loc. = LCCOMB_X36_Y36_N26; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un13_m_acklto31'
        Info: 8: + IC(0.875 ns) + CELL(0.408 ns) = 11.912 ns; Loc. = LCCOMB_X39_Y36_N18; Fanout = 13; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|mess_state_1_sqmuxa'
        Info: 9: + IC(1.944 ns) + CELL(0.455 ns) = 14.311 ns; Loc. = LCCOMB_X48_Y38_N2; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un2_m_ack_2_iv[8]'
        Info: 10: + IC(0.544 ns) + CELL(0.552 ns) = 15.407 ns; Loc. = LCCOMB_X48_Y38_N8; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_carry_0'
        Info: 11: + IC(0.000 ns) + CELL(0.073 ns) = 15.480 ns; Loc. = LCCOMB_X48_Y38_N10; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_carry_1'
        Info: 12: + IC(0.000 ns) + CELL(0.073 ns) = 15.553 ns; Loc. = LCCOMB_X48_Y38_N12; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_carry_2'
        Info: 13: + IC(0.000 ns) + CELL(0.073 ns) = 15.626 ns; Loc. = LCCOMB_X48_Y38_N14; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_carry_3'
        Info: 14: + IC(0.000 ns) + CELL(0.073 ns) = 15.699 ns; Loc. = LCCOMB_X48_Y38_N16; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_carry_4'
        Info: 15: + IC(0.000 ns) + CELL(0.073 ns) = 15.772 ns; Loc. = LCCOMB_X48_Y38_N18; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_carry_5'
        Info: 16: + IC(0.000 ns) + CELL(0.073 ns) = 15.845 ns; Loc. = LCCOMB_X48_Y38_N20; Fanout = 2; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_carry_6'
        Info: 17: + IC(0.000 ns) + CELL(0.073 ns) = 15.918 ns; Loc. = LCCOMB_X48_Y38_N22; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_carry_7'
        Info: 18: + IC(0.000 ns) + CELL(0.607 ns) = 16.525 ns; Loc. = LCCOMB_X48_Y38_N24; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|un1_m_datai_2_add8'
        Info: 19: + IC(0.000 ns) + CELL(0.115 ns) = 16.640 ns; Loc. = FF_X48_Y38_N25; Fanout = 2; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]'
        Info: Total cell delay = 5.153 ns ( 30.97 % )
        Info: Total interconnect delay = 11.487 ns ( 69.03 % )
    Info: + Micro setup delay of destination is -0.021 ns
    Info: - Shortest clock path from clock "CLK_BRD" to destination register is 3.181 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
        Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 2322; COMB Node = 'CLK_BRD~inputclkctrl'
        Info: 4: + IC(1.340 ns) + CELL(0.680 ns) = 3.181 ns; Loc. = FF_X48_Y38_N25; Fanout = 2; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_TX:U_MAC32_TX|len[8]'
        Info: Total cell delay = 1.644 ns ( 51.68 % )
        Info: Total interconnect delay = 1.537 ns ( 48.32 % )
Info: tco from clock "CLK_BRD" to destination pin "SRAM0_E" through register "TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3" is 20.875 ns
    Info: + Longest clock path from clock "CLK_BRD" to source register is 3.201 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
        Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 2322; COMB Node = 'CLK_BRD~inputclkctrl'
        Info: 4: + IC(1.360 ns) + CELL(0.680 ns) = 3.201 ns; Loc. = FF_X44_Y27_N5; Fanout = 4; REG Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3'
        Info: Total cell delay = 1.644 ns ( 51.36 % )
        Info: Total interconnect delay = 1.557 ns ( 48.64 % )
    Info: + Micro clock to output delay of source is 0.261 ns
    Info: + Longest register to pin delay is 17.413 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X44_Y27_N5; Fanout = 4; REG Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3'
        Info: 2: + IC(0.990 ns) + CELL(0.421 ns) = 1.411 ns; Loc. = LCCOMB_X44_Y26_N22; Fanout = 1; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|DataHazardResolverA:U_DataHazardResolverA|rega_usedatafromma3_NE_1'
        Info: 3: + IC(0.309 ns) + CELL(0.472 ns) = 2.192 ns; Loc. = LCCOMB_X44_Y26_N24; Fanout = 37; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|DataHazardResolverA:U_DataHazardResolverA|rega_usedatafromma3_NE'
        Info: 4: + IC(0.313 ns) + CELL(0.177 ns) = 2.682 ns; Loc. = LCCOMB_X44_Y26_N0; Fanout = 25; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|DataHazardResolverA:U_DataHazardResolverA|LoadHazard_MA'
        Info: 5: + IC(0.803 ns) + CELL(0.324 ns) = 3.809 ns; Loc. = LCCOMB_X48_Y27_N20; Fanout = 38; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Execute:U_Execute|MDU_EnableControl:U_MDU_EnableControl|Enable_x'
        Info: 6: + IC(0.282 ns) + CELL(0.177 ns) = 4.268 ns; Loc. = LCCOMB_X48_Y27_N10; Fanout = 4; COMB Node = 'TSK3000A_MDU:U_Unique_MAC_System_MCU_SubPart_MDU|MultDiv:U_MultDiv|Busy_i'
        Info: 7: + IC(0.513 ns) + CELL(0.177 ns) = 4.958 ns; Loc. = LCCOMB_X49_Y27_N16; Fanout = 18; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Execute:U_Execute|ExecuteBusy:U_ExecuteBusy|Busy_EX_x'
        Info: 8: + IC(1.224 ns) + CELL(0.177 ns) = 6.359 ns; Loc. = LCCOMB_X51_Y29_N6; Fanout = 4; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|Main_STB_O_1_0_a2_1_x'
        Info: 9: + IC(0.296 ns) + CELL(0.177 ns) = 6.832 ns; Loc. = LCCOMB_X51_Y29_N0; Fanout = 23; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|MainMemoryIsData_0_o2'
        Info: 10: + IC(1.475 ns) + CELL(0.324 ns) = 8.631 ns; Loc. = LCCOMB_X48_Y24_N12; Fanout = 2; COMB Node = 'TSK3000A_MCU:U_Unique_MAC_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|Main_SEL_O_x_3'
        Info: 11: + IC(2.153 ns) + CELL(0.327 ns) = 11.111 ns; Loc. = LCCOMB_X55_Y35_N28; Fanout = 5; COMB Node = 'Configurable_WB_MULTIMASTER_1:U_Unique_MAC_System_WB_MULTIMASTER_1|INST_m0_SEL_O_3'
        Info: 12: + IC(0.949 ns) + CELL(0.453 ns) = 12.513 ns; Loc. = LCCOMB_X55_Y39_N28; Fanout = 3; COMB Node = 'Configurable_SRAM:U_Unique_MAC_System_SRAM|n3v~0'
        Info: 13: + IC(0.326 ns) + CELL(0.455 ns) = 13.294 ns; Loc. = LCCOMB_X55_Y39_N20; Fanout = 1; COMB Node = 'Configurable_SRAM:U_Unique_MAC_System_SRAM|INST_SRAM0_CE~2'
        Info: 14: + IC(1.667 ns) + CELL(2.452 ns) = 17.413 ns; Loc. = IOOBUF_X63_Y43_N9; Fanout = 1; COMB Node = 'SRAM0_E~output'
        Info: 15: + IC(0.000 ns) + CELL(0.000 ns) = 17.413 ns; Loc. = PIN_G20; Fanout = 0; PIN Node = 'SRAM0_E'
        Info: Total cell delay = 6.113 ns ( 35.11 % )
        Info: Total interconnect delay = 11.300 ns ( 64.89 % )
Info: Longest tpd from source pin "TEST_BUTTON" to destination pin "ETH_RESETB_E" is 16.212 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AG12; Fanout = 1; PIN Node = 'TEST_BUTTON'
    Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y0_N22; Fanout = 3; COMB Node = 'TEST_BUTTON~input'
    Info: 3: + IC(5.090 ns) + CELL(0.496 ns) = 6.550 ns; Loc. = LCCOMB_X48_Y31_N22; Fanout = 298; COMB Node = 'PinSignal_U2_O'
    Info: 4: + IC(2.552 ns) + CELL(0.324 ns) = 9.426 ns; Loc. = LCCOMB_X41_Y38_N14; Fanout = 54; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reset_0_o2_x'
    Info: 5: + IC(4.095 ns) + CELL(2.691 ns) = 16.212 ns; Loc. = IOOBUF_X0_Y37_N2; Fanout = 1; COMB Node = 'ETH_RESETB_E~output'
    Info: 6: + IC(0.000 ns) + CELL(0.000 ns) = 16.212 ns; Loc. = PIN_F5; Fanout = 0; PIN Node = 'ETH_RESETB_E'
    Info: Total cell delay = 4.475 ns ( 27.60 % )
    Info: Total interconnect delay = 11.737 ns ( 72.40 % )
Info: th for register "EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[0]" (data pin = "ETH_MDIO", clock pin = "CLK_REF") is 0.777 ns
    Info: + Longest clock path from clock "CLK_REF" to destination register is 6.324 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AH14; Fanout = 1; CLK Node = 'CLK_REF'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X36_Y0_N15; Fanout = 1; COMB Node = 'CLK_REF~input'
        Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G19; Fanout = 5; COMB Node = 'CLK_REF~inputclkctrl'
        Info: 4: + IC(1.341 ns) + CELL(0.941 ns) = 3.443 ns; Loc. = FF_X66_Y22_N19; Fanout = 3; REG Node = 'CDIV20DC50:U4|OutState_Z'
        Info: 5: + IC(0.835 ns) + CELL(0.000 ns) = 4.278 ns; Loc. = CLKCTRL_G7; Fanout = 61; COMB Node = 'CDIV20DC50:U4|OutState_Z~clkctrl'
        Info: 6: + IC(1.366 ns) + CELL(0.680 ns) = 6.324 ns; Loc. = FF_X37_Y38_N31; Fanout = 2; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[0]'
        Info: Total cell delay = 2.585 ns ( 40.88 % )
        Info: Total interconnect delay = 3.739 ns ( 59.12 % )
    Info: + Micro hold delay of destination is 0.212 ns
    Info: - Shortest pin to register delay is 5.759 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G6; Fanout = 1; PIN Node = 'ETH_MDIO'
        Info: 2: + IC(0.000 ns) + CELL(0.988 ns) = 0.988 ns; Loc. = IOIBUF_X0_Y39_N1; Fanout = 1; COMB Node = 'ETH_MDIO~input'
        Info: 3: + IC(4.329 ns) + CELL(0.327 ns) = 5.644 ns; Loc. = LCCOMB_X37_Y38_N30; Fanout = 1; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in_0_0_a2_1_x[0]'
        Info: 4: + IC(0.000 ns) + CELL(0.115 ns) = 5.759 ns; Loc. = FF_X37_Y38_N31; Fanout = 2; REG Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|data_in[0]'
        Info: Total cell delay = 1.430 ns ( 24.83 % )
        Info: Total interconnect delay = 4.329 ns ( 75.17 % )
Info: Minimum tco from clock "CLK_BRD" to destination pin "SPI_CLK" through register "WB_SPI32:U_Unique_MAC_System_SPI_SubPart_Port|spi32:U_spi|SPI_CLK" is 8.069 ns
    Info: + Shortest clock path from clock "CLK_BRD" to source register is 3.168 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
        Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 2322; COMB Node = 'CLK_BRD~inputclkctrl'
        Info: 4: + IC(1.327 ns) + CELL(0.680 ns) = 3.168 ns; Loc. = FF_X35_Y34_N5; Fanout = 2; REG Node = 'WB_SPI32:U_Unique_MAC_System_SPI_SubPart_Port|spi32:U_spi|SPI_CLK'
        Info: Total cell delay = 1.644 ns ( 51.89 % )
        Info: Total interconnect delay = 1.524 ns ( 48.11 % )
    Info: + Micro clock to output delay of source is 0.261 ns
    Info: + Shortest register to pin delay is 4.640 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X35_Y34_N5; Fanout = 2; REG Node = 'WB_SPI32:U_Unique_MAC_System_SPI_SubPart_Port|spi32:U_spi|SPI_CLK'
        Info: 2: + IC(2.168 ns) + CELL(2.472 ns) = 4.640 ns; Loc. = IOOBUF_X34_Y0_N9; Fanout = 1; COMB Node = 'SPI_CLK~output'
        Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 4.640 ns; Loc. = PIN_AE14; Fanout = 0; PIN Node = 'SPI_CLK'
        Info: Total cell delay = 2.472 ns ( 53.28 % )
        Info: Total interconnect delay = 2.168 ns ( 46.72 % )
Info: Shortest tpd from source pin "TEST_BUTTON" to destination pin "ETH_RESETB_E" is 16.212 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AG12; Fanout = 1; PIN Node = 'TEST_BUTTON'
    Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y0_N22; Fanout = 3; COMB Node = 'TEST_BUTTON~input'
    Info: 3: + IC(5.090 ns) + CELL(0.496 ns) = 6.550 ns; Loc. = LCCOMB_X48_Y31_N22; Fanout = 298; COMB Node = 'PinSignal_U2_O'
    Info: 4: + IC(2.552 ns) + CELL(0.324 ns) = 9.426 ns; Loc. = LCCOMB_X41_Y38_N14; Fanout = 54; COMB Node = 'EMAC32:U_Unique_MAC_System_EMAC|MAC32_MDI:U_MAC32_MDI|reset_0_o2_x'
    Info: 5: + IC(4.095 ns) + CELL(2.691 ns) = 16.212 ns; Loc. = IOOBUF_X0_Y37_N2; Fanout = 1; COMB Node = 'ETH_RESETB_E~output'
    Info: 6: + IC(0.000 ns) + CELL(0.000 ns) = 16.212 ns; Loc. = PIN_F5; Fanout = 0; PIN Node = 'ETH_RESETB_E'
    Info: Total cell delay = 4.475 ns ( 27.60 % )
    Info: Total interconnect delay = 11.737 ns ( 72.40 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings
    Info: Peak virtual memory: 275 megabytes
    Info: Processing ended: Wed Mar 06 21:28:56 2013
    Info: Elapsed time: 00:00:16
    Info: Total CPU time (on all processors): 00:00:11


