Classic Timing Analyzer report for PCF2123_RTC
Thu Mar 07 22:21:17 2013
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'JTAG_NEXUS_TCK'
  7. Clock Setup: 'CLK_BRD'
  8. tsu
  9. tco
 10. th
 11. Minimum tco
 12. Board Trace Model Assignments
 13. Input Transition Times
 14. Slow Corner Signal Integrity Metrics
 15. Fast Corner Signal Integrity Metrics
 16. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+
; Type                          ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                            ; To                                                                                                                                                            ; From Clock     ; To Clock       ; Failed Paths ;
+-------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+
; Worst-case tsu                ; N/A   ; None          ; 7.805 ns                         ; TEST_BUTTON                                                                                                                                                                     ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[15]                                                                                                     ; --             ; CLK_BRD        ; 0            ;
; Worst-case tco                ; N/A   ; None          ; 22.938 ns                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite                                                                                    ; SRAM0_A[7]                                                                                                                                                    ; CLK_BRD        ; --             ; 0            ;
; Worst-case th                 ; N/A   ; None          ; -1.725 ns                        ; SRAM1_D[0]                                                                                                                                                                      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[0]                                                    ; --             ; CLK_BRD        ; 0            ;
; Worst-case Minimum tco        ; N/A   ; None          ; 7.735 ns                         ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                               ; SRAM0_W                                                                                                                                                       ; CLK_BRD        ; --             ; 0            ;
; Clock Setup: 'CLK_BRD'        ; N/A   ; None          ; 48.98 MHz ( period = 20.418 ns ) ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD        ; CLK_BRD        ; 0            ;
; Clock Setup: 'JTAG_NEXUS_TCK' ; N/A   ; None          ; 106.66 MHz ( period = 9.376 ns ) ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z                    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0            ;
; Total number of failed paths  ;       ;               ;                                  ;                                                                                                                                                                                 ;                                                                                                                                                               ;                ;                ; 0            ;
+-------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP3C40F780C8       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; On                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; On                 ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; JTAG_NEXUS_TCK  ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLK_BRD         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                ; To                                                                                                                                                           ; From Clock     ; To Clock       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 106.66 MHz ( period = 9.376 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 9.149 ns                ;
; N/A                                     ; 111.04 MHz ( period = 9.006 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 8.766 ns                ;
; N/A                                     ; 118.47 MHz ( period = 8.441 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 8.217 ns                ;
; N/A                                     ; 123.90 MHz ( period = 8.071 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.834 ns                ;
; N/A                                     ; 127.03 MHz ( period = 7.872 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.632 ns                ;
; N/A                                     ; 127.29 MHz ( period = 7.856 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.629 ns                ;
; N/A                                     ; 127.86 MHz ( period = 7.821 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z       ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.599 ns                ;
; N/A                                     ; 128.17 MHz ( period = 7.802 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.576 ns                ;
; N/A                                     ; 132.43 MHz ( period = 7.551 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.326 ns                ;
; N/A                                     ; 133.32 MHz ( period = 7.501 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.260 ns                ;
; N/A                                     ; 133.99 MHz ( period = 7.463 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.235 ns                ;
; N/A                                     ; 134.21 MHz ( period = 7.451 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z       ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.216 ns                ;
; N/A                                     ; 135.83 MHz ( period = 7.362 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.124 ns                ;
; N/A                                     ; 135.83 MHz ( period = 7.362 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.124 ns                ;
; N/A                                     ; 135.83 MHz ( period = 7.362 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.124 ns                ;
; N/A                                     ; 135.83 MHz ( period = 7.362 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.124 ns                ;
; N/A                                     ; 135.83 MHz ( period = 7.362 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.124 ns                ;
; N/A                                     ; 135.83 MHz ( period = 7.362 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.124 ns                ;
; N/A                                     ; 135.83 MHz ( period = 7.362 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.124 ns                ;
; N/A                                     ; 136.15 MHz ( period = 7.345 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.107 ns                ;
; N/A                                     ; 136.15 MHz ( period = 7.345 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.107 ns                ;
; N/A                                     ; 136.15 MHz ( period = 7.345 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.107 ns                ;
; N/A                                     ; 136.15 MHz ( period = 7.345 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.107 ns                ;
; N/A                                     ; 136.15 MHz ( period = 7.345 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.107 ns                ;
; N/A                                     ; 136.15 MHz ( period = 7.345 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.107 ns                ;
; N/A                                     ; 136.15 MHz ( period = 7.345 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.107 ns                ;
; N/A                                     ; 137.78 MHz ( period = 7.258 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.019 ns                ;
; N/A                                     ; 137.78 MHz ( period = 7.258 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.019 ns                ;
; N/A                                     ; 137.78 MHz ( period = 7.258 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.019 ns                ;
; N/A                                     ; 137.78 MHz ( period = 7.258 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.019 ns                ;
; N/A                                     ; 137.78 MHz ( period = 7.258 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.019 ns                ;
; N/A                                     ; 137.78 MHz ( period = 7.258 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.019 ns                ;
; N/A                                     ; 137.78 MHz ( period = 7.258 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.019 ns                ;
; N/A                                     ; 137.87 MHz ( period = 7.253 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.015 ns                ;
; N/A                                     ; 137.87 MHz ( period = 7.253 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.015 ns                ;
; N/A                                     ; 137.87 MHz ( period = 7.253 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.015 ns                ;
; N/A                                     ; 137.87 MHz ( period = 7.253 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.015 ns                ;
; N/A                                     ; 137.87 MHz ( period = 7.253 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.015 ns                ;
; N/A                                     ; 137.87 MHz ( period = 7.253 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.015 ns                ;
; N/A                                     ; 137.87 MHz ( period = 7.253 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 7.015 ns                ;
; N/A                                     ; 139.16 MHz ( period = 7.186 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.947 ns                ;
; N/A                                     ; 139.16 MHz ( period = 7.186 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.947 ns                ;
; N/A                                     ; 139.16 MHz ( period = 7.186 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.947 ns                ;
; N/A                                     ; 139.16 MHz ( period = 7.186 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.947 ns                ;
; N/A                                     ; 139.16 MHz ( period = 7.186 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.947 ns                ;
; N/A                                     ; 139.16 MHz ( period = 7.186 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.947 ns                ;
; N/A                                     ; 139.16 MHz ( period = 7.186 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.947 ns                ;
; N/A                                     ; 139.53 MHz ( period = 7.167 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z        ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.940 ns                ;
; N/A                                     ; 140.00 MHz ( period = 7.143 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.897 ns                ;
; N/A                                     ; 140.29 MHz ( period = 7.128 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.882 ns                ;
; N/A                                     ; 140.86 MHz ( period = 7.099 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z              ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.852 ns                ;
; N/A                                     ; 142.27 MHz ( period = 7.029 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.783 ns                ;
; N/A                                     ; 142.37 MHz ( period = 7.024 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.786 ns                ;
; N/A                                     ; 142.37 MHz ( period = 7.024 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.786 ns                ;
; N/A                                     ; 142.37 MHz ( period = 7.024 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.786 ns                ;
; N/A                                     ; 142.37 MHz ( period = 7.024 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.786 ns                ;
; N/A                                     ; 142.37 MHz ( period = 7.024 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.786 ns                ;
; N/A                                     ; 142.37 MHz ( period = 7.024 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.786 ns                ;
; N/A                                     ; 142.37 MHz ( period = 7.024 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.786 ns                ;
; N/A                                     ; 142.61 MHz ( period = 7.012 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.767 ns                ;
; N/A                                     ; 142.63 MHz ( period = 7.011 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.772 ns                ;
; N/A                                     ; 142.63 MHz ( period = 7.011 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.772 ns                ;
; N/A                                     ; 142.63 MHz ( period = 7.011 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.772 ns                ;
; N/A                                     ; 142.63 MHz ( period = 7.011 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.772 ns                ;
; N/A                                     ; 142.63 MHz ( period = 7.011 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.772 ns                ;
; N/A                                     ; 142.63 MHz ( period = 7.011 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.772 ns                ;
; N/A                                     ; 142.63 MHz ( period = 7.011 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.772 ns                ;
; N/A                                     ; 143.53 MHz ( period = 6.967 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_28__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.728 ns                ;
; N/A                                     ; 143.53 MHz ( period = 6.967 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.728 ns                ;
; N/A                                     ; 143.53 MHz ( period = 6.967 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_29__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.728 ns                ;
; N/A                                     ; 143.53 MHz ( period = 6.967 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_0__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.728 ns                ;
; N/A                                     ; 143.53 MHz ( period = 6.967 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_3__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.728 ns                ;
; N/A                                     ; 143.53 MHz ( period = 6.967 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_1__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.728 ns                ;
; N/A                                     ; 143.53 MHz ( period = 6.967 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_5__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.728 ns                ;
; N/A                                     ; 144.15 MHz ( period = 6.937 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.700 ns                ;
; N/A                                     ; 144.49 MHz ( period = 6.921 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.697 ns                ;
; N/A                                     ; 145.62 MHz ( period = 6.867 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.644 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_24__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_21__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_14__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_13__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.05 MHz ( period = 6.847 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.594 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_24__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_21__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_14__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_13__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.41 MHz ( period = 6.830 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.577 ns                ;
; N/A                                     ; 146.52 MHz ( period = 6.825 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.587 ns                ;
; N/A                                     ; 146.52 MHz ( period = 6.825 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.587 ns                ;
; N/A                                     ; 146.52 MHz ( period = 6.825 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.587 ns                ;
; N/A                                     ; 146.52 MHz ( period = 6.825 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.587 ns                ;
; N/A                                     ; 146.52 MHz ( period = 6.825 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_16__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.587 ns                ;
; N/A                                     ; 146.52 MHz ( period = 6.825 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.587 ns                ;
; N/A                                     ; 146.52 MHz ( period = 6.825 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_20__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.587 ns                ;
; N/A                                     ; 146.89 MHz ( period = 6.808 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.570 ns                ;
; N/A                                     ; 146.89 MHz ( period = 6.808 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.570 ns                ;
; N/A                                     ; 146.89 MHz ( period = 6.808 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.570 ns                ;
; N/A                                     ; 146.89 MHz ( period = 6.808 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.570 ns                ;
; N/A                                     ; 146.89 MHz ( period = 6.808 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_16__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.570 ns                ;
; N/A                                     ; 146.89 MHz ( period = 6.808 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.570 ns                ;
; N/A                                     ; 146.89 MHz ( period = 6.808 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_20__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.570 ns                ;
; N/A                                     ; 147.65 MHz ( period = 6.773 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.514 ns                ;
; N/A                                     ; 147.97 MHz ( period = 6.758 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                  ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.499 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_24__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_21__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_14__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_13__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.30 MHz ( period = 6.743 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.489 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_24__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_21__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_14__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_13__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.485 ns                ;
; N/A                                     ; 148.61 MHz ( period = 6.729 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z              ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.469 ns                ;
; N/A                                     ; 148.79 MHz ( period = 6.721 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.482 ns                ;
; N/A                                     ; 148.79 MHz ( period = 6.721 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.482 ns                ;
; N/A                                     ; 148.79 MHz ( period = 6.721 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.482 ns                ;
; N/A                                     ; 148.79 MHz ( period = 6.721 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.482 ns                ;
; N/A                                     ; 148.79 MHz ( period = 6.721 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_16__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.482 ns                ;
; N/A                                     ; 148.79 MHz ( period = 6.721 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.482 ns                ;
; N/A                                     ; 148.79 MHz ( period = 6.721 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_20__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.482 ns                ;
; N/A                                     ; 148.90 MHz ( period = 6.716 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.478 ns                ;
; N/A                                     ; 148.90 MHz ( period = 6.716 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.478 ns                ;
; N/A                                     ; 148.90 MHz ( period = 6.716 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.478 ns                ;
; N/A                                     ; 148.90 MHz ( period = 6.716 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.478 ns                ;
; N/A                                     ; 148.90 MHz ( period = 6.716 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_16__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.478 ns                ;
; N/A                                     ; 148.90 MHz ( period = 6.716 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.478 ns                ;
; N/A                                     ; 148.90 MHz ( period = 6.716 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_20__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.478 ns                ;
; N/A                                     ; 149.72 MHz ( period = 6.679 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_19__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.443 ns                ;
; N/A                                     ; 149.72 MHz ( period = 6.679 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_22__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.443 ns                ;
; N/A                                     ; 149.72 MHz ( period = 6.679 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_18__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.443 ns                ;
; N/A                                     ; 149.72 MHz ( period = 6.679 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_25__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.443 ns                ;
; N/A                                     ; 149.72 MHz ( period = 6.679 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.443 ns                ;
; N/A                                     ; 149.72 MHz ( period = 6.679 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_11__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.443 ns                ;
; N/A                                     ; 149.72 MHz ( period = 6.679 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_9__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.443 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_2__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_24__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_21__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_15__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_14__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_12__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_13__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_6__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_7__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_8__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 149.90 MHz ( period = 6.671 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_10__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.417 ns                ;
; N/A                                     ; 150.11 MHz ( period = 6.662 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_19__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.426 ns                ;
; N/A                                     ; 150.11 MHz ( period = 6.662 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_22__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.426 ns                ;
; N/A                                     ; 150.11 MHz ( period = 6.662 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_18__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.426 ns                ;
; N/A                                     ; 150.11 MHz ( period = 6.662 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_25__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.426 ns                ;
; N/A                                     ; 150.11 MHz ( period = 6.662 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.426 ns                ;
; N/A                                     ; 150.11 MHz ( period = 6.662 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_11__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.426 ns                ;
; N/A                                     ; 150.11 MHz ( period = 6.662 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_9__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.426 ns                ;
; N/A                                     ; 150.17 MHz ( period = 6.659 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_30__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.410 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_27__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.410 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_26__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.410 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_4__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.410 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_16__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.410 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_23__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.410 ns                ;
; N/A                                     ; 150.40 MHz ( period = 6.649 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_20__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.410 ns                ;
; N/A                                     ; 150.56 MHz ( period = 6.642 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z           ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.384 ns                ;
; N/A                                     ; 151.15 MHz ( period = 6.616 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_0__Z ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.394 ns                ;
; N/A                                     ; 151.29 MHz ( period = 6.610 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z              ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.364 ns                ;
; N/A                                     ; 152.09 MHz ( period = 6.575 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_19__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.338 ns                ;
; N/A                                     ; 152.09 MHz ( period = 6.575 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_22__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.338 ns                ;
; N/A                                     ; 152.09 MHz ( period = 6.575 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_18__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.338 ns                ;
; N/A                                     ; 152.09 MHz ( period = 6.575 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_25__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.338 ns                ;
; N/A                                     ; 152.09 MHz ( period = 6.575 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.338 ns                ;
; N/A                                     ; 152.09 MHz ( period = 6.575 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_11__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.338 ns                ;
; N/A                                     ; 152.09 MHz ( period = 6.575 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                  ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_9__Z  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.338 ns                ;
; N/A                                     ; 152.21 MHz ( period = 6.570 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_22__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 152.21 MHz ( period = 6.570 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_18__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 152.21 MHz ( period = 6.570 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_25__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 152.21 MHz ( period = 6.570 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_17__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.334 ns                ;
; N/A                                     ; 152.21 MHz ( period = 6.570 ns )                    ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z           ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|RegOut_11__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; None                        ; None                      ; 6.334 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                     ;                                                                                                                                                              ;                ;                ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                            ; To                                                                                                                                                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 48.98 MHz ( period = 20.418 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.936 ns                ;
; N/A                                     ; 49.30 MHz ( period = 20.284 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.870 ns                ;
; N/A                                     ; 49.37 MHz ( period = 20.256 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.855 ns                ;
; N/A                                     ; 49.70 MHz ( period = 20.122 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.789 ns                ;
; N/A                                     ; 50.62 MHz ( period = 19.754 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.584 ns                ;
; N/A                                     ; 50.97 MHz ( period = 19.620 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.518 ns                ;
; N/A                                     ; 51.04 MHz ( period = 19.594 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.516 ns                ;
; N/A                                     ; 51.05 MHz ( period = 19.588 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.508 ns                ;
; N/A                                     ; 51.10 MHz ( period = 19.568 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.500 ns                ;
; N/A                                     ; 51.21 MHz ( period = 19.526 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.460 ns                ;
; N/A                                     ; 51.32 MHz ( period = 19.484 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite                                                                                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.498 ns                ;
; N/A                                     ; 51.34 MHz ( period = 19.478 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.552 ns                ;
; N/A                                     ; 51.35 MHz ( period = 19.476 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.435 ns                ;
; N/A                                     ; 51.35 MHz ( period = 19.476 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5                                                                                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.495 ns                ;
; N/A                                     ; 51.40 MHz ( period = 19.454 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.554 ns                ;
; N/A                                     ; 51.46 MHz ( period = 19.434 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.434 ns                ;
; N/A                                     ; 51.52 MHz ( period = 19.410 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.426 ns                ;
; N/A                                     ; 51.57 MHz ( period = 19.390 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.392 ns                ;
; N/A                                     ; 51.70 MHz ( period = 19.342 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.369 ns                ;
; N/A                                     ; 51.77 MHz ( period = 19.316 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.476 ns                ;
; N/A                                     ; 51.83 MHz ( period = 19.292 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.473 ns                ;
; N/A                                     ; 51.84 MHz ( period = 19.290 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.358 ns                ;
; N/A                                     ; 51.86 MHz ( period = 19.284 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.364 ns                ;
; N/A                                     ; 51.91 MHz ( period = 19.264 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.330 ns                ;
; N/A                                     ; 52.07 MHz ( period = 19.206 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.410 ns                ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.302 ns                ;
; N/A                                     ; 52.10 MHz ( period = 19.194 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3                                                                                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.863 ns                ;
; N/A                                     ; 52.16 MHz ( period = 19.172 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.290 ns                ;
; N/A                                     ; 52.24 MHz ( period = 19.144 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.358 ns                ;
; N/A                                     ; 52.45 MHz ( period = 19.066 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.236 ns                ;
; N/A                                     ; 52.50 MHz ( period = 19.046 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.228 ns                ;
; N/A                                     ; 52.51 MHz ( period = 19.044 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.278 ns                ;
; N/A                                     ; 52.57 MHz ( period = 19.024 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1                                                                                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.778 ns                ;
; N/A                                     ; 52.64 MHz ( period = 18.998 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.295 ns                ;
; N/A                                     ; 52.68 MHz ( period = 18.982 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.277 ns                ;
; N/A                                     ; 52.87 MHz ( period = 18.916 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4                                                                                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.724 ns                ;
; N/A                                     ; 53.03 MHz ( period = 18.858 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.250 ns                ;
; N/A                                     ; 53.07 MHz ( period = 18.842 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.248 ns                ;
; N/A                                     ; 53.08 MHz ( period = 18.838 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.216 ns                ;
; N/A                                     ; 53.09 MHz ( period = 18.836 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.119 ns                ;
; N/A                                     ; 53.27 MHz ( period = 18.772 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.142 ns                ;
; N/A                                     ; 53.39 MHz ( period = 18.730 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0                                                                                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.121 ns                ;
; N/A                                     ; 53.42 MHz ( period = 18.720 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.116 ns                ;
; N/A                                     ; 53.42 MHz ( period = 18.720 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.086 ns                ;
; N/A                                     ; 53.53 MHz ( period = 18.680 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.167 ns                ;
; N/A                                     ; 53.71 MHz ( period = 18.620 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.114 ns                ;
; N/A                                     ; 53.74 MHz ( period = 18.608 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 53.75 MHz ( period = 18.604 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.118 ns                ;
; N/A                                     ; 53.77 MHz ( period = 18.598 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.001 ns                ;
; N/A                                     ; 53.83 MHz ( period = 18.578 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.046 ns                ;
; N/A                                     ; 53.87 MHz ( period = 18.562 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0[4]                                                                 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.100 ns                ;
; N/A                                     ; 53.88 MHz ( period = 18.560 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_3                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.099 ns                ;
; N/A                                     ; 53.97 MHz ( period = 18.530 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.066 ns                ;
; N/A                                     ; 54.08 MHz ( period = 18.492 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_2                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.065 ns                ;
; N/A                                     ; 54.11 MHz ( period = 18.480 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.006 ns                ;
; N/A                                     ; 54.19 MHz ( period = 18.454 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.004 ns                ;
; N/A                                     ; 54.20 MHz ( period = 18.450 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.043 ns                ;
; N/A                                     ; 54.21 MHz ( period = 18.448 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.996 ns                ;
; N/A                                     ; 54.24 MHz ( period = 18.437 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.831 ns               ;
; N/A                                     ; 54.34 MHz ( period = 18.402 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.019 ns                ;
; N/A                                     ; 54.35 MHz ( period = 18.400 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0[4]                                                                 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.019 ns                ;
; N/A                                     ; 54.35 MHz ( period = 18.398 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_3                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 9.018 ns                ;
; N/A                                     ; 54.37 MHz ( period = 18.392 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.952 ns                ;
; N/A                                     ; 54.39 MHz ( period = 18.386 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.948 ns                ;
; N/A                                     ; 54.40 MHz ( period = 18.382 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.987 ns                ;
; N/A                                     ; 54.45 MHz ( period = 18.364 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2                                                                                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.938 ns                ;
; N/A                                     ; 54.47 MHz ( period = 18.360 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.937 ns                ;
; N/A                                     ; 54.54 MHz ( period = 18.335 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.729 ns               ;
; N/A                                     ; 54.54 MHz ( period = 18.334 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.963 ns                ;
; N/A                                     ; 54.56 MHz ( period = 18.330 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_2                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.984 ns                ;
; N/A                                     ; 54.58 MHz ( period = 18.322 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.918 ns                ;
; N/A                                     ; 54.66 MHz ( period = 18.296 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.694 ns               ;
; N/A                                     ; 54.66 MHz ( period = 18.294 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.922 ns                ;
; N/A                                     ; 54.71 MHz ( period = 18.279 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.675 ns               ;
; N/A                                     ; 54.84 MHz ( period = 18.236 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.920 ns                ;
; N/A                                     ; 54.94 MHz ( period = 18.202 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.857 ns                ;
; N/A                                     ; 54.98 MHz ( period = 18.190 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.908 ns                ;
; N/A                                     ; 55.01 MHz ( period = 18.178 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.896 ns                ;
; N/A                                     ; 55.08 MHz ( period = 18.154 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.529 ns               ;
; N/A                                     ; 55.11 MHz ( period = 18.144 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.852 ns                ;
; N/A                                     ; 55.14 MHz ( period = 18.136 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.512 ns               ;
; N/A                                     ; 55.18 MHz ( period = 18.124 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.818 ns                ;
; N/A                                     ; 55.24 MHz ( period = 18.104 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.807 ns                ;
; N/A                                     ; 55.24 MHz ( period = 18.102 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.766 ns                ;
; N/A                                     ; 55.28 MHz ( period = 18.090 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.842 ns                ;
; N/A                                     ; 55.30 MHz ( period = 18.084 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.478 ns               ;
; N/A                                     ; 55.43 MHz ( period = 18.040 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.916 ns               ;
; N/A                                     ; 55.46 MHz ( period = 18.032 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.772 ns                ;
; N/A                                     ; 55.51 MHz ( period = 18.015 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.850 ns               ;
; N/A                                     ; 55.52 MHz ( period = 18.010 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.818 ns                ;
; N/A                                     ; 55.54 MHz ( period = 18.006 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.395 ns               ;
; N/A                                     ; 55.57 MHz ( period = 17.995 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.872 ns               ;
; N/A                                     ; 55.58 MHz ( period = 17.992 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.812 ns                ;
; N/A                                     ; 55.61 MHz ( period = 17.982 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2                                                                                        ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.747 ns                ;
; N/A                                     ; 55.62 MHz ( period = 17.979 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.332 ns               ;
; N/A                                     ; 55.66 MHz ( period = 17.966 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.373 ns               ;
; N/A                                     ; 55.69 MHz ( period = 17.958 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.800 ns                ;
; N/A                                     ; 55.71 MHz ( period = 17.949 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.353 ns               ;
; N/A                                     ; 55.74 MHz ( period = 17.942 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.319 ns               ;
; N/A                                     ; 55.75 MHz ( period = 17.938 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.766 ns                ;
; N/A                                     ; 55.78 MHz ( period = 17.926 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.724 ns                ;
; N/A                                     ; 55.79 MHz ( period = 17.924 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.783 ns                ;
; N/A                                     ; 55.80 MHz ( period = 17.920 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[3]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.786 ns                ;
; N/A                                     ; 55.83 MHz ( period = 17.913 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.748 ns               ;
; N/A                                     ; 55.85 MHz ( period = 17.906 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[2]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.716 ns                ;
; N/A                                     ; 55.85 MHz ( period = 17.904 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.749 ns                ;
; N/A                                     ; 55.87 MHz ( period = 17.900 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.747 ns                ;
; N/A                                     ; 55.87 MHz ( period = 17.898 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0[4]                                                                 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.748 ns                ;
; N/A                                     ; 55.88 MHz ( period = 17.896 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_3                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.747 ns                ;
; N/A                                     ; 55.88 MHz ( period = 17.894 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.670 ns                ;
; N/A                                     ; 55.92 MHz ( period = 17.882 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.729 ns               ;
; N/A                                     ; 55.98 MHz ( period = 17.864 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.230 ns               ;
; N/A                                     ; 56.00 MHz ( period = 17.857 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.694 ns               ;
; N/A                                     ; 56.02 MHz ( period = 17.852 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.232 ns               ;
; N/A                                     ; 56.03 MHz ( period = 17.847 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.218 ns               ;
; N/A                                     ; 56.07 MHz ( period = 17.834 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.631 ns                ;
; N/A                                     ; 56.09 MHz ( period = 17.828 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_2                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.713 ns                ;
; N/A                                     ; 56.13 MHz ( period = 17.816 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.655 ns               ;
; N/A                                     ; 56.15 MHz ( period = 17.809 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_2                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.648 ns               ;
; N/A                                     ; 56.15 MHz ( period = 17.809 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.193 ns               ;
; N/A                                     ; 56.16 MHz ( period = 17.807 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.188 ns               ;
; N/A                                     ; 56.18 MHz ( period = 17.800 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.154 ns               ;
; N/A                                     ; 56.24 MHz ( period = 17.780 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.621 ns                ;
; N/A                                     ; 56.29 MHz ( period = 17.764 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.140 ns               ;
; N/A                                     ; 56.30 MHz ( period = 17.762 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a6~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.608 ns                ;
; N/A                                     ; 56.31 MHz ( period = 17.758 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_1                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.699 ns                ;
; N/A                                     ; 56.32 MHz ( period = 17.757 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.111 ns               ;
; N/A                                     ; 56.33 MHz ( period = 17.752 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram_1|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.603 ns                ;
; N/A                                     ; 56.33 MHz ( period = 17.752 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.131 ns               ;
; N/A                                     ; 56.34 MHz ( period = 17.750 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.617 ns               ;
; N/A                                     ; 56.35 MHz ( period = 17.745 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.116 ns               ;
; N/A                                     ; 56.36 MHz ( period = 17.744 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.699 ns                ;
; N/A                                     ; 56.37 MHz ( period = 17.741 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.144 ns               ;
; N/A                                     ; 56.43 MHz ( period = 17.720 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.664 ns                ;
; N/A                                     ; 56.45 MHz ( period = 17.716 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.589 ns               ;
; N/A                                     ; 56.46 MHz ( period = 17.712 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0[4]                                                                 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.664 ns                ;
; N/A                                     ; 56.47 MHz ( period = 17.710 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_3                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.663 ns                ;
; N/A                                     ; 56.48 MHz ( period = 17.705 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.573 ns               ;
; N/A                                     ; 56.50 MHz ( period = 17.698 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.105 ns               ;
; N/A                                     ; 56.52 MHz ( period = 17.693 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.575 ns               ;
; N/A                                     ; 56.53 MHz ( period = 17.689 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.062 ns               ;
; N/A                                     ; 56.54 MHz ( period = 17.688 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a4~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.098 ns               ;
; N/A                                     ; 56.54 MHz ( period = 17.686 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.541 ns               ;
; N/A                                     ; 56.54 MHz ( period = 17.686 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.530 ns               ;
; N/A                                     ; 56.54 MHz ( period = 17.686 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a4~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[1]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.647 ns                ;
; N/A                                     ; 56.57 MHz ( period = 17.678 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_19                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.552 ns               ;
; N/A                                     ; 56.57 MHz ( period = 17.676 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[0]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.658 ns                ;
; N/A                                     ; 56.59 MHz ( period = 17.671 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.051 ns               ;
; N/A                                     ; 56.59 MHz ( period = 17.670 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_21                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.050 ns               ;
; N/A                                     ; 56.60 MHz ( period = 17.668 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.048 ns               ;
; N/A                                     ; 56.60 MHz ( period = 17.668 ns )                    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10                                                                                       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|ram_1_reg_41                                                                    ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.591 ns                ;
; N/A                                     ; 56.60 MHz ( period = 17.667 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_22                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.047 ns               ;
; N/A                                     ; 56.62 MHz ( period = 17.663 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.043 ns               ;
; N/A                                     ; 56.62 MHz ( period = 17.662 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.497 ns               ;
; N/A                                     ; 56.64 MHz ( period = 17.654 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.036 ns               ;
; N/A                                     ; 56.64 MHz ( period = 17.654 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.508 ns               ;
; N/A                                     ; 56.65 MHz ( period = 17.653 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.030 ns               ;
; N/A                                     ; 56.66 MHz ( period = 17.648 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.531 ns               ;
; N/A                                     ; 56.68 MHz ( period = 17.642 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_2                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.629 ns                ;
; N/A                                     ; 56.69 MHz ( period = 17.641 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.497 ns               ;
; N/A                                     ; 56.69 MHz ( period = 17.639 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.482 ns               ;
; N/A                                     ; 56.74 MHz ( period = 17.624 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2[4]                                                                   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.614 ns                ;
; N/A                                     ; 56.75 MHz ( period = 17.620 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0[4]                                                                 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.599 ns                ;
; N/A                                     ; 56.76 MHz ( period = 17.618 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a2~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_3                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.598 ns                ;
; N/A                                     ; 56.77 MHz ( period = 17.614 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.487 ns               ;
; N/A                                     ; 56.77 MHz ( period = 17.614 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.985 ns               ;
; N/A                                     ; 56.81 MHz ( period = 17.603 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.984 ns               ;
; N/A                                     ; 56.81 MHz ( period = 17.603 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a2~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.984 ns               ;
; N/A                                     ; 56.82 MHz ( period = 17.598 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.453 ns               ;
; N/A                                     ; 56.83 MHz ( period = 17.596 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a3~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0_1                                                                  ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.618 ns                ;
; N/A                                     ; 56.83 MHz ( period = 17.595 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.969 ns               ;
; N/A                                     ; 56.84 MHz ( period = 17.592 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.430 ns               ;
; N/A                                     ; 56.84 MHz ( period = 17.592 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.980 ns               ;
; N/A                                     ; 56.87 MHz ( period = 17.585 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.402 ns               ;
; N/A                                     ; 56.87 MHz ( period = 17.584 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a0~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.964 ns               ;
; N/A                                     ; 56.87 MHz ( period = 17.583 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.959 ns               ;
; N/A                                     ; 56.88 MHz ( period = 17.582 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_21                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.958 ns               ;
; N/A                                     ; 56.88 MHz ( period = 17.580 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.956 ns               ;
; N/A                                     ; 56.89 MHz ( period = 17.579 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_22                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.955 ns               ;
; N/A                                     ; 56.89 MHz ( period = 17.577 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.960 ns               ;
; N/A                                     ; 56.90 MHz ( period = 17.576 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.930 ns               ;
; N/A                                     ; 56.90 MHz ( period = 17.575 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.951 ns               ;
; N/A                                     ; 56.90 MHz ( period = 17.575 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_21                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.929 ns               ;
; N/A                                     ; 56.91 MHz ( period = 17.573 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.927 ns               ;
; N/A                                     ; 56.91 MHz ( period = 17.572 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_22                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.926 ns               ;
; N/A                                     ; 56.91 MHz ( period = 17.571 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.950 ns               ;
; N/A                                     ; 56.92 MHz ( period = 17.570 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_21                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.949 ns               ;
; N/A                                     ; 56.92 MHz ( period = 17.568 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.947 ns               ;
; N/A                                     ; 56.92 MHz ( period = 17.568 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.922 ns               ;
; N/A                                     ; 56.92 MHz ( period = 17.567 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_22                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.946 ns               ;
; N/A                                     ; 56.93 MHz ( period = 17.566 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a6~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.944 ns               ;
; N/A                                     ; 56.93 MHz ( period = 17.566 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.440 ns               ;
; N/A                                     ; 56.94 MHz ( period = 17.563 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                                                                            ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.942 ns               ;
; N/A                                     ; 56.95 MHz ( period = 17.560 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_8                                                                      ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.393 ns               ;
; N/A                                     ; 56.95 MHz ( period = 17.559 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a3~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.915 ns               ;
; N/A                                     ; 56.95 MHz ( period = 17.559 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.431 ns               ;
; N/A                                     ; 56.95 MHz ( period = 17.558 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u3:Memory_MCU_u3_component|altsyncram:altsyncram_component|altsyncram_ihg2:auto_generated|ram_block1a7~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0   ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.497 ns                ;
; N/A                                     ; 56.95 MHz ( period = 17.558 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a1~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26                                                                     ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 17.433 ns               ;
; N/A                                     ; 56.97 MHz ( period = 17.554 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u2:Memory_MCU_u2_component|altsyncram:altsyncram_component|altsyncram_hhg2:auto_generated|ram_block1a5~portb_we_reg       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_1                                                                             ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 16.935 ns               ;
; N/A                                     ; 56.97 MHz ( period = 17.554 ns )                    ; Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u4:Memory_MCU_u4_component|altsyncram:altsyncram_component|altsyncram_jhg2:auto_generated|ram_block1a5~porta_address_reg0 ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|RADDR_REG2_0[4]                                                                 ; CLK_BRD    ; CLK_BRD  ; None                        ; None                      ; 8.590 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                                 ;                                                                                                                                                                 ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+---------------------------------------------------------------------------------------------+----------+
; Slack                                   ; Required tsu                                        ; Actual tsu ; From        ; To                                                                                          ; To Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+---------------------------------------------------------------------------------------------+----------+
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[0]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[8]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[16]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[9]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[17]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[1]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[2]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[10]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[7]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[3]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[5]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[6]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[4]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.805 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[15]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.736 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|SPI_DOUT                                     ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.678 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[0]                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.678 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[1]                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.678 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[2]                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.678 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[3]                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.678 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[4]                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.678 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[5]                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.678 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[6]                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.678 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[7]                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[24]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[25]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[26]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[18]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[31]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[27]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[19]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[29]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[30]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[28]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[22]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[23]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[21]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.512 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[20]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.489 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[11]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.489 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[12]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[31]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[24]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[28]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[19]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[20]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[16]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[22]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[23]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[18]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[21]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[30]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[29]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[17]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[26]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[25]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.461 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[27]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.411 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[14]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.411 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[13]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.178 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|INTENABLE[3]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.172 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|INTENABLE[7]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.160 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|INTENABLE[0]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.160 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|INTENABLE[1]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.160 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|INTENABLE[2]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.160 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|INTENABLE[6]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.160 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|INTENABLE[4]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 7.160 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|INTENABLE[5]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[7]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[12]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[9]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[14]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[8]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[11]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[6]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[5]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[4]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[3]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[2]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[13]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[15]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[10]                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[1]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.928 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TimeoutCounter[0]                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.867 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[25]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.867 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[26]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.867 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[18]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.867 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[21]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.867 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[27]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.867 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[19]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.867 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[29]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.818 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[15]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.818 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[14]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.818 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[10]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.818 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[4]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.818 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[12]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[0]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[8]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[9]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[7]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[1]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[2]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[6]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[11]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[5]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[13]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.779 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[3]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.755 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|gpo_2                                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.755 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|gpo_7                                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.755 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|gpo_4                                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.716 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|gpo_0                                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.716 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|gpo_1                                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.716 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|gpo_3                                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.716 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|gpo_5                                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.716 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|gpo_6                                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.534 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[23]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.534 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[17]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.534 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[31]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.525 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[24]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.525 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[16]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.525 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[22]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.525 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[30]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.525 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[20]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.525 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[28]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[24]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[16]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[23]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[17]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[25]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[22]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[26]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[18]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[21]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[31]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[30]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[27]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[19]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[20]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[29]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.461 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[28]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[0]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[8]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[9]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[7]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[15]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[1]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[2]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[6]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[14]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[10]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[11]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[5]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[13]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[3]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[4]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.392 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[12]                                 ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.370 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[2]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.370 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[3]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.370 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[4]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.370 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[1]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.370 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[0]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.370 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[5]                                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.256 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[8]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.256 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[0]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.256 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[9]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.256 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[6]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.256 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[7]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.226 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_STATUS[7]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.151 ns   ; TEST_BUTTON ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.151 ns   ; TEST_BUTTON ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.151 ns   ; TEST_BUTTON ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5] ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.151 ns   ; TEST_BUTTON ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4] ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.151 ns   ; TEST_BUTTON ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.151 ns   ; TEST_BUTTON ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.151 ns   ; TEST_BUTTON ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2] ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.151 ns   ; TEST_BUTTON ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3] ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.069 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|wordlen[5]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 6.067 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|wordlen[3]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.954 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|IsInstrumentOnline                  ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.954 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|GoOnlineFF1                         ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.954 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|GoOfflineFF0                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.954 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|GoOfflineFF1                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.820 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[3]                                     ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.820 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[0]                                     ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.818 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|IsOffline                           ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.806 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|RxSetFF1                            ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.806 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|SPI_CLK                                      ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.789 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|GoOnlineFF0                         ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.661 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[1]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.661 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[2]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.661 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[3]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.661 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[5]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.661 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[4]                                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.600 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|RxSetFF0                            ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.585 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_STATUS[1]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.582 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_STATUS[3]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.574 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_STATUS[0]                        ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.548 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TxAcknowledgeFF1                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.393 ns   ; TEST_BUTTON ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TxAcknowledgeFF0                    ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.325 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|wordlen[4]                                   ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.289 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[1]                                     ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.289 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[2]                                     ; CLK_BRD  ;
; N/A                                     ; None                                                ; 5.268 ns   ; TEST_BUTTON ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[4]                                     ; CLK_BRD  ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;             ;                                                                                             ;          ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+---------------------------------------------------------------------------------------------+----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+-------------+------------+
; Slack                                   ; Required tco                                        ; Actual tco ; From                                                                                                     ; To          ; From Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+-------------+------------+
; N/A                                     ; None                                                ; 22.938 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.934 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.793 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.718 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.708 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.654 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.582 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.561 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0             ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.556 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.485 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.392 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.378 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2             ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.376 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.357 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.248 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.212 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.187 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2                 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 22.030 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10                ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.681 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.677 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.584 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.580 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.536 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.461 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.451 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.439 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.397 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.364 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.354 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.347 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.343 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.325 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.304 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0             ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.300 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.299 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.228 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.228 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.207 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0             ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.202 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.202 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.135 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.131 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.127 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.124 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_9 ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.121 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2             ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.119 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.117 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.100 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.099 ns  ; TSK3000A_MDU:U_System_MCU_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                       ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.063 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.039 ns  ; TSK3000A_MDU:U_System_MCU_SubPart_MDU|MultDiv:U_MultDiv|State_i_8__Z                                     ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.038 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.024 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2             ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.022 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 21.003 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.991 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.991 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.970 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0             ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.965 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.955 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.939 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_27                ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.930 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2                 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.929 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.925 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.894 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.894 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.887 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.883 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.858 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.833 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2                 ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.801 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.787 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2             ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.785 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.784 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.773 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10                ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.766 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.742 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.736 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_26                ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.709 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.699 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.676 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10                ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.667 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.657 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.657 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.645 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.642 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.638 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.621 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.603 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.596 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2                 ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.573 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.552 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0             ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.547 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.531 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.510 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0             ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.506 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead              ; SRAM0_A[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.505 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.497 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.476 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.467 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.463 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.439 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10                ; SRAM0_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.434 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.422 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.412 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.383 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.369 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2             ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.367 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.358 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.348 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.341 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.327 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2             ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.325 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.322 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.306 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.286 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.273 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.265 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0             ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.260 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.247 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.239 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.237 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.203 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.197 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.189 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.183 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.178 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2                 ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.161 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.155 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.151 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.145 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.141 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.136 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2                 ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.113 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_D[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.113 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.111 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_3                 ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.109 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_D[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.109 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.109 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.105 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.099 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_D[10] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.096 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.095 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_D[10] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.090 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_0             ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.085 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_4                 ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.083 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_D[5]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.082 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2             ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.080 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.079 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_D[5]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.061 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.021 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10                ; SRAM1_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.018 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.014 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_6                 ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.014 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.010 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM0_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 20.000 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.999 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.995 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.979 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_10                ; SRAM1_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.968 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_D[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.968 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.967 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                     ; SRAM1_E     ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.964 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM0_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.954 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_D[10] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.952 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_7                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.938 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM0_D[5]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.935 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM0_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.925 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM0_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.925 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM1_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.921 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_1                 ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.916 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_5                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.915 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM1_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.907 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_2             ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.907 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                     ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.905 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_8                 ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.893 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM1_D[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.893 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM1_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.891 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_2                 ; SRAM0_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.889 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM0_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.886 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_9                 ; SRAM0_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.883 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM1_D[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.883 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM1_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.879 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM1_D[10] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.879 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM0_D[11] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.873 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM0_UB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.871 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM0_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.869 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM1_D[10] ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.867 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_9 ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.863 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_VLWcst_0                 ; SRAM0_D[5]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.861 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM1_D[8]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.854 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_3             ; SRAM1_D[7]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.853 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_1             ; SRAM0_D[5]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.850 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.846 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_A[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.842 ns  ; TSK3000A_MDU:U_System_MCU_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                       ; SRAM1_LB    ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.837 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite             ; SRAM0_D[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.833 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5             ; SRAM0_D[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.829 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM1_D[6]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.829 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM1_D[9]  ; CLK_BRD    ;
; N/A                                     ; None                                                ; 19.825 ns  ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_4             ; SRAM0_D[11] ; CLK_BRD    ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                                          ;             ;            ;
+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+-------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Minimum Slack                           ; Required th                                         ; Actual th ; From           ; To                                                                                                                                                                   ; To Clock       ;
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; N/A                                     ; None                                                ; -1.725 ns ; SRAM1_D[0]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[0]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -1.832 ns ; SRAM1_D[12]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[12]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -1.890 ns ; SRAM0_D[13]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[29]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.030 ns ; SRAM0_D[3]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[19]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.169 ns ; SRAM0_D[0]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[16]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.192 ns ; SRAM1_D[11]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[11]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.239 ns ; SRAM1_D[3]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[3]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.263 ns ; SRAM0_D[15]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[31]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.263 ns ; SRAM0_D[8]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[24]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.284 ns ; SRAM1_D[1]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[1]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.286 ns ; SRAM0_D[6]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[22]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.293 ns ; SRAM0_D[10]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[26]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.360 ns ; SRAM0_D[14]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[30]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.387 ns ; SRAM0_D[5]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[21]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.397 ns ; SRAM1_D[13]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[13]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.405 ns ; SRAM1_D[10]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[10]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.422 ns ; SRAM0_D[11]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[27]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.487 ns ; SRAM0_D[7]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[23]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.494 ns ; SRAM0_D[12]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[28]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.568 ns ; SRAM1_D[0]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[0]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.588 ns ; SRAM1_D[5]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[5]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.612 ns ; SRAM0_D[2]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[18]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.615 ns ; SRAM1_D[2]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[2]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.620 ns ; SRAM0_D[1]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[17]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.638 ns ; SRAM0_D[9]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[25]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.660 ns ; SRAM1_D[4]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[4]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.677 ns ; SRAM1_D[12]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[12]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.679 ns ; SRAM0_D[4]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[20]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.681 ns ; SRAM1_D[14]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[14]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.690 ns ; SRAM0_D[13]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[29]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.716 ns ; SRAM1_D[8]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[8]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.718 ns ; JTAG_NEXUS_TDI ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.762 ns ; SPI_DIN        ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[0]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.822 ns ; SRAM1_D[6]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[6]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.825 ns ; JTAG_NEXUS_TMS ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                                                              ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.825 ns ; JTAG_NEXUS_TMS ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[2]                                                              ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.826 ns ; JTAG_NEXUS_TMS ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[1]                                                              ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.829 ns ; JTAG_NEXUS_TDI ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.829 ns ; JTAG_NEXUS_TMS ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[0]                                                              ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -2.913 ns ; SRAM1_D[7]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[7]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.944 ns ; SPI_DIN        ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[0]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -2.965 ns ; SRAM1_D[9]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[9]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.036 ns ; SRAM1_D[3]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[3]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.038 ns ; SRAM1_D[11]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[11]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.110 ns ; JTAG_NEXUS_TDI ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_3__Z                   ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -3.111 ns ; JTAG_NEXUS_TMS ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z            ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -3.111 ns ; JTAG_NEXUS_TMS ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z            ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -3.111 ns ; JTAG_NEXUS_TMS ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z            ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -3.111 ns ; JTAG_NEXUS_TMS ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z            ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -3.122 ns ; JTAG_NEXUS_TDI ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_31__Z                   ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -3.131 ns ; SRAM0_D[3]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[19]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.247 ns ; SRAM1_D[15]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[15]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.248 ns ; SRAM1_D[10]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[10]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.262 ns ; SRAM0_D[0]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[16]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.265 ns ; SRAM0_D[11]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[27]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.294 ns ; SRAM0_D[12]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[28]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.436 ns ; SRAM1_D[15]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[15]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.445 ns ; SRAM0_D[5]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[21]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.475 ns ; SRAM0_D[4]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[20]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.475 ns ; JTAG_NEXUS_TDI ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -3.496 ns ; SRAM1_D[13]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[13]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.550 ns ; JTAG_NEXUS_TDI ; TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; -3.683 ns ; SRAM0_D[7]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[23]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.719 ns ; SRAM0_D[14]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[30]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.726 ns ; SRAM0_D[10]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[26]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.744 ns ; SRAM1_D[1]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[1]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.747 ns ; SRAM0_D[8]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[24]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.759 ns ; TEST_BUTTON    ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                   ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.770 ns ; SRAM0_D[2]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[18]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.775 ns ; SRAM0_D[15]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[31]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.778 ns ; SRAM0_D[6]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[22]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.785 ns ; SRAM1_D[4]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[4]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.791 ns ; SRAM1_D[5]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[5]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.846 ns ; TEST_BUTTON    ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.846 ns ; TEST_BUTTON    ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                    ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.847 ns ; SRAM0_D[9]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[25]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.894 ns ; SRAM1_D[14]    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[14]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.908 ns ; TEST_BUTTON    ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.933 ns ; SRAM1_D[8]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[8]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -3.942 ns ; SRAM1_D[6]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[6]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.006 ns ; SRAM1_D[2]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[2]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.111 ns ; SRAM0_D[1]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[17]                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.146 ns ; SRAM1_D[9]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[9]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.372 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|ctrl[0]                                                                                                               ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.376 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.391 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|stat[0]                                                                                                               ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.447 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                               ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.448 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                               ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.457 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                                ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.458 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                               ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.460 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                                ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.533 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[1]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.533 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[2]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.533 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[3]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.533 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[5]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.533 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[4]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.598 ns ; SRAM1_D[7]     ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[7]                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.626 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.626 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.659 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clk                                                                                                                   ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.683 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.738 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[3]                                                                                                              ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.738 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[0]                                                                                                              ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.747 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[23]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.747 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[17]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.747 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[31]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.784 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[8]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.784 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[0]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.784 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[9]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.784 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[6]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -4.784 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkdiv[7]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[1]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[0]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[3]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[5]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[4]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[2]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[6]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[7]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[8]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.068 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|clkval[9]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.077 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[4]                                                                                                              ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.077 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[24]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.077 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[16]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.077 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[22]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.077 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[30]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.077 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[20]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.077 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[28]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.098 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[1]                                                                                                              ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.098 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|state[2]                                                                                                              ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.098 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[3]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.098 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[4]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.098 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|bitcount[5]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.121 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[5]                                                                                               ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.123 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_TXBUFFER[4]                                                                                               ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.134 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|wordlen[4]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.202 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TxAcknowledgeFF0                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[0]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[8]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[9]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[7]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[15]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[1]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[2]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[6]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[14]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[10]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[11]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[5]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[13]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[3]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[4]                                                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.350 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[12]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.357 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TxAcknowledgeFF1                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[24]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[16]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[23]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[17]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[25]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[22]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[26]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[18]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[21]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[31]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[30]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[27]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[19]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[20]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[29]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.361 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|shiftreg[28]                                                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[0]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[8]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[9]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[7]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[1]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[2]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[6]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[11]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[5]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[13]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.369 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[3]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.383 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                 ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.390 ns ; TEST_BUTTON    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.390 ns ; TEST_BUTTON    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.390 ns ; TEST_BUTTON    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.390 ns ; TEST_BUTTON    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.390 ns ; TEST_BUTTON    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.390 ns ; TEST_BUTTON    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                           ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.390 ns ; TEST_BUTTON    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.390 ns ; TEST_BUTTON    ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                          ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.391 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                 ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.394 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                 ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.409 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|RxSetFF0                                                                                                     ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.412 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[15]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.412 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[14]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.412 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[10]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.412 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[4]                                                                                                             ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.412 ns ; TEST_BUTTON    ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|txdata[12]                                                                                                            ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.598 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|GoOnlineFF0                                                                                                  ; CLK_BRD        ;
; N/A                                     ; None                                                ; -5.615 ns ; TEST_BUTTON    ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|RxSetFF1                                                                                                     ; CLK_BRD        ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;                ;                                                                                                                                                                      ;                ;
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum tco                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+----------------+------------------------------------------------------------------------------------------------------------------------+----------------+----------------+
; Minimum Slack                           ; Required Min tco                                    ; Actual Min tco ; From                                                                                                                   ; To             ; From Clock     ;
+-----------------------------------------+-----------------------------------------------------+----------------+------------------------------------------------------------------------------------------------------------------------+----------------+----------------+
; N/A                                     ; None                                                ; 7.735 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_W        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.050 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_15                        ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.276 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_3                         ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.309 ns       ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|SPI_DOUT                                                                ; SPI_DOUT       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.369 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_29                        ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.446 ns       ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|ctrl_2                                                                  ; SPI_MODE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.569 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.666 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_20                        ; SRAM0_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.714 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.731 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.737 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.767 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_17                        ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.784 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.824 ns       ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|ctrl_1                                                                  ; SPI_SEL        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.825 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.835 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.851 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.851 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.856 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.867 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.871 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.876 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.882 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.885 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.887 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.892 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.906 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.926 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.929 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.936 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.969 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.970 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.976 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_26                        ; SRAM0_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.980 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.996 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 8.996 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.001 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.006 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.012 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.016 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.023 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_21                        ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.030 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.032 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.037 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.051 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.071 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.081 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.100 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.111 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_6                         ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.114 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.188 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.188 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.218 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_31                        ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.232 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.245 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.273 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.286 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_27                        ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.287 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.289 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.304 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_22                        ; SRAM0_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.333 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.333 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.377 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.383 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_9                         ; SRAM1_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.418 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.432 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.433 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_4                         ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.449 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.533 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.549 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.559 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.563 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.563 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.583 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_W        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.594 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.595 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.605 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.629 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.631 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_LB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.634 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.678 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.694 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.704 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.708 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.708 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.740 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.750 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.761 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_2                         ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.784 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_0                         ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.791 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.796 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.797 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.802 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.838 ns       ; WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|SPI_CLK                                                                 ; SPI_CLK        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.844 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.849 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.857 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                                   ; SRAM0_A[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.885 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_19                        ; SRAM1_A[17]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.885 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.890 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.895 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.897 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_30                        ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.900 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.911 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.911 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.914 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_LB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.916 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.916 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.916 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.917 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.919 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.921 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.927 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.931 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.932 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.936 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.945 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.947 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.950 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.952 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.952 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.956 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.956 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_5                         ; SRAM1_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.957 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.959 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_16                        ; SRAM0_D[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.966 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.971 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.986 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.991 ns       ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.992 ns       ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_25                        ; SRAM0_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 9.996 ns       ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.001 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.029 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.034 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.062 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM0_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.067 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_19                        ; SRAM0_A[17]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.078 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_17                        ; SRAM0_A[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.116 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_19                        ; SRAM0_D[3]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.160 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.165 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_OE       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.167 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                   ; SRAM0_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.186 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_18                        ; SRAM0_D[2]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.195 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_2                         ; SRAM1_A[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.202 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.233 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_18                        ; SRAM0_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.248 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.248 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.253 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.253 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[4]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.283 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_24                        ; SRAM0_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.291 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                                   ; SRAM1_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.292 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.297 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.333 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.337 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.338 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.347 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.352 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.357 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemByteLane_0                        ; SRAM0_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.357 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_18                        ; SRAM1_A[16]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.368 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_14                        ; SRAM1_D[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.373 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                                   ; SRAM1_A[17]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.382 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_7                         ; SRAM1_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.445 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_12                        ; SRAM1_A[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.482 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]      ; SRAM1_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.499 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_12                        ; SRAM1_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.508 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_28                        ; SRAM0_D[12]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.509 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.514 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.555 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                                   ; SRAM0_A[17]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.561 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_1                         ; SRAM1_D[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.580 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_LB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.593 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.598 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[5]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.609 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.614 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[10]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.619 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.621 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_8                         ; SRAM1_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.623 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.623 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.624 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[11]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.628 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.628 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[6]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.636 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                                   ; SRAM1_A[15]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.652 ns      ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                        ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 10.652 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_23                        ; SRAM0_D[7]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.655 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM1_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.660 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM1_D[8]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.665 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]     ; SRAM0_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.666 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_15                        ; SRAM0_A[13]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.670 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM1_LB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.670 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_D[9]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.676 ns      ; TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|tapstate_r_i[3]                ; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ;
; N/A                                     ; None                                                ; 10.695 ns      ; Configurable_INTERCON_MEM:U_System_INTERCON_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0] ; SRAM0_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.723 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                      ; SRAM1_A[0]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.741 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemByteLane_3                        ; SRAM0_UB       ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.772 ns      ; Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]        ; SRAM0_E        ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.810 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_16                        ; SRAM1_A[14]    ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.848 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                                    ; SRAM0_A[1]     ; CLK_BRD        ;
; N/A                                     ; None                                                ; 10.850 ns      ; TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                                   ; SRAM1_A[14]    ; CLK_BRD        ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                ;                                                                                                                        ;                ;                ;
+-----------------------------------------+-----------------------------------------------------+----------------+------------------------------------------------------------------------------------------------------------------------+----------------+----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SPI_CLK        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SPI_DOUT       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SPI_MODE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SPI_SEL        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[16]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_A[17]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_E        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_LB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_OE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_UB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_W        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[16]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_A[17]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_E        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_LB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_OE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_UB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_W        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM0_D[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; SRAM1_D[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; SRAM0_D[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TCK          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TMS          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK_BRD                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; TEST_BUTTON             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TDI          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SPI_DIN                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DCLK~           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SPI_CLK        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SPI_DOUT       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SPI_MODE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00566 V          ; 0.066 V                              ; 0.016 V                              ; 6.89e-010 s                 ; 6.77e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00566 V         ; 0.066 V                             ; 0.016 V                             ; 6.89e-010 s                ; 6.77e-010 s                ; Yes                       ; Yes                       ;
; SPI_SEL        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM0_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00566 V          ; 0.066 V                              ; 0.016 V                              ; 6.89e-010 s                 ; 6.77e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00566 V         ; 0.066 V                             ; 0.016 V                             ; 6.89e-010 s                ; 6.77e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM0_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.33 V              ; -0.00201 V          ; 0.092 V                              ; 0.05 V                               ; 3.78e-009 s                 ; 3.59e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.33 V             ; -0.00201 V         ; 0.092 V                             ; 0.05 V                              ; 3.78e-009 s                ; 3.59e-009 s                ; Yes                       ; Yes                       ;
; SRAM1_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM1_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM1_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-009 s                 ; 3.76e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-009 s                ; 3.76e-009 s                ; Yes                       ; Yes                       ;
; SRAM0_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00566 V          ; 0.066 V                              ; 0.016 V                              ; 6.89e-010 s                 ; 6.77e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00566 V         ; 0.066 V                             ; 0.016 V                             ; 6.89e-010 s                ; 6.77e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-007 V                  ; 2.34 V              ; -0.00564 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-010 s                 ; 8.83e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-007 V                 ; 2.34 V             ; -0.00564 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-010 s                ; 8.83e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-007 V                   ; 2.35 V              ; -0.00118 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-010 s                 ; 4.97e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-007 V                  ; 2.35 V             ; -0.00118 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-010 s                ; 4.97e-010 s                ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SPI_CLK        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SPI_DOUT       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SPI_MODE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.72 V              ; -0.0405 V           ; 0.163 V                              ; 0.077 V                              ; 4.51e-010 s                 ; 4.33e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.72 V             ; -0.0405 V          ; 0.163 V                             ; 0.077 V                             ; 4.51e-010 s                ; 4.33e-010 s                ; No                        ; Yes                       ;
; SPI_SEL        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM0_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.72 V              ; -0.0405 V           ; 0.163 V                              ; 0.077 V                              ; 4.51e-010 s                 ; 4.33e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.72 V             ; -0.0405 V          ; 0.163 V                             ; 0.077 V                             ; 4.51e-010 s                ; 4.33e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM0_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.64 V              ; -0.011 V            ; 0.212 V                              ; 0.198 V                              ; 2.38e-009 s                 ; 2.29e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.64 V             ; -0.011 V           ; 0.212 V                             ; 0.198 V                             ; 2.38e-009 s                ; 2.29e-009 s                ; No                        ; Yes                       ;
; SRAM1_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM1_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM1_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-009 s                 ; 2.37e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-009 s                ; 2.37e-009 s                ; No                        ; Yes                       ;
; SRAM0_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM0_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM0_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.72 V              ; -0.0405 V           ; 0.163 V                              ; 0.077 V                              ; 4.51e-010 s                 ; 4.33e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.72 V             ; -0.0405 V          ; 0.163 V                             ; 0.077 V                             ; 4.51e-010 s                ; 4.33e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-008 V                  ; 2.71 V              ; -0.0343 V           ; 0.253 V                              ; 0.066 V                              ; 4.96e-010 s                 ; 5.19e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-008 V                 ; 2.71 V             ; -0.0343 V          ; 0.253 V                             ; 0.066 V                             ; 4.96e-010 s                ; 5.19e-010 s                ; No                        ; Yes                       ;
; SRAM1_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
; SRAM1_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-008 V                  ; 2.73 V              ; -0.0561 V           ; 0.191 V                              ; 0.122 V                              ; 2.69e-010 s                 ; 2.76e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-008 V                 ; 2.73 V             ; -0.0561 V          ; 0.191 V                             ; 0.122 V                             ; 2.69e-010 s                ; 2.76e-010 s                ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Copyright (C) 1991-2009 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Thu Mar 07 22:21:07 2013
Info: Command: quartus_tan PCF2123_RTC
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found USE_TIMEQUEST_TIMING_ANALYZER=ON. The Classic Timing Analyzer is not the default timing analysis tool during full compilation
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "JTAG_NEXUS_TCK" is an undefined clock
    Info: Assuming node "CLK_BRD" is an undefined clock
Warning: Clock Setting "CLK_BRD" is unassigned
Warning: Clock Setting "JTAG_NEXUS_TCK" is unassigned
Info: Clock "JTAG_NEXUS_TCK" has Internal fmax of 106.66 MHz between source register "TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z" and destination register "TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg" (period= 9.376 ns)
    Info: + Longest register to register delay is 9.149 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X27_Y19_N29; Fanout = 2; REG Node = 'TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z'
        Info: 2: + IC(3.177 ns) + CELL(0.177 ns) = 3.354 ns; Loc. = LCCOMB_X45_Y25_N4; Fanout = 1; COMB Node = 'TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tdo_0_i_m2_x'
        Info: 3: + IC(0.264 ns) + CELL(0.324 ns) = 3.942 ns; Loc. = LCCOMB_X45_Y25_N18; Fanout = 1; COMB Node = 'TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tdo_u_0_0'
        Info: 4: + IC(0.302 ns) + CELL(0.473 ns) = 4.717 ns; Loc. = LCCOMB_X45_Y25_N8; Fanout = 1; COMB Node = 'TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tdo_u_0_2'
        Info: 5: + IC(0.474 ns) + CELL(0.472 ns) = 5.663 ns; Loc. = LCCOMB_X46_Y25_N18; Fanout = 8; COMB Node = 'TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tdo_u_0'
        Info: 6: + IC(1.501 ns) + CELL(0.327 ns) = 7.491 ns; Loc. = LCCOMB_X51_Y24_N6; Fanout = 2; COMB Node = 'TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg_0_0_g2_x'
        Info: 7: + IC(1.193 ns) + CELL(0.465 ns) = 9.149 ns; Loc. = FF_X49_Y25_N9; Fanout = 1; REG Node = 'TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg'
        Info: Total cell delay = 2.238 ns ( 24.46 % )
        Info: Total interconnect delay = 6.911 ns ( 75.54 % )
    Info: - Smallest clock skew is 0.013 ns
        Info: + Shortest clock path from clock "JTAG_NEXUS_TCK" to destination register is 3.279 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_Y27; Fanout = 1; CLK Node = 'JTAG_NEXUS_TCK'
            Info: 2: + IC(0.000 ns) + CELL(1.048 ns) = 1.048 ns; Loc. = IOIBUF_X67_Y22_N15; Fanout = 1; COMB Node = 'JTAG_NEXUS_TCK~input'
            Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.245 ns; Loc. = CLKCTRL_G9; Fanout = 350; COMB Node = 'JTAG_NEXUS_TCK~inputclkctrl'
            Info: 4: + IC(1.354 ns) + CELL(0.680 ns) = 3.279 ns; Loc. = FF_X49_Y25_N9; Fanout = 1; REG Node = 'TERMINAL:U_System_SOFT_TERMINAL|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg'
            Info: Total cell delay = 1.728 ns ( 52.70 % )
            Info: Total interconnect delay = 1.551 ns ( 47.30 % )
        Info: - Longest clock path from clock "JTAG_NEXUS_TCK" to source register is 3.266 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_Y27; Fanout = 1; CLK Node = 'JTAG_NEXUS_TCK'
            Info: 2: + IC(0.000 ns) + CELL(1.048 ns) = 1.048 ns; Loc. = IOIBUF_X67_Y22_N15; Fanout = 1; COMB Node = 'JTAG_NEXUS_TCK~input'
            Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.245 ns; Loc. = CLKCTRL_G9; Fanout = 350; COMB Node = 'JTAG_NEXUS_TCK~inputclkctrl'
            Info: 4: + IC(1.341 ns) + CELL(0.680 ns) = 3.266 ns; Loc. = FF_X27_Y19_N29; Fanout = 2; REG Node = 'TSK3000A_OCDS:U_System_MCU_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_0__Z'
            Info: Total cell delay = 1.728 ns ( 52.91 % )
            Info: Total interconnect delay = 1.538 ns ( 47.09 % )
    Info: + Micro clock to output delay of source is 0.261 ns
    Info: + Micro setup delay of destination is -0.021 ns
Info: Clock "CLK_BRD" has Internal fmax of 48.98 MHz between source memory "Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0" and destination memory "TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0" (period= 20.418 ns)
    Info: + Longest memory to memory delay is 9.936 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y32_N0; Fanout = 1; MEM Node = 'Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(3.204 ns) = 3.204 ns; Loc. = M9K_X40_Y32_N0; Fanout = 1; MEM Node = 'Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|q_a[0]'
        Info: 3: + IC(1.256 ns) + CELL(0.177 ns) = 4.637 ns; Loc. = LCCOMB_X41_Y29_N30; Fanout = 1; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_ID_EX:U_Regs_ID_EX|Reg_IR_2_0_0_0__g2_0_2238_m3_x'
        Info: 4: + IC(0.843 ns) + CELL(0.177 ns) = 5.657 ns; Loc. = LCCOMB_X42_Y26_N26; Fanout = 22; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|IMem_DataOut_3_0_0_0'
        Info: 5: + IC(0.364 ns) + CELL(0.471 ns) = 6.492 ns; Loc. = LCCOMB_X42_Y26_N10; Fanout = 4; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Decode:U_PipeStage_Decode|local_muxc_ctrl_1_0_0_o2_6_0_0'
        Info: 6: + IC(0.281 ns) + CELL(0.177 ns) = 6.950 ns; Loc. = LCCOMB_X42_Y26_N16; Fanout = 12; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Decode:U_PipeStage_Decode|local_muxc_ctrl_1_0_0_o2_6_0'
        Info: 7: + IC(0.320 ns) + CELL(0.177 ns) = 7.447 ns; Loc. = LCCOMB_X42_Y26_N18; Fanout = 8; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Decode:U_PipeStage_Decode|local_alumode_1_0_a6_1_0'
        Info: 8: + IC(0.281 ns) + CELL(0.177 ns) = 7.905 ns; Loc. = LCCOMB_X42_Y26_N6; Fanout = 4; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Decode:U_PipeStage_Decode|local_rs_1_i_o6_0'
        Info: 9: + IC(0.902 ns) + CELL(0.177 ns) = 8.984 ns; Loc. = LCCOMB_X39_Y26_N18; Fanout = 3; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rs_Index_Local_0_0_0_1_3'
        Info: 10: + IC(0.864 ns) + CELL(0.088 ns) = 9.936 ns; Loc. = M9K_X40_Y26_N0; Fanout = 32; MEM Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0'
        Info: Total cell delay = 4.825 ns ( 48.56 % )
        Info: Total interconnect delay = 5.111 ns ( 51.44 % )
    Info: - Smallest clock skew is -0.047 ns
        Info: + Shortest clock path from clock "CLK_BRD" to destination memory is 3.558 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
            Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
            Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 1926; COMB Node = 'CLK_BRD~inputclkctrl'
            Info: 4: + IC(1.366 ns) + CELL(1.031 ns) = 3.558 ns; Loc. = M9K_X40_Y26_N0; Fanout = 32; MEM Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|altsyncram:ram|altsyncram_j5g1:auto_generated|ram_block1a0~portb_address_reg0'
            Info: Total cell delay = 1.995 ns ( 56.07 % )
            Info: Total interconnect delay = 1.563 ns ( 43.93 % )
        Info: - Longest clock path from clock "CLK_BRD" to source memory is 3.605 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
            Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
            Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 1926; COMB Node = 'CLK_BRD~inputclkctrl'
            Info: 4: + IC(1.338 ns) + CELL(1.106 ns) = 3.605 ns; Loc. = M9K_X40_Y32_N0; Fanout = 1; MEM Node = 'Memory_MCU:U_System_MCU_SubPart_BootMemory|Memory_MCU_u1:Memory_MCU_u1_component|altsyncram:altsyncram_component|altsyncram_ghg2:auto_generated|ram_block1a0~porta_address_reg0'
            Info: Total cell delay = 2.070 ns ( 57.42 % )
            Info: Total interconnect delay = 1.535 ns ( 42.58 % )
    Info: + Micro clock to output delay of source is 0.294 ns
    Info: + Micro setup delay of destination is -0.068 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: tsu for register "WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[0]" (data pin = "TEST_BUTTON", clock pin = "CLK_BRD") is 7.805 ns
    Info: + Longest pin to register delay is 11.027 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AG12; Fanout = 1; PIN Node = 'TEST_BUTTON'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y0_N22; Fanout = 2; COMB Node = 'TEST_BUTTON~input'
        Info: 3: + IC(4.950 ns) + CELL(0.324 ns) = 6.238 ns; Loc. = LCCOMB_X43_Y30_N30; Fanout = 144; COMB Node = 'PinSignal_U8_O'
        Info: 4: + IC(1.222 ns) + CELL(0.481 ns) = 7.941 ns; Loc. = LCCOMB_X49_Y30_N20; Fanout = 3; COMB Node = 'WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|SPI_CLK_0_0_g0_i_o4_x'
        Info: 5: + IC(0.326 ns) + CELL(0.437 ns) = 8.704 ns; Loc. = LCCOMB_X49_Y30_N8; Fanout = 33; COMB Node = 'WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata_1_0_31__g0_i_o4'
        Info: 6: + IC(1.528 ns) + CELL(0.795 ns) = 11.027 ns; Loc. = FF_X46_Y26_N11; Fanout = 3; REG Node = 'WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[0]'
        Info: Total cell delay = 3.001 ns ( 27.22 % )
        Info: Total interconnect delay = 8.026 ns ( 72.78 % )
    Info: + Micro setup delay of destination is -0.021 ns
    Info: - Shortest clock path from clock "CLK_BRD" to destination register is 3.201 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
        Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 1926; COMB Node = 'CLK_BRD~inputclkctrl'
        Info: 4: + IC(1.360 ns) + CELL(0.680 ns) = 3.201 ns; Loc. = FF_X46_Y26_N11; Fanout = 3; REG Node = 'WB_SPI32:U_System_RTC_SubPart_Port|spi32:U_spi|rxdata[0]'
        Info: Total cell delay = 1.644 ns ( 51.36 % )
        Info: Total interconnect delay = 1.557 ns ( 48.64 % )
Info: tco from clock "CLK_BRD" to destination pin "SRAM0_A[7]" through register "TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite" is 22.938 ns
    Info: + Longest clock path from clock "CLK_BRD" to source register is 3.206 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
        Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 1926; COMB Node = 'CLK_BRD~inputclkctrl'
        Info: 4: + IC(1.365 ns) + CELL(0.680 ns) = 3.206 ns; Loc. = FF_X37_Y27_N25; Fanout = 3; REG Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite'
        Info: Total cell delay = 1.644 ns ( 51.28 % )
        Info: Total interconnect delay = 1.562 ns ( 48.72 % )
    Info: + Micro clock to output delay of source is 0.261 ns
    Info: + Longest register to pin delay is 19.471 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y27_N25; Fanout = 3; REG Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_DoRegWrite'
        Info: 2: + IC(0.631 ns) + CELL(0.486 ns) = 1.117 ns; Loc. = LCCOMB_X37_Y27_N30; Fanout = 1; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|DataHazardResolverA:U_DataHazardResolverA|rega_usedatafromma3_NE_1'
        Info: 3: + IC(0.310 ns) + CELL(0.472 ns) = 1.899 ns; Loc. = LCCOMB_X37_Y27_N20; Fanout = 37; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|DataHazardResolverA:U_DataHazardResolverA|rega_usedatafromma3_NE'
        Info: 4: + IC(0.581 ns) + CELL(0.433 ns) = 2.913 ns; Loc. = LCCOMB_X38_Y27_N20; Fanout = 25; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|DataHazardResolverA:U_DataHazardResolverA|LoadHazard_MA'
        Info: 5: + IC(0.282 ns) + CELL(0.177 ns) = 3.372 ns; Loc. = LCCOMB_X38_Y27_N8; Fanout = 38; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Execute:U_Execute|MDU_EnableControl:U_MDU_EnableControl|Enable_x'
        Info: 6: + IC(0.290 ns) + CELL(0.327 ns) = 3.989 ns; Loc. = LCCOMB_X38_Y27_N30; Fanout = 4; COMB Node = 'TSK3000A_MDU:U_System_MCU_SubPart_MDU|MultDiv:U_MultDiv|Busy_i'
        Info: 7: + IC(0.538 ns) + CELL(0.327 ns) = 4.854 ns; Loc. = LCCOMB_X38_Y26_N2; Fanout = 18; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|PipeStage_Execute:U_Execute|ExecuteBusy:U_ExecuteBusy|Busy_EX_x'
        Info: 8: + IC(0.580 ns) + CELL(0.491 ns) = 5.925 ns; Loc. = LCCOMB_X37_Y26_N26; Fanout = 4; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|Main_STB_O_1_0_a2_1_x'
        Info: 9: + IC(0.367 ns) + CELL(0.471 ns) = 6.763 ns; Loc. = LCCOMB_X37_Y26_N8; Fanout = 31; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|MainMemoryIsData_0_o2'
        Info: 10: + IC(2.451 ns) + CELL(0.487 ns) = 9.701 ns; Loc. = LCCOMB_X57_Y29_N26; Fanout = 2; COMB Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|Main_ADR_O_0_0_0_1_x_9'
        Info: 11: + IC(5.670 ns) + CELL(4.100 ns) = 19.471 ns; Loc. = IOOBUF_X0_Y40_N9; Fanout = 1; COMB Node = 'SRAM0_A[7]~output'
        Info: 12: + IC(0.000 ns) + CELL(0.000 ns) = 19.471 ns; Loc. = PIN_H7; Fanout = 0; PIN Node = 'SRAM0_A[7]'
        Info: Total cell delay = 7.771 ns ( 39.91 % )
        Info: Total interconnect delay = 11.700 ns ( 60.09 % )
Info: th for register "TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[0]" (data pin = "SRAM1_D[0]", clock pin = "CLK_BRD") is -1.725 ns
    Info: + Longest clock path from clock "CLK_BRD" to destination register is 3.199 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
        Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 1926; COMB Node = 'CLK_BRD~inputclkctrl'
        Info: 4: + IC(1.358 ns) + CELL(0.680 ns) = 3.199 ns; Loc. = FF_X43_Y29_N15; Fanout = 1; REG Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[0]'
        Info: Total cell delay = 1.644 ns ( 51.39 % )
        Info: Total interconnect delay = 1.555 ns ( 48.61 % )
    Info: + Micro hold delay of destination is 0.212 ns
    Info: - Shortest pin to register delay is 5.136 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_J17; Fanout = 1; PIN Node = 'SRAM1_D[0]'
        Info: 2: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = IOIBUF_X43_Y43_N15; Fanout = 1; COMB Node = 'SRAM1_D[0]~input'
        Info: 3: + IC(3.910 ns) + CELL(0.177 ns) = 5.021 ns; Loc. = LCCOMB_X43_Y29_N14; Fanout = 2; COMB Node = 'Configurable_INTERCON_MEM:U_System_INTERCON_MEM|INST_m0_DAT_O_0'
        Info: 4: + IC(0.000 ns) + CELL(0.115 ns) = 5.136 ns; Loc. = FF_X43_Y29_N15; Fanout = 1; REG Node = 'TSK3000A_MCU:U_System_MCU_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_IMain[0]'
        Info: Total cell delay = 1.226 ns ( 23.87 % )
        Info: Total interconnect delay = 3.910 ns ( 76.13 % )
Info: Minimum tco from clock "CLK_BRD" to destination pin "SRAM0_W" through register "Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]" is 7.735 ns
    Info: + Shortest clock path from clock "CLK_BRD" to source register is 3.196 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_A14; Fanout = 1; CLK Node = 'CLK_BRD'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X34_Y43_N15; Fanout = 1; COMB Node = 'CLK_BRD~input'
        Info: 3: + IC(0.197 ns) + CELL(0.000 ns) = 1.161 ns; Loc. = CLKCTRL_G14; Fanout = 1926; COMB Node = 'CLK_BRD~inputclkctrl'
        Info: 4: + IC(1.355 ns) + CELL(0.680 ns) = 3.196 ns; Loc. = FF_X43_Y30_N15; Fanout = 9; REG Node = 'Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]'
        Info: Total cell delay = 1.644 ns ( 51.44 % )
        Info: Total interconnect delay = 1.552 ns ( 48.56 % )
    Info: + Micro clock to output delay of source is 0.261 ns
    Info: + Shortest register to pin delay is 4.278 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X43_Y30_N15; Fanout = 9; REG Node = 'Configurable_MEM:U_System_MEM|PCF2123_RTC__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]'
        Info: 2: + IC(1.617 ns) + CELL(2.661 ns) = 4.278 ns; Loc. = IOOBUF_X67_Y29_N2; Fanout = 1; COMB Node = 'SRAM0_W~output'
        Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 4.278 ns; Loc. = PIN_K22; Fanout = 0; PIN Node = 'SRAM0_W'
        Info: Total cell delay = 2.661 ns ( 62.20 % )
        Info: Total interconnect delay = 1.617 ns ( 37.80 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 266 megabytes
    Info: Processing ended: Thu Mar 07 22:21:20 2013
    Info: Elapsed time: 00:00:13
    Info: Total CPU time (on all processors): 00:00:08


