Analysis & Synthesis report for QT10N01
Wed Sep 02 00:12:04 2020
Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                              ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Failed - Wed Sep 02 00:12:03 2020           ;
; Quartus Prime Version       ; 20.1.0 Build 711 06/05/2020 SJ Lite Edition ;
; Revision Name               ; QT10N01                                     ;
; Top-level Entity Name       ; QT10N01                                     ;
; Family                      ; Cyclone V                                   ;
; Logic utilization (in ALMs) ; N/A until Partition Merge                   ;
; Total registers             ; N/A until Partition Merge                   ;
; Total pins                  ; N/A until Partition Merge                   ;
; Total virtual pins          ; N/A until Partition Merge                   ;
; Total block memory bits     ; N/A until Partition Merge                   ;
; Total PLLs                  ; N/A until Partition Merge                   ;
; Total DLLs                  ; N/A until Partition Merge                   ;
+-----------------------------+---------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                          ; Setting            ; Default Value      ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                          ; 5CSEBA6U23I7       ;                    ;
; Top-level entity name                                                           ; QT10N01            ; QT10N01            ;
; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
; Use smart compilation                                                           ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
; Enable compact report table                                                     ; Off                ; Off                ;
; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
; Preserve fewer node names                                                       ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                        ; Auto               ; Auto               ;
; Safe State Machine                                                              ; Off                ; Off                ;
; Extract Verilog State Machines                                                  ; On                 ; On                 ;
; Extract VHDL State Machines                                                     ; On                 ; On                 ;
; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
; Parallel Synthesis                                                              ; On                 ; On                 ;
; DSP Block Balancing                                                             ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                              ; On                 ; On                 ;
; Power-Up Don't Care                                                             ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
; Remove Duplicate Registers                                                      ; On                 ; On                 ;
; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
; Optimization Technique                                                          ; Balanced           ; Balanced           ;
; Carry Chain Length                                                              ; 70                 ; 70                 ;
; Auto Carry Chains                                                               ; On                 ; On                 ;
; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
; Auto ROM Replacement                                                            ; On                 ; On                 ;
; Auto RAM Replacement                                                            ; On                 ; On                 ;
; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
; Strict RAM Replacement                                                          ; Off                ; Off                ;
; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                           ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
; Report Parameter Settings                                                       ; On                 ; On                 ;
; Report Source Assignments                                                       ; On                 ; On                 ;
; Report Connectivity Checks                                                      ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
; HDL message level                                                               ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                            ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
; Block Design Naming                                                             ; Auto               ; Auto               ;
; SDC constraint protection                                                       ; Off                ; Off                ;
; Synthesis Effort                                                                ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
+---------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
+----------------------------+-------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
    Info: Processing started: Wed Sep 02 00:11:05 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off QT10N01 -c QT10N01
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file counter.v
    Info (12023): Found entity 1: counter File: P:/Projects/DE10-Nano-Projects/QT10N01/counter.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file qt10n01.bdf
    Info (12023): Found entity 1: QT10N01
Info (12021): Found 1 design units, including 1 entities, in source file kittcounter.v
    Info (12023): Found entity 1: KITTcounter File: P:/Projects/DE10-Nano-Projects/QT10N01/KITTcounter.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file frequencydivider.v
    Info (12023): Found entity 1: frequencyDivider File: P:/Projects/DE10-Nano-Projects/QT10N01/frequencyDivider.v Line: 1
Critical Warning (10226): Verilog HDL Port Declaration warning at KITTcounter.v(4): port declaration for "lights" declares packed dimensions but the data type declaration does not File: P:/Projects/DE10-Nano-Projects/QT10N01/KITTcounter.v Line: 4
Info (10499): HDL info at KITTcounter.v(3): see declaration for object "lights" File: P:/Projects/DE10-Nano-Projects/QT10N01/KITTcounter.v Line: 3
Info (12127): Elaborating entity "QT10N01" for the top level hierarchy
Warning (275085): Found inconsistent dimensions for element "lights"
Warning (275080): Converted elements in bus name "lights" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "lights[0]" to "lights0"
    Warning (275081): Converted element name(s) from "lights[1]" to "lights1"
    Warning (275081): Converted element name(s) from "lights[2]" to "lights2"
    Warning (275081): Converted element name(s) from "lights[3]" to "lights3"
    Warning (275081): Converted element name(s) from "lights[4]" to "lights4"
    Warning (275081): Converted element name(s) from "lights[5]" to "lights5"
    Warning (275081): Converted element name(s) from "lights[6]" to "lights6"
    Warning (275081): Converted element name(s) from "lights[7]" to "lights7"
Info (12128): Elaborating entity "frequencyDivider" for hierarchy "frequencyDivider:inst"
Info (12128): Elaborating entity "KITTcounter" for hierarchy "KITTcounter:inst2"
Warning (10230): Verilog HDL assignment warning at KITTcounter.v(12): truncated value with size 8 to match size of target (1) File: P:/Projects/DE10-Nano-Projects/QT10N01/KITTcounter.v Line: 12
Warning (10230): Verilog HDL assignment warning at KITTcounter.v(25): truncated value with size 32 to match size of target (1) File: P:/Projects/DE10-Nano-Projects/QT10N01/KITTcounter.v Line: 25
Warning (10230): Verilog HDL assignment warning at KITTcounter.v(33): truncated value with size 8 to match size of target (1) File: P:/Projects/DE10-Nano-Projects/QT10N01/KITTcounter.v Line: 33
Error (12009): Node "lights0" is missing source
Error (12009): Node "lights1" is missing source
Error (12009): Node "lights2" is missing source
Error (12009): Node "lights3" is missing source
Error (12009): Node "lights4" is missing source
Error (12009): Node "lights5" is missing source
Error (12009): Node "lights6" is missing source
Error (12009): Node "lights7" is missing source
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 15 warnings
    Error: Peak virtual memory: 4787 megabytes
    Error: Processing ended: Wed Sep 02 00:12:05 2020
    Error: Elapsed time: 00:01:00
    Error: Total CPU time (on all processors): 00:00:23


