Classic Timing Analyzer report for clock1
Sat Nov 08 22:28:43 2008
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk50mhz'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
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and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                     ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------+--------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                  ; To                 ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------+--------------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 64.700 ns                        ; clock1_timer:292|v_seconds[2]         ; seg_e              ; clk50mhz   ; --       ; 0            ;
; Clock Setup: 'clk50mhz'      ; N/A   ; None          ; 34.01 MHz ( period = 29.400 ns ) ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|33 ; clk50mhz   ; clk50mhz ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                       ;                    ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------+--------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EPF10K10LC84-4     ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; Off                ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Minimum tpd to report                                               ; 0 ns               ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk50mhz        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk50mhz'                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                  ; To                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 34.01 MHz ( period = 29.400 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 11.100 ns               ;
; N/A                                     ; 34.01 MHz ( period = 29.400 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 11.100 ns               ;
; N/A                                     ; 34.01 MHz ( period = 29.400 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 11.100 ns               ;
; N/A                                     ; 34.01 MHz ( period = 29.400 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 11.100 ns               ;
; N/A                                     ; 34.01 MHz ( period = 29.400 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 11.100 ns               ;
; N/A                                     ; 34.01 MHz ( period = 29.400 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 11.100 ns               ;
; N/A                                     ; 35.21 MHz ( period = 28.400 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 10.600 ns               ;
; N/A                                     ; 35.21 MHz ( period = 28.400 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 10.600 ns               ;
; N/A                                     ; 40.32 MHz ( period = 24.800 ns )                    ; clock1_base:283|div1000_reg:18|reg[3] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 8.800 ns                ;
; N/A                                     ; 40.32 MHz ( period = 24.800 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 8.800 ns                ;
; N/A                                     ; 40.32 MHz ( period = 24.800 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 8.800 ns                ;
; N/A                                     ; 40.65 MHz ( period = 24.600 ns )                    ; clock1_base:283|div1000_reg:18|reg[1] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 8.700 ns                ;
; N/A                                     ; 40.65 MHz ( period = 24.600 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 8.700 ns                ;
; N/A                                     ; 40.65 MHz ( period = 24.600 ns )                    ; clock1_base:283|div50_reg:17|reg[2]   ; clock1_base:283|31                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 8.700 ns                ;
; N/A                                     ; 40.65 MHz ( period = 24.600 ns )                    ; clock1_base:283|div1000_reg:21|reg[3] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 8.700 ns                ;
; N/A                                     ; 42.74 MHz ( period = 23.400 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 19.800 ns               ;
; N/A                                     ; 45.66 MHz ( period = 21.900 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 18.300 ns               ;
; N/A                                     ; 45.66 MHz ( period = 21.900 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 18.300 ns               ;
; N/A                                     ; 45.87 MHz ( period = 21.800 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_minute[5]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 18.200 ns               ;
; N/A                                     ; 45.87 MHz ( period = 21.800 ns )                    ; clock1_timer:292|v_seconds[1]         ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 18.200 ns               ;
; N/A                                     ; 45.87 MHz ( period = 21.800 ns )                    ; clock1_timer:292|v_seconds[4]         ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 18.200 ns               ;
; N/A                                     ; 46.08 MHz ( period = 21.700 ns )                    ; clock1_timer:292|v_hour[2]            ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 18.100 ns               ;
; N/A                                     ; 46.08 MHz ( period = 21.700 ns )                    ; clock1_timer:292|v_hour[2]            ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 18.100 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; clock1_base:283|div50_reg:17|reg[1]   ; clock1_base:283|31                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 46.95 MHz ( period = 21.300 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_minute[3]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.700 ns               ;
; N/A                                     ; 46.95 MHz ( period = 21.300 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_minute[1]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.700 ns               ;
; N/A                                     ; 46.95 MHz ( period = 21.300 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_minute[2]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.700 ns               ;
; N/A                                     ; 46.95 MHz ( period = 21.300 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_minute[4]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.700 ns               ;
; N/A                                     ; 46.95 MHz ( period = 21.300 ns )                    ; clock1_timer:292|v_seconds[5]         ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.700 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; clock1_timer:292|v_hour[1]            ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.600 ns               ;
; N/A                                     ; 47.17 MHz ( period = 21.200 ns )                    ; clock1_timer:292|v_hour[1]            ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.600 ns               ;
; N/A                                     ; 48.08 MHz ( period = 20.800 ns )                    ; clock1_timer:292|v_hour[5]            ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.200 ns               ;
; N/A                                     ; 48.08 MHz ( period = 20.800 ns )                    ; clock1_timer:292|v_hour[5]            ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.200 ns               ;
; N/A                                     ; 48.31 MHz ( period = 20.700 ns )                    ; clock1_timer:292|v_hour[4]            ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.100 ns               ;
; N/A                                     ; 48.31 MHz ( period = 20.700 ns )                    ; clock1_timer:292|v_hour[4]            ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 17.100 ns               ;
; N/A                                     ; 49.02 MHz ( period = 20.400 ns )                    ; clock1_base:283|div50_reg:17|reg[4]   ; clock1_base:283|31                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.600 ns                ;
; N/A                                     ; 49.26 MHz ( period = 20.300 ns )                    ; clock1_timer:292|v_seconds[1]         ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.700 ns               ;
; N/A                                     ; 49.26 MHz ( period = 20.300 ns )                    ; clock1_timer:292|v_seconds[4]         ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.700 ns               ;
; N/A                                     ; 49.26 MHz ( period = 20.300 ns )                    ; clock1_timer:292|v_seconds[1]         ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.700 ns               ;
; N/A                                     ; 49.26 MHz ( period = 20.300 ns )                    ; clock1_timer:292|v_seconds[4]         ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.700 ns               ;
; N/A                                     ; 49.26 MHz ( period = 20.300 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.800 ns               ;
; N/A                                     ; 49.26 MHz ( period = 20.300 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.700 ns               ;
; N/A                                     ; 49.26 MHz ( period = 20.300 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.700 ns               ;
; N/A                                     ; 49.26 MHz ( period = 20.300 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.700 ns               ;
; N/A                                     ; 49.50 MHz ( period = 20.200 ns )                    ; clock1_timer:292|v_seconds[1]         ; clock1_timer:292|v_minute[5]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.600 ns               ;
; N/A                                     ; 49.50 MHz ( period = 20.200 ns )                    ; clock1_timer:292|v_seconds[4]         ; clock1_timer:292|v_minute[5]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.600 ns               ;
; N/A                                     ; 49.50 MHz ( period = 20.200 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.600 ns               ;
; N/A                                     ; 49.50 MHz ( period = 20.200 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.600 ns               ;
; N/A                                     ; 49.50 MHz ( period = 20.200 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.600 ns               ;
; N/A                                     ; 49.50 MHz ( period = 20.200 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.600 ns               ;
; N/A                                     ; 49.50 MHz ( period = 20.200 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.600 ns               ;
; N/A                                     ; 49.50 MHz ( period = 20.200 ns )                    ; clock1_base:283|div1000_reg:21|reg[0] ; clock1_base:283|div1000_reg:21|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.600 ns               ;
; N/A                                     ; 50.00 MHz ( period = 20.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[2] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 50.00 MHz ( period = 20.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[4] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 50.00 MHz ( period = 20.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[2] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 50.00 MHz ( period = 20.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[9] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 50.00 MHz ( period = 20.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[4] ; clock1_base:283|33                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 50.51 MHz ( period = 19.800 ns )                    ; clock1_base:283|div50_reg:17|reg[3]   ; clock1_base:283|31                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 50.51 MHz ( period = 19.800 ns )                    ; clock1_base:283|div50_reg:17|reg[0]   ; clock1_base:283|31                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 50.51 MHz ( period = 19.800 ns )                    ; clock1_timer:292|v_seconds[5]         ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.200 ns               ;
; N/A                                     ; 50.51 MHz ( period = 19.800 ns )                    ; clock1_timer:292|v_seconds[5]         ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.200 ns               ;
; N/A                                     ; 50.51 MHz ( period = 19.800 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.300 ns               ;
; N/A                                     ; 50.51 MHz ( period = 19.800 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.200 ns               ;
; N/A                                     ; 50.51 MHz ( period = 19.800 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.200 ns               ;
; N/A                                     ; 50.51 MHz ( period = 19.800 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.200 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[1]         ; clock1_timer:292|v_minute[3]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[4]         ; clock1_timer:292|v_minute[3]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[1]         ; clock1_timer:292|v_minute[1]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[4]         ; clock1_timer:292|v_minute[1]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[1]         ; clock1_timer:292|v_minute[2]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[4]         ; clock1_timer:292|v_minute[2]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[5]         ; clock1_timer:292|v_minute[5]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[1]         ; clock1_timer:292|v_minute[4]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[4]         ; clock1_timer:292|v_minute[4]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_hour[1]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_hour[2]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_hour[3]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_timer:292|v_seconds[0]         ; clock1_timer:292|v_hour[4]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 50.76 MHz ( period = 19.700 ns )                    ; clock1_base:283|div1000_reg:21|reg[1] ; clock1_base:283|div1000_reg:21|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 16.100 ns               ;
; N/A                                     ; 51.02 MHz ( period = 19.600 ns )                    ; clock1_base:283|div1000_reg:18|reg[9] ; clock1_base:283|32                    ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 51.28 MHz ( period = 19.500 ns )                    ; clock1_timer:292|v_hour[2]            ; clock1_timer:292|v_hour[1]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 51.28 MHz ( period = 19.500 ns )                    ; clock1_timer:292|v_hour[2]            ; clock1_timer:292|v_hour[2]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 51.28 MHz ( period = 19.500 ns )                    ; clock1_timer:292|v_hour[2]            ; clock1_timer:292|v_hour[3]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 51.28 MHz ( period = 19.500 ns )                    ; clock1_timer:292|v_hour[2]            ; clock1_timer:292|v_hour[4]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 51.55 MHz ( period = 19.400 ns )                    ; clock1_timer:292|v_seconds[3]         ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.800 ns               ;
; N/A                                     ; 51.81 MHz ( period = 19.300 ns )                    ; clock1_timer:292|v_minute[3]          ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.700 ns               ;
; N/A                                     ; 51.81 MHz ( period = 19.300 ns )                    ; clock1_timer:292|v_minute[1]          ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.700 ns               ;
; N/A                                     ; 51.81 MHz ( period = 19.300 ns )                    ; clock1_timer:292|v_minute[4]          ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.700 ns               ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; clock1_timer:292|v_seconds[5]         ; clock1_timer:292|v_minute[3]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.600 ns               ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; clock1_timer:292|v_seconds[5]         ; clock1_timer:292|v_minute[1]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.600 ns               ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; clock1_timer:292|v_seconds[5]         ; clock1_timer:292|v_minute[2]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.600 ns               ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; clock1_timer:292|v_seconds[5]         ; clock1_timer:292|v_minute[4]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.600 ns               ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.600 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.600 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.600 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.36 MHz ( period = 19.100 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.500 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_timer:292|v_hour[1]            ; clock1_timer:292|v_hour[1]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_timer:292|v_hour[1]            ; clock1_timer:292|v_hour[2]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_timer:292|v_seconds[2]         ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_timer:292|v_hour[1]            ; clock1_timer:292|v_hour[3]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_timer:292|v_hour[1]            ; clock1_timer:292|v_hour[4]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[7] ; clock1_base:283|div1000_reg:21|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[6] ; clock1_base:283|div1000_reg:21|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:21|reg[5] ; clock1_base:283|div1000_reg:21|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[7] ; clock1_base:283|div1000_reg:18|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[6] ; clock1_base:283|div1000_reg:18|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; clock1_base:283|div1000_reg:18|reg[5] ; clock1_base:283|div1000_reg:18|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.400 ns               ;
; N/A                                     ; 53.19 MHz ( period = 18.800 ns )                    ; clock1_timer:292|v_minute[5]          ; clock1_timer:292|v_minute[0]          ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.200 ns               ;
; N/A                                     ; 53.19 MHz ( period = 18.800 ns )                    ; clock1_timer:292|v_hour[3]            ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.200 ns               ;
; N/A                                     ; 53.19 MHz ( period = 18.800 ns )                    ; clock1_timer:292|v_hour[0]            ; clock1_timer:292|v_hour[5]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.200 ns               ;
; N/A                                     ; 53.19 MHz ( period = 18.800 ns )                    ; clock1_timer:292|v_hour[3]            ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.200 ns               ;
; N/A                                     ; 53.19 MHz ( period = 18.800 ns )                    ; clock1_timer:292|v_hour[0]            ; clock1_timer:292|v_hour[0]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.200 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; clock1_timer:292|v_hour[5]            ; clock1_timer:292|v_hour[1]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; clock1_timer:292|v_hour[5]            ; clock1_timer:292|v_hour[2]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; clock1_timer:292|v_hour[5]            ; clock1_timer:292|v_hour[3]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; clock1_timer:292|v_hour[5]            ; clock1_timer:292|v_hour[4]            ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[9] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.100 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 15.000 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:21|reg[8] ; clock1_base:283|div1000_reg:21|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[8] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[7] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[2] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[4] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[6] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[5] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[1] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[0] ; clock1_base:283|div1000_reg:18|reg[0] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; clock1_base:283|div1000_reg:18|reg[8] ; clock1_base:283|div1000_reg:18|reg[3] ; clk50mhz   ; clk50mhz ; None                        ; None                      ; 14.900 ns               ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                       ;                                       ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------+
; tco                                                                                           ;
+-------+--------------+------------+-------------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From                                ; To     ; From Clock ;
+-------+--------------+------------+-------------------------------------+--------+------------+
; N/A   ; None         ; 64.700 ns  ; clock1_timer:292|v_seconds[2]       ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 64.700 ns  ; clock1_timer:292|v_seconds[2]       ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 64.700 ns  ; clock1_timer:292|v_seconds[2]       ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 64.700 ns  ; clock1_timer:292|v_seconds[2]       ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 64.100 ns  ; clock1_timer:292|v_seconds[1]       ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 64.100 ns  ; clock1_timer:292|v_seconds[4]       ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 64.100 ns  ; clock1_timer:292|v_seconds[1]       ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 64.100 ns  ; clock1_timer:292|v_seconds[4]       ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 64.100 ns  ; clock1_timer:292|v_seconds[1]       ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 64.100 ns  ; clock1_timer:292|v_seconds[4]       ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 64.100 ns  ; clock1_timer:292|v_seconds[1]       ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 64.100 ns  ; clock1_timer:292|v_seconds[4]       ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 63.900 ns  ; clock1_timer:292|v_seconds[3]       ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 63.900 ns  ; clock1_timer:292|v_seconds[3]       ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 63.900 ns  ; clock1_timer:292|v_seconds[3]       ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 63.900 ns  ; clock1_timer:292|v_seconds[3]       ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 63.900 ns  ; clock1_timer:292|v_seconds[2]       ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 63.800 ns  ; clock1_timer:292|v_seconds[2]       ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 63.800 ns  ; clock1_timer:292|v_seconds[2]       ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 63.300 ns  ; clock1_timer:292|v_seconds[1]       ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 63.300 ns  ; clock1_timer:292|v_seconds[4]       ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 63.200 ns  ; clock1_timer:292|v_seconds[1]       ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 63.200 ns  ; clock1_timer:292|v_seconds[4]       ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 63.200 ns  ; clock1_timer:292|v_seconds[1]       ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 63.200 ns  ; clock1_timer:292|v_seconds[4]       ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 63.100 ns  ; clock1_timer:292|v_seconds[3]       ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 63.000 ns  ; clock1_timer:292|v_seconds[3]       ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 63.000 ns  ; clock1_timer:292|v_seconds[3]       ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 62.300 ns  ; clock1_timer:292|v_minute[2]        ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 62.300 ns  ; clock1_timer:292|v_minute[2]        ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 62.300 ns  ; clock1_timer:292|v_minute[2]        ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 62.300 ns  ; clock1_timer:292|v_minute[2]        ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 62.200 ns  ; clock1_timer:292|v_minute[1]        ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 62.200 ns  ; clock1_timer:292|v_minute[1]        ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 62.200 ns  ; clock1_timer:292|v_minute[1]        ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 62.200 ns  ; clock1_timer:292|v_minute[1]        ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 61.800 ns  ; clock1_timer:292|v_minute[4]        ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 61.800 ns  ; clock1_timer:292|v_minute[4]        ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 61.800 ns  ; clock1_timer:292|v_minute[4]        ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 61.800 ns  ; clock1_timer:292|v_minute[4]        ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 61.700 ns  ; clock1_timer:292|v_minute[3]        ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 61.700 ns  ; clock1_timer:292|v_minute[3]        ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 61.700 ns  ; clock1_timer:292|v_minute[3]        ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 61.700 ns  ; clock1_timer:292|v_minute[3]        ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 61.500 ns  ; clock1_timer:292|v_minute[2]        ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 61.400 ns  ; clock1_timer:292|v_minute[2]        ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 61.400 ns  ; clock1_timer:292|v_minute[2]        ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 61.400 ns  ; clock1_timer:292|v_minute[1]        ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 61.300 ns  ; clock1_timer:292|v_minute[1]        ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 61.300 ns  ; clock1_timer:292|v_minute[1]        ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 61.000 ns  ; clock1_timer:292|v_minute[4]        ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 60.900 ns  ; clock1_timer:292|v_minute[4]        ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 60.900 ns  ; clock1_timer:292|v_minute[4]        ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 60.900 ns  ; clock1_timer:292|v_minute[3]        ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 60.800 ns  ; clock1_timer:292|v_minute[3]        ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 60.800 ns  ; clock1_timer:292|v_minute[3]        ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 58.700 ns  ; clock1_timer:292|v_hour[3]          ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 58.700 ns  ; clock1_timer:292|v_seconds[5]       ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 58.700 ns  ; clock1_timer:292|v_hour[3]          ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 58.700 ns  ; clock1_timer:292|v_seconds[5]       ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 58.700 ns  ; clock1_timer:292|v_hour[3]          ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 58.700 ns  ; clock1_timer:292|v_seconds[5]       ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 58.700 ns  ; clock1_timer:292|v_hour[3]          ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 58.700 ns  ; clock1_timer:292|v_seconds[5]       ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 58.600 ns  ; clock1_timer:292|v_hour[2]          ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 58.600 ns  ; clock1_timer:292|v_hour[2]          ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 58.600 ns  ; clock1_timer:292|v_hour[2]          ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 58.600 ns  ; clock1_timer:292|v_hour[2]          ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 58.400 ns  ; clock1_timer:292|v_minute[5]        ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 58.400 ns  ; clock1_timer:292|v_hour[5]          ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 58.400 ns  ; clock1_timer:292|v_minute[5]        ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 58.400 ns  ; clock1_timer:292|v_hour[5]          ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 58.400 ns  ; clock1_timer:292|v_minute[5]        ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 58.400 ns  ; clock1_timer:292|v_hour[5]          ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 58.400 ns  ; clock1_timer:292|v_minute[5]        ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 58.400 ns  ; clock1_timer:292|v_hour[5]          ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 58.100 ns  ; clock1_timer:292|v_hour[1]          ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 58.100 ns  ; clock1_timer:292|v_hour[1]          ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 58.100 ns  ; clock1_timer:292|v_hour[1]          ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 58.100 ns  ; clock1_timer:292|v_hour[1]          ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 57.900 ns  ; clock1_timer:292|v_hour[3]          ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 57.900 ns  ; clock1_timer:292|v_seconds[5]       ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_hour[3]          ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_seconds[5]       ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_hour[4]          ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_hour[3]          ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_seconds[5]       ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_hour[4]          ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_hour[4]          ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_hour[4]          ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 57.800 ns  ; clock1_timer:292|v_hour[2]          ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 57.700 ns  ; clock1_timer:292|v_hour[2]          ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 57.700 ns  ; clock1_timer:292|v_hour[2]          ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 57.600 ns  ; clock1_timer:292|v_minute[5]        ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 57.600 ns  ; clock1_timer:292|v_hour[5]          ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 57.500 ns  ; clock1_timer:292|v_minute[5]        ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 57.500 ns  ; clock1_timer:292|v_hour[5]          ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 57.500 ns  ; clock1_timer:292|v_minute[5]        ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 57.500 ns  ; clock1_timer:292|v_hour[5]          ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 57.300 ns  ; clock1_timer:292|v_hour[1]          ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 57.200 ns  ; clock1_timer:292|v_hour[1]          ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 57.200 ns  ; clock1_timer:292|v_hour[1]          ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 57.000 ns  ; clock1_timer:292|v_hour[4]          ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 56.900 ns  ; clock1_timer:292|v_hour[4]          ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 56.900 ns  ; clock1_timer:292|v_hour[4]          ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 50.900 ns  ; digilab_display:272|digitcounter[0] ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 50.900 ns  ; digilab_display:272|digitcounter[0] ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 50.900 ns  ; digilab_display:272|digitcounter[0] ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 50.900 ns  ; digilab_display:272|digitcounter[0] ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 50.800 ns  ; digilab_display:272|digitcounter[1] ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 50.800 ns  ; digilab_display:272|digitcounter[1] ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 50.800 ns  ; digilab_display:272|digitcounter[1] ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 50.800 ns  ; digilab_display:272|digitcounter[1] ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 50.300 ns  ; digilab_display:272|digitcounter[2] ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 50.300 ns  ; digilab_display:272|digitcounter[2] ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 50.300 ns  ; digilab_display:272|digitcounter[2] ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 50.300 ns  ; digilab_display:272|digitcounter[2] ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 50.100 ns  ; digilab_display:272|digitcounter[0] ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 50.000 ns  ; digilab_display:272|digitcounter[0] ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 50.000 ns  ; digilab_display:272|digitcounter[0] ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 50.000 ns  ; digilab_display:272|digitcounter[1] ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 49.900 ns  ; digilab_display:272|digitcounter[1] ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 49.900 ns  ; digilab_display:272|digitcounter[1] ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 49.500 ns  ; digilab_display:272|digitcounter[2] ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 49.400 ns  ; digilab_display:272|digitcounter[2] ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 49.400 ns  ; digilab_display:272|digitcounter[2] ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 44.200 ns  ; clock1_timer:292|v_hour[0]          ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 44.200 ns  ; clock1_timer:292|v_hour[0]          ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 44.200 ns  ; clock1_timer:292|v_hour[0]          ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 44.100 ns  ; clock1_timer:292|v_seconds[0]       ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 44.100 ns  ; clock1_timer:292|v_seconds[0]       ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 44.100 ns  ; clock1_timer:292|v_seconds[0]       ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 44.000 ns  ; clock1_timer:292|v_hour[0]          ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 43.900 ns  ; clock1_timer:292|v_seconds[0]       ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 43.400 ns  ; clock1_timer:292|v_hour[0]          ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 43.300 ns  ; clock1_timer:292|v_hour[0]          ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 43.300 ns  ; clock1_timer:292|v_seconds[0]       ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 43.200 ns  ; clock1_timer:292|v_seconds[0]       ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 43.200 ns  ; clock1_timer:292|v_minute[0]        ; seg_a  ; clk50mhz   ;
; N/A   ; None         ; 43.200 ns  ; clock1_timer:292|v_minute[0]        ; seg_f  ; clk50mhz   ;
; N/A   ; None         ; 43.200 ns  ; clock1_timer:292|v_minute[0]        ; seg_d  ; clk50mhz   ;
; N/A   ; None         ; 43.200 ns  ; clock1_timer:292|v_hour[0]          ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 43.100 ns  ; clock1_timer:292|v_seconds[0]       ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 43.000 ns  ; clock1_timer:292|v_minute[0]        ; seg_e  ; clk50mhz   ;
; N/A   ; None         ; 42.400 ns  ; clock1_timer:292|v_minute[0]        ; seg_b  ; clk50mhz   ;
; N/A   ; None         ; 42.300 ns  ; clock1_timer:292|v_minute[0]        ; seg_c  ; clk50mhz   ;
; N/A   ; None         ; 42.200 ns  ; clock1_timer:292|v_minute[0]        ; seg_g  ; clk50mhz   ;
; N/A   ; None         ; 41.300 ns  ; clock1_timer:292|v_seconds[2]       ; led2   ; clk50mhz   ;
; N/A   ; None         ; 40.800 ns  ; clock1_timer:292|v_seconds[3]       ; led2   ; clk50mhz   ;
; N/A   ; None         ; 38.800 ns  ; clock1_timer:292|v_seconds[1]       ; led4   ; clk50mhz   ;
; N/A   ; None         ; 38.800 ns  ; clock1_timer:292|v_seconds[4]       ; led4   ; clk50mhz   ;
; N/A   ; None         ; 38.700 ns  ; clock1_timer:292|v_seconds[2]       ; led3   ; clk50mhz   ;
; N/A   ; None         ; 38.300 ns  ; clock1_timer:292|v_seconds[5]       ; led4   ; clk50mhz   ;
; N/A   ; None         ; 38.300 ns  ; clock1_timer:292|v_seconds[4]       ; led3   ; clk50mhz   ;
; N/A   ; None         ; 38.200 ns  ; clock1_timer:292|v_seconds[0]       ; led4   ; clk50mhz   ;
; N/A   ; None         ; 38.200 ns  ; clock1_timer:292|v_seconds[3]       ; led3   ; clk50mhz   ;
; N/A   ; None         ; 37.800 ns  ; clock1_timer:292|v_seconds[5]       ; led3   ; clk50mhz   ;
; N/A   ; None         ; 37.600 ns  ; clock1_timer:292|v_seconds[1]       ; led2   ; clk50mhz   ;
; N/A   ; None         ; 37.600 ns  ; clock1_timer:292|v_seconds[4]       ; led2   ; clk50mhz   ;
; N/A   ; None         ; 37.600 ns  ; clock1_timer:292|v_seconds[5]       ; led2   ; clk50mhz   ;
; N/A   ; None         ; 37.200 ns  ; clock1_timer:292|v_seconds[2]       ; led1   ; clk50mhz   ;
; N/A   ; None         ; 36.800 ns  ; clock1_timer:292|v_seconds[1]       ; led1   ; clk50mhz   ;
; N/A   ; None         ; 36.700 ns  ; clock1_timer:292|v_seconds[3]       ; led1   ; clk50mhz   ;
; N/A   ; None         ; 36.200 ns  ; clock1_timer:292|v_seconds[0]       ; led1   ; clk50mhz   ;
; N/A   ; None         ; 35.900 ns  ; clock1_timer:292|v_seconds[1]       ; led3   ; clk50mhz   ;
; N/A   ; None         ; 35.800 ns  ; clock1_timer:292|v_seconds[2]       ; led4   ; clk50mhz   ;
; N/A   ; None         ; 35.800 ns  ; clock1_timer:292|v_seconds[0]       ; led3   ; clk50mhz   ;
; N/A   ; None         ; 35.700 ns  ; clock1_base:283|33                  ; seg_dp ; clk50mhz   ;
; N/A   ; None         ; 35.300 ns  ; clock1_timer:292|v_seconds[3]       ; led4   ; clk50mhz   ;
; N/A   ; None         ; 34.400 ns  ; clock1_timer:292|v_seconds[4]       ; led1   ; clk50mhz   ;
; N/A   ; None         ; 34.400 ns  ; clock1_timer:292|v_seconds[5]       ; led1   ; clk50mhz   ;
; N/A   ; None         ; 34.000 ns  ; digilab_display:272|digitcounter[0] ; seg_dp ; clk50mhz   ;
; N/A   ; None         ; 33.900 ns  ; digilab_display:272|digitcounter[2] ; seg_dp ; clk50mhz   ;
; N/A   ; None         ; 33.400 ns  ; digilab_display:272|digitcounter[1] ; seg_dp ; clk50mhz   ;
; N/A   ; None         ; 31.700 ns  ; key_debounce:290|8                  ; seg_dp ; clk50mhz   ;
; N/A   ; None         ; 31.700 ns  ; key_debounce:290|7                  ; seg_dp ; clk50mhz   ;
; N/A   ; None         ; 31.700 ns  ; key_debounce:290|6                  ; seg_dp ; clk50mhz   ;
; N/A   ; None         ; 31.200 ns  ; key_debounce:290|9                  ; seg_dp ; clk50mhz   ;
; N/A   ; None         ; 28.200 ns  ; digilab_display:272|digitcounter[2] ; dig1   ; clk50mhz   ;
; N/A   ; None         ; 28.200 ns  ; digilab_display:272|digitcounter[0] ; dig4   ; clk50mhz   ;
; N/A   ; None         ; 28.200 ns  ; digilab_display:272|digitcounter[0] ; dig3   ; clk50mhz   ;
; N/A   ; None         ; 28.200 ns  ; digilab_display:272|digitcounter[0] ; dig5   ; clk50mhz   ;
; N/A   ; None         ; 28.100 ns  ; digilab_display:272|digitcounter[2] ; dig4   ; clk50mhz   ;
; N/A   ; None         ; 28.100 ns  ; digilab_display:272|digitcounter[2] ; dig3   ; clk50mhz   ;
; N/A   ; None         ; 28.100 ns  ; digilab_display:272|digitcounter[2] ; dig6   ; clk50mhz   ;
; N/A   ; None         ; 28.100 ns  ; digilab_display:272|digitcounter[1] ; dig5   ; clk50mhz   ;
; N/A   ; None         ; 28.000 ns  ; digilab_display:272|digitcounter[1] ; dig6   ; clk50mhz   ;
; N/A   ; None         ; 27.900 ns  ; digilab_display:272|digitcounter[1] ; dig1   ; clk50mhz   ;
; N/A   ; None         ; 27.700 ns  ; digilab_display:272|digitcounter[0] ; dig6   ; clk50mhz   ;
; N/A   ; None         ; 27.600 ns  ; digilab_display:272|digitcounter[0] ; dig1   ; clk50mhz   ;
; N/A   ; None         ; 27.600 ns  ; digilab_display:272|digitcounter[1] ; dig4   ; clk50mhz   ;
; N/A   ; None         ; 27.600 ns  ; digilab_display:272|digitcounter[1] ; dig3   ; clk50mhz   ;
; N/A   ; None         ; 27.600 ns  ; digilab_display:272|digitcounter[2] ; dig5   ; clk50mhz   ;
; N/A   ; None         ; 25.600 ns  ; digilab_display:272|digitcounter[1] ; dig2   ; clk50mhz   ;
; N/A   ; None         ; 25.600 ns  ; digilab_display:272|digitcounter[2] ; dig2   ; clk50mhz   ;
; N/A   ; None         ; 25.100 ns  ; digilab_display:272|digitcounter[0] ; dig2   ; clk50mhz   ;
+-------+--------------+------------+-------------------------------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Sat Nov 08 22:28:42 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock1 -c clock1
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk50mhz" is an undefined clock
Warning: Found 27 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "key_debounce:289|11" as buffer
    Info: Detected gated clock "key_debounce:288|11" as buffer
    Info: Detected gated clock "key_debounce:287|11" as buffer
    Info: Detected ripple clock "key_debounce:287|9" as buffer
    Info: Detected ripple clock "key_debounce:287|8" as buffer
    Info: Detected ripple clock "key_debounce:287|7" as buffer
    Info: Detected ripple clock "key_debounce:287|6" as buffer
    Info: Detected ripple clock "key_debounce:290|6" as buffer
    Info: Detected gated clock "key_debounce:290|12~25" as buffer
    Info: Detected ripple clock "key_debounce:290|7" as buffer
    Info: Detected gated clock "key_debounce:290|11" as buffer
    Info: Detected ripple clock "key_debounce:290|8" as buffer
    Info: Detected ripple clock "key_debounce:290|9" as buffer
    Info: Detected ripple clock "key_debounce:289|9" as buffer
    Info: Detected ripple clock "key_debounce:289|8" as buffer
    Info: Detected ripple clock "key_debounce:289|7" as buffer
    Info: Detected ripple clock "key_debounce:289|6" as buffer
    Info: Detected gated clock "key_debounce:289|12~24" as buffer
    Info: Detected gated clock "key_debounce:287|12~29" as buffer
    Info: Detected ripple clock "key_debounce:288|9" as buffer
    Info: Detected ripple clock "key_debounce:288|8" as buffer
    Info: Detected ripple clock "key_debounce:288|7" as buffer
    Info: Detected ripple clock "key_debounce:288|6" as buffer
    Info: Detected gated clock "key_debounce:288|12~24" as buffer
    Info: Detected ripple clock "clock1_base:283|33" as buffer
    Info: Detected ripple clock "clock1_base:283|31" as buffer
    Info: Detected ripple clock "clock1_base:283|32" as buffer
Info: Clock "clk50mhz" has Internal fmax of 34.01 MHz between source register "clock1_base:283|div1000_reg:18|reg[7]" and destination register "clock1_base:283|32" (period= 29.4 ns)
    Info: + Longest register to register delay is 11.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_B4; Fanout = 3; REG Node = 'clock1_base:283|div1000_reg:18|reg[7]'
        Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_B4; Fanout = 4; COMB Node = 'clock1_base:283|div1000_loop:19|div1000~91'
        Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 6.900 ns; Loc. = LC2_B3; Fanout = 2; COMB Node = 'clock1_base:283|div1000_loop:19|div1000~92'
        Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 9.300 ns; Loc. = LC3_B3; Fanout = 1; COMB Node = 'clock1_base:283|div1000_loop:19|div1000'
        Info: 5: + IC(0.600 ns) + CELL(1.200 ns) = 11.100 ns; Loc. = LC4_B3; Fanout = 19; REG Node = 'clock1_base:283|32'
        Info: Total cell delay = 7.100 ns ( 63.96 % )
        Info: Total interconnect delay = 4.000 ns ( 36.04 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk50mhz" to destination register is 10.700 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk50mhz'
            Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC6_A13; Fanout = 12; REG Node = 'clock1_base:283|31'
            Info: 3: + IC(4.300 ns) + CELL(0.000 ns) = 10.700 ns; Loc. = LC4_B3; Fanout = 19; REG Node = 'clock1_base:283|32'
            Info: Total cell delay = 3.900 ns ( 36.45 % )
            Info: Total interconnect delay = 6.800 ns ( 63.55 % )
        Info: - Longest clock path from clock "clk50mhz" to source register is 10.700 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk50mhz'
            Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC6_A13; Fanout = 12; REG Node = 'clock1_base:283|31'
            Info: 3: + IC(4.300 ns) + CELL(0.000 ns) = 10.700 ns; Loc. = LC7_B4; Fanout = 3; REG Node = 'clock1_base:283|div1000_reg:18|reg[7]'
            Info: Total cell delay = 3.900 ns ( 36.45 % )
            Info: Total interconnect delay = 6.800 ns ( 63.55 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: tco from clock "clk50mhz" to destination pin "seg_a" through register "clock1_timer:292|v_seconds[2]" is 64.700 ns
    Info: + Longest clock path from clock "clk50mhz" to source register is 21.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk50mhz'
        Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC6_A13; Fanout = 12; REG Node = 'clock1_base:283|31'
        Info: 3: + IC(4.300 ns) + CELL(1.100 ns) = 11.800 ns; Loc. = LC4_B3; Fanout = 19; REG Node = 'clock1_base:283|32'
        Info: 4: + IC(3.800 ns) + CELL(1.100 ns) = 16.700 ns; Loc. = LC1_C2; Fanout = 20; REG Node = 'clock1_base:283|33'
        Info: 5: + IC(4.500 ns) + CELL(0.000 ns) = 21.200 ns; Loc. = LC1_B19; Fanout = 20; REG Node = 'clock1_timer:292|v_seconds[2]'
        Info: Total cell delay = 6.100 ns ( 28.77 % )
        Info: Total interconnect delay = 15.100 ns ( 71.23 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 42.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B19; Fanout = 20; REG Node = 'clock1_timer:292|v_seconds[2]'
        Info: 2: + IC(5.000 ns) + CELL(2.300 ns) = 7.300 ns; Loc. = LC8_A1; Fanout = 2; COMB Node = 'bin6bcd:274|op_5~55'
        Info: 3: + IC(2.500 ns) + CELL(2.300 ns) = 12.100 ns; Loc. = LC1_A7; Fanout = 3; COMB Node = 'bin6bcd:274|dig2[2]~398'
        Info: 4: + IC(2.300 ns) + CELL(2.300 ns) = 16.700 ns; Loc. = LC5_A1; Fanout = 2; COMB Node = 'digilab_display:272|digitvalue[1]~3348'
        Info: 5: + IC(2.600 ns) + CELL(2.300 ns) = 21.600 ns; Loc. = LC5_A12; Fanout = 1; COMB Node = 'digilab_display:272|digitvalue[2]~3349'
        Info: 6: + IC(0.600 ns) + CELL(1.800 ns) = 24.000 ns; Loc. = LC4_A12; Fanout = 1; COMB Node = 'digilab_display:272|digitvalue[2]~3350'
        Info: 7: + IC(2.200 ns) + CELL(1.700 ns) = 27.900 ns; Loc. = LC7_A9; Fanout = 1; COMB Node = 'digilab_display:272|digitvalue[2]~3476'
        Info: 8: + IC(0.000 ns) + CELL(1.500 ns) = 29.400 ns; Loc. = LC8_A9; Fanout = 7; COMB Node = 'digilab_display:272|digitvalue[2]~3427'
        Info: 9: + IC(3.100 ns) + CELL(2.300 ns) = 34.800 ns; Loc. = LC1_A18; Fanout = 1; COMB Node = 'digilab_display:272|sega~13'
        Info: 10: + IC(2.500 ns) + CELL(5.100 ns) = 42.400 ns; Loc. = PIN_67; Fanout = 0; PIN Node = 'seg_a'
        Info: Total cell delay = 21.600 ns ( 50.94 % )
        Info: Total interconnect delay = 20.800 ns ( 49.06 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 124 megabytes
    Info: Processing ended: Sat Nov 08 22:28:43 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:02


