Analysis & Synthesis report for clock1
Mon Oct 06 20:56:25 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Source assignments for clock1_timer:292|lpm_add_sub:op_1|addcore:adder
  9. Source assignments for clock1_timer:292|lpm_add_sub:op_2|addcore:adder
 10. Source assignments for clock1_timer:292|lpm_add_sub:op_3|addcore:adder
 11. Source assignments for clock1_base:283|div1000_loop:20|lpm_add_sub:op_3|addcore:adder
 12. Source assignments for clock1_base:283|div1000_loop:19|lpm_add_sub:op_3|addcore:adder
 13. Parameter Settings for Inferred Entity Instance: clock1_timer:292|lpm_add_sub:op_1
 14. Parameter Settings for Inferred Entity Instance: clock1_timer:292|lpm_add_sub:op_2
 15. Parameter Settings for Inferred Entity Instance: clock1_timer:292|lpm_add_sub:op_3
 16. Parameter Settings for Inferred Entity Instance: clock1_base:283|div1000_loop:20|lpm_add_sub:op_3
 17. Parameter Settings for Inferred Entity Instance: clock1_base:283|div1000_loop:19|lpm_add_sub:op_3
 18. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary                                          ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Oct 06 20:56:25 2008   ;
; Quartus II Version          ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name               ; clock1                                  ;
; Top-level Entity Name       ; clock1                                  ;
; Family                      ; FLEX10K                                 ;
; Total logic elements        ; 268                                     ;
; Total pins                  ; 30                                      ;
; Total memory bits           ; 0                                       ;
+-----------------------------+-----------------------------------------+


+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                             ;
+----------------------------------------------------------+----------------+---------------+
; Option                                                   ; Setting        ; Default Value ;
+----------------------------------------------------------+----------------+---------------+
; Device                                                   ; EPF10K10LC84-4 ;               ;
; Top-level entity name                                    ; clock1         ; clock1        ;
; Family name                                              ; FLEX10K        ; Stratix II    ;
; Use smart compilation                                    ; Off            ; Off           ;
; Create Debugging Nodes for IP Cores                      ; Off            ; Off           ;
; Preserve fewer node names                                ; On             ; On            ;
; Disable OpenCore Plus hardware evaluation                ; Off            ; Off           ;
; Verilog Version                                          ; Verilog_2001   ; Verilog_2001  ;
; VHDL Version                                             ; VHDL93         ; VHDL93        ;
; State Machine Processing                                 ; Auto           ; Auto          ;
; Safe State Machine                                       ; Off            ; Off           ;
; Extract Verilog State Machines                           ; On             ; On            ;
; Extract VHDL State Machines                              ; On             ; On            ;
; Ignore Verilog initial constructs                        ; Off            ; Off           ;
; Add Pass-Through Logic to Inferred RAMs                  ; On             ; On            ;
; Parallel Synthesis                                       ; Off            ; Off           ;
; NOT Gate Push-Back                                       ; On             ; On            ;
; Power-Up Don't Care                                      ; On             ; On            ;
; Remove Redundant Logic Cells                             ; Off            ; Off           ;
; Remove Duplicate Registers                               ; On             ; On            ;
; Ignore CARRY Buffers                                     ; Off            ; Off           ;
; Ignore CASCADE Buffers                                   ; Off            ; Off           ;
; Ignore GLOBAL Buffers                                    ; Off            ; Off           ;
; Ignore ROW GLOBAL Buffers                                ; Off            ; Off           ;
; Ignore LCELL Buffers                                     ; Off            ; Off           ;
; Ignore SOFT Buffers                                      ; On             ; On            ;
; Limit AHDL Integers to 32 Bits                           ; Off            ; Off           ;
; Auto Implement in ROM                                    ; Off            ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K     ; Area           ; Area          ;
; Carry Chain Length -- FLEX 10K                           ; 32             ; 32            ;
; Cascade Chain Length                                     ; 2              ; 2             ;
; Auto Carry Chains                                        ; On             ; On            ;
; Auto Open-Drain Pins                                     ; On             ; On            ;
; Auto ROM Replacement                                     ; On             ; On            ;
; Auto RAM Replacement                                     ; On             ; On            ;
; Auto Clock Enable Replacement                            ; On             ; On            ;
; Auto Resource Sharing                                    ; Off            ; Off           ;
; Allow Any RAM Size For Recognition                       ; Off            ; Off           ;
; Allow Any ROM Size For Recognition                       ; Off            ; Off           ;
; Ignore translate_off and synthesis_off directives        ; Off            ; Off           ;
; Show Parameter Settings Tables in Synthesis Report       ; On             ; On            ;
; HDL message level                                        ; Level2         ; Level2        ;
; Suppress Register Optimization Related Messages          ; Off            ; Off           ;
; Number of Removed Registers Reported in Synthesis Report ; 100            ; 100           ;
; Block Design Naming                                      ; Auto           ; Auto          ;
+----------------------------------------------------------+----------------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                   ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                   ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
; key_debounce.gdf                 ; yes             ; User Graphic Design File           ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/key_debounce.gdf             ;
; div1000_reg.tdf                  ; yes             ; User AHDL File                     ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/div1000_reg.tdf              ;
; div50_loop.tdf                   ; yes             ; User AHDL File                     ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/div50_loop.tdf               ;
; div50_reg.tdf                    ; yes             ; User AHDL File                     ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/div50_reg.tdf                ;
; div1000_loop.tdf                 ; yes             ; User AHDL File                     ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/div1000_loop.tdf             ;
; clock1_base.gdf                  ; yes             ; User Graphic Design File           ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/clock1_base.gdf              ;
; bin6bcd.tdf                      ; yes             ; User AHDL File                     ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/bin6bcd.tdf                  ;
; clock1_timer.tdf                 ; yes             ; User AHDL File                     ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/clock1_timer.tdf             ;
; ../common/digilab_display.tdf    ; yes             ; User AHDL File                     ; L:/BACKUP_C_20071124/Projects/Digilab/common/digilab_display.tdf               ;
; clock1.bdf                       ; yes             ; User Block Diagram/Schematic File  ; L:/BACKUP_C_20071124/Projects/Digilab/Clock_1_001/clock1.bdf                   ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/addcore.inc             ;
; look_add.inc                     ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/look_add.inc            ;
; bypassff.inc                     ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/altshift.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/aglobal72.inc           ;
; addcore.tdf                      ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; Megafunction                       ; k:/programme/altera/72/quartus/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                    ;
+-----------------------------------+----------------------------+
; Resource                          ; Usage                      ;
+-----------------------------------+----------------------------+
; Total logic elements              ; 268                        ;
; Total combinational functions     ; 268                        ;
;     -- Total 4-input functions    ; 129                        ;
;     -- Total 3-input functions    ; 46                         ;
;     -- Total 2-input functions    ; 39                         ;
;     -- Total 1-input functions    ; 54                         ;
;     -- Total 0-input functions    ; 0                          ;
; Total registers                   ; 66                         ;
; Total logic cells in carry chains ; 38                         ;
; I/O pins                          ; 30                         ;
; Maximum fan-out node              ; clock1_timer:292|v_hour[3] ;
; Maximum fan-out                   ; 20                         ;
; Total fan-out                     ; 954                        ;
; Average fan-out                   ; 3.20                       ;
+-----------------------------------+----------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                             ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node               ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                            ; Library Name ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------+--------------+
; |clock1                                  ; 268 (0)     ; 66           ; 0           ; 30   ; 202 (0)      ; 0 (0)             ; 66 (0)           ; 38 (0)          ; 0 (0)      ; |clock1                                                                                        ; work         ;
;    |bin6bcd:274|                         ; 12 (12)     ; 0            ; 0           ; 0    ; 12 (12)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock1|bin6bcd:274                                                                            ; work         ;
;    |bin6bcd:275|                         ; 11 (11)     ; 0            ; 0           ; 0    ; 11 (11)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock1|bin6bcd:275                                                                            ; work         ;
;    |bin6bcd:293|                         ; 11 (11)     ; 0            ; 0           ; 0    ; 11 (11)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock1|bin6bcd:293                                                                            ; work         ;
;    |clock1_base:283|                     ; 74 (3)      ; 29           ; 0           ; 0    ; 45 (0)       ; 0 (0)             ; 29 (3)           ; 20 (0)          ; 0 (0)      ; |clock1|clock1_base:283                                                                        ; work         ;
;       |div1000_loop:19|                  ; 19 (10)     ; 0            ; 0           ; 0    ; 19 (10)      ; 0 (0)             ; 0 (0)            ; 9 (0)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_loop:19                                                        ; work         ;
;          |lpm_add_sub:op_3|              ; 9 (0)       ; 0            ; 0           ; 0    ; 9 (0)        ; 0 (0)             ; 0 (0)            ; 9 (0)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_loop:19|lpm_add_sub:op_3                                       ; work         ;
;             |addcore:adder|              ; 9 (1)       ; 0            ; 0           ; 0    ; 9 (1)        ; 0 (0)             ; 0 (0)            ; 9 (1)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_loop:19|lpm_add_sub:op_3|addcore:adder                         ; work         ;
;                |a_csnbuffer:result_node| ; 8 (8)       ; 0            ; 0           ; 0    ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 8 (8)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_loop:19|lpm_add_sub:op_3|addcore:adder|a_csnbuffer:result_node ; work         ;
;       |div1000_loop:20|                  ; 19 (10)     ; 0            ; 0           ; 0    ; 19 (10)      ; 0 (0)             ; 0 (0)            ; 9 (0)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_loop:20                                                        ; work         ;
;          |lpm_add_sub:op_3|              ; 9 (0)       ; 0            ; 0           ; 0    ; 9 (0)        ; 0 (0)             ; 0 (0)            ; 9 (0)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_loop:20|lpm_add_sub:op_3                                       ; work         ;
;             |addcore:adder|              ; 9 (1)       ; 0            ; 0           ; 0    ; 9 (1)        ; 0 (0)             ; 0 (0)            ; 9 (1)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_loop:20|lpm_add_sub:op_3|addcore:adder                         ; work         ;
;                |a_csnbuffer:result_node| ; 8 (8)       ; 0            ; 0           ; 0    ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 8 (8)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_loop:20|lpm_add_sub:op_3|addcore:adder|a_csnbuffer:result_node ; work         ;
;       |div1000_reg:18|                   ; 10 (10)     ; 10           ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 10 (10)          ; 1 (1)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_reg:18                                                         ; work         ;
;       |div1000_reg:21|                   ; 10 (10)     ; 10           ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 10 (10)          ; 1 (1)           ; 0 (0)      ; |clock1|clock1_base:283|div1000_reg:21                                                         ; work         ;
;       |div50_loop:16|                    ; 7 (7)       ; 0            ; 0           ; 0    ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock1|clock1_base:283|div50_loop:16                                                          ; work         ;
;       |div50_reg:17|                     ; 6 (6)       ; 6            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 6 (6)            ; 0 (0)           ; 0 (0)      ; |clock1|clock1_base:283|div50_reg:17                                                           ; work         ;
;    |clock1_timer:292|                    ; 52 (37)     ; 18           ; 0           ; 0    ; 34 (19)      ; 0 (0)             ; 18 (18)          ; 18 (3)          ; 0 (0)      ; |clock1|clock1_timer:292                                                                       ; work         ;
;       |lpm_add_sub:op_1|                 ; 5 (0)       ; 0            ; 0           ; 0    ; 5 (0)        ; 0 (0)             ; 0 (0)            ; 5 (0)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_1                                                      ; work         ;
;          |addcore:adder|                 ; 5 (1)       ; 0            ; 0           ; 0    ; 5 (1)        ; 0 (0)             ; 0 (0)            ; 5 (1)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_1|addcore:adder                                        ; work         ;
;             |a_csnbuffer:result_node|    ; 4 (4)       ; 0            ; 0           ; 0    ; 4 (4)        ; 0 (0)             ; 0 (0)            ; 4 (4)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_1|addcore:adder|a_csnbuffer:result_node                ; work         ;
;       |lpm_add_sub:op_2|                 ; 5 (0)       ; 0            ; 0           ; 0    ; 5 (0)        ; 0 (0)             ; 0 (0)            ; 5 (0)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_2                                                      ; work         ;
;          |addcore:adder|                 ; 5 (1)       ; 0            ; 0           ; 0    ; 5 (1)        ; 0 (0)             ; 0 (0)            ; 5 (1)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_2|addcore:adder                                        ; work         ;
;             |a_csnbuffer:result_node|    ; 4 (4)       ; 0            ; 0           ; 0    ; 4 (4)        ; 0 (0)             ; 0 (0)            ; 4 (4)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_2|addcore:adder|a_csnbuffer:result_node                ; work         ;
;       |lpm_add_sub:op_3|                 ; 5 (0)       ; 0            ; 0           ; 0    ; 5 (0)        ; 0 (0)             ; 0 (0)            ; 5 (0)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_3                                                      ; work         ;
;          |addcore:adder|                 ; 5 (1)       ; 0            ; 0           ; 0    ; 5 (1)        ; 0 (0)             ; 0 (0)            ; 5 (1)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_3|addcore:adder                                        ; work         ;
;             |a_csnbuffer:result_node|    ; 4 (4)       ; 0            ; 0           ; 0    ; 4 (4)        ; 0 (0)             ; 0 (0)            ; 4 (4)           ; 0 (0)      ; |clock1|clock1_timer:292|lpm_add_sub:op_3|addcore:adder|a_csnbuffer:result_node                ; work         ;
;    |digilab_display:272|                 ; 84 (84)     ; 3            ; 0           ; 0    ; 81 (81)      ; 0 (0)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |clock1|digilab_display:272                                                                    ; work         ;
;    |key_debounce:287|                    ; 6 (6)       ; 4            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |clock1|key_debounce:287                                                                       ; work         ;
;    |key_debounce:288|                    ; 6 (6)       ; 4            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |clock1|key_debounce:288                                                                       ; work         ;
;    |key_debounce:289|                    ; 6 (6)       ; 4            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |clock1|key_debounce:289                                                                       ; work         ;
;    |key_debounce:290|                    ; 6 (6)       ; 4            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |clock1|key_debounce:290                                                                       ; work         ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 66    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 16    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------+
; Source assignments for clock1_timer:292|lpm_add_sub:op_1|addcore:adder ;
+---------------------------+-------+------+-----------------------------+
; Assignment                ; Value ; From ; To                          ;
+---------------------------+-------+------+-----------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -                           ;
+---------------------------+-------+------+-----------------------------+


+------------------------------------------------------------------------+
; Source assignments for clock1_timer:292|lpm_add_sub:op_2|addcore:adder ;
+---------------------------+-------+------+-----------------------------+
; Assignment                ; Value ; From ; To                          ;
+---------------------------+-------+------+-----------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -                           ;
+---------------------------+-------+------+-----------------------------+


+------------------------------------------------------------------------+
; Source assignments for clock1_timer:292|lpm_add_sub:op_3|addcore:adder ;
+---------------------------+-------+------+-----------------------------+
; Assignment                ; Value ; From ; To                          ;
+---------------------------+-------+------+-----------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -                           ;
+---------------------------+-------+------+-----------------------------+


+---------------------------------------------------------------------------------------+
; Source assignments for clock1_base:283|div1000_loop:20|lpm_add_sub:op_3|addcore:adder ;
+---------------------------+-------+------+--------------------------------------------+
; Assignment                ; Value ; From ; To                                         ;
+---------------------------+-------+------+--------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -                                          ;
+---------------------------+-------+------+--------------------------------------------+


+---------------------------------------------------------------------------------------+
; Source assignments for clock1_base:283|div1000_loop:19|lpm_add_sub:op_3|addcore:adder ;
+---------------------------+-------+------+--------------------------------------------+
; Assignment                ; Value ; From ; To                                         ;
+---------------------------+-------+------+--------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -                                          ;
+---------------------------+-------+------+--------------------------------------------+


+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: clock1_timer:292|lpm_add_sub:op_1 ;
+------------------------+-------------+---------------------------------------------+
; Parameter Name         ; Value       ; Type                                        ;
+------------------------+-------------+---------------------------------------------+
; LPM_WIDTH              ; 6           ; Untyped                                     ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                     ;
; LPM_DIRECTION          ; ADD         ; Untyped                                     ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                     ;
; LPM_PIPELINE           ; 0           ; Untyped                                     ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                     ;
; REGISTERED_AT_END      ; 0           ; Untyped                                     ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                     ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                     ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                     ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                          ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                                     ;
; USE_WYS                ; OFF         ; Untyped                                     ;
; STYLE                  ; FAST        ; Untyped                                     ;
; CBXI_PARAMETER         ; add_sub_jch ; Untyped                                     ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                              ;
+------------------------+-------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: clock1_timer:292|lpm_add_sub:op_2 ;
+------------------------+-------------+---------------------------------------------+
; Parameter Name         ; Value       ; Type                                        ;
+------------------------+-------------+---------------------------------------------+
; LPM_WIDTH              ; 6           ; Untyped                                     ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                     ;
; LPM_DIRECTION          ; ADD         ; Untyped                                     ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                     ;
; LPM_PIPELINE           ; 0           ; Untyped                                     ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                     ;
; REGISTERED_AT_END      ; 0           ; Untyped                                     ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                     ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                     ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                     ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                          ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                                     ;
; USE_WYS                ; OFF         ; Untyped                                     ;
; STYLE                  ; FAST        ; Untyped                                     ;
; CBXI_PARAMETER         ; add_sub_jch ; Untyped                                     ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                              ;
+------------------------+-------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: clock1_timer:292|lpm_add_sub:op_3 ;
+------------------------+-------------+---------------------------------------------+
; Parameter Name         ; Value       ; Type                                        ;
+------------------------+-------------+---------------------------------------------+
; LPM_WIDTH              ; 6           ; Untyped                                     ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                     ;
; LPM_DIRECTION          ; ADD         ; Untyped                                     ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                     ;
; LPM_PIPELINE           ; 0           ; Untyped                                     ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                     ;
; REGISTERED_AT_END      ; 0           ; Untyped                                     ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                     ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                     ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                     ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                          ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                                     ;
; USE_WYS                ; OFF         ; Untyped                                     ;
; STYLE                  ; FAST        ; Untyped                                     ;
; CBXI_PARAMETER         ; add_sub_jch ; Untyped                                     ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                              ;
+------------------------+-------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: clock1_base:283|div1000_loop:20|lpm_add_sub:op_3 ;
+------------------------+-------------+------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                       ;
+------------------------+-------------+------------------------------------------------------------+
; LPM_WIDTH              ; 10          ; Untyped                                                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                                                    ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                                    ;
; LPM_PIPELINE           ; 0           ; Untyped                                                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                    ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                         ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                                                    ;
; USE_WYS                ; OFF         ; Untyped                                                    ;
; STYLE                  ; FAST        ; Untyped                                                    ;
; CBXI_PARAMETER         ; add_sub_udh ; Untyped                                                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                             ;
+------------------------+-------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: clock1_base:283|div1000_loop:19|lpm_add_sub:op_3 ;
+------------------------+-------------+------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                       ;
+------------------------+-------------+------------------------------------------------------------+
; LPM_WIDTH              ; 10          ; Untyped                                                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                                                    ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                                    ;
; LPM_PIPELINE           ; 0           ; Untyped                                                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                    ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                         ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                                                    ;
; USE_WYS                ; OFF         ; Untyped                                                    ;
; STYLE                  ; FAST        ; Untyped                                                    ;
; CBXI_PARAMETER         ; add_sub_udh ; Untyped                                                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                             ;
+------------------------+-------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Mon Oct 06 20:56:20 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock1 -c clock1
Info: Found 1 design units, including 1 entities, in source file key_debounce.gdf
    Info: Found entity 1: key_debounce
Info: Found 1 design units, including 1 entities, in source file div1000_reg.tdf
    Info: Found entity 1: div1000_reg
Info: Found 1 design units, including 1 entities, in source file div50_loop.tdf
    Info: Found entity 1: div50_loop
Info: Found 1 design units, including 1 entities, in source file div50_reg.tdf
    Info: Found entity 1: div50_reg
Info: Found 1 design units, including 1 entities, in source file div1000_loop.tdf
    Info: Found entity 1: div1000_loop
Info: Found 1 design units, including 1 entities, in source file clock1_base.gdf
    Info: Found entity 1: clock1_base
Info: Found 1 design units, including 1 entities, in source file clock1_divider.tdf
    Info: Found entity 1: clock1_divider
Info: Found 1 design units, including 1 entities, in source file bin6bcd.tdf
    Info: Found entity 1: bin6bcd
Info: Found 1 design units, including 1 entities, in source file clock1_timer.tdf
    Info: Found entity 1: clock1_timer
Info: Found 1 design units, including 1 entities, in source file ../common/digilab_display.tdf
    Info: Found entity 1: digilab_display
Info: Found 1 design units, including 1 entities, in source file clock1.bdf
    Info: Found entity 1: clock1
Info: Elaborating entity "clock1" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "clock1" with Max+Plus II bus and instance naming rules
Warning: Primitive "WIRE" of instance "190" not used
Warning: Primitive "WIRE" of instance "229" not used
Info: Elaborating entity "digilab_display" for hierarchy "digilab_display:272"
Info: Elaborating entity "key_debounce" for hierarchy "key_debounce:290"
Warning: Processing legacy GDF or BDF entity "key_debounce" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "clock1_base" for hierarchy "clock1_base:283"
Warning: Processing legacy GDF or BDF entity "clock1_base" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "div50_loop" for hierarchy "clock1_base:283|div50_loop:16"
Info: Elaborating entity "div50_reg" for hierarchy "clock1_base:283|div50_reg:17"
Info: Elaborating entity "div1000_loop" for hierarchy "clock1_base:283|div1000_loop:19"
Info: Elaborating entity "div1000_reg" for hierarchy "clock1_base:283|div1000_reg:18"
Info: Elaborating entity "bin6bcd" for hierarchy "bin6bcd:274"
Info: Elaborating entity "clock1_timer" for hierarchy "clock1_timer:292"
Info: Inferred 5 megafunctions from design logic
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "clock1_timer:292|op_1"
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "clock1_timer:292|op_2"
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "clock1_timer:292|op_3"
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "clock1_base:283|div1000_loop:20|op_3"
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "clock1_base:283|div1000_loop:19|op_3"
Info: Found 1 design units, including 1 entities, in source file k:/programme/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1"
Info: Found 1 design units, including 1 entities, in source file k:/programme/altera/72/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1|addcore:adder", which is child of megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1"
Info: Instantiated megafunction "clock1_timer:292|lpm_add_sub:op_1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file k:/programme/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1"
Info: Instantiated megafunction "clock1_timer:292|lpm_add_sub:op_1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1"
Info: Instantiated megafunction "clock1_timer:292|lpm_add_sub:op_1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file k:/programme/altera/72/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1"
Info: Instantiated megafunction "clock1_timer:292|lpm_add_sub:op_1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "clock1_timer:292|lpm_add_sub:op_1"
Info: Instantiated megafunction "clock1_timer:292|lpm_add_sub:op_1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3"
Info: Elaborated megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3|addcore:adder", which is child of megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3"
Info: Instantiated megafunction "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3"
Info: Instantiated megafunction "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3"
Info: Instantiated megafunction "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3"
Info: Instantiated megafunction "clock1_base:283|div1000_loop:20|lpm_add_sub:op_3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Ignored 6 buffer(s)
    Info: Ignored 6 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "green" stuck at GND
    Warning (13410): Pin "red" stuck at GND
    Warning (13410): Pin "blue" stuck at GND
    Warning (13410): Pin "horiz" stuck at GND
    Warning (13410): Pin "vert" stuck at GND
Info: Implemented 298 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 24 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 268 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Allocated 141 megabytes of memory during processing
    Info: Processing ended: Mon Oct 06 20:56:25 2008
    Info: Elapsed time: 00:00:05


