Project Information                 c:\projects\digilab\clock_1_001\clock1.rpt

MAX+plus II Compiler Report File
Version 9.6 3/22/2000
Compiled: 09/01/2002 16:04:54

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

clock1    EPF10K10LC84-4   5      24     1    0         0  %    241      41 %

User Pins:                 5      24     1  



Project Information                 c:\projects\digilab\clock_1_001\clock1.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Ignored logic function symbol "key_debounce" (ID :287) -- it has no output
Warning: Ignored logic function symbol "key_debounce" (ID :290) -- it has no output
Warning: Line 6, File c:\projects\digilab\clock_1_001\bin6bcd.tdf:
   Symbolic name "lo4" was declared but never used
Warning: Line 6, File c:\projects\digilab\clock_1_001\bin6bcd.tdf:
   Symbolic name "lo5" was declared but never used
Info: Reserved unused input pin 't4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 't2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board


Project Information                 c:\projects\digilab\clock_1_001\clock1.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

clock1@39                         blue
clock1@43                         clk50
clock1@5                          dig1
clock1@83                         dig2
clock1@79                         dig3
clock1@80                         dig4
clock1@78                         dig5
clock1@81                         dig6
clock1@38                         green
clock1@48                         horiz
clock1@52                         kbd_clk
clock1@51                         kbd_dta
clock1@53                         led1
clock1@58                         led2
clock1@60                         led3
clock1@62                         led4
clock1@37                         red
clock1@67                         seg_a
clock1@70                         seg_b
clock1@69                         seg_c
clock1@66                         seg_d
clock1@71                         seg_dp
clock1@73                         seg_e
clock1@65                         seg_f
clock1@72                         seg_g
clock1@54                         t1
clock1@59                         t2
clock1@61                         t3
clock1@64                         t4
clock1@47                         vert


Project Information                 c:\projects\digilab\clock_1_001\clock1.rpt

** FILE HIERARCHY **



|digilab_display:272|
|bin6bcd:274|
|bin6bcd:293|
|bin6bcd:275|
|clock1_base:283|
|clock1_base:283|div50_loop:16|
|clock1_base:283|div50_reg:17|
|clock1_base:283|div1000_reg:21|
|clock1_base:283|div1000_reg:18|
|clock1_base:283|div1000_loop:20|
|clock1_base:283|div1000_loop:19|
|key_debounce:287|
|key_debounce:290|
|key_debounce:289|
|key_debounce:288|
|clock1_timer:292|


Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

***** Logic for device 'clock1' compiled without errors.




Device: EPF10K10LC84-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f

                                                                         ^     
                                                                         C     
                R  R  R  R  R  R        R                                O     
                E  E  E  E  E  E        E                                N     
                S  S  S  S  S  S     V  S  G  G  G     G                 F     
                E  E  E  E  E  E     C  E  N  N  N     N                 _  ^  
                R  R  R  R  R  R  d  C  R  D  D  D  d  D  d  d  d  d  #  D  n  
                V  V  V  V  V  V  i  I  V  I  I  I  i  I  i  i  i  i  T  O  C  
                E  E  E  E  E  E  g  N  E  N  N  N  g  N  g  g  g  g  C  N  E  
                D  D  D  D  D  D  1  T  D  T  T  T  2  T  6  4  3  5  K  E  O  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    ^DATA0 | 12                                                              74 | #TDO 
     ^DCLK | 13                                                              73 | seg_e 
      ^nCE | 14                                                              72 | seg_g 
      #TDI | 15                                                              71 | seg_dp 
  RESERVED | 16                                                              70 | seg_b 
  RESERVED | 17                                                              69 | seg_c 
  RESERVED | 18                                                              68 | GNDINT 
  RESERVED | 19                                                              67 | seg_a 
    VCCINT | 20                                                              66 | seg_d 
  RESERVED | 21                                                              65 | seg_f 
  RESERVED | 22                        EPF10K10LC84-4                        64 | t4 
  RESERVED | 23                                                              63 | VCCINT 
  RESERVED | 24                                                              62 | led4 
  RESERVED | 25                                                              61 | t3 
    GNDINT | 26                                                              60 | led3 
  RESERVED | 27                                                              59 | t2 
  RESERVED | 28                                                              58 | led2 
  RESERVED | 29                                                              57 | #TMS 
  RESERVED | 30                                                              56 | #TRST 
    ^MSEL0 | 31                                                              55 | ^nSTATUS 
    ^MSEL1 | 32                                                              54 | t1 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                V  ^  R  R  r  g  b  V  G  G  c  G  V  G  v  h  R  R  k  k  l  
                C  n  E  E  e  r  l  C  N  N  l  N  C  N  e  o  E  E  b  b  e  
                C  C  S  S  d  e  u  C  D  D  k  D  C  D  r  r  S  S  d  d  d  
                I  O  E  E     e  e  I  I  I  5  I  I  I  t  i  E  E  _  _  1  
                N  N  R  R     n     N  N  N  0  N  N  N     z  R  R  d  c     
                T  F  V  V           T  T  T     T  T  T        V  V  t  l     
                   I  E  E                                      E  E  a  k     
                   G  D  D                                      D  D           
                                                                               
                                                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A1       1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       3/22( 13%)   
A2       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    2/2    1/2       4/22( 18%)   
A3       8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    0/2       9/22( 40%)   
A4       7/ 8( 87%)   0/ 8(  0%)   5/ 8( 62%)    0/2    0/2      11/22( 50%)   
A5       8/ 8(100%)   4/ 8( 50%)   4/ 8( 50%)    1/2    0/2       8/22( 36%)   
A6       1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       2/22(  9%)   
A7       8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    0/2       5/22( 22%)   
A8       8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      17/22( 77%)   
A9       8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    0/2       4/22( 18%)   
A10      7/ 8( 87%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      10/22( 45%)   
A11      7/ 8( 87%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       8/22( 36%)   
A12      8/ 8(100%)   0/ 8(  0%)   7/ 8( 87%)    0/2    0/2       6/22( 27%)   
A13      3/ 8( 37%)   0/ 8(  0%)   3/ 8( 37%)    0/2    0/2       4/22( 18%)   
A14      6/ 8( 75%)   1/ 8( 12%)   3/ 8( 37%)    0/2    0/2      13/22( 59%)   
A16      8/ 8(100%)   1/ 8( 12%)   5/ 8( 62%)    1/2    0/2       4/22( 18%)   
A17      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2      14/22( 63%)   
A18      8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    0/2    0/2       8/22( 36%)   
A19      8/ 8(100%)   2/ 8( 25%)   6/ 8( 75%)    1/2    0/2       6/22( 27%)   
A20      8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      17/22( 77%)   
A21      8/ 8(100%)   1/ 8( 12%)   5/ 8( 62%)    0/2    0/2       8/22( 36%)   
A22      8/ 8(100%)   0/ 8(  0%)   7/ 8( 87%)    0/2    0/2       6/22( 27%)   
A23      7/ 8( 87%)   0/ 8(  0%)   3/ 8( 37%)    0/2    0/2      11/22( 50%)   
A24      8/ 8(100%)   2/ 8( 25%)   2/ 8( 25%)    0/2    0/2       4/22( 18%)   
B2       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2       7/22( 31%)   
B7       3/ 8( 37%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       2/22(  9%)   
B9       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       4/22( 18%)   
B11      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       2/22(  9%)   
B12      8/ 8(100%)   1/ 8( 12%)   4/ 8( 50%)    2/2    0/2       7/22( 31%)   
C2       8/ 8(100%)   1/ 8( 12%)   5/ 8( 62%)    2/2    0/2       7/22( 31%)   
C4       6/ 8( 75%)   1/ 8( 12%)   0/ 8(  0%)    1/2    1/2       2/22(  9%)   
C10      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2       5/22( 22%)   
C11      4/ 8( 50%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       8/22( 36%)   
C12      8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       4/22( 18%)   
C13      1/ 8( 12%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2       3/22( 13%)   
C21      7/ 8( 87%)   0/ 8(  0%)   3/ 8( 37%)    2/2    0/2       6/22( 27%)   
C22      1/ 8( 12%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2       3/22( 13%)   
C23      3/ 8( 37%)   3/ 8( 37%)   0/ 8(  0%)    0/2    0/2       3/22( 13%)   
C24      8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    0/2       2/22(  9%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 1/6      ( 16%)
Total I/O pins used:                            29/53     ( 54%)
Total logic cells used:                        241/576    ( 41%)
Total embedded cells used:                       0/24     (  0%)
Total EABs used:                                 0/3      (  0%)
Average fan-in:                                 3.34/4    ( 83%)
Total fan-in:                                 807/2304    ( 35%)

Total input pins required:                       5
Total input I/O cell registers required:         0
Total output pins required:                     24
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               1
Total reserved pins required                     0
Total logic cells required:                    241
Total flipflops required:                       58
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                        56/ 576   (  9%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      1   8   8   7   8   1   8   8   8   7   7   8   0   3   6   0   8   8   8   8   8   8   8   7   8    159/0  
 B:      0   8   0   0   0   0   3   0   8   0   1   8   0   0   0   0   0   0   0   0   0   0   0   0   0     28/0  
 C:      0   8   0   6   0   0   0   0   0   8   4   8   0   1   0   0   0   0   0   0   0   7   1   3   8     54/0  

Total:   1  24   8  13   8   1  11   8  16  15  12  24   0   4   6   0   8   8   8   8   8  15   9  10  16    241/0  



Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  43      -     -    -    --      INPUT  G             0    0    0    0  clk50
  51      -     -    -    18     OPNDRN                0    0    0    0  kbd_dta
  54      -     -    -    21      INPUT                0    0    0    4  t1
  59      -     -    C    --      INPUT                0    0    0    0  t2
  61      -     -    C    --      INPUT                0    0    0    4  t3
  64      -     -    B    --      INPUT                0    0    0    0  t4


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  39      -     -    -    11     OUTPUT                0    0    0    0  blue
   5      -     -    -    05     OUTPUT                0    1    0    0  dig1
  83      -     -    -    13     OUTPUT                0    1    0    0  dig2
  79      -     -    -    24     OUTPUT                0    1    0    0  dig3
  80      -     -    -    23     OUTPUT                0    1    0    0  dig4
  78      -     -    -    24     OUTPUT                0    1    0    0  dig5
  81      -     -    -    22     OUTPUT                0    1    0    0  dig6
  38      -     -    -    10     OUTPUT                0    0    0    0  green
  48      -     -    -    15     OUTPUT                0    0    0    0  horiz
  52      -     -    -    19     OPNDRN                0    0    0    0  kbd_clk
  51      -     -    -    18     OPNDRN                0    0    0    0  kbd_dta
  53      -     -    -    20     OUTPUT                0    1    0    0  led1
  58      -     -    C    --     OUTPUT                0    1    0    0  led2
  60      -     -    C    --     OUTPUT                0    1    0    0  led3
  62      -     -    C    --     OUTPUT                0    1    0    0  led4
  37      -     -    -    09     OUTPUT                0    0    0    0  red
  67      -     -    B    --     OUTPUT                0    1    0    0  seg_a
  70      -     -    A    --     OUTPUT                0    1    0    0  seg_b
  69      -     -    A    --     OUTPUT                0    1    0    0  seg_c
  66      -     -    B    --     OUTPUT                0    1    0    0  seg_d
  71      -     -    A    --     OUTPUT                0    1    0    0  seg_dp
  73      -     -    A    --     OUTPUT                0    1    0    0  seg_e
  65      -     -    B    --     OUTPUT                0    1    0    0  seg_f
  72      -     -    A    --     OUTPUT                0    1    0    0  seg_g
  47      -     -    -    14     OUTPUT                0    0    0    0  vert


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      8     -    A    05       AND2    s   !       0    3    0    2  |bin6bcd:274|lo1~1
   -      1     -    A    17        OR2    s   !       0    4    0    3  |bin6bcd:274|lo2~1
   -      2     -    A    23        OR2    s           0    3    0    1  |bin6bcd:274|lo2~2
   -      3     -    A    20        OR2    s   !       0    4    0    1  |bin6bcd:274|lo2~3
   -      4     -    A    20        OR2    s   !       0    4    0    1  |bin6bcd:274|lo2~4
   -      5     -    A    20        OR2                0    4    0    1  |bin6bcd:274|lo2
   -      3     -    A    23        OR2    s   !       0    4    0    1  |bin6bcd:274|lo3~1
   -      6     -    A    23        OR2    s   !       0    4    0    1  |bin6bcd:274|lo3~2
   -      7     -    A    23        OR2    s   !       0    4    0    1  |bin6bcd:274|lo3~3
   -      2     -    A    20       AND2        !       0    2    0    5  |bin6bcd:274|:48
   -      7     -    A    21        OR2        !       0    4    0    8  |bin6bcd:274|:52
   -      5     -    A    19        OR2                0    4    0    7  |bin6bcd:274|:58
   -      7     -    A    19        OR2        !       0    4    1    2  |bin6bcd:274|:67
   -      3     -    A    21       AND2        !       0    2    0    3  |bin6bcd:274|:70
   -      2     -    A    21        OR2        !       0    4    0    4  |bin6bcd:274|:80
   -      7     -    A    17       AND2                0    3    0    1  |bin6bcd:274|:89
   -      2     -    A    17        OR2        !       0    4    0    4  |bin6bcd:274|:116
   -      6     -    A    21        OR2        !       0    4    0    4  |bin6bcd:274|:154
   -      5     -    A    21        OR2    s           0    3    0    2  |bin6bcd:274|~187~1
   -      4     -    A    21       AND2                0    3    0    3  |bin6bcd:274|:187
   -      4     -    A    19        OR2        !       0    2    0    2  |bin6bcd:274|:198
   -      4     -    A    23        OR2        !       0    3    0    2  |bin6bcd:274|:225
   -      8     -    A    21        OR2        !       0    4    0    3  |bin6bcd:274|:262
   -      5     -    A    23        OR2                0    4    0    1  |bin6bcd:274|:293
   -      4     -    A    11       AND2    s   !       0    3    0    2  |bin6bcd:275|lo1~1
   -      6     -    A    04        OR2    s   !       0    4    0    3  |bin6bcd:275|lo2~1
   -      2     -    A    11        OR2    s   !       0    4    0    1  |bin6bcd:275|lo2~2
   -      5     -    A    11        OR2    s   !       0    4    0    1  |bin6bcd:275|lo2~3
   -      6     -    A    11        OR2    s           0    3    0    1  |bin6bcd:275|lo2~4
   -      3     -    A    11        OR2                0    4    0    1  |bin6bcd:275|lo2
   -      1     -    A    10        OR2    s   !       0    4    0    1  |bin6bcd:275|lo3~1
   -      6     -    A    10        OR2    s   !       0    4    0    1  |bin6bcd:275|lo3~2
   -      5     -    A    10       AND2        !       0    2    0    4  |bin6bcd:275|:48
   -      7     -    A    12        OR2        !       0    4    0    8  |bin6bcd:275|:52
   -      4     -    A    12        OR2                0    4    0    7  |bin6bcd:275|:58
   -      6     -    A    12        OR2        !       0    4    0    2  |bin6bcd:275|:66
   -      5     -    A    12        OR2        !       0    4    0    4  |bin6bcd:275|:80
   -      1     -    A    12        OR2    s   !       0    3    0    4  |bin6bcd:275|~88~1
   -      4     -    A    04       AND2                0    3    0    1  |bin6bcd:275|:89
   -      3     -    A    04        OR2        !       0    4    0    4  |bin6bcd:275|:116
   -      4     -    A    10        OR2                0    3    0    1  |bin6bcd:275|:147
   -      2     -    A    12        OR2    s           0    4    0    1  |bin6bcd:275|~154~1
   -      2     -    A    04        OR2        !       0    2    0    4  |bin6bcd:275|:154
   -      8     -    A    12        OR2    s           0    4    0    2  |bin6bcd:275|~187~1
   -      1     -    A    11       AND2                0    3    0    3  |bin6bcd:275|:187
   -      3     -    A    10        OR2                0    4    0    1  |bin6bcd:275|:218
   -      3     -    A    12        OR2        !       0    4    0    2  |bin6bcd:275|:225
   -      5     -    A    17        OR2                0    2    0    1  |bin6bcd:275|:226
   -      8     -    A    11        OR2        !       0    4    0    3  |bin6bcd:275|:262
   -      2     -    A    10        OR2                0    4    0    1  |bin6bcd:275|:293
   -      4     -    A    18       AND2    s   !       0    3    0    2  |bin6bcd:293|lo1~1
   -      6     -    A    18        OR2    s   !       0    3    0    3  |bin6bcd:293|lo2~1
   -      5     -    A    18        OR2    s   !       0    4    0    1  |bin6bcd:293|lo2~2
   -      6     -    A    20        OR2    s   !       0    4    0    1  |bin6bcd:293|lo2~3
   -      6     -    A    13        OR2    s           0    3    0    1  |bin6bcd:293|lo2~4
   -      7     -    A    20        OR2                0    4    0    1  |bin6bcd:293|lo2
   -      1     -    A    18        OR2    s   !       0    4    0    1  |bin6bcd:293|lo3~1
   -      8     -    A    22        OR2    s   !       0    4    0    1  |bin6bcd:293|lo3~2
   -      5     -    A    14        OR2                0    4    0    1  |bin6bcd:293|lo3
   -      1     -    A    22       AND2        !       0    2    0    4  |bin6bcd:293|:48
   -      4     -    A    22        OR2        !       0    4    0    8  |bin6bcd:293|:52
   -      6     -    A    22        OR2                0    4    0    7  |bin6bcd:293|:58
   -      6     -    A    03        OR2    s           0    3    0    3  |bin6bcd:293|~66~1
   -      5     -    A    03        OR2                0    3    0    1  |bin6bcd:293|:67
   -      5     -    A    22        OR2        !       0    4    0    4  |bin6bcd:293|:80
   -      7     -    A    22       AND2                0    4    0    3  |bin6bcd:293|:88
   -      3     -    A    18        OR2        !       0    3    0    4  |bin6bcd:293|:116
   -      3     -    A    22        OR2    s           0    4    0    2  |bin6bcd:293|~154~1
   -      8     -    A    18        OR2        !       0    2    0    3  |bin6bcd:293|:154
   -      2     -    A    18        OR2                0    4    0    1  |bin6bcd:293|:155
   -      4     -    A    03        OR2    s           0    4    0    2  |bin6bcd:293|~187~1
   -      4     -    A    13       AND2                0    3    0    3  |bin6bcd:293|:187
   -      4     -    A    14        OR2                0    4    0    1  |bin6bcd:293|:218
   -      7     -    A    18        OR2        !       0    3    0    2  |bin6bcd:293|:225
   -      4     -    A    17        OR2                0    2    0    1  |bin6bcd:293|:226
   -      8     -    A    13        OR2        !       0    4    0    3  |bin6bcd:293|:262
   -      2     -    A    22        OR2                0    4    0    1  |bin6bcd:293|:293
   -      5     -    C    21       AND2        !       0    4    0    4  |clock1_base:283|div50_loop:16|:87
   -      1     -    C    24       AND2        !       0    3    0    2  |clock1_base:283|div50_loop:16|:132
   -      1     -    C    21        OR2                0    4    0    2  |clock1_base:283|div50_loop:16|:154
   -      8     -    C    24       AND2                0    3    0    1  |clock1_base:283|div50_loop:16|:165
   -      4     -    C    24       AND2                0    4    0    2  |clock1_base:283|div50_loop:16|:169
   -      7     -    C    21        OR2    s           0    4    0    5  |clock1_base:283|div50_loop:16|~187~1
   -      4     -    C    21       AND2    s           0    4    0    1  |clock1_base:283|div50_loop:16|~197~1
   -      6     -    C    24       AND2    s           0    2    0    1  |clock1_base:283|div50_loop:16|~197~2
   -      5     -    C    24       DFFE   +            0    2    0    6  |clock1_base:283|div50_reg:17|reg0
   -      7     -    C    24       DFFE   +            0    2    0    5  |clock1_base:283|div50_reg:17|reg1
   -      3     -    C    24       DFFE   +            0    3    0    4  |clock1_base:283|div50_reg:17|reg2
   -      2     -    C    24       DFFE   +            0    3    0    5  |clock1_base:283|div50_reg:17|reg3
   -      2     -    C    21       DFFE   +            0    3    0    5  |clock1_base:283|div50_reg:17|reg4
   -      3     -    C    21       DFFE   +            0    3    0    4  |clock1_base:283|div50_reg:17|reg5
   -      5     -    C    10       AND2        !       0    2    0    4  |clock1_base:283|div1000_loop:19|:50
   -      3     -    C    10        OR2                0    3    0    1  |clock1_base:283|div1000_loop:19|:67
   -      1     -    C    12        OR2    s   !       0    4    0    3  |clock1_base:283|div1000_loop:19|~136~1
   -      1     -    C    10       AND2        !       0    4    0    7  |clock1_base:283|div1000_loop:19|:136
   -      4     -    C    10       AND2        !       0    2    0    3  |clock1_base:283|div1000_loop:19|:208
   -      8     -    C    02        OR2    s   !       0    2    0    3  |clock1_base:283|div1000_loop:19|~218~1
   -      3     -    C    02        OR2                0    4    0    1  |clock1_base:283|div1000_loop:19|:243
   -      4     -    C    11        OR2                0    4    0    2  |clock1_base:283|div1000_loop:19|:244
   -      2     -    C    10       AND2                0    2    0    5  |clock1_base:283|div1000_loop:19|:255
   -      5     -    C    02       AND2                0    2    0    1  |clock1_base:283|div1000_loop:19|:259
   -      4     -    C    02       AND2                0    3    0    4  |clock1_base:283|div1000_loop:19|:263
   -      7     -    C    12       AND2                0    2    0    1  |clock1_base:283|div1000_loop:19|:267
   -      4     -    C    12       AND2                0    3    0    1  |clock1_base:283|div1000_loop:19|:271
   -      2     -    C    12       AND2                0    4    0    2  |clock1_base:283|div1000_loop:19|:275
   -      3     -    C    11        OR2    s           0    3    0    9  |clock1_base:283|div1000_loop:19|~301~1
   -      2     -    C    11        OR2    s   !       0    2    0    1  |clock1_base:283|div1000_loop:19|~320~1
   -      7     -    C    02       AND2    s           0    4    0    1  |clock1_base:283|div1000_loop:19|~320~2
   -      8     -    B    07       AND2        !       0    2    0    4  |clock1_base:283|div1000_loop:20|:50
   -      7     -    B    02        OR2                0    3    0    1  |clock1_base:283|div1000_loop:20|:67
   -      1     -    B    09        OR2    s   !       0    4    0    3  |clock1_base:283|div1000_loop:20|~136~1
   -      1     -    B    02       AND2        !       0    4    0    7  |clock1_base:283|div1000_loop:20|:136
   -      3     -    B    02       AND2        !       0    2    0    3  |clock1_base:283|div1000_loop:20|:208
   -      1     -    B    12        OR2    s   !       0    2    0    3  |clock1_base:283|div1000_loop:20|~218~1
   -      2     -    B    12        OR2                0    4    0    1  |clock1_base:283|div1000_loop:20|:243
   -      4     -    B    02        OR2                0    4    0    2  |clock1_base:283|div1000_loop:20|:244
   -      2     -    B    02       AND2                0    2    0    5  |clock1_base:283|div1000_loop:20|:255
   -      4     -    B    12       AND2                0    2    0    1  |clock1_base:283|div1000_loop:20|:259
   -      3     -    B    12       AND2                0    3    0    4  |clock1_base:283|div1000_loop:20|:263
   -      7     -    B    09       AND2                0    2    0    1  |clock1_base:283|div1000_loop:20|:267
   -      4     -    B    09       AND2                0    3    0    1  |clock1_base:283|div1000_loop:20|:271
   -      2     -    B    09       AND2                0    4    0    2  |clock1_base:283|div1000_loop:20|:275
   -      6     -    B    02        OR2    s           0    3    0    9  |clock1_base:283|div1000_loop:20|~301~1
   -      1     -    B    11        OR2    s   !       0    2    0    1  |clock1_base:283|div1000_loop:20|~320~1
   -      7     -    B    12       AND2    s           0    4    0    1  |clock1_base:283|div1000_loop:20|~320~2
   -      7     -    C    10       DFFE                0    2    0    2  |clock1_base:283|div1000_reg:18|reg0
   -      6     -    C    10       DFFE                0    3    0    1  |clock1_base:283|div1000_reg:18|reg1
   -      8     -    C    10       DFFE                0    4    0    2  |clock1_base:283|div1000_reg:18|reg2
   -      2     -    C    02       DFFE                0    3    0    5  |clock1_base:283|div1000_reg:18|reg3
   -      6     -    C    02       DFFE                0    4    0    4  |clock1_base:283|div1000_reg:18|reg4
   -      6     -    C    12       DFFE                0    4    0    4  |clock1_base:283|div1000_reg:18|reg5
   -      8     -    C    12       DFFE                0    4    0    3  |clock1_base:283|div1000_reg:18|reg6
   -      5     -    C    12       DFFE                0    4    0    2  |clock1_base:283|div1000_reg:18|reg7
   -      3     -    C    12       DFFE                0    4    0    2  |clock1_base:283|div1000_reg:18|reg8
   -      1     -    C    11       DFFE                0    4    0    5  |clock1_base:283|div1000_reg:18|reg9
   -      2     -    B    07       DFFE                0    2    0    2  |clock1_base:283|div1000_reg:21|reg0
   -      1     -    B    07       DFFE                0    3    0    1  |clock1_base:283|div1000_reg:21|reg1
   -      8     -    B    02       DFFE                0    4    0    2  |clock1_base:283|div1000_reg:21|reg2
   -      8     -    B    12       DFFE                0    3    0    5  |clock1_base:283|div1000_reg:21|reg3
   -      5     -    B    12       DFFE                0    4    0    4  |clock1_base:283|div1000_reg:21|reg4
   -      6     -    B    09       DFFE                0    4    0    4  |clock1_base:283|div1000_reg:21|reg5
   -      8     -    B    09       DFFE                0    4    0    3  |clock1_base:283|div1000_reg:21|reg6
   -      5     -    B    09       DFFE                0    4    0    2  |clock1_base:283|div1000_reg:21|reg7
   -      3     -    B    09       DFFE                0    4    0    2  |clock1_base:283|div1000_reg:21|reg8
   -      5     -    B    02       DFFE                0    4    0    5  |clock1_base:283|div1000_reg:21|reg9
   -      6     -    C    21       DFFE   +            0    3    0   11  |clock1_base:283|CLK1MHZ (|clock1_base:283|:31)
   -      1     -    C    02       DFFE                0    4    0   16  |clock1_base:283|CLK1KHZ (|clock1_base:283|:32)
   -      6     -    B    12       DFFE                0    4    0   19  |clock1_base:283|CLK1HZ (|clock1_base:283|:33)
   -      5     -    A    09       DFFE                0    3    0    5  |clock1_timer:292|v_hour0
   -      1     -    A    09       DFFE                0    4    0    8  |clock1_timer:292|v_hour1
   -      3     -    A    03       DFFE                0    4    0   10  |clock1_timer:292|v_hour2
   -      3     -    A    09       DFFE                0    4    0   14  |clock1_timer:292|v_hour3
   -      2     -    A    09       DFFE                0    4    0    8  |clock1_timer:292|v_hour4
   -      4     -    A    09       DFFE                0    4    0    8  |clock1_timer:292|v_hour5
   -      2     -    A    02       DFFE                0    4    0    3  |clock1_timer:292|v_minute0
   -      1     -    A    07       DFFE                0    4    0    7  |clock1_timer:292|v_minute1
   -      3     -    A    07       DFFE                0    4    0   13  |clock1_timer:292|v_minute2
   -      2     -    A    07       DFFE                0    4    0   14  |clock1_timer:292|v_minute3
   -      4     -    A    07       DFFE                0    4    0    8  |clock1_timer:292|v_minute4
   -      8     -    A    07       DFFE                0    4    0    7  |clock1_timer:292|v_minute5
   -      2     -    A    19       DFFE                0    1    0    6  |clock1_timer:292|v_seconds0
   -      3     -    A    19       DFFE                0    3    0    8  |clock1_timer:292|v_seconds1
   -      5     -    A    16       DFFE                0    3    0   14  |clock1_timer:292|v_seconds2
   -      3     -    A    16       DFFE                0    4    0   12  |clock1_timer:292|v_seconds3
   -      1     -    A    16       DFFE                0    3    0    9  |clock1_timer:292|v_seconds4
   -      2     -    A    16       DFFE                0    4    0   10  |clock1_timer:292|v_seconds5
   -      1     -    A    19        OR2    s           0    3    0    4  |clock1_timer:292|~79~1
   -      6     -    A    16        OR2                0    3    0   10  |clock1_timer:292|:79
   -      1     -    A    04        OR2                0    3    0    3  |clock1_timer:292|:89
   -      7     -    A    03        OR2                0    4    0    1  |clock1_timer:292|:101
   -      7     -    A    16        OR2        !       0    2    0    3  |clock1_timer:292|:183
   -      8     -    A    16       AND2                0    4    0    3  |clock1_timer:292|:191
   -      8     -    A    03       AND2                0    2    0    1  |clock1_timer:292|:213
   -      6     -    A    09       AND2                0    3    0    3  |clock1_timer:292|:217
   -      7     -    A    09       AND2                0    2    0    1  |clock1_timer:292|:221
   -      8     -    A    09       AND2                0    3    0    1  |clock1_timer:292|:225
   -      2     -    A    03        OR2    s           0    4    0    6  |clock1_timer:292|~253~1
   -      1     -    A    03        OR2    s           0    3    0    6  |clock1_timer:292|~255~1
   -      1     -    A    06       AND2                0    2    0    3  |clock1_timer:292|:263
   -      5     -    A    07       AND2                0    2    0    3  |clock1_timer:292|:267
   -      6     -    A    07       AND2                0    2    0    1  |clock1_timer:292|:271
   -      7     -    A    07       AND2                0    3    0    1  |clock1_timer:292|:275
   -      1     -    A    02       AND2                0    2    0    6  |clock1_timer:292|:293
   -      1     -    A    01        OR2    s           0    3    0    5  |clock1_timer:292|~303~1
   -      1     -    A    21       AND2        !       0    4    1    0  |clock1_timer:292|:312
   -      4     -    A    16       AND2        !       0    3    1    0  |clock1_timer:292|:322
   -      6     -    A    19        OR2    s           0    3    0    1  |clock1_timer:292|~338~1
   -      8     -    A    19        OR2        !       0    4    1    0  |clock1_timer:292|:341
   -      7     -    A    05       DFFE                0    1    0    9  |digilab_display:272|digitcounter0
   -      2     -    A    05       DFFE                0    2    0    8  |digilab_display:272|digitcounter1
   -      3     -    A    05       DFFE                0    3    0    7  |digilab_display:272|digitcounter2
   -      4     -    A    08        OR2    s           0    4    0    1  |digilab_display:272|digitvalue0~1
   -      5     -    A    08        OR2    s           0    3    0    1  |digilab_display:272|digitvalue0~2
   -      2     -    A    08       AND2        !       0    4    0    9  |digilab_display:272|digitvalue0
   -      6     -    A    17        OR2    s   !       0    4    0    1  |digilab_display:272|digitvalue1~1
   -      8     -    A    17        OR2    s   !       0    4    0    1  |digilab_display:272|digitvalue1~2
   -      1     -    A    08        OR2                0    4    0    9  |digilab_display:272|digitvalue1
   -      5     -    A    04        OR2    s   !       0    4    0    1  |digilab_display:272|digitvalue2~1
   -      8     -    A    20        OR2    s   !       0    4    0    1  |digilab_display:272|digitvalue2~2
   -      1     -    A    20        OR2                0    4    0    9  |digilab_display:272|digitvalue2
   -      4     -    A    05        OR2                0    4    1    0  |digilab_display:272|dpvalue
   -      6     -    A    05        OR2                0    3    1    4  |digilab_display:272|:92
   -      1     -    A    05        OR2        !       0    4    0    1  |digilab_display:272|:94
   -      5     -    A    05        OR2                0    4    0    1  |digilab_display:272|:96
   -      1     -    A    23        OR2                0    4    0    1  |digilab_display:272|:100
   -      2     -    C    13        OR2                0    3    1    3  |digilab_display:272|:105
   -      3     -    A    17        OR2                0    4    0    1  |digilab_display:272|:113
   -      8     -    C    23        OR2                0    3    1    4  |digilab_display:272|:123
   -      6     -    A    08        OR2        !       0    4    0    1  |digilab_display:272|:125
   -      7     -    A    08        OR2                0    4    0    1  |digilab_display:272|:128
   -      8     -    A    10        OR2                0    4    0    1  |digilab_display:272|:134
   -      6     -    C    23        OR2                0    3    1    3  |digilab_display:272|:142
   -      7     -    A    04        OR2                0    4    0    1  |digilab_display:272|:150
   -      5     -    C    23        OR2                0    3    1    4  |digilab_display:272|:160
   -      3     -    A    08        OR2        !       0    4    0    1  |digilab_display:272|:162
   -      8     -    A    08        OR2                0    4    0    1  |digilab_display:272|:165
   -      2     -    A    14        OR2                0    4    0    9  |digilab_display:272|:172
   -      1     -    C    22        OR2                0    3    1    3  |digilab_display:272|:179
   -      6     -    A    24       AND2        !       0    4    0    1  |digilab_display:272|:253
   -      1     -    A    24        OR2                0    4    1    0  |digilab_display:272|:299
   -      3     -    A    14        OR2                0    4    1    0  |digilab_display:272|:327
   -      1     -    A    14        OR2                0    4    1    0  |digilab_display:272|:335
   -      3     -    A    24        OR2    s           0    4    0    2  |digilab_display:272|~337~1
   -      4     -    A    24        OR2    s           0    4    0    1  |digilab_display:272|~337~2
   -      5     -    A    24        OR2                0    2    1    0  |digilab_display:272|:337
   -      8     -    A    14        OR2                0    4    1    0  |digilab_display:272|:356
   -      7     -    A    24        OR2                0    4    1    0  |digilab_display:272|:358
   -      8     -    A    24        OR2    s           0    4    0    1  |digilab_display:272|~360~1
   -      2     -    A    24        OR2                0    3    1    0  |digilab_display:272|:360
   -      5     -    A    02       DFFE                1    1    0    2  |key_debounce:288|:6
   -      6     -    A    02       DFFE                1    2    0    2  |key_debounce:288|:7
   -      7     -    A    02       DFFE                1    2    0    2  |key_debounce:288|:8
   -      8     -    A    02       DFFE                1    2    0    1  |key_debounce:288|:9
   -      4     -    A    02       AND2                0    2    0    4  |key_debounce:288|:11
   -      3     -    A    02        OR2        !       0    4    0    4  |key_debounce:288|KEYDEB (|key_debounce:288|:12)
   -      3     -    C    04       DFFE                1    1    0    2  |key_debounce:289|:6
   -      4     -    C    04       DFFE                1    2    0    2  |key_debounce:289|:7
   -      5     -    C    04       DFFE                1    2    0    2  |key_debounce:289|:8
   -      6     -    C    04       DFFE                1    2    0    1  |key_debounce:289|:9
   -      2     -    C    04       AND2                0    2    0    4  |key_debounce:289|:11
   -      1     -    C    04        OR2        !       0    4    0    3  |key_debounce:289|KEYDEB (|key_debounce:289|:12)


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      48/ 96( 50%)    27/ 48( 56%)    25/ 48( 52%)    0/16(  0%)      5/16( 31%)     0/16(  0%)
B:       1/ 96(  1%)    13/ 48( 27%)     3/ 48(  6%)    1/16(  6%)      3/16( 18%)     0/16(  0%)
C:       8/ 96(  8%)    14/ 48( 29%)    11/ 48( 22%)    2/16( 12%)      3/16( 18%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      4/24( 16%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
12:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
14:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
16:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
19:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
21:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
23:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
24:      3/24( 12%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

** CLOCK SIGNALS **

Type     Fan-out       Name
DFF         20         |clock1_base:283|CLK1HZ
DFF         17         |clock1_base:283|CLK1KHZ
DFF         12         |clock1_base:283|CLK1MHZ
INPUT        7         clk50
LCELL        4         |key_debounce:288|:11
LCELL        4         |key_debounce:289|:11


Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        4         t1
INPUT        4         t3


Device-Specific Information:        c:\projects\digilab\clock_1_001\clock1.rpt
clock1

** EQUATIONS **

clk50    : INPUT;
t1       : INPUT;
t2       : INPUT;
t3       : INPUT;
t4       : INPUT;

-- Node name is 'blue' 
-- Equation name is 'blue', type is output 
blue     =  GND;

-- Node name is 'dig1' 
-- Equation name is 'dig1', type is output 
dig1     = !_LC6_A5;

-- Node name is 'dig2' 
-- Equation name is 'dig2', type is output 
dig2     = !_LC2_C13;

-- Node name is 'dig3' 
-- Equation name is 'dig3', type is output 
dig3     = !_LC8_C23;

-- Node name is 'dig4' 
-- Equation name is 'dig4', type is output 
dig4     = !_LC6_C23;

-- Node name is 'dig5' 
-- Equation name is 'dig5', type is output 
dig5     = !_LC5_C23;

-- Node name is 'dig6' 
-- Equation name is 'dig6', type is output 
dig6     = !_LC1_C22;

-- Node name is 'green' 
-- Equation name is 'green', type is output 
green    =  GND;

-- Node name is 'horiz' 
-- Equation name is 'horiz', type is output 
horiz    =  GND;

-- Node name is 'kbd_clk' 
-- Equation name is 'kbd_clk', type is output 
kbd_clk  = OPNDRN(VCC);

-- Node name is 'kbd_dta' 
-- Equation name is 'kbd_dta', type is bidir 
kbd_dta  = OPNDRN(VCC);

-- Node name is 'led1' 
-- Equation name is 'led1', type is output 
led1     = !_LC8_A19;

-- Node name is 'led2' 
-- Equation name is 'led2', type is output 
led2     = !_LC7_A19;

-- Node name is 'led3' 
-- Equation name is 'led3', type is output 
led3     = !_LC4_A16;

-- Node name is 'led4' 
-- Equation name is 'led4', type is output 
led4     = !_LC1_A21;

-- Node name is 'red' 
-- Equation name is 'red', type is output 
red      =  GND;

-- Node name is 'seg_a' 
-- Equation name is 'seg_a', type is output 
seg_a    =  _LC1_A14;

-- Node name is 'seg_b' 
-- Equation name is 'seg_b', type is output 
seg_b    =  _LC8_A14;

-- Node name is 'seg_c' 
-- Equation name is 'seg_c', type is output 
seg_c    =  _LC7_A24;

-- Node name is 'seg_d' 
-- Equation name is 'seg_d', type is output 
seg_d    =  _LC2_A24;

-- Node name is 'seg_dp' 
-- Equation name is 'seg_dp', type is output 
seg_dp   =  _LC4_A5;

-- Node name is 'seg_e' 
-- Equation name is 'seg_e', type is output 
seg_e    =  _LC1_A24;

-- Node name is 'seg_f' 
-- Equation name is 'seg_f', type is output 
seg_f    =  _LC5_A24;

-- Node name is 'seg_g' 
-- Equation name is 'seg_g', type is output 
seg_g    =  _LC3_A14;

-- Node name is 'vert' 
-- Equation name is 'vert', type is output 
vert     =  GND;

-- Node name is '|bin6bcd:274|lo1~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC8_A5', type is buried 
-- synthesized logic cell 
!_LC8_A5 = _LC8_A5~NOT;
_LC8_A5~NOT = LCELL( _EQ001);
  _EQ001 = !_LC1_A17 & !_LC6_A21 &  _LC7_A21;

-- Node name is '|bin6bcd:274|lo2~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC1_A17', type is buried 
-- synthesized logic cell 
!_LC1_A17 = _LC1_A17~NOT;
_LC1_A17~NOT = LCELL( _EQ002);
  _EQ002 = !_LC4_A23 & !_LC5_A16
         #  _LC1_A19 & !_LC4_A23
         # !_LC2_A21 & !_LC4_A23;

-- Node name is '|bin6bcd:274|lo2~2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC2_A23', type is buried 
-- synthesized logic cell 
_LC2_A23 = LCELL( _EQ003);
  _EQ003 = !_LC5_A19 &  _LC7_A21
         #  _LC2_A17;

-- Node name is '|bin6bcd:274|lo2~3' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC3_A20', type is buried 
-- synthesized logic cell 
!_LC3_A20 = _LC3_A20~NOT;
_LC3_A20~NOT = LCELL( _EQ004);
  _EQ004 =  _LC1_A17 & !_LC5_A16
         #  _LC5_A16 &  _LC6_A21
         #  _LC5_A16 & !_LC7_A21;

-- Node name is '|bin6bcd:274|lo2~4' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC4_A20', type is buried 
-- synthesized logic cell 
!_LC4_A20 = _LC4_A20~NOT;
_LC4_A20~NOT = LCELL( _EQ005);
  _EQ005 =  _LC2_A23 & !_LC3_A19 & !_LC5_A16
         #  _LC2_A23 &  _LC3_A19 &  _LC5_A16
         # !_LC3_A20;

-- Node name is '|bin6bcd:274|lo2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ006);
  _EQ006 =  _LC3_A19 &  _LC4_A21 & !_LC5_A16
         # !_LC3_A19 &  _LC4_A21 &  _LC5_A16
         # !_LC4_A20;

-- Node name is '|bin6bcd:274|lo3~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC3_A23', type is buried 
-- synthesized logic cell 
!_LC3_A23 = _LC3_A23~NOT;
_LC3_A23~NOT = LCELL( _EQ007);
  _EQ007 = !_LC3_A16 &  _LC4_A23 & !_LC5_A16
         #  _LC3_A16 &  _LC4_A23 &  _LC5_A16
         # !_LC3_A16 &  _LC6_A21;

-- Node name is '|bin6bcd:274|lo3~2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC6_A23', type is buried 
-- synthesized logic cell 
!_LC6_A23 = _LC6_A23~NOT;
_LC6_A23~NOT = LCELL( _EQ008);
  _EQ008 =  _LC2_A17 &  _LC2_A20 &  _LC3_A16
         #  _LC2_A17 & !_LC2_A20 & !_LC3_A16
         #  _LC3_A16 & !_LC7_A21;

-- Node name is '|bin6bcd:274|lo3~3' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC7_A23', type is buried 
-- synthesized logic cell 
!_LC7_A23 = _LC7_A23~NOT;
_LC7_A23~NOT = LCELL( _EQ009);
  _EQ009 = !_LC3_A16 &  _LC4_A19 &  _LC4_A21
         #  _LC3_A16 & !_LC4_A19 &  _LC4_A21
         # !_LC6_A23;

-- Node name is '|bin6bcd:274|:48' from file "bin6bcd.tdf" line 8, column 13
-- Equation name is '_LC2_A20', type is buried 
!_LC2_A20 = _LC2_A20~NOT;
_LC2_A20~NOT = LCELL( _EQ010);
  _EQ010 = !_LC3_A19 & !_LC5_A16;

-- Node name is '|bin6bcd:274|:52' from file "bin6bcd.tdf" line 8, column 13
-- Equation name is '_LC7_A21', type is buried 
!_LC7_A21 = _LC7_A21~NOT;
_LC7_A21~NOT = LCELL( _EQ011);
  _EQ011 = !_LC1_A16 & !_LC2_A16 & !_LC2_A20
         # !_LC1_A16 & !_LC2_A16 & !_LC3_A16;

-- Node name is '|bin6bcd:274|:58' from file "bin6bcd.tdf" line 9, column 15
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = LCELL( _EQ012);
  _EQ012 =  _LC1_A16 &  _LC3_A16
         #  _LC1_A16 &  _LC5_A16
         #  _LC2_A16;

-- Node name is '|bin6bcd:274|:67' from file "bin6bcd.tdf" line 10, column 17
-- Equation name is '_LC7_A19', type is buried 
!_LC7_A19 = _LC7_A19~NOT;
_LC7_A19~NOT = LCELL( _EQ013);
  _EQ013 = !_LC1_A16 & !_LC2_A16
         # !_LC2_A16 & !_LC3_A16
         # !_LC2_A16 & !_LC4_A19;

-- Node name is '|bin6bcd:274|:70' from file "bin6bcd.tdf" line 11, column 19
-- Equation name is '_LC3_A21', type is buried 
!_LC3_A21 = _LC3_A21~NOT;
_LC3_A21~NOT = LCELL( _EQ014);
  _EQ014 = !_LC1_A16 & !_LC3_A16;

-- Node name is '|bin6bcd:274|:80' from file "bin6bcd.tdf" line 12, column 21
-- Equation name is '_LC2_A21', type is buried 
!_LC2_A21 = _LC2_A21~NOT;
_LC2_A21~NOT = LCELL( _EQ015);
  _EQ015 = !_LC2_A20 & !_LC3_A16
         # !_LC2_A16
         # !_LC1_A16;

-- Node name is '|bin6bcd:274|:89' from file "bin6bcd.tdf" line 13, column 15
-- Equation name is '_LC7_A17', type is buried 
_LC7_A17 = LCELL( _EQ016);
  _EQ016 = !_LC1_A19 &  _LC2_A21 &  _LC5_A16;

-- Node name is '|bin6bcd:274|:116' from file "bin6bcd.tdf" line 13, column 15
-- Equation name is '_LC2_A17', type is buried 
!_LC2_A17 = _LC2_A17~NOT;
_LC2_A17~NOT = LCELL( _EQ017);
  _EQ017 = !_LC2_A21
         # !_LC1_A19 &  _LC5_A16
         # !_LC5_A19;

-- Node name is '|bin6bcd:274|:154' from file "bin6bcd.tdf" line 12, column 13
-- Equation name is '_LC6_A21', type is buried 
!_LC6_A21 = _LC6_A21~NOT;
_LC6_A21~NOT = LCELL( _EQ018);
  _EQ018 = !_LC3_A21
         # !_LC2_A16
         # !_LC5_A19
         #  _LC2_A21;

-- Node name is '|bin6bcd:274|~187~1' from file "bin6bcd.tdf" line 11, column 11
-- Equation name is '_LC5_A21', type is buried 
-- synthesized logic cell 
_LC5_A21 = LCELL( _EQ019);
  _EQ019 =  _LC2_A16 &  _LC3_A21
         # !_LC7_A19;

-- Node name is '|bin6bcd:274|:187' from file "bin6bcd.tdf" line 11, column 11
-- Equation name is '_LC4_A21', type is buried 
_LC4_A21 = LCELL( _EQ020);
  _EQ020 =  _LC5_A19 & !_LC5_A21 &  _LC7_A21;

-- Node name is '|bin6bcd:274|:198' from file "bin6bcd.tdf" line 26, column 23
-- Equation name is '_LC4_A19', type is buried 
!_LC4_A19 = _LC4_A19~NOT;
_LC4_A19~NOT = LCELL( _EQ021);
  _EQ021 = !_LC5_A16
         # !_LC3_A19;

-- Node name is '|bin6bcd:274|:225' from file "bin6bcd.tdf" line 10, column 9
-- Equation name is '_LC4_A23', type is buried 
!_LC4_A23 = _LC4_A23~NOT;
_LC4_A23~NOT = LCELL( _EQ022);
  _EQ022 = !_LC7_A21
         # !_LC5_A19
         #  _LC7_A19;

-- Node name is '|bin6bcd:274|:262' from file "bin6bcd.tdf" line 33, column 15
-- Equation name is '_LC8_A21', type is buried 
!_LC8_A21 = _LC8_A21~NOT;
_LC8_A21~NOT = LCELL( _EQ023);
  _EQ023 = !_LC2_A17 & !_LC7_A21
         # !_LC2_A17 &  _LC5_A19 &  _LC5_A21;

-- Node name is '|bin6bcd:274|:293' from file "bin6bcd.tdf" line 34, column 13
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ024);
  _EQ024 =  _LC2_A20 & !_LC3_A16 & !_LC5_A19 &  _LC7_A21
         # !_LC2_A20 &  _LC3_A16 & !_LC5_A19 &  _LC7_A21;

-- Node name is '|bin6bcd:275|lo1~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC4_A11', type is buried 
-- synthesized logic cell 
!_LC4_A11 = _LC4_A11~NOT;
_LC4_A11~NOT = LCELL( _EQ025);
  _EQ025 = !_LC2_A4 & !_LC6_A4 &  _LC7_A12;

-- Node name is '|bin6bcd:275|lo2~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC6_A4', type is buried 
-- synthesized logic cell 
!_LC6_A4 = _LC6_A4~NOT;
_LC6_A4~NOT = LCELL( _EQ026);
  _EQ026 = !_LC3_A7 & !_LC3_A12
         # !_LC1_A12 & !_LC3_A12
         # !_LC3_A12 & !_LC5_A12;

-- Node name is '|bin6bcd:275|lo2~2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC2_A11', type is buried 
-- synthesized logic cell 
!_LC2_A11 = _LC2_A11~NOT;
_LC2_A11~NOT = LCELL( _EQ027);
  _EQ027 = !_LC3_A7 &  _LC6_A4
         #  _LC2_A4 &  _LC3_A7
         #  _LC3_A7 & !_LC7_A12;

-- Node name is '|bin6bcd:275|lo2~3' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC5_A11', type is buried 
-- synthesized logic cell 
!_LC5_A11 = _LC5_A11~NOT;
_LC5_A11~NOT = LCELL( _EQ028);
  _EQ028 =  _LC1_A7 &  _LC1_A11 & !_LC3_A7
         # !_LC1_A7 &  _LC1_A11 &  _LC3_A7
         # !_LC2_A11;

-- Node name is '|bin6bcd:275|lo2~4' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC6_A11', type is buried 
-- synthesized logic cell 
_LC6_A11 = LCELL( _EQ029);
  _EQ029 = !_LC4_A12 &  _LC7_A12
         #  _LC3_A4;

-- Node name is '|bin6bcd:275|lo2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC3_A11', type is buried 
_LC3_A11 = LCELL( _EQ030);
  _EQ030 = !_LC5_A11
         #  _LC1_A7 &  _LC3_A7 &  _LC6_A11
         # !_LC1_A7 & !_LC3_A7 &  _LC6_A11;

-- Node name is '|bin6bcd:275|lo3~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC1_A10', type is buried 
-- synthesized logic cell 
!_LC1_A10 = _LC1_A10~NOT;
_LC1_A10~NOT = LCELL( _EQ031);
  _EQ031 = !_LC2_A7 & !_LC3_A7 &  _LC3_A12
         #  _LC2_A7 &  _LC3_A7 &  _LC3_A12
         #  _LC2_A4 & !_LC2_A7;

-- Node name is '|bin6bcd:275|lo3~2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC6_A10', type is buried 
-- synthesized logic cell 
!_LC6_A10 = _LC6_A10~NOT;
_LC6_A10~NOT = LCELL( _EQ032);
  _EQ032 =  _LC3_A10
         #  _LC4_A10
         #  _LC2_A7 & !_LC7_A12;

-- Node name is '|bin6bcd:275|:48' from file "bin6bcd.tdf" line 8, column 13
-- Equation name is '_LC5_A10', type is buried 
!_LC5_A10 = _LC5_A10~NOT;
_LC5_A10~NOT = LCELL( _EQ033);
  _EQ033 = !_LC1_A7 & !_LC3_A7;

-- Node name is '|bin6bcd:275|:52' from file "bin6bcd.tdf" line 8, column 13
-- Equation name is '_LC7_A12', type is buried 
!_LC7_A12 = _LC7_A12~NOT;
_LC7_A12~NOT = LCELL( _EQ034);
  _EQ034 = !_LC4_A7 & !_LC5_A10 & !_LC8_A7
         # !_LC2_A7 & !_LC4_A7 & !_LC8_A7;

-- Node name is '|bin6bcd:275|:58' from file "bin6bcd.tdf" line 9, column 15
-- Equation name is '_LC4_A12', type is buried 
_LC4_A12 = LCELL( _EQ035);
  _EQ035 =  _LC2_A7 &  _LC4_A7
         #  _LC3_A7 &  _LC4_A7
         #  _LC8_A7;

-- Node name is '|bin6bcd:275|:66' from file "bin6bcd.tdf" line 10, column 17
-- Equation name is '_LC6_A12', type is buried 
!_LC6_A12 = _LC6_A12~NOT;
_LC6_A12~NOT = LCELL( _EQ036);
  _EQ036 = !_LC1_A7
         # !_LC3_A7
         # !_LC4_A7
         # !_LC2_A7;

-- Node name is '|bin6bcd:275|:80' from file "bin6bcd.tdf" line 12, column 21
-- Equation name is '_LC5_A12', type is buried 
!_LC5_A12 = _LC5_A12~NOT;
_LC5_A12~NOT = LCELL( _EQ037);
  _EQ037 = !_LC8_A7
         # !_LC4_A7
         # !_LC2_A7 & !_LC5_A10;

-- Node name is '|bin6bcd:275|~88~1' from file "bin6bcd.tdf" line 13, column 23
-- Equation name is '_LC1_A12', type is buried 
-- synthesized logic cell 
!_LC1_A12 = _LC1_A12~NOT;
_LC1_A12~NOT = LCELL( _EQ038);
  _EQ038 = !_LC2_A7
         # !_LC8_A7
         # !_LC4_A7;

-- Node name is '|bin6bcd:275|:89' from file "bin6bcd.tdf" line 13, column 15
-- Equation name is '_LC4_A4', type is buried 
_LC4_A4  = LCELL( _EQ039);
  _EQ039 =  _LC1_A12 &  _LC3_A7 &  _LC5_A12;

-- Node name is '|bin6bcd:275|:116' from file "bin6bcd.tdf" line 13, column 15
-- Equation name is '_LC3_A4', type is buried 
!_LC3_A4 = _LC3_A4~NOT;
_LC3_A4~NOT = LCELL( _EQ040);
  _EQ040 = !_LC5_A12
         #  _LC1_A12 &  _LC3_A7
         # !_LC4_A12;

-- Node name is '|bin6bcd:275|:147' from file "bin6bcd.tdf" line 18, column 21
-- Equation name is '_LC4_A10', type is buried 
_LC4_A10 = LCELL( _EQ041);
  _EQ041 =  _LC2_A7 &  _LC3_A4 &  _LC5_A10
         # !_LC2_A7 &  _LC3_A4 & !_LC5_A10;

-- Node name is '|bin6bcd:275|~154~1' from file "bin6bcd.tdf" line 12, column 13
-- Equation name is '_LC2_A12', type is buried 
-- synthesized logic cell 
_LC2_A12 = LCELL( _EQ042);
  _EQ042 = !_LC2_A7 & !_LC4_A7
         # !_LC8_A7
         # !_LC4_A12;

-- Node name is '|bin6bcd:275|:154' from file "bin6bcd.tdf" line 12, column 13
-- Equation name is '_LC2_A4', type is buried 
!_LC2_A4 = _LC2_A4~NOT;
_LC2_A4~NOT = LCELL( _EQ043);
  _EQ043 =  _LC2_A12
         #  _LC5_A12;

-- Node name is '|bin6bcd:275|~187~1' from file "bin6bcd.tdf" line 11, column 11
-- Equation name is '_LC8_A12', type is buried 
-- synthesized logic cell 
_LC8_A12 = LCELL( _EQ044);
  _EQ044 = !_LC6_A12 & !_LC8_A7
         #  _LC2_A7 &  _LC8_A7
         #  _LC4_A7 &  _LC8_A7;

-- Node name is '|bin6bcd:275|:187' from file "bin6bcd.tdf" line 11, column 11
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = LCELL( _EQ045);
  _EQ045 =  _LC4_A12 &  _LC7_A12 & !_LC8_A12;

-- Node name is '|bin6bcd:275|:218' from file "bin6bcd.tdf" line 26, column 17
-- Equation name is '_LC3_A10', type is buried 
_LC3_A10 = LCELL( _EQ046);
  _EQ046 =  _LC1_A7 &  _LC1_A11 & !_LC2_A7 &  _LC3_A7
         # !_LC1_A7 &  _LC1_A11 &  _LC2_A7
         #  _LC1_A11 &  _LC2_A7 & !_LC3_A7;

-- Node name is '|bin6bcd:275|:225' from file "bin6bcd.tdf" line 10, column 9
-- Equation name is '_LC3_A12', type is buried 
!_LC3_A12 = _LC3_A12~NOT;
_LC3_A12~NOT = LCELL( _EQ047);
  _EQ047 = !_LC7_A12
         # !_LC4_A12
         #  _LC6_A12
         #  _LC8_A7;

-- Node name is '|bin6bcd:275|:226' from file "bin6bcd.tdf" line 29, column 17
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = LCELL( _EQ048);
  _EQ048 =  _LC1_A11
         #  _LC6_A4;

-- Node name is '|bin6bcd:275|:262' from file "bin6bcd.tdf" line 33, column 15
-- Equation name is '_LC8_A11', type is buried 
!_LC8_A11 = _LC8_A11~NOT;
_LC8_A11~NOT = LCELL( _EQ049);
  _EQ049 = !_LC3_A4 & !_LC7_A12
         # !_LC3_A4 &  _LC4_A12 &  _LC8_A12;

-- Node name is '|bin6bcd:275|:293' from file "bin6bcd.tdf" line 34, column 13
-- Equation name is '_LC2_A10', type is buried 
_LC2_A10 = LCELL( _EQ050);
  _EQ050 = !_LC2_A7 & !_LC4_A12 &  _LC5_A10 &  _LC7_A12
         #  _LC2_A7 & !_LC4_A12 & !_LC5_A10 &  _LC7_A12;

-- Node name is '|bin6bcd:293|lo1~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC4_A18', type is buried 
-- synthesized logic cell 
!_LC4_A18 = _LC4_A18~NOT;
_LC4_A18~NOT = LCELL( _EQ051);
  _EQ051 =  _LC4_A22 & !_LC6_A18 & !_LC8_A18;

-- Node name is '|bin6bcd:293|lo2~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC6_A18', type is buried 
-- synthesized logic cell 
!_LC6_A18 = _LC6_A18~NOT;
_LC6_A18~NOT = LCELL( _EQ052);
  _EQ052 = !_LC5_A22 & !_LC7_A18
         # !_LC7_A18 & !_LC7_A22;

-- Node name is '|bin6bcd:293|lo2~2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC5_A18', type is buried 
-- synthesized logic cell 
!_LC5_A18 = _LC5_A18~NOT;
_LC5_A18~NOT = LCELL( _EQ053);
  _EQ053 = !_LC3_A3 &  _LC6_A18
         #  _LC3_A3 &  _LC8_A18
         #  _LC3_A3 & !_LC4_A22;

-- Node name is '|bin6bcd:293|lo2~3' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC6_A20', type is buried 
-- synthesized logic cell 
!_LC6_A20 = _LC6_A20~NOT;
_LC6_A20~NOT = LCELL( _EQ054);
  _EQ054 =  _LC1_A9 & !_LC3_A3 &  _LC4_A13
         # !_LC1_A9 &  _LC3_A3 &  _LC4_A13
         # !_LC5_A18;

-- Node name is '|bin6bcd:293|lo2~4' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC6_A13', type is buried 
-- synthesized logic cell 
_LC6_A13 = LCELL( _EQ055);
  _EQ055 =  _LC4_A22 & !_LC6_A22
         #  _LC3_A18;

-- Node name is '|bin6bcd:293|lo2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = LCELL( _EQ056);
  _EQ056 = !_LC6_A20
         #  _LC1_A9 &  _LC3_A3 &  _LC6_A13
         # !_LC1_A9 & !_LC3_A3 &  _LC6_A13;

-- Node name is '|bin6bcd:293|lo3~1' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC1_A18', type is buried 
-- synthesized logic cell 
!_LC1_A18 = _LC1_A18~NOT;
_LC1_A18~NOT = LCELL( _EQ057);
  _EQ057 = !_LC3_A3 & !_LC3_A9 &  _LC7_A18
         #  _LC3_A3 &  _LC3_A9 &  _LC7_A18
         # !_LC3_A9 &  _LC8_A18;

-- Node name is '|bin6bcd:293|lo3~2' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC8_A22', type is buried 
-- synthesized logic cell 
!_LC8_A22 = _LC8_A22~NOT;
_LC8_A22~NOT = LCELL( _EQ058);
  _EQ058 =  _LC1_A22 &  _LC3_A9 &  _LC3_A18
         # !_LC1_A22 & !_LC3_A9 &  _LC3_A18
         #  _LC3_A9 & !_LC4_A22;

-- Node name is '|bin6bcd:293|lo3' from file "bin6bcd.tdf" line 38, column 11
-- Equation name is '_LC5_A14', type is buried 
_LC5_A14 = LCELL( _EQ059);
  _EQ059 = !_LC1_A18
         #  _LC2_A22
         #  _LC4_A14
         # !_LC8_A22;

-- Node name is '|bin6bcd:293|:48' from file "bin6bcd.tdf" line 8, column 13
-- Equation name is '_LC1_A22', type is buried 
!_LC1_A22 = _LC1_A22~NOT;
_LC1_A22~NOT = LCELL( _EQ060);
  _EQ060 = !_LC1_A9 & !_LC3_A3;

-- Node name is '|bin6bcd:293|:52' from file "bin6bcd.tdf" line 8, column 13
-- Equation name is '_LC4_A22', type is buried 
!_LC4_A22 = _LC4_A22~NOT;
_LC4_A22~NOT = LCELL( _EQ061);
  _EQ061 = !_LC1_A22 & !_LC2_A9 & !_LC4_A9
         # !_LC2_A9 & !_LC3_A9 & !_LC4_A9;

-- Node name is '|bin6bcd:293|:58' from file "bin6bcd.tdf" line 9, column 15
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = LCELL( _EQ062);
  _EQ062 =  _LC2_A9 &  _LC3_A9
         #  _LC2_A9 &  _LC3_A3
         #  _LC4_A9;

-- Node name is '|bin6bcd:293|~66~1' from file "bin6bcd.tdf" line 10, column 17
-- Equation name is '_LC6_A3', type is buried 
-- synthesized logic cell 
_LC6_A3  = LCELL( _EQ063);
  _EQ063 = !_LC2_A9
         # !_LC1_A9
         # !_LC3_A3;

-- Node name is '|bin6bcd:293|:67' from file "bin6bcd.tdf" line 10, column 17
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ064);
  _EQ064 =  _LC3_A9 & !_LC6_A3
         #  _LC4_A9;

-- Node name is '|bin6bcd:293|:80' from file "bin6bcd.tdf" line 12, column 21
-- Equation name is '_LC5_A22', type is buried 
!_LC5_A22 = _LC5_A22~NOT;
_LC5_A22~NOT = LCELL( _EQ065);
  _EQ065 = !_LC1_A22 & !_LC3_A9
         # !_LC4_A9
         # !_LC2_A9;

-- Node name is '|bin6bcd:293|:88' from file "bin6bcd.tdf" line 13, column 23
-- Equation name is '_LC7_A22', type is buried 
_LC7_A22 = LCELL( _EQ066);
  _EQ066 =  _LC2_A9 &  _LC3_A3 &  _LC3_A9 &  _LC4_A9;

-- Node name is '|bin6bcd:293|:116' from file "bin6bcd.tdf" line 13, column 15
-- Equation name is '_LC3_A18', type is buried 
!_LC3_A18 = _LC3_A18~NOT;
_LC3_A18~NOT = LCELL( _EQ067);
  _EQ067 = !_LC5_A22
         #  _LC7_A22
         # !_LC6_A22;

-- Node name is '|bin6bcd:293|~154~1' from file "bin6bcd.tdf" line 12, column 13
-- Equation name is '_LC3_A22', type is buried 
-- synthesized logic cell 
_LC3_A22 = LCELL( _EQ068);
  _EQ068 = !_LC2_A9 & !_LC3_A9
         # !_LC4_A9
         # !_LC6_A22;

-- Node name is '|bin6bcd:293|:154' from file "bin6bcd.tdf" line 12, column 13
-- Equation name is '_LC8_A18', type is buried 
!_LC8_A18 = _LC8_A18~NOT;
_LC8_A18~NOT = LCELL( _EQ069);
  _EQ069 =  _LC3_A22
         #  _LC5_A22;

-- Node name is '|bin6bcd:293|:155' from file "bin6bcd.tdf" line 21, column 21
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = LCELL( _EQ070);
  _EQ070 = !_LC3_A22 & !_LC5_A22
         #  _LC3_A18
         #  _LC5_A22 &  _LC7_A22;

-- Node name is '|bin6bcd:293|~187~1' from file "bin6bcd.tdf" line 11, column 11
-- Equation name is '_LC4_A3', type is buried 
-- synthesized logic cell 
_LC4_A3  = LCELL( _EQ071);
  _EQ071 = !_LC3_A9 & !_LC4_A9
         # !_LC4_A9 &  _LC6_A3
         #  _LC3_A9 &  _LC4_A9
         #  _LC2_A9 &  _LC4_A9;

-- Node name is '|bin6bcd:293|:187' from file "bin6bcd.tdf" line 11, column 11
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = LCELL( _EQ072);
  _EQ072 = !_LC4_A3 &  _LC4_A22 &  _LC6_A22;

-- Node name is '|bin6bcd:293|:218' from file "bin6bcd.tdf" line 26, column 17
-- Equation name is '_LC4_A14', type is buried 
_LC4_A14 = LCELL( _EQ073);
  _EQ073 =  _LC1_A9 &  _LC3_A3 & !_LC3_A9 &  _LC4_A13
         # !_LC1_A9 &  _LC3_A9 &  _LC4_A13
         # !_LC3_A3 &  _LC3_A9 &  _LC4_A13;

-- Node name is '|bin6bcd:293|:225' from file "bin6bcd.tdf" line 10, column 9
-- Equation name is '_LC7_A18', type is buried 
!_LC7_A18 = _LC7_A18~NOT;
_LC7_A18~NOT = LCELL( _EQ074);
  _EQ074 = !_LC4_A22
         # !_LC6_A22
         #  _LC5_A3;

-- Node name is '|bin6bcd:293|:226' from file "bin6bcd.tdf" line 29, column 17
-- Equation name is '_LC4_A17', type is buried 
_LC4_A17 = LCELL( _EQ075);
  _EQ075 =  _LC4_A13
         #  _LC6_A18;

-- Node name is '|bin6bcd:293|:262' from file "bin6bcd.tdf" line 33, column 15
-- Equation name is '_LC8_A13', type is buried 
!_LC8_A13 = _LC8_A13~NOT;
_LC8_A13~NOT = LCELL( _EQ076);
  _EQ076 = !_LC3_A18 & !_LC4_A22
         # !_LC3_A18 &  _LC4_A3 &  _LC6_A22;

-- Node name is '|bin6bcd:293|:293' from file "bin6bcd.tdf" line 34, column 13
-- Equation name is '_LC2_A22', type is buried 
_LC2_A22 = LCELL( _EQ077);
  _EQ077 =  _LC1_A22 & !_LC3_A9 &  _LC4_A22 & !_LC6_A22
         # !_LC1_A22 &  _LC3_A9 &  _LC4_A22 & !_LC6_A22;

-- Node name is '|clock1_base:283|:33' = '|clock1_base:283|CLK1HZ' 
-- Equation name is '_LC6_B12', type is buried 
_LC6_B12 = DFFE( _EQ078,  _LC1_C2,  VCC,  VCC,  VCC);
  _EQ078 =  _LC1_B2 &  _LC6_B12 & !_LC7_B12
         #  _LC1_B2 & !_LC2_B2 &  _LC6_B12
         #  _LC2_B2 & !_LC6_B12 &  _LC7_B12
         # !_LC1_B2 & !_LC6_B12;

-- Node name is '|clock1_base:283|:32' = '|clock1_base:283|CLK1KHZ' 
-- Equation name is '_LC1_C2', type is buried 
_LC1_C2  = DFFE( _EQ079,  _LC6_C21,  VCC,  VCC,  VCC);
  _EQ079 =  _LC1_C2 &  _LC1_C10 & !_LC7_C2
         #  _LC1_C2 &  _LC1_C10 & !_LC2_C10
         # !_LC1_C2 &  _LC2_C10 &  _LC7_C2
         # !_LC1_C2 & !_LC1_C10;

-- Node name is '|clock1_base:283|:31' = '|clock1_base:283|CLK1MHZ' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = DFFE( _EQ080, GLOBAL( clk50),  VCC,  VCC,  VCC);
  _EQ080 = !_LC4_C21 &  _LC5_C21 &  _LC6_C21
         #  _LC5_C21 &  _LC6_C21 & !_LC6_C24
         #  _LC4_C21 & !_LC6_C21 &  _LC6_C24
         # !_LC5_C21 & !_LC6_C21;

-- Node name is '|clock1_base:283|div50_loop:16|:87' from file "div50_loop.tdf" line 10, column 14
-- Equation name is '_LC5_C21', type is buried 
!_LC5_C21 = _LC5_C21~NOT;
_LC5_C21~NOT = LCELL( _EQ081);
  _EQ081 = !_LC1_C24 &  _LC2_C21 &  _LC2_C24 & !_LC3_C21;

-- Node name is '|clock1_base:283|div50_loop:16|:132' from file "div50_loop.tdf" line 13, column 14
-- Equation name is '_LC1_C24', type is buried 
!_LC1_C24 = _LC1_C24~NOT;
_LC1_C24~NOT = LCELL( _EQ082);
  _EQ082 = !_LC3_C24 & !_LC5_C24 & !_LC7_C24;

-- Node name is '|clock1_base:283|div50_loop:16|:154' from file "div50_loop.tdf" line 13, column 20
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ083);
  _EQ083 = !_LC1_C24 & !_LC2_C24 &  _LC3_C21
         #  _LC1_C24 &  _LC2_C21 &  _LC2_C24 & !_LC3_C21
         # !_LC2_C21 &  _LC3_C21;

-- Node name is '|clock1_base:283|div50_loop:16|:165' from file "div50_loop.tdf" line 14, column 15
-- Equation name is '_LC8_C24', type is buried 
_LC8_C24 = LCELL( _EQ084);
  _EQ084 =  _LC3_C24 &  _LC5_C24 &  _LC7_C24;

-- Node name is '|clock1_base:283|div50_loop:16|:169' from file "div50_loop.tdf" line 14, column 15
-- Equation name is '_LC4_C24', type is buried 
_LC4_C24 = LCELL( _EQ085);
  _EQ085 =  _LC2_C24 &  _LC3_C24 &  _LC5_C24 &  _LC7_C24;

-- Node name is '|clock1_base:283|div50_loop:16|~187~1' from file "div50_loop.tdf" line 14, column 8
-- Equation name is '_LC7_C21', type is buried 
-- synthesized logic cell 
_LC7_C21 = LCELL( _EQ086);
  _EQ086 =  _LC1_C21
         # !_LC2_C24 & !_LC3_C21
         # !_LC2_C21 & !_LC3_C21;

-- Node name is '|clock1_base:283|div50_loop:16|~197~1' from file "div50_loop.tdf" line 16, column 14
-- Equation name is '_LC4_C21', type is buried 
-- synthesized logic cell 
_LC4_C21 = LCELL( _EQ087);
  _EQ087 =  _LC2_C21 &  _LC3_C21 & !_LC3_C24 & !_LC7_C24;

-- Node name is '|clock1_base:283|div50_loop:16|~197~2' from file "div50_loop.tdf" line 16, column 14
-- Equation name is '_LC6_C24', type is buried 
-- synthesized logic cell 
_LC6_C24 = LCELL( _EQ088);
  _EQ088 = !_LC2_C24 &  _LC5_C24;

-- Node name is '|clock1_base:283|div50_reg:17|reg0' from file "div50_reg.tdf" line 7, column 6
-- Equation name is '_LC5_C24', type is buried 
_LC5_C24 = DFFE( _EQ089, GLOBAL(!clk50),  VCC,  VCC,  VCC);
  _EQ089 = !_LC5_C24 &  _LC7_C21
         # !_LC5_C21;

-- Node name is '|clock1_base:283|div50_reg:17|reg1' from file "div50_reg.tdf" line 7, column 6
-- Equation name is '_LC7_C24', type is buried 
_LC7_C24 = DFFE( _EQ090, GLOBAL(!clk50),  VCC,  VCC,  VCC);
  _EQ090 =  _LC5_C24 &  _LC7_C21 & !_LC7_C24
         # !_LC5_C24 &  _LC7_C21 &  _LC7_C24;

-- Node name is '|clock1_base:283|div50_reg:17|reg2' from file "div50_reg.tdf" line 7, column 6
-- Equation name is '_LC3_C24', type is buried 
_LC3_C24 = DFFE( _EQ091, GLOBAL(!clk50),  VCC,  VCC,  VCC);
  _EQ091 =  _LC3_C24 & !_LC5_C24 &  _LC7_C21
         #  _LC3_C24 &  _LC7_C21 & !_LC7_C24
         # !_LC3_C24 &  _LC5_C24 &  _LC7_C21 &  _LC7_C24;

-- Node name is '|clock1_base:283|div50_reg:17|reg3' from file "div50_reg.tdf" line 7, column 6
-- Equation name is '_LC2_C24', type is buried 
_LC2_C24 = DFFE( _EQ092, GLOBAL(!clk50),  VCC,  VCC,  VCC);
  _EQ092 =  _LC2_C24 &  _LC7_C21 & !_LC8_C24
         # !_LC2_C24 &  _LC7_C21 &  _LC8_C24
         # !_LC5_C21;

-- Node name is '|clock1_base:283|div50_reg:17|reg4' from file "div50_reg.tdf" line 7, column 6
-- Equation name is '_LC2_C21', type is buried 
_LC2_C21 = DFFE( _EQ093, GLOBAL(!clk50),  VCC,  VCC,  VCC);
  _EQ093 =  _LC2_C21 & !_LC4_C24 &  _LC7_C21
         # !_LC2_C21 &  _LC4_C24 &  _LC7_C21
         # !_LC5_C21;

-- Node name is '|clock1_base:283|div50_reg:17|reg5' from file "div50_reg.tdf" line 7, column 6
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = DFFE( _EQ094, GLOBAL(!clk50),  VCC,  VCC,  VCC);
  _EQ094 =  _LC1_C21 & !_LC2_C21 &  _LC3_C21
         #  _LC1_C21 &  _LC3_C21 & !_LC4_C24
         #  _LC1_C21 &  _LC2_C21 & !_LC3_C21 &  _LC4_C24;

-- Node name is '|clock1_base:283|div1000_loop:19|:50' from file "div1000_loop.tdf" line 7, column 29
-- Equation name is '_LC5_C10', type is buried 
!_LC5_C10 = _LC5_C10~NOT;
_LC5_C10~NOT = LCELL( _EQ095);
  _EQ095 =  _LC6_C10 &  _LC7_C10;

-- Node name is '|clock1_base:283|div1000_loop:19|:67' from file "div1000_loop.tdf" line 7, column 29
-- Equation name is '_LC3_C10', type is buried 
_LC3_C10 = LCELL( _EQ096);
  _EQ096 = !_LC8_C2
         # !_LC4_C10 &  _LC5_C10;

-- Node name is '|clock1_base:283|div1000_loop:19|~136~1' from file "div1000_loop.tdf" line 10, column 14
-- Equation name is '_LC1_C12', type is buried 
-- synthesized logic cell 
!_LC1_C12 = _LC1_C12~NOT;
_LC1_C12~NOT = LCELL( _EQ097);
  _EQ097 = !_LC3_C12
         # !_LC5_C12
         # !_LC6_C12
         # !_LC8_C12;

-- Node name is '|clock1_base:283|div1000_loop:19|:136' from file "div1000_loop.tdf" line 10, column 14
-- Equation name is '_LC1_C10', type is buried 
!_LC1_C10 = _LC1_C10~NOT;
_LC1_C10~NOT = LCELL( _EQ098);
  _EQ098 = !_LC1_C11 & !_LC4_C10 & !_LC5_C10 &  _LC8_C2;

-- Node name is '|clock1_base:283|div1000_loop:19|:208' from file "div1000_loop.tdf" line 13, column 14
-- Equation name is '_LC4_C10', type is buried 
!_LC4_C10 = _LC4_C10~NOT;
_LC4_C10~NOT = LCELL( _EQ099);
  _EQ099 = !_LC2_C2 & !_LC8_C10;

-- Node name is '|clock1_base:283|div1000_loop:19|~218~1' from file "div1000_loop.tdf" line 13, column 14
-- Equation name is '_LC8_C2', type is buried 
-- synthesized logic cell 
!_LC8_C2 = _LC8_C2~NOT;
_LC8_C2~NOT = LCELL( _EQ100);
  _EQ100 = !_LC6_C2
         # !_LC1_C12;

-- Node name is '|clock1_base:283|div1000_loop:19|:243' from file "div1000_loop.tdf" line 13, column 31
-- Equation name is '_LC3_C2', type is buried 
_LC3_C2  = LCELL( _EQ101);
  _EQ101 = !_LC2_C2 & !_LC2_C10 & !_LC6_C2
         # !_LC2_C11;

-- Node name is '|clock1_base:283|div1000_loop:19|:244' from file "div1000_loop.tdf" line 13, column 21
-- Equation name is '_LC4_C11', type is buried 
_LC4_C11 = LCELL( _EQ102);
  _EQ102 =  _LC1_C11 &  _LC3_C2
         #  _LC3_C2 &  _LC4_C10 &  _LC8_C2;

-- Node name is '|clock1_base:283|div1000_loop:19|:255' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC2_C10', type is buried 
_LC2_C10 = LCELL( _EQ103);
  _EQ103 = !_LC5_C10 &  _LC8_C10;

-- Node name is '|clock1_base:283|div1000_loop:19|:259' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC5_C2', type is buried 
_LC5_C2  = LCELL( _EQ104);
  _EQ104 =  _LC2_C2 &  _LC2_C10;

-- Node name is '|clock1_base:283|div1000_loop:19|:263' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC4_C2', type is buried 
_LC4_C2  = LCELL( _EQ105);
  _EQ105 =  _LC2_C2 &  _LC2_C10 &  _LC6_C2;

-- Node name is '|clock1_base:283|div1000_loop:19|:267' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC7_C12', type is buried 
_LC7_C12 = LCELL( _EQ106);
  _EQ106 =  _LC4_C2 &  _LC6_C12;

-- Node name is '|clock1_base:283|div1000_loop:19|:271' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = LCELL( _EQ107);
  _EQ107 =  _LC4_C2 &  _LC6_C12 &  _LC8_C12;

-- Node name is '|clock1_base:283|div1000_loop:19|:275' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC2_C12', type is buried 
_LC2_C12 = LCELL( _EQ108);
  _EQ108 =  _LC4_C2 &  _LC5_C12 &  _LC6_C12 &  _LC8_C12;

-- Node name is '|clock1_base:283|div1000_loop:19|~301~1' from file "div1000_loop.tdf" line 14, column 8
-- Equation name is '_LC3_C11', type is buried 
-- synthesized logic cell 
_LC3_C11 = LCELL( _EQ109);
  _EQ109 =  _LC4_C11
         # !_LC1_C11 &  _LC3_C10;

-- Node name is '|clock1_base:283|div1000_loop:19|~320~1' from file "div1000_loop.tdf" line 16, column 14
-- Equation name is '_LC2_C11', type is buried 
-- synthesized logic cell 
!_LC2_C11 = _LC2_C11~NOT;
_LC2_C11~NOT = LCELL( _EQ110);
  _EQ110 = !_LC1_C11
         # !_LC1_C12;

-- Node name is '|clock1_base:283|div1000_loop:19|~320~2' from file "div1000_loop.tdf" line 16, column 14
-- Equation name is '_LC7_C2', type is buried 
-- synthesized logic cell 
_LC7_C2  = LCELL( _EQ111);
  _EQ111 =  _LC1_C11 &  _LC1_C12 & !_LC2_C2 & !_LC6_C2;

-- Node name is '|clock1_base:283|div1000_loop:20|:50' from file "div1000_loop.tdf" line 7, column 29
-- Equation name is '_LC8_B7', type is buried 
!_LC8_B7 = _LC8_B7~NOT;
_LC8_B7~NOT = LCELL( _EQ112);
  _EQ112 =  _LC1_B7 &  _LC2_B7;

-- Node name is '|clock1_base:283|div1000_loop:20|:67' from file "div1000_loop.tdf" line 7, column 29
-- Equation name is '_LC7_B2', type is buried 
_LC7_B2  = LCELL( _EQ113);
  _EQ113 = !_LC1_B12
         # !_LC3_B2 &  _LC8_B7;

-- Node name is '|clock1_base:283|div1000_loop:20|~136~1' from file "div1000_loop.tdf" line 10, column 14
-- Equation name is '_LC1_B9', type is buried 
-- synthesized logic cell 
!_LC1_B9 = _LC1_B9~NOT;
_LC1_B9~NOT = LCELL( _EQ114);
  _EQ114 = !_LC3_B9
         # !_LC5_B9
         # !_LC6_B9
         # !_LC8_B9;

-- Node name is '|clock1_base:283|div1000_loop:20|:136' from file "div1000_loop.tdf" line 10, column 14
-- Equation name is '_LC1_B2', type is buried 
!_LC1_B2 = _LC1_B2~NOT;
_LC1_B2~NOT = LCELL( _EQ115);
  _EQ115 =  _LC1_B12 & !_LC3_B2 & !_LC5_B2 & !_LC8_B7;

-- Node name is '|clock1_base:283|div1000_loop:20|:208' from file "div1000_loop.tdf" line 13, column 14
-- Equation name is '_LC3_B2', type is buried 
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ116);
  _EQ116 = !_LC8_B2 & !_LC8_B12;

-- Node name is '|clock1_base:283|div1000_loop:20|~218~1' from file "div1000_loop.tdf" line 13, column 14
-- Equation name is '_LC1_B12', type is buried 
-- synthesized logic cell 
!_LC1_B12 = _LC1_B12~NOT;
_LC1_B12~NOT = LCELL( _EQ117);
  _EQ117 = !_LC5_B12
         # !_LC1_B9;

-- Node name is '|clock1_base:283|div1000_loop:20|:243' from file "div1000_loop.tdf" line 13, column 31
-- Equation name is '_LC2_B12', type is buried 
_LC2_B12 = LCELL( _EQ118);
  _EQ118 = !_LC2_B2 & !_LC5_B12 & !_LC8_B12
         # !_LC1_B11;

-- Node name is '|clock1_base:283|div1000_loop:20|:244' from file "div1000_loop.tdf" line 13, column 21
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = LCELL( _EQ119);
  _EQ119 =  _LC2_B12 &  _LC5_B2
         #  _LC1_B12 &  _LC2_B12 &  _LC3_B2;

-- Node name is '|clock1_base:283|div1000_loop:20|:255' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = LCELL( _EQ120);
  _EQ120 =  _LC8_B2 & !_LC8_B7;

-- Node name is '|clock1_base:283|div1000_loop:20|:259' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC4_B12', type is buried 
_LC4_B12 = LCELL( _EQ121);
  _EQ121 =  _LC2_B2 &  _LC8_B12;

-- Node name is '|clock1_base:283|div1000_loop:20|:263' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC3_B12', type is buried 
_LC3_B12 = LCELL( _EQ122);
  _EQ122 =  _LC2_B2 &  _LC5_B12 &  _LC8_B12;

-- Node name is '|clock1_base:283|div1000_loop:20|:267' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC7_B9', type is buried 
_LC7_B9  = LCELL( _EQ123);
  _EQ123 =  _LC3_B12 &  _LC6_B9;

-- Node name is '|clock1_base:283|div1000_loop:20|:271' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC4_B9', type is buried 
_LC4_B9  = LCELL( _EQ124);
  _EQ124 =  _LC3_B12 &  _LC6_B9 &  _LC8_B9;

-- Node name is '|clock1_base:283|div1000_loop:20|:275' from file "div1000_loop.tdf" line 14, column 15
-- Equation name is '_LC2_B9', type is buried 
_LC2_B9  = LCELL( _EQ125);
  _EQ125 =  _LC3_B12 &  _LC5_B9 &  _LC6_B9 &  _LC8_B9;

-- Node name is '|clock1_base:283|div1000_loop:20|~301~1' from file "div1000_loop.tdf" line 14, column 8
-- Equation name is '_LC6_B2', type is buried 
-- synthesized logic cell 
_LC6_B2  = LCELL( _EQ126);
  _EQ126 =  _LC4_B2
         # !_LC5_B2 &  _LC7_B2;

-- Node name is '|clock1_base:283|div1000_loop:20|~320~1' from file "div1000_loop.tdf" line 16, column 14
-- Equation name is '_LC1_B11', type is buried 
-- synthesized logic cell 
!_LC1_B11 = _LC1_B11~NOT;
_LC1_B11~NOT = LCELL( _EQ127);
  _EQ127 = !_LC5_B2
         # !_LC1_B9;

-- Node name is '|clock1_base:283|div1000_loop:20|~320~2' from file "div1000_loop.tdf" line 16, column 14
-- Equation name is '_LC7_B12', type is buried 
-- synthesized logic cell 
_LC7_B12 = LCELL( _EQ128);
  _EQ128 =  _LC1_B9 &  _LC5_B2 & !_LC5_B12 & !_LC8_B12;

-- Node name is '|clock1_base:283|div1000_reg:18|reg0' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC7_C10', type is buried 
_LC7_C10 = DFFE( _EQ129, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ129 =  _LC3_C11 & !_LC7_C10;

-- Node name is '|clock1_base:283|div1000_reg:18|reg1' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC6_C10', type is buried 
_LC6_C10 = DFFE( _EQ130, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ130 =  _LC3_C11 & !_LC6_C10 &  _LC7_C10
         #  _LC3_C11 &  _LC6_C10 & !_LC7_C10;

-- Node name is '|clock1_base:283|div1000_reg:18|reg2' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC8_C10', type is buried 
_LC8_C10 = DFFE( _EQ131, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ131 =  _LC3_C11 &  _LC5_C10 &  _LC8_C10
         #  _LC3_C11 & !_LC5_C10 & !_LC8_C10
         # !_LC1_C10;

-- Node name is '|clock1_base:283|div1000_reg:18|reg3' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC2_C2', type is buried 
_LC2_C2  = DFFE( _EQ132, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ132 =  _LC2_C2 & !_LC2_C10 &  _LC3_C11
         # !_LC2_C2 &  _LC2_C10 &  _LC3_C11;

-- Node name is '|clock1_base:283|div1000_reg:18|reg4' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC6_C2', type is buried 
_LC6_C2  = DFFE( _EQ133, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ133 =  _LC3_C11 & !_LC5_C2 &  _LC6_C2
         #  _LC3_C11 &  _LC5_C2 & !_LC6_C2
         # !_LC1_C10;

-- Node name is '|clock1_base:283|div1000_reg:18|reg5' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC6_C12', type is buried 
_LC6_C12 = DFFE( _EQ134, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ134 =  _LC3_C11 & !_LC4_C2 &  _LC6_C12
         #  _LC3_C11 &  _LC4_C2 & !_LC6_C12
         # !_LC1_C10;

-- Node name is '|clock1_base:283|div1000_reg:18|reg6' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC8_C12', type is buried 
_LC8_C12 = DFFE( _EQ135, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ135 = !_LC1_C10
         #  _LC3_C11 & !_LC7_C12 &  _LC8_C12
         #  _LC3_C11 &  _LC7_C12 & !_LC8_C12;

-- Node name is '|clock1_base:283|div1000_reg:18|reg7' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = DFFE( _EQ136, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ136 =  _LC3_C11 & !_LC4_C12 &  _LC5_C12
         #  _LC3_C11 &  _LC4_C12 & !_LC5_C12
         # !_LC1_C10;

-- Node name is '|clock1_base:283|div1000_reg:18|reg8' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = DFFE( _EQ137, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ137 = !_LC2_C12 &  _LC3_C11 &  _LC3_C12
         #  _LC2_C12 &  _LC3_C11 & !_LC3_C12
         # !_LC1_C10;

-- Node name is '|clock1_base:283|div1000_reg:18|reg9' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC1_C11', type is buried 
_LC1_C11 = DFFE( _EQ138, !_LC6_C21,  VCC,  VCC,  VCC);
  _EQ138 =  _LC1_C11 & !_LC3_C12 &  _LC4_C11
         #  _LC1_C11 & !_LC2_C12 &  _LC4_C11
         # !_LC1_C11 &  _LC2_C12 &  _LC3_C12 &  _LC4_C11;

-- Node name is '|clock1_base:283|div1000_reg:21|reg0' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC2_B7', type is buried 
_LC2_B7  = DFFE( _EQ139, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ139 = !_LC2_B7 &  _LC6_B2;

-- Node name is '|clock1_base:283|div1000_reg:21|reg1' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC1_B7', type is buried 
_LC1_B7  = DFFE( _EQ140, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ140 = !_LC1_B7 &  _LC2_B7 &  _LC6_B2
         #  _LC1_B7 & !_LC2_B7 &  _LC6_B2;

-- Node name is '|clock1_base:283|div1000_reg:21|reg2' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = DFFE( _EQ141, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ141 =  _LC6_B2 &  _LC8_B2 &  _LC8_B7
         #  _LC6_B2 & !_LC8_B2 & !_LC8_B7
         # !_LC1_B2;

-- Node name is '|clock1_base:283|div1000_reg:21|reg3' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC8_B12', type is buried 
_LC8_B12 = DFFE( _EQ142, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ142 = !_LC2_B2 &  _LC6_B2 &  _LC8_B12
         #  _LC2_B2 &  _LC6_B2 & !_LC8_B12;

-- Node name is '|clock1_base:283|div1000_reg:21|reg4' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC5_B12', type is buried 
_LC5_B12 = DFFE( _EQ143, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ143 = !_LC4_B12 &  _LC5_B12 &  _LC6_B2
         #  _LC4_B12 & !_LC5_B12 &  _LC6_B2
         # !_LC1_B2;

-- Node name is '|clock1_base:283|div1000_reg:21|reg5' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC6_B9', type is buried 
_LC6_B9  = DFFE( _EQ144, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ144 = !_LC3_B12 &  _LC6_B2 &  _LC6_B9
         #  _LC3_B12 &  _LC6_B2 & !_LC6_B9
         # !_LC1_B2;

-- Node name is '|clock1_base:283|div1000_reg:21|reg6' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC8_B9', type is buried 
_LC8_B9  = DFFE( _EQ145, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ145 = !_LC1_B2
         #  _LC6_B2 & !_LC7_B9 &  _LC8_B9
         #  _LC6_B2 &  _LC7_B9 & !_LC8_B9;

-- Node name is '|clock1_base:283|div1000_reg:21|reg7' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC5_B9', type is buried 
_LC5_B9  = DFFE( _EQ146, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ146 = !_LC4_B9 &  _LC5_B9 &  _LC6_B2
         #  _LC4_B9 & !_LC5_B9 &  _LC6_B2
         # !_LC1_B2;

-- Node name is '|clock1_base:283|div1000_reg:21|reg8' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC3_B9', type is buried 
_LC3_B9  = DFFE( _EQ147, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ147 = !_LC2_B9 &  _LC3_B9 &  _LC6_B2
         #  _LC2_B9 & !_LC3_B9 &  _LC6_B2
         # !_LC1_B2;

-- Node name is '|clock1_base:283|div1000_reg:21|reg9' from file "div1000_reg.tdf" line 7, column 6
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = DFFE( _EQ148, !_LC1_C2,  VCC,  VCC,  VCC);
  _EQ148 = !_LC3_B9 &  _LC4_B2 &  _LC5_B2
         # !_LC2_B9 &  _LC4_B2 &  _LC5_B2
         #  _LC2_B9 &  _LC3_B9 &  _LC4_B2 & !_LC5_B2;

-- Node name is '|clock1_timer:292|v_hour0' from file "clock1_timer.tdf" line 12, column 10
-- Equation name is '_LC5_A9', type is buried 
_LC5_A9  = DFFE( _EQ149,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ149 =  _LC2_A3 & !_LC5_A9
         #  _LC1_A3 &  _LC5_A9;

-- Node name is '|clock1_timer:292|v_hour1' from file "clock1_timer.tdf" line 12, column 10
-- Equation name is '_LC1_A9', type is buried 
_LC1_A9  = DFFE( _EQ150,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ150 =  _LC1_A3 &  _LC1_A9
         # !_LC1_A9 &  _LC2_A3 &  _LC5_A9
         #  _LC1_A9 &  _LC2_A3 & !_LC5_A9;

-- Node name is '|clock1_timer:292|v_hour2' from file "clock1_timer.tdf" line 12, column 10
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = DFFE( _EQ151,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ151 =  _LC2_A3 &  _LC3_A3 & !_LC8_A3
         #  _LC2_A3 & !_LC3_A3 &  _LC8_A3
         #  _LC1_A3 &  _LC3_A3;

-- Node name is '|clock1_timer:292|v_hour3' from file "clock1_timer.tdf" line 12, column 10
-- Equation name is '_LC3_A9', type is buried 
_LC3_A9  = DFFE( _EQ152,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ152 =  _LC1_A3 &  _LC3_A9
         #  _LC2_A3 &  _LC3_A9 & !_LC6_A9
         #  _LC2_A3 & !_LC3_A9 &  _LC6_A9;

-- Node name is '|clock1_timer:292|v_hour4' from file "clock1_timer.tdf" line 12, column 10
-- Equation name is '_LC2_A9', type is buried 
_LC2_A9  = DFFE( _EQ153,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ153 =  _LC1_A3 &  _LC2_A9
         #  _LC2_A3 &  _LC2_A9 & !_LC7_A9
         #  _LC2_A3 & !_LC2_A9 &  _LC7_A9;

-- Node name is '|clock1_timer:292|v_hour5' from file "clock1_timer.tdf" line 12, column 10
-- Equation name is '_LC4_A9', type is buried 
_LC4_A9  = DFFE( _EQ154,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ154 =  _LC2_A3 &  _LC4_A9 & !_LC8_A9
         #  _LC2_A3 & !_LC4_A9 &  _LC8_A9
         #  _LC1_A3 &  _LC4_A9;

-- Node name is '|clock1_timer:292|v_minute0' from file "clock1_timer.tdf" line 12, column 25
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = DFFE( _EQ155,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ155 =  _LC1_A2 &  _LC2_A2
         # !_LC2_A2 &  _LC3_A2
         # !_LC2_A2 & !_LC6_A16;

-- Node name is '|clock1_timer:292|v_minute1' from file "clock1_timer.tdf" line 12, column 25
-- Equation name is '_LC1_A7', type is buried 
_LC1_A7  = DFFE( _EQ156,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ156 =  _LC1_A1 &  _LC1_A7 & !_LC2_A2
         #  _LC1_A1 & !_LC1_A7 &  _LC2_A2
         #  _LC1_A2 &  _LC1_A7;

-- Node name is '|clock1_timer:292|v_minute2' from file "clock1_timer.tdf" line 12, column 25
-- Equation name is '_LC3_A7', type is buried 
_LC3_A7  = DFFE( _EQ157,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ157 =  _LC1_A1 & !_LC1_A6 &  _LC3_A7
         #  _LC1_A1 &  _LC1_A6 & !_LC3_A7
         #  _LC1_A2 &  _LC3_A7;

-- Node name is '|clock1_timer:292|v_minute3' from file "clock1_timer.tdf" line 12, column 25
-- Equation name is '_LC2_A7', type is buried 
_LC2_A7  = DFFE( _EQ158,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ158 =  _LC1_A1 &  _LC2_A7 & !_LC5_A7
         #  _LC1_A1 & !_LC2_A7 &  _LC5_A7
         #  _LC1_A2 &  _LC2_A7;

-- Node name is '|clock1_timer:292|v_minute4' from file "clock1_timer.tdf" line 12, column 25
-- Equation name is '_LC4_A7', type is buried 
_LC4_A7  = DFFE( _EQ159,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ159 =  _LC1_A1 &  _LC4_A7 & !_LC6_A7
         #  _LC1_A1 & !_LC4_A7 &  _LC6_A7
         #  _LC1_A2 &  _LC4_A7;

-- Node name is '|clock1_timer:292|v_minute5' from file "clock1_timer.tdf" line 12, column 25
-- Equation name is '_LC8_A7', type is buried 
_LC8_A7  = DFFE( _EQ160,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ160 =  _LC1_A1 & !_LC7_A7 &  _LC8_A7
         #  _LC1_A1 &  _LC7_A7 & !_LC8_A7
         #  _LC1_A2 &  _LC8_A7;

-- Node name is '|clock1_timer:292|v_seconds0' from file "clock1_timer.tdf" line 13, column 13
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = DFFE(!_LC2_A19,  _LC6_B12,  VCC,  VCC,  VCC);

-- Node name is '|clock1_timer:292|v_seconds1' from file "clock1_timer.tdf" line 13, column 13
-- Equation name is '_LC3_A19', type is buried 
_LC3_A19 = DFFE( _EQ161,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ161 = !_LC2_A19 &  _LC3_A19 &  _LC6_A16
         #  _LC2_A19 & !_LC3_A19 &  _LC6_A16;

-- Node name is '|clock1_timer:292|v_seconds2' from file "clock1_timer.tdf" line 13, column 13
-- Equation name is '_LC5_A16', type is buried 
_LC5_A16 = DFFE( _EQ162,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ162 =  _LC5_A16 &  _LC6_A16 & !_LC7_A16
         # !_LC5_A16 &  _LC6_A16 &  _LC7_A16;

-- Node name is '|clock1_timer:292|v_seconds3' from file "clock1_timer.tdf" line 13, column 13
-- Equation name is '_LC3_A16', type is buried 
_LC3_A16 = DFFE( _EQ163,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ163 =  _LC3_A16 & !_LC5_A16 &  _LC6_A16
         #  _LC3_A16 &  _LC6_A16 & !_LC7_A16
         # !_LC3_A16 &  _LC5_A16 &  _LC6_A16 &  _LC7_A16;

-- Node name is '|clock1_timer:292|v_seconds4' from file "clock1_timer.tdf" line 13, column 13
-- Equation name is '_LC1_A16', type is buried 
_LC1_A16 = DFFE( _EQ164,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ164 =  _LC1_A16 &  _LC6_A16 & !_LC8_A16
         # !_LC1_A16 &  _LC6_A16 &  _LC8_A16;

-- Node name is '|clock1_timer:292|v_seconds5' from file "clock1_timer.tdf" line 13, column 13
-- Equation name is '_LC2_A16', type is buried 
_LC2_A16 = DFFE( _EQ165,  _LC6_B12,  VCC,  VCC,  VCC);
  _EQ165 = !_LC1_A16 &  _LC2_A16 &  _LC6_A16
         #  _LC2_A16 &  _LC6_A16 & !_LC8_A16
         #  _LC1_A16 & !_LC2_A16 &  _LC6_A16 &  _LC8_A16;

-- Node name is '|clock1_timer:292|~79~1' from file "clock1_timer.tdf" line 19, column 19
-- Equation name is '_LC1_A19', type is buried 
-- synthesized logic cell 
_LC1_A19 = LCELL( _EQ166);
  _EQ166 = !_LC2_A16
         # !_LC1_A16
         # !_LC3_A16;

-- Node name is '|clock1_timer:292|:79' from file "clock1_timer.tdf" line 19, column 19
-- Equation name is '_LC6_A16', type is buried 
_LC6_A16 = LCELL( _EQ167);
  _EQ167 =  _LC1_A19
         #  _LC5_A16
         # !_LC7_A16;

-- Node name is '|clock1_timer:292|:89' from file "clock1_timer.tdf" line 21, column 20
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = LCELL( _EQ168);
  _EQ168 = !_LC1_A12
         #  _LC3_A7
         # !_LC1_A6;

-- Node name is '|clock1_timer:292|:101' from file "clock1_timer.tdf" line 23, column 20
-- Equation name is '_LC7_A3', type is buried 
_LC7_A3  = LCELL( _EQ169);
  _EQ169 =  _LC6_A3
         #  _LC3_A9
         # !_LC5_A9
         #  _LC4_A9;

-- Node name is '|clock1_timer:292|:183' from file "clock1_timer.tdf" line 33, column 32
-- Equation name is '_LC7_A16', type is buried 
!_LC7_A16 = _LC7_A16~NOT;
_LC7_A16~NOT = LCELL( _EQ170);
  _EQ170 = !_LC3_A19
         # !_LC2_A19;

-- Node name is '|clock1_timer:292|:191' from file "clock1_timer.tdf" line 33, column 32
-- Equation name is '_LC8_A16', type is buried 
_LC8_A16 = LCELL( _EQ171);
  _EQ171 =  _LC2_A19 &  _LC3_A16 &  _LC3_A19 &  _LC5_A16;

-- Node name is '|clock1_timer:292|:213' from file "clock1_timer.tdf" line 35, column 28
-- Equation name is '_LC8_A3', type is buried 
_LC8_A3  = LCELL( _EQ172);
  _EQ172 =  _LC1_A9 &  _LC5_A9;

-- Node name is '|clock1_timer:292|:217' from file "clock1_timer.tdf" line 35, column 28
-- Equation name is '_LC6_A9', type is buried 
_LC6_A9  = LCELL( _EQ173);
  _EQ173 =  _LC1_A9 &  _LC3_A3 &  _LC5_A9;

-- Node name is '|clock1_timer:292|:221' from file "clock1_timer.tdf" line 35, column 28
-- Equation name is '_LC7_A9', type is buried 
_LC7_A9  = LCELL( _EQ174);
  _EQ174 =  _LC3_A9 &  _LC6_A9;

-- Node name is '|clock1_timer:292|:225' from file "clock1_timer.tdf" line 35, column 28
-- Equation name is '_LC8_A9', type is buried 
_LC8_A9  = LCELL( _EQ175);
  _EQ175 =  _LC2_A9 &  _LC3_A9 &  _LC6_A9;

-- Node name is '|clock1_timer:292|~253~1' from file "clock1_timer.tdf" line 37, column 18
-- Equation name is '_LC2_A3', type is buried 
-- synthesized logic cell 
_LC2_A3  = LCELL( _EQ176);
  _EQ176 =  _LC1_C4 &  _LC6_A16
         # !_LC1_A4 & !_LC6_A16 &  _LC7_A3;

-- Node name is '|clock1_timer:292|~255~1' from file "clock1_timer.tdf" line 37, column 18
-- Equation name is '_LC1_A3', type is buried 
-- synthesized logic cell 
_LC1_A3  = LCELL( _EQ177);
  _EQ177 =  _LC1_A4 & !_LC6_A16
         # !_LC1_C4 &  _LC6_A16;

-- Node name is '|clock1_timer:292|:263' from file "clock1_timer.tdf" line 40, column 32
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ178);
  _EQ178 =  _LC1_A7 &  _LC2_A2;

-- Node name is '|clock1_timer:292|:267' from file "clock1_timer.tdf" line 40, column 32
-- Equation name is '_LC5_A7', type is buried 
_LC5_A7  = LCELL( _EQ179);
  _EQ179 =  _LC1_A6 &  _LC3_A7;

-- Node name is '|clock1_timer:292|:271' from file "clock1_timer.tdf" line 40, column 32
-- Equation name is '_LC6_A7', type is buried 
_LC6_A7  = LCELL( _EQ180);
  _EQ180 =  _LC2_A7 &  _LC5_A7;

-- Node name is '|clock1_timer:292|:275' from file "clock1_timer.tdf" line 40, column 32
-- Equation name is '_LC7_A7', type is buried 
_LC7_A7  = LCELL( _EQ181);
  _EQ181 =  _LC2_A7 &  _LC4_A7 &  _LC5_A7;

-- Node name is '|clock1_timer:292|:293' from file "clock1_timer.tdf" line 39, column 7
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ182);
  _EQ182 = !_LC3_A2 &  _LC6_A16;

-- Node name is '|clock1_timer:292|~303~1' from file "clock1_timer.tdf" line 42, column 20
-- Equation name is '_LC1_A1', type is buried 
-- synthesized logic cell 
_LC1_A1  = LCELL( _EQ183);
  _EQ183 =  _LC3_A2 &  _LC6_A16
         #  _LC1_A4 & !_LC6_A16;

-- Node name is '|clock1_timer:292|:312' from file "clock1_timer.tdf" line 50, column 17
-- Equation name is '_LC1_A21', type is buried 
!_LC1_A21 = _LC1_A21~NOT;
_LC1_A21~NOT = LCELL( _EQ184);
  _EQ184 = !_LC2_A16 & !_LC2_A19 & !_LC2_A20 & !_LC3_A21;

-- Node name is '|clock1_timer:292|:322' from file "clock1_timer.tdf" line 55, column 17
-- Equation name is '_LC4_A16', type is buried 
!_LC4_A16 = _LC4_A16~NOT;
_LC4_A16~NOT = LCELL( _EQ185);
  _EQ185 = !_LC1_A16 & !_LC2_A16 & !_LC8_A16;

-- Node name is '|clock1_timer:292|~338~1' from file "clock1_timer.tdf" line 65, column 17
-- Equation name is '_LC6_A19', type is buried 
-- synthesized logic cell 
_LC6_A19 = LCELL( _EQ186);
  _EQ186 = !_LC2_A19 & !_LC3_A19
         # !_LC5_A16;

-- Node name is '|clock1_timer:292|:341' from file "clock1_timer.tdf" line 65, column 17
-- Equation name is '_LC8_A19', type is buried 
!_LC8_A19 = _LC8_A19~NOT;
_LC8_A19~NOT = LCELL( _EQ187);
  _EQ187 = !_LC1_A16 &  _LC6_A19
         # !_LC1_A16 & !_LC3_A16
         # !_LC2_A16;

-- Node name is '|digilab_display:272|digitcounter0' from file "digilab_display.tdf" line 15, column 17
-- Equation name is '_LC7_A5', type is buried 
_LC7_A5  = DFFE(!_LC7_A5,  _LC1_C2,  VCC,  VCC,  VCC);

-- Node name is '|digilab_display:272|digitcounter1' from file "digilab_display.tdf" line 15, column 17
-- Equation name is '_LC2_A5', type is buried 
_LC2_A5  = DFFE( _EQ188,  _LC1_C2,  VCC,  VCC,  VCC);
  _EQ188 = !_LC2_A5 &  _LC7_A5
         #  _LC2_A5 & !_LC7_A5;

-- Node name is '|digilab_display:272|digitcounter2' from file "digilab_display.tdf" line 15, column 17
-- Equation name is '_LC3_A5', type is buried 
_LC3_A5  = DFFE( _EQ189,  _LC1_C2,  VCC,  VCC,  VCC);
  _EQ189 =  _LC3_A5 & !_LC7_A5
         # !_LC2_A5 &  _LC3_A5
         #  _LC2_A5 & !_LC3_A5 &  _LC7_A5;

-- Node name is '|digilab_display:272|digitvalue0~1' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC4_A8', type is buried 
-- synthesized logic cell 
_LC4_A8  = LCELL( _EQ190);
  _EQ190 = !_LC8_A11 & !_LC8_A21
         #  _LC6_C23 & !_LC8_A21
         #  _LC2_C13 & !_LC8_A11
         #  _LC2_C13 &  _LC6_C23;

-- Node name is '|digilab_display:272|digitvalue0~2' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC5_A8', type is buried 
-- synthesized logic cell 
_LC5_A8  = LCELL( _EQ191);
  _EQ191 =  _LC4_A8 & !_LC8_A13
         #  _LC1_C22 &  _LC4_A8;

-- Node name is '|digilab_display:272|digitvalue0' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC2_A8', type is buried 
!_LC2_A8 = _LC2_A8~NOT;
_LC2_A8~NOT = LCELL( _EQ192);
  _EQ192 = !_LC1_A5 & !_LC3_A8 &  _LC5_A8 & !_LC6_A8;

-- Node name is '|digilab_display:272|digitvalue1~1' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC6_A17', type is buried 
-- synthesized logic cell 
!_LC6_A17 = _LC6_A17~NOT;
_LC6_A17~NOT = LCELL( _EQ193);
  _EQ193 = !_LC1_C22 &  _LC4_A17
         #  _LC5_A17 & !_LC6_C23;

-- Node name is '|digilab_display:272|digitvalue1~2' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC8_A17', type is buried 
-- synthesized logic cell 
!_LC8_A17 = _LC8_A17~NOT;
_LC8_A17~NOT = LCELL( _EQ194);
  _EQ194 = !_LC2_C13 &  _LC4_A21
         #  _LC1_A17 & !_LC2_C13
         # !_LC6_A17;

-- Node name is '|digilab_display:272|digitvalue1' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC1_A8', type is buried 
_LC1_A8  = LCELL( _EQ195);
  _EQ195 =  _LC7_A8
         # !_LC8_A17
         #  _LC5_A5
         #  _LC8_A8;

-- Node name is '|digilab_display:272|digitvalue2~1' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC5_A4', type is buried 
-- synthesized logic cell 
!_LC5_A4 = _LC5_A4~NOT;
_LC5_A4~NOT = LCELL( _EQ196);
  _EQ196 = !_LC1_C22 &  _LC2_A18
         #  _LC7_A4
         #  _LC3_A17;

-- Node name is '|digilab_display:272|digitvalue2~2' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC8_A20', type is buried 
-- synthesized logic cell 
!_LC8_A20 = _LC8_A20~NOT;
_LC8_A20~NOT = LCELL( _EQ197);
  _EQ197 = !_LC5_C23 &  _LC7_A20
         #  _LC3_A11 & !_LC8_C23;

-- Node name is '|digilab_display:272|digitvalue2' from file "digilab_display.tdf" line 34, column 26
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ198);
  _EQ198 =  _LC5_A20 & !_LC6_A5
         # !_LC5_A4
         # !_LC8_A20;

-- Node name is '|digilab_display:272|dpvalue' from file "digilab_display.tdf" line 34, column 47
-- Equation name is '_LC4_A5', type is buried 
_LC4_A5  = LCELL( _EQ199);
  _EQ199 = !_LC2_A5 &  _LC3_A5
         # !_LC3_A5 &  _LC7_A5
         # !_LC2_A5 & !_LC7_A5
         #  _LC2_A5 & !_LC3_A5 & !_LC6_B12;

-- Node name is '|digilab_display:272|:92' from file "digilab_display.tdf" line 29, column 3
-- Equation name is '_LC6_A5', type is buried 
_LC6_A5  = LCELL( _EQ200);
  _EQ200 =  _LC3_A5
         #  _LC2_A5
         #  _LC7_A5;

-- Node name is '|digilab_display:272|:94' from file "digilab_display.tdf" line 29, column 26
-- Equation name is '_LC1_A5', type is buried 
!_LC1_A5 = _LC1_A5~NOT;
_LC1_A5~NOT = LCELL( _EQ201);
  _EQ201 = !_LC8_A5 & !_LC8_A21
         #  _LC6_A5
         # !_LC2_A19;

-- Node name is '|digilab_display:272|:96' from file "digilab_display.tdf" line 29, column 26
-- Equation name is '_LC5_A5', type is buried 
_LC5_A5  = LCELL( _EQ202);
  _EQ202 = !_LC3_A19 & !_LC6_A5 &  _LC8_A21
         #  _LC3_A19 & !_LC6_A5 &  _LC8_A5;

-- Node name is '|digilab_display:272|:100' from file "digilab_display.tdf" line 29, column 26
-- Equation name is '_LC1_A23', type is buried 
_LC1_A23 = LCELL( _EQ203);
  _EQ203 = !_LC3_A23 & !_LC6_A5
         #  _LC5_A23 & !_LC6_A5
         # !_LC6_A5 & !_LC7_A23;

-- Node name is '|digilab_display:272|:105' from file "digilab_display.tdf" line 30, column 3
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = LCELL( _EQ204);
  _EQ204 =  _LC3_A5
         #  _LC2_A5
         # !_LC7_A5;

-- Node name is '|digilab_display:272|:113' from file "digilab_display.tdf" line 30, column 26
-- Equation name is '_LC3_A17', type is buried 
_LC3_A17 = LCELL( _EQ205);
  _EQ205 = !_LC2_C13 &  _LC7_A17
         # !_LC2_C13 &  _LC6_A21
         #  _LC2_A17 & !_LC2_C13;

-- Node name is '|digilab_display:272|:123' from file "digilab_display.tdf" line 31, column 3
-- Equation name is '_LC8_C23', type is buried 
_LC8_C23 = LCELL( _EQ206);
  _EQ206 =  _LC3_A5
         # !_LC2_A5
         #  _LC7_A5;

-- Node name is '|digilab_display:272|:125' from file "digilab_display.tdf" line 31, column 26
-- Equation name is '_LC6_A8', type is buried 
!_LC6_A8 = _LC6_A8~NOT;
_LC6_A8~NOT = LCELL( _EQ207);
  _EQ207 = !_LC4_A11 & !_LC8_A11
         #  _LC8_C23
         # !_LC2_A2;

-- Node name is '|digilab_display:272|:128' from file "digilab_display.tdf" line 31, column 26
-- Equation name is '_LC7_A8', type is buried 
_LC7_A8  = LCELL( _EQ208);
  _EQ208 =  _LC1_A7 &  _LC4_A11 & !_LC8_C23
         # !_LC1_A7 &  _LC8_A11 & !_LC8_C23;

-- Node name is '|digilab_display:272|:134' from file "digilab_display.tdf" line 31, column 26
-- Equation name is '_LC8_A10', type is buried 
_LC8_A10 = LCELL( _EQ209);
  _EQ209 = !_LC1_A10 & !_LC8_C23
         #  _LC2_A10 & !_LC8_C23
         # !_LC6_A10 & !_LC8_C23;

-- Node name is '|digilab_display:272|:142' from file "digilab_display.tdf" line 32, column 3
-- Equation name is '_LC6_C23', type is buried 
_LC6_C23 = LCELL( _EQ210);
  _EQ210 = !_LC7_A5
         # !_LC2_A5
         #  _LC3_A5;

-- Node name is '|digilab_display:272|:150' from file "digilab_display.tdf" line 32, column 26
-- Equation name is '_LC7_A4', type is buried 
_LC7_A4  = LCELL( _EQ211);
  _EQ211 =  _LC2_A4 & !_LC6_C23
         #  _LC3_A4 & !_LC6_C23
         #  _LC4_A4 & !_LC6_C23;

-- Node name is '|digilab_display:272|:160' from file "digilab_display.tdf" line 33, column 3
-- Equation name is '_LC5_C23', type is buried 
_LC5_C23 = LCELL( _EQ212);
  _EQ212 = !_LC3_A5
         #  _LC2_A5
         #  _LC7_A5;

-- Node name is '|digilab_display:272|:162' from file "digilab_display.tdf" line 33, column 26
-- Equation name is '_LC3_A8', type is buried 
!_LC3_A8 = _LC3_A8~NOT;
_LC3_A8~NOT = LCELL( _EQ213);
  _EQ213 = !_LC4_A18 & !_LC8_A13
         #  _LC5_C23
         # !_LC5_A9;

-- Node name is '|digilab_display:272|:165' from file "digilab_display.tdf" line 33, column 26
-- Equation name is '_LC8_A8', type is buried 
_LC8_A8  = LCELL( _EQ214);
  _EQ214 =  _LC1_A9 &  _LC4_A18 & !_LC5_C23
         # !_LC1_A9 & !_LC5_C23 &  _LC8_A13;

-- Node name is '|digilab_display:272|:172' from file "digilab_display.tdf" line 33, column 26
-- Equation name is '_LC2_A14', type is buried 
_LC2_A14 = LCELL( _EQ215);
  _EQ215 =  _LC5_A14 & !_LC5_C23
         #  _LC8_A10
         #  _LC1_A23;

-- Node name is '|digilab_display:272|:179' from file "digilab_display.tdf" line 34, column 3
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ216);
  _EQ216 = !_LC3_A5
         #  _LC2_A5
         # !_LC7_A5;

-- Node name is '|digilab_display:272|:253' from file "digilab_display.tdf" line 55, column 4
-- Equation name is '_LC6_A24', type is buried 
!_LC6_A24 = _LC6_A24~NOT;
_LC6_A24~NOT = LCELL( _EQ217);
  _EQ217 = !_LC1_A8 &  _LC1_A20 & !_LC2_A8 & !_LC2_A14;

-- Node name is '|digilab_display:272|:299' from file "digilab_display.tdf" line 60, column 21
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = LCELL( _EQ218);
  _EQ218 = !_LC1_A8 & !_LC1_A20 &  _LC2_A8
         # !_LC1_A8 &  _LC1_A20 & !_LC2_A14
         #  _LC2_A8 & !_LC2_A14;

-- Node name is '|digilab_display:272|:327' from file "digilab_display.tdf" line 63, column 29
-- Equation name is '_LC3_A14', type is buried 
_LC3_A14 = LCELL( _EQ219);
  _EQ219 = !_LC1_A8 &  _LC1_A20 & !_LC2_A8 &  _LC2_A14
         #  _LC1_A8 &  _LC1_A20 &  _LC2_A8 & !_LC2_A14
         # !_LC1_A8 & !_LC1_A20 & !_LC2_A14;

-- Node name is '|digilab_display:272|:335' from file "digilab_display.tdf" line 64, column 9
-- Equation name is '_LC1_A14', type is buried 
_LC1_A14 = LCELL( _EQ220);
  _EQ220 = !_LC1_A8 &  _LC1_A20 & !_LC2_A8 & !_LC2_A14
         #  _LC1_A8 & !_LC1_A20 &  _LC2_A8 &  _LC2_A14
         # !_LC1_A8 & !_LC1_A20 &  _LC2_A8 & !_LC2_A14
         # !_LC1_A8 &  _LC1_A20 &  _LC2_A8 &  _LC2_A14;

-- Node name is '|digilab_display:272|~337~1' from file "digilab_display.tdf" line 64, column 25
-- Equation name is '_LC3_A24', type is buried 
-- synthesized logic cell 
_LC3_A24 = LCELL( _EQ221);
  _EQ221 =  _LC1_A8 &  _LC1_A20 &  _LC2_A8 & !_LC2_A14
         # !_LC1_A8 & !_LC1_A20 &  _LC2_A8 & !_LC2_A14;

-- Node name is '|digilab_display:272|~337~2' from file "digilab_display.tdf" line 64, column 25
-- Equation name is '_LC4_A24', type is buried 
-- synthesized logic cell 
_LC4_A24 = LCELL( _EQ222);
  _EQ222 =  _LC1_A8 & !_LC1_A20 & !_LC2_A14
         # !_LC1_A8 &  _LC1_A20 &  _LC2_A8 &  _LC2_A14;

-- Node name is '|digilab_display:272|:337' from file "digilab_display.tdf" line 64, column 25
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = LCELL( _EQ223);
  _EQ223 =  _LC3_A24
         #  _LC4_A24;

-- Node name is '|digilab_display:272|:356' from file "digilab_display.tdf" line 66, column 12
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = LCELL( _EQ224);
  _EQ224 = !_LC1_A8 &  _LC1_A20 &  _LC2_A8 & !_LC2_A14
         #  _LC1_A8 &  _LC2_A8 &  _LC2_A14
         #  _LC1_A20 & !_LC2_A8 &  _LC2_A14
         #  _LC1_A8 &  _LC1_A20 & !_LC2_A8;

-- Node name is '|digilab_display:272|:358' from file "digilab_display.tdf" line 66, column 16
-- Equation name is '_LC7_A24', type is buried 
_LC7_A24 = LCELL( _EQ225);
  _EQ225 =  _LC1_A8 & !_LC1_A20 & !_LC2_A8 & !_LC2_A14
         #  _LC1_A20 & !_LC2_A8 &  _LC2_A14
         #  _LC1_A8 &  _LC1_A20 &  _LC2_A14;

-- Node name is '|digilab_display:272|~360~1' from file "digilab_display.tdf" line 66, column 20
-- Equation name is '_LC8_A24', type is buried 
-- synthesized logic cell 
_LC8_A24 = LCELL( _EQ226);
  _EQ226 =  _LC1_A8 & !_LC1_A20 & !_LC2_A8 &  _LC2_A14
         #  _LC1_A8 &  _LC1_A20 &  _LC2_A8 &  _LC2_A14;

-- Node name is '|digilab_display:272|:360' from file "digilab_display.tdf" line 66, column 20
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = LCELL( _EQ227);
  _EQ227 = !_LC6_A24
         #  _LC3_A24
         #  _LC8_A24;

-- Node name is '|key_debounce:288|:12' = '|key_debounce:288|KEYDEB' 
-- Equation name is '_LC3_A2', type is buried 
!_LC3_A2 = _LC3_A2~NOT;
_LC3_A2~NOT = LCELL( _EQ228);
  _EQ228 = !_LC5_A2
         # !_LC6_A2
         # !_LC7_A2
         # !_LC8_A2;

-- Node name is '|key_debounce:288|:6' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = DFFE(!_LC5_A2,  _LC4_A2, !t1,  VCC,  VCC);

-- Node name is '|key_debounce:288|:7' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = DFFE( _EQ229,  _LC4_A2, !t1,  VCC,  VCC);
  _EQ229 =  _LC5_A2 & !_LC6_A2
         # !_LC5_A2 &  _LC6_A2;

-- Node name is '|key_debounce:288|:8' 
-- Equation name is '_LC7_A2', type is buried 
_LC7_A2  = DFFE( _EQ230,  _LC4_A2, !t1,  VCC,  VCC);
  _EQ230 =  _LC6_A2 & !_LC7_A2
         # !_LC6_A2 &  _LC7_A2;

-- Node name is '|key_debounce:288|:9' 
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = DFFE( _EQ231,  _LC4_A2, !t1,  VCC,  VCC);
  _EQ231 =  _LC7_A2 & !_LC8_A2
         # !_LC7_A2 &  _LC8_A2;

-- Node name is '|key_debounce:288|:11' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ232);
  _EQ232 =  _LC1_C2 & !_LC3_A2;

-- Node name is '|key_debounce:289|:12' = '|key_debounce:289|KEYDEB' 
-- Equation name is '_LC1_C4', type is buried 
!_LC1_C4 = _LC1_C4~NOT;
_LC1_C4~NOT = LCELL( _EQ233);
  _EQ233 = !_LC3_C4
         # !_LC4_C4
         # !_LC5_C4
         # !_LC6_C4;

-- Node name is '|key_debounce:289|:6' 
-- Equation name is '_LC3_C4', type is buried 
_LC3_C4  = DFFE(!_LC3_C4,  _LC2_C4, !t3,  VCC,  VCC);

-- Node name is '|key_debounce:289|:7' 
-- Equation name is '_LC4_C4', type is buried 
_LC4_C4  = DFFE( _EQ234,  _LC2_C4, !t3,  VCC,  VCC);
  _EQ234 =  _LC3_C4 & !_LC4_C4
         # !_LC3_C4 &  _LC4_C4;

-- Node name is '|key_debounce:289|:8' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = DFFE( _EQ235,  _LC2_C4, !t3,  VCC,  VCC);
  _EQ235 =  _LC4_C4 & !_LC5_C4
         # !_LC4_C4 &  _LC5_C4;

-- Node name is '|key_debounce:289|:9' 
-- Equation name is '_LC6_C4', type is buried 
_LC6_C4  = DFFE( _EQ236,  _LC2_C4, !t3,  VCC,  VCC);
  _EQ236 =  _LC5_C4 & !_LC6_C4
         # !_LC5_C4 &  _LC6_C4;

-- Node name is '|key_debounce:289|:11' 
-- Equation name is '_LC2_C4', type is buried 
_LC2_C4  = LCELL( _EQ237);
  _EQ237 =  _LC1_C2 & !_LC1_C4;



Project Information                 c:\projects\digilab\clock_1_001\clock1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:03
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:09


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,981K
