Project Information                c:\projects\digilab\clock1\key_debounce.rpt

MAX+plus II Compiler Report File
Version 9.6 3/22/2000
Compiled: 09/24/2000 22:55:32

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

key_debounce
      EPF10K10LC84-3       2      1      0    0         0  %    6        1  %

User Pins:                 2      1      0  



Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

***** Logic for device 'key_debounce' compiled without errors.




Device: EPF10K10LC84-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f

                                                                         ^     
                                                                         C     
                R  R  R  R  R  R  R     R                 R  R  R  R     O     
                E  E  E  E  E  E  E     E                 E  E  E  E     N     
                S  S  S  S  S  S  S  V  S  G  G  G  K  G  S  S  S  S     F     
                E  E  E  E  E  E  E  C  E  N  N  N  E  N  E  E  E  E     _  ^  
                R  R  R  R  R  R  R  C  R  D  D  D  Y  D  R  R  R  R  #  D  n  
                V  V  V  V  V  V  V  I  V  I  I  I  D  I  V  V  V  V  T  O  C  
                E  E  E  E  E  E  E  N  E  N  N  N  E  N  E  E  E  E  C  N  E  
                D  D  D  D  D  D  D  T  D  T  T  T  B  T  D  D  D  D  K  E  O  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    ^DATA0 | 12                                                              74 | #TDO 
     ^DCLK | 13                                                              73 | RESERVED 
      ^nCE | 14                                                              72 | RESERVED 
      #TDI | 15                                                              71 | RESERVED 
  RESERVED | 16                                                              70 | RESERVED 
  RESERVED | 17                                                              69 | RESERVED 
  RESERVED | 18                                                              68 | GNDINT 
  RESERVED | 19                                                              67 | RESERVED 
    VCCINT | 20                                                              66 | RESERVED 
  RESERVED | 21                                                              65 | RESERVED 
  RESERVED | 22                        EPF10K10LC84-3                        64 | RESERVED 
  RESERVED | 23                                                              63 | VCCINT 
  RESERVED | 24                                                              62 | RESERVED 
  RESERVED | 25                                                              61 | RESERVED 
    GNDINT | 26                                                              60 | RESERVED 
  RESERVED | 27                                                              59 | RESERVED 
  RESERVED | 28                                                              58 | RESERVED 
  RESERVED | 29                                                              57 | #TMS 
       CLK | 30                                                              56 | #TRST 
    ^MSEL0 | 31                                                              55 | ^nSTATUS 
    ^MSEL1 | 32                                                              54 | RESERVED 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                V  ^  R  R  R  R  R  V  G  K  G  G  V  G  R  R  R  R  R  R  R  
                C  n  E  E  E  E  E  C  N  E  N  N  C  N  E  E  E  E  E  E  E  
                C  C  S  S  S  S  S  C  D  Y  D  D  C  D  S  S  S  S  S  S  S  
                I  O  E  E  E  E  E  I  I     I  I  I  I  E  E  E  E  E  E  E  
                N  N  R  R  R  R  R  N  N     N  N  N  N  R  R  R  R  R  R  R  
                T  F  V  V  V  V  V  T  T     T  T  T  T  V  V  V  V  V  V  V  
                   I  E  E  E  E  E                       E  E  E  E  E  E  E  
                   G  D  D  D  D  D                       D  D  D  D  D  D  D  
                                                                               
                                                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
C13      6/ 8( 75%)   1/ 8( 12%)   0/ 8(  0%)    1/2    1/2       1/22(  4%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 1/6      ( 16%)
Total I/O pins used:                             2/53     (  3%)
Total logic cells used:                          6/576    (  1%)
Total embedded cells used:                       0/24     (  0%)
Total EABs used:                                 0/3      (  0%)
Average fan-in:                                 2.16/4    ( 54%)
Total fan-in:                                  13/2304    (  0%)

Total input pins required:                       2
Total input I/O cell registers required:         0
Total output pins required:                      1
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                      6
Total flipflops required:                        4
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                         0/ 576   (  0%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 B:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 C:      0   0   0   0   0   0   0   0   0   0   0   0   0   6   0   0   0   0   0   0   0   0   0   0   0      6/0  

Total:   0   0   0   0   0   0   0   0   0   0   0   0   0   6   0   0   0   0   0   0   0   0   0   0   0      6/0  



Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  30      -     -    C    --      INPUT                0    0    0    1  CLK
  42      -     -    -    --      INPUT  G             0    0    0    0  KEY


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  83      -     -    -    13     OUTPUT                0    1    0    0  KEYDEB


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      3     -    C    13       DFFE                0    1    0    2  :6
   -      4     -    C    13       DFFE                0    2    0    2  :7
   -      5     -    C    13       DFFE                0    2    0    2  :8
   -      6     -    C    13       DFFE                0    2    0    1  :9
   -      1     -    C    13       AND2                1    1    0    4  :11
   -      2     -    C    13        OR2        !       0    4    1    1  :12


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       1/ 96(  1%)     0/ 48(  0%)     0/ 48(  0%)    1/16(  6%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

** CLOCK SIGNALS **

Type     Fan-out       Name
LCELL        4         :11


Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        4         KEY


Device-Specific Information:       c:\projects\digilab\clock1\key_debounce.rpt
key_debounce

** EQUATIONS **

CLK      : INPUT;
KEY      : INPUT;

-- Node name is 'KEYDEB' 
-- Equation name is 'KEYDEB', type is output 
KEYDEB   =  _LC2_C13;

-- Node name is ':6' 
-- Equation name is '_LC3_C13', type is buried 
_LC3_C13 = DFFE(!_LC3_C13,  _LC1_C13, GLOBAL(!KEY),  VCC,  VCC);

-- Node name is ':7' 
-- Equation name is '_LC4_C13', type is buried 
_LC4_C13 = DFFE( _EQ001,  _LC1_C13, GLOBAL(!KEY),  VCC,  VCC);
  _EQ001 =  _LC3_C13 & !_LC4_C13
         # !_LC3_C13 &  _LC4_C13;

-- Node name is ':8' 
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = DFFE( _EQ002,  _LC1_C13, GLOBAL(!KEY),  VCC,  VCC);
  _EQ002 =  _LC4_C13 & !_LC5_C13
         # !_LC4_C13 &  _LC5_C13;

-- Node name is ':9' 
-- Equation name is '_LC6_C13', type is buried 
_LC6_C13 = DFFE( _EQ003,  _LC1_C13, GLOBAL(!KEY),  VCC,  VCC);
  _EQ003 =  _LC5_C13 & !_LC6_C13
         # !_LC5_C13 &  _LC6_C13;

-- Node name is ':11' 
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = LCELL( _EQ004);
  _EQ004 =  CLK & !_LC2_C13;

-- Node name is ':12' 
-- Equation name is '_LC2_C13', type is buried 
!_LC2_C13 = _LC2_C13~NOT;
_LC2_C13~NOT = LCELL( _EQ005);
  _EQ005 = !_LC3_C13
         # !_LC4_C13
         # !_LC5_C13
         # !_LC6_C13;



Project Information                c:\projects\digilab\clock1\key_debounce.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:02
   Fitter                                 00:00:15
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:05
   --------------------------             --------
   Total Time                             00:00:23


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,913K
