Project Information                c:\projects\digilab\keyctl001\keyctl001.rpt

MAX+plus II Compiler Report File
Version 9.6 3/22/2000
Compiled: 12/19/2000 23:04:26

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

keyctl001
      EPM7064SLC44-10      3        10       0      30      0           46 %

User Pins:                 3        10       0  



Project Information                c:\projects\digilab\keyctl001\keyctl001.rpt

** PROJECT COMPILATION MESSAGES **

Warning: GLOBAL primitive on node 'RCLK' feeds logic -- non-global signal usage may result


Project Information                c:\projects\digilab\keyctl001\keyctl001.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal '4MhzClock' chosen for auto global Clock
INFO: Signal 'RCLK' chosen for auto global Clock


Project Information                c:\projects\digilab\keyctl001\keyctl001.rpt

** FILE HIERARCHY **



|cnt38dmux:1|


Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

***** Logic for device 'keyctl001' compiled without errors.




Device: EPM7064SLC44-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff

                           4                    
               R  R  R     M              R  R  
               E  E  E     h              E  E  
               S  S  S     z              S  S  
               E  E  E     C              E  E  
               R  R  R     l        R     R  R  
               V  V  V  V  o  G  G  C  G  V  V  
               E  E  E  C  c  N  N  L  N  E  E  
               D  D  D  C  k  D  D  K  D  D  D  
             -----------------------------------_ 
           /   6  5  4  3  2  1 44 43 42 41 40   | 
     #TDI |  7                                39 | RESERVED 
 RESERVED |  8                                38 | #TDO 
 RESERVED |  9                                37 | RESERVED 
      GND | 10                                36 | ODAT 
 RESERVED | 11                                35 | VCC 
     RDAT | 12        EPM7064SLC44-10         34 | RESERVED 
     #TMS | 13                                33 | RESERVED 
 RESERVED | 14                                32 | #TCK 
      VCC | 15                                31 | scan3 
 RESERVED | 16                                30 | GND 
 RESERVED | 17                                29 | scan4 
          |_  18 19 20 21 22 23 24 25 26 27 28  _| 
            ------------------------------------ 
               R  R  s  s  G  V  s  s  s  s  s  
               E  E  c  c  N  C  t  c  c  c  c  
               S  S  a  a  D  C  4  a  a  a  a  
               E  E  n  n           n  n  n  n  
               R  R  1  0           2  7  6  5  
               V  V                             
               E  E                             
               D  D                             
                                                


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   2/ 8( 25%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     2/16( 12%)   3/ 8( 37%)   0/16(  0%)   3/36(  8%) 
C:    LC33 - LC48    12/16( 75%)   8/ 8(100%)   0/16(  0%)   5/36( 13%) 
D:    LC49 - LC64    16/16(100%)   2/ 8( 25%)   0/16(  0%)  17/36( 47%) 


Total dedicated input pins used:                 2/4      ( 50%)
Total I/O pins used:                            15/32     ( 46%)
Total logic cells used:                         30/64     ( 46%)
Total shareable expanders used:                  0/64     (  0%)
Total Turbo logic cells used:                   30/64     ( 46%)
Total shareable expanders not available (n/a):   0/64     (  0%)
Average fan-in:                                  4.60
Total fan-in:                                   138

Total input pins required:                       3
Total fast input logic cells required:           0
Total output pins required:                     10
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     30
Total flipflops required:                       22
Total product terms required:                   38
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  64   (  0%)



Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  43      -   -       INPUT  G            0      0   0    0    0    1    7  RCLK
  12    (1)  (A)      INPUT               0      0   0    0    0    0    2  RDAT
   2      -   -       INPUT  G            0      0   0    0    0    0    0  4MhzClock


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  36     52    D         FF      t        0      0   0    1    9    0    0  ODAT
  21     17    B     OUTPUT      t        0      0   0    0    3    0    0  scan0
  20     19    B     OUTPUT      t        0      0   0    0    3    0    0  scan1
  25     35    C     OUTPUT      t        0      0   0    0    3    0    0  scan2
  31     46    C     OUTPUT      t        0      0   0    0    3    0    0  scan3
  29     41    C     OUTPUT      t        0      0   0    0    3    0    0  scan4
  28     40    C     OUTPUT      t        0      0   0    0    3    0    0  scan5
  27     37    C     OUTPUT      t        0      0   0    0    3    0    0  scan6
  26     36    C     OUTPUT      t        0      0   0    0    3    0    0  scan7
  24     33    C         FF   +  t        0      0   0    0    2    0    0  st4


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     38    C       TFFE   +  t        0      0   0    0    0    8    2  |cnt38dmux:1|v_cnt0
   -     34    C       TFFE   +  t        0      0   0    0    1    8    1  |cnt38dmux:1|v_cnt1
   -     39    C       TFFE   +  t        0      0   0    0    2    8    0  |cnt38dmux:1|v_cnt2
   -     54    D       DFFE   +  t        0      0   0    1    0    1    8  :14
   -     55    D       DFFE   +  t        0      0   0    0    1    1    8  :15
 (38)    56    D       DFFE   +  t        0      0   0    0    1    1    8  :16
   -     50    D       DFFE   +  t        0      0   0    0    1    1    8  :17
 (41)    64    D       DFFE   +  t        0      0   0    0    1    1    8  :18
 (33)    49    D       DFFE   +  t        0      0   0    0    1    1    8  :19
 (34)    51    D       DFFE   +  t        0      0   0    0    1    1    8  :20
 (37)    53    D       DFFE   +  t        0      0   0    0    1    1    7  :21
 (39)    57    D       DFFE      t        0      0   0    1    9    1    0  :25
   -     58    D       DFFE      t        0      0   0    1    9    0    1  :26
   -     59    D       DFFE      t        0      0   0    1    9    0    1  :27
   -     60    D       DFFE      t        0      0   0    1    9    0    1  :28
   -     61    D       DFFE      t        0      0   0    1    9    0    1  :29
 (40)    62    D       DFFE      t        0      0   0    1    9    0    1  :30
   -     63    D       DFFE      t        0      0   0    2    8    0    1  :31
   -     42    C       TFFE   +  t        0      0   0    0    0    1    1  :42
   -     43    C       TFFE   +  t        0      0   0    0    1    1    0  :43


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

             Logic cells placed in LAB 'B'
        +--- LC17 scan0
        | +- LC19 scan1
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'B'
LC      | | | A B C D |     Logic cells that feed LAB 'B':

Pin
43   -> - - | - - - * | <-- RCLK
2    -> - - | - - - - | <-- 4MhzClock
LC38 -> * * | - * * - | <-- |cnt38dmux:1|v_cnt0
LC34 -> * * | - * * - | <-- |cnt38dmux:1|v_cnt1
LC39 -> * * | - * * - | <-- |cnt38dmux:1|v_cnt2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                 Logic cells placed in LAB 'C'
        +----------------------- LC38 |cnt38dmux:1|v_cnt0
        | +--------------------- LC34 |cnt38dmux:1|v_cnt1
        | | +------------------- LC39 |cnt38dmux:1|v_cnt2
        | | | +----------------- LC35 scan2
        | | | | +--------------- LC46 scan3
        | | | | | +------------- LC41 scan4
        | | | | | | +----------- LC40 scan5
        | | | | | | | +--------- LC37 scan6
        | | | | | | | | +------- LC36 scan7
        | | | | | | | | | +----- LC33 st4
        | | | | | | | | | | +--- LC42 :42
        | | | | | | | | | | | +- LC43 :43
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC38 -> * * * * * * * * * - - - | - * * - | <-- |cnt38dmux:1|v_cnt0
LC34 -> - * * * * * * * * - - - | - * * - | <-- |cnt38dmux:1|v_cnt1
LC39 -> - - * * * * * * * - - - | - * * - | <-- |cnt38dmux:1|v_cnt2
LC42 -> - - - - - - - - - * * * | - - * - | <-- :42
LC43 -> - - - - - - - - - * - * | - - * - | <-- :43

Pin
43   -> - - - - - - - - - - - - | - - - * | <-- RCLK
2    -> - - - - - - - - - - - - | - - - - | <-- 4MhzClock


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC52 ODAT
        | +----------------------------- LC54 :14
        | | +--------------------------- LC55 :15
        | | | +------------------------- LC56 :16
        | | | | +----------------------- LC50 :17
        | | | | | +--------------------- LC64 :18
        | | | | | | +------------------- LC49 :19
        | | | | | | | +----------------- LC51 :20
        | | | | | | | | +--------------- LC53 :21
        | | | | | | | | | +------------- LC57 :25
        | | | | | | | | | | +----------- LC58 :26
        | | | | | | | | | | | +--------- LC59 :27
        | | | | | | | | | | | | +------- LC60 :28
        | | | | | | | | | | | | | +----- LC61 :29
        | | | | | | | | | | | | | | +--- LC62 :30
        | | | | | | | | | | | | | | | +- LC63 :31
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC54 -> * - - * - - - - - * * * * * * * | - - - * | <-- :14
LC55 -> * - - - - * - - - * * * * * * * | - - - * | <-- :15
LC56 -> * - - - * - - - - * * * * * * * | - - - * | <-- :16
LC50 -> * - * - - - - - - * * * * * * * | - - - * | <-- :17
LC64 -> * - - - - - * - - * * * * * * * | - - - * | <-- :18
LC49 -> * - - - - - - * - * * * * * * * | - - - * | <-- :19
LC51 -> * - - - - - - - * * * * * * * * | - - - * | <-- :20
LC53 -> * - - - - - - - - * * * * * * * | - - - * | <-- :21
LC57 -> * - - - - - - - - - - - - - - - | - - - * | <-- :25
LC58 -> - - - - - - - - - * - - - - - - | - - - * | <-- :26
LC59 -> - - - - - - - - - - * - - - - - | - - - * | <-- :27
LC60 -> - - - - - - - - - - - * - - - - | - - - * | <-- :28
LC61 -> - - - - - - - - - - - - * - - - | - - - * | <-- :29
LC62 -> - - - - - - - - - - - - - * - - | - - - * | <-- :30
LC63 -> - - - - - - - - - - - - - - * - | - - - * | <-- :31

Pin
43   -> * - - - - - - - - * * * * * * * | - - - * | <-- RCLK
12   -> - * - - - - - - - - - - - - - * | - - - * | <-- RDAT
2    -> - - - - - - - - - - - - - - - - | - - - - | <-- 4MhzClock


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       c:\projects\digilab\keyctl001\keyctl001.rpt
keyctl001

** EQUATIONS **

RCLK     : INPUT;
RDAT     : INPUT;
4MhzClock : INPUT;

-- Node name is 'ODAT' = ':24' 
-- Equation name is 'ODAT', type is output 
 ODAT    = DFFE( _LC057 $  GND,  _EQ001,  VCC,  VCC,  VCC);
  _EQ001 =  _LC049 &  _LC050 &  _LC051 &  _LC053 &  _LC054 &  _LC055 & 
              _LC056 &  _LC064 &  RCLK;

-- Node name is 'scan0' 
-- Equation name is 'scan0', location is LC017, type is output.
 scan0   = LCELL( _EQ002 $  GND);
  _EQ002 = !_LC034 & !_LC038 & !_LC039;

-- Node name is 'scan1' 
-- Equation name is 'scan1', location is LC019, type is output.
 scan1   = LCELL( _EQ003 $  GND);
  _EQ003 = !_LC034 &  _LC038 & !_LC039;

-- Node name is 'scan2' 
-- Equation name is 'scan2', location is LC035, type is output.
 scan2   = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC034 & !_LC038 & !_LC039;

-- Node name is 'scan3' 
-- Equation name is 'scan3', location is LC046, type is output.
 scan3   = LCELL( _EQ005 $  GND);
  _EQ005 =  _LC034 &  _LC038 & !_LC039;

-- Node name is 'scan4' 
-- Equation name is 'scan4', location is LC041, type is output.
 scan4   = LCELL( _EQ006 $  GND);
  _EQ006 = !_LC034 & !_LC038 &  _LC039;

-- Node name is 'scan5' 
-- Equation name is 'scan5', location is LC040, type is output.
 scan5   = LCELL( _EQ007 $  GND);
  _EQ007 = !_LC034 &  _LC038 &  _LC039;

-- Node name is 'scan6' 
-- Equation name is 'scan6', location is LC037, type is output.
 scan6   = LCELL( _EQ008 $  GND);
  _EQ008 =  _LC034 & !_LC038 &  _LC039;

-- Node name is 'scan7' 
-- Equation name is 'scan7', location is LC036, type is output.
 scan7   = LCELL( _EQ009 $  GND);
  _EQ009 =  _LC034 &  _LC038 &  _LC039;

-- Node name is 'st4' = ':44' 
-- Equation name is 'st4', type is output 
 st4     = TFFE( _EQ010, GLOBAL( RCLK),  VCC,  VCC,  VCC);
  _EQ010 =  _LC042 &  _LC043;

-- Node name is '|cnt38dmux:1|v_cnt0' from file "cnt38dmux.tdf" line 9, column 9
-- Equation name is '_LC038', type is buried 
_LC038   = TFFE( VCC, GLOBAL( 4MhzClock),  VCC,  VCC,  VCC);

-- Node name is '|cnt38dmux:1|v_cnt1' from file "cnt38dmux.tdf" line 9, column 9
-- Equation name is '_LC034', type is buried 
_LC034   = TFFE( _LC038, GLOBAL( 4MhzClock),  VCC,  VCC,  VCC);

-- Node name is '|cnt38dmux:1|v_cnt2' from file "cnt38dmux.tdf" line 9, column 9
-- Equation name is '_LC039', type is buried 
_LC039   = TFFE( _EQ011, GLOBAL( 4MhzClock),  VCC,  VCC,  VCC);
  _EQ011 =  _LC034 &  _LC038;

-- Node name is ':14' 
-- Equation name is '_LC054', type is buried 
_LC054   = DFFE( RDAT $  GND, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':15' 
-- Equation name is '_LC055', type is buried 
_LC055   = DFFE( _LC050 $  GND, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':16' 
-- Equation name is '_LC056', type is buried 
_LC056   = DFFE( _LC054 $  GND, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':17' 
-- Equation name is '_LC050', type is buried 
_LC050   = DFFE( _LC056 $  GND, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':18' 
-- Equation name is '_LC064', type is buried 
_LC064   = DFFE( _LC055 $  GND, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':19' 
-- Equation name is '_LC049', type is buried 
_LC049   = DFFE( _LC064 $  GND, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':20' 
-- Equation name is '_LC051', type is buried 
_LC051   = DFFE( _LC049 $  GND, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':21' 
-- Equation name is '_LC053', type is buried 
_LC053   = DFFE( _LC051 $  GND, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':25' 
-- Equation name is '_LC057', type is buried 
_LC057   = DFFE( _LC058 $  GND,  _EQ012,  VCC,  VCC,  VCC);
  _EQ012 =  _LC049 &  _LC050 &  _LC051 &  _LC053 &  _LC054 &  _LC055 & 
              _LC056 &  _LC064 &  RCLK;

-- Node name is ':26' 
-- Equation name is '_LC058', type is buried 
_LC058   = DFFE( _LC059 $  GND,  _EQ013,  VCC,  VCC,  VCC);
  _EQ013 =  _LC049 &  _LC050 &  _LC051 &  _LC053 &  _LC054 &  _LC055 & 
              _LC056 &  _LC064 &  RCLK;

-- Node name is ':27' 
-- Equation name is '_LC059', type is buried 
_LC059   = DFFE( _LC060 $  GND,  _EQ014,  VCC,  VCC,  VCC);
  _EQ014 =  _LC049 &  _LC050 &  _LC051 &  _LC053 &  _LC054 &  _LC055 & 
              _LC056 &  _LC064 &  RCLK;

-- Node name is ':28' 
-- Equation name is '_LC060', type is buried 
_LC060   = DFFE( _LC061 $  GND,  _EQ015,  VCC,  VCC,  VCC);
  _EQ015 =  _LC049 &  _LC050 &  _LC051 &  _LC053 &  _LC054 &  _LC055 & 
              _LC056 &  _LC064 &  RCLK;

-- Node name is ':29' 
-- Equation name is '_LC061', type is buried 
_LC061   = DFFE( _LC062 $  GND,  _EQ016,  VCC,  VCC,  VCC);
  _EQ016 =  _LC049 &  _LC050 &  _LC051 &  _LC053 &  _LC054 &  _LC055 & 
              _LC056 &  _LC064 &  RCLK;

-- Node name is ':30' 
-- Equation name is '_LC062', type is buried 
_LC062   = DFFE( _LC063 $  GND,  _EQ017,  VCC,  VCC,  VCC);
  _EQ017 =  _LC049 &  _LC050 &  _LC051 &  _LC053 &  _LC054 &  _LC055 & 
              _LC056 &  _LC064 &  RCLK;

-- Node name is ':31' 
-- Equation name is '_LC063', type is buried 
_LC063   = DFFE( RDAT $  GND,  _EQ018,  VCC,  VCC,  VCC);
  _EQ018 =  _LC049 &  _LC050 &  _LC051 &  _LC053 &  _LC054 &  _LC055 & 
              _LC056 &  _LC064 &  RCLK;

-- Node name is ':42' 
-- Equation name is '_LC042', type is buried 
_LC042   = TFFE( VCC, GLOBAL( RCLK),  VCC,  VCC,  VCC);

-- Node name is ':43' 
-- Equation name is '_LC043', type is buried 
_LC043   = TFFE( _LC042, GLOBAL( RCLK),  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                c:\projects\digilab\keyctl001\keyctl001.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:15
   --------------------------             --------
   Total Time                             00:00:17


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,137K
