Analysis & Synthesis report for DE2_TOP
Sun May 15 01:05:37 2016
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. Registers Removed During Synthesis
 11. Removed Registers Triggering Further Register Optimizations
 12. General Register Statistics
 13. Registers Packed Into Inferred Megafunctions
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated
 16. Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated
 17. Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated
 18. Source assignments for Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0|altsyncram_l371:auto_generated
 19. Source assignments for CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0|altsyncram_6071:auto_generated
 20. Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated
 21. Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated
 22. Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated
 23. Parameter Settings for User Entity Instance: VGA_PLL:p1|altpll:altpll_component
 24. Parameter Settings for User Entity Instance: VGA_Controller:u1
 25. Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0
 26. Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|altsyncram:RAM_rtl_0
 27. Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|altsyncram:RAM_rtl_0
 28. Parameter Settings for Inferred Entity Instance: Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0
 29. Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0
 30. Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|altsyncram:RAM_rtl_0
 31. Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|altsyncram:RAM_rtl_0
 32. Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|altsyncram:RAM_rtl_0
 33. Parameter Settings for Inferred Entity Instance: Troll_Controller:tc0|lpm_mult:Mult0
 34. altpll Parameter Settings by Entity Instance
 35. altsyncram Parameter Settings by Entity Instance
 36. lpm_mult Parameter Settings by Entity Instance
 37. Port Connectivity Checks: "CA_Controller:cc0|TempRegion_Controller:trc0"
 38. Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD"
 39. Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM"
 40. Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD"
 41. Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM"
 42. Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD"
 43. Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM"
 44. Port Connectivity Checks: "VGA_Controller:u1"
 45. Elapsed Time Per Partition
 46. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                         ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun May 15 01:05:36 2016           ;
; Quartus II 32-bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name                      ; DE2_TOP                                         ;
; Top-level Entity Name              ; DE2_TOP                                         ;
; Family                             ; Cyclone II                                      ;
; Total logic elements               ; 3,601                                           ;
;     Total combinational functions  ; 3,469                                           ;
;     Dedicated logic registers      ; 1,513                                           ;
; Total registers                    ; 1513                                            ;
; Total pins                         ; 425                                             ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 290,816                                         ;
; Embedded Multiplier 9-bit elements ; 0                                               ;
; Total PLLs                         ; 1                                               ;
+------------------------------------+-------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                      ; DE2_TOP            ; DE2_TOP            ;
; Family name                                                                ; Cyclone II         ; Cyclone IV GX      ;
; Remove Redundant Logic Cells                                               ; On                 ; Off                ;
; Remove Duplicate Registers                                                 ; Off                ; On                 ;
; Optimization Technique                                                     ; Speed              ; Balanced           ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                        ;
+--------------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path           ; Used in Netlist ; File Type                                             ; File Name with Absolute Path                                                                                 ; Library ;
+--------------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+---------+
; VGA_PLL.v                                  ; yes             ; User Wizard-Generated File                            ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/VGA_PLL.v                                  ;         ;
; VGA_Param.h                                ; yes             ; User Unspecified File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/VGA_Param.h                                ;         ;
; VGA_Controller.v                           ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/VGA_Controller.v                           ;         ;
; ColorROM.v                                 ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/ColorROM.v                                 ;         ;
; Reset_Delay.v                              ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/Reset_Delay.v                              ;         ;
; DE2_TOP.v                                  ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/DE2_TOP.v                                  ;         ;
; SRAM_Controller.v                          ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/SRAM_Controller.v                          ;         ;
; CA_Controller.v                            ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/CA_Controller.v                            ;         ;
; Input_Controller.v                         ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/Input_Controller.v                         ;         ;
; ColorSelector.v                            ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/ColorSelector.v                            ;         ;
; RAM_256_16.v                               ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/RAM_256_16.v                               ;         ;
; Particle_Update.v                          ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/Particle_Update.v                          ;         ;
; CircleROM.v                                ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/CircleROM.v                                ;         ;
; TempRegion_Controller.v                    ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/TempRegion_Controller.v                    ;         ;
; project_params.h                           ; yes             ; User Unspecified File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/project_params.h                           ;         ;
; RNG_4b.v                                   ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/RNG_4b.v                                   ;         ;
; PS2_ScanCodeReader.v                       ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/PS2_ScanCodeReader.v                       ;         ;
; Keyboard_Controller.v                      ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/Keyboard_Controller.v                      ;         ;
; ScanCodeToEvent.v                          ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/ScanCodeToEvent.v                          ;         ;
; scan_events.h                              ; yes             ; User Unspecified File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/scan_events.h                              ;         ;
; Troll_Controller.v                         ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/Troll_Controller.v                         ;         ;
; TrollROM.v                                 ; yes             ; User Verilog HDL File                                 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/TrollROM.v                                 ;         ;
; altpll.tdf                                 ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf                                                 ;         ;
; aglobal130.inc                             ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc                                             ;         ;
; stratix_pll.inc                            ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc                                            ;         ;
; stratixii_pll.inc                          ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc                                          ;         ;
; cycloneii_pll.inc                          ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc                                          ;         ;
; altsyncram.tdf                             ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf                                             ;         ;
; stratix_ram_block.inc                      ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc                                      ;         ;
; lpm_mux.inc                                ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc                                                ;         ;
; lpm_decode.inc                             ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc                                             ;         ;
; a_rdenreg.inc                              ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc                                              ;         ;
; altrom.inc                                 ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altrom.inc                                                 ;         ;
; altram.inc                                 ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altram.inc                                                 ;         ;
; altdpram.inc                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc                                               ;         ;
; db/altsyncram_mrg1.tdf                     ; yes             ; Auto-Generated Megafunction                           ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/db/altsyncram_mrg1.tdf                     ;         ;
; db/altsyncram_l371.tdf                     ; yes             ; Auto-Generated Megafunction                           ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/db/altsyncram_l371.tdf                     ;         ;
; db/project.rom0_TrollROM_31c8eb6.hdl.mif   ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/db/project.rom0_TrollROM_31c8eb6.hdl.mif   ;         ;
; db/decode_4oa.tdf                          ; yes             ; Auto-Generated Megafunction                           ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/db/decode_4oa.tdf                          ;         ;
; db/mux_3kb.tdf                             ; yes             ; Auto-Generated Megafunction                           ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/db/mux_3kb.tdf                             ;         ;
; db/altsyncram_6071.tdf                     ; yes             ; Auto-Generated Megafunction                           ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/db/altsyncram_6071.tdf                     ;         ;
; db/project.rom0_CircleROM_68958870.hdl.mif ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/db/project.rom0_CircleROM_68958870.hdl.mif ;         ;
; lpm_mult.tdf                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf                                               ;         ;
; lpm_add_sub.inc                            ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc                                            ;         ;
; multcore.inc                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.inc                                               ;         ;
; bypassff.inc                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc                                               ;         ;
; altshift.inc                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc                                               ;         ;
; multcore.tdf                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf                                               ;         ;
; csa_add.inc                                ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/csa_add.inc                                                ;         ;
; mpar_add.inc                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.inc                                               ;         ;
; muleabz.inc                                ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/muleabz.inc                                                ;         ;
; mul_lfrg.inc                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mul_lfrg.inc                                               ;         ;
; mul_boothc.inc                             ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mul_boothc.inc                                             ;         ;
; alt_ded_mult.inc                           ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult.inc                                           ;         ;
; alt_ded_mult_y.inc                         ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult_y.inc                                         ;         ;
; dffpipe.inc                                ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffpipe.inc                                                ;         ;
; mpar_add.tdf                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf                                               ;         ;
; altshift.tdf                               ; yes             ; Megafunction                                          ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.tdf                                               ;         ;
+--------------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+---------+


+----------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                            ;
+---------------------------------------------+------------------------------------------+
; Resource                                    ; Usage                                    ;
+---------------------------------------------+------------------------------------------+
; Estimated Total logic elements              ; 3,601                                    ;
;                                             ;                                          ;
; Total combinational functions               ; 3469                                     ;
; Logic element usage by number of LUT inputs ;                                          ;
;     -- 4 input functions                    ; 1746                                     ;
;     -- 3 input functions                    ; 690                                      ;
;     -- <=2 input functions                  ; 1033                                     ;
;                                             ;                                          ;
; Logic elements by mode                      ;                                          ;
;     -- normal mode                          ; 3126                                     ;
;     -- arithmetic mode                      ; 343                                      ;
;                                             ;                                          ;
; Total registers                             ; 1513                                     ;
;     -- Dedicated logic registers            ; 1513                                     ;
;     -- I/O registers                        ; 0                                        ;
;                                             ;                                          ;
; I/O pins                                    ; 425                                      ;
; Total memory bits                           ; 290816                                   ;
; Embedded Multiplier 9-bit elements          ; 0                                        ;
; Total PLLs                                  ; 1                                        ;
;     -- PLLs                                 ; 1                                        ;
;                                             ;                                          ;
; Maximum fan-out node                        ; VGA_PLL:p1|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 1675                                     ;
; Total fan-out                               ; 17214                                    ;
; Average fan-out                             ; 3.09                                     ;
+---------------------------------------------+------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                         ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                      ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                            ; Library Name ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------+--------------+
; |DE2_TOP                                        ; 3469 (1)          ; 1513 (0)     ; 290816      ; 0            ; 0       ; 0         ; 425  ; 0            ; |DE2_TOP                                                                                                                       ; work         ;
;    |CA_Controller:cc0|                          ; 1693 (542)        ; 401 (67)     ; 28672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0                                                                                                     ; work         ;
;       |RAM_256_16:RAMgen[0].OLD|                ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD                                                                            ; work         ;
;          |altsyncram:RAM_rtl_0|                 ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|altsyncram:RAM_rtl_0                                                       ; work         ;
;             |altsyncram_mrg1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated                        ; work         ;
;       |RAM_256_16:RAMgen[0].RAM|                ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM                                                                            ; work         ;
;          |altsyncram:RAM_rtl_0|                 ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0                                                       ; work         ;
;             |altsyncram_mrg1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated                        ; work         ;
;       |RAM_256_16:RAMgen[1].OLD|                ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD                                                                            ; work         ;
;          |altsyncram:RAM_rtl_0|                 ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|altsyncram:RAM_rtl_0                                                       ; work         ;
;             |altsyncram_mrg1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated                        ; work         ;
;       |RAM_256_16:RAMgen[1].RAM|                ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM                                                                            ; work         ;
;          |altsyncram:RAM_rtl_0|                 ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|altsyncram:RAM_rtl_0                                                       ; work         ;
;             |altsyncram_mrg1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated                        ; work         ;
;       |RAM_256_16:RAMgen[2].OLD|                ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD                                                                            ; work         ;
;          |altsyncram:RAM_rtl_0|                 ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|altsyncram:RAM_rtl_0                                                       ; work         ;
;             |altsyncram_mrg1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated                        ; work         ;
;       |RAM_256_16:RAMgen[2].RAM|                ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM                                                                            ; work         ;
;          |altsyncram:RAM_rtl_0|                 ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|altsyncram:RAM_rtl_0                                                       ; work         ;
;             |altsyncram_mrg1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated                        ; work         ;
;       |TempRegion_Controller:trc0|              ; 1151 (933)        ; 334 (334)    ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0                                                                          ; work         ;
;          |CircleROM:circleROM|                  ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM                                                      ; work         ;
;             |altsyncram:Ram0_rtl_0|             ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0                                ; work         ;
;                |altsyncram_6071:auto_generated| ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0|altsyncram_6071:auto_generated ; work         ;
;          |Particle_Update:pu0|                  ; 218 (218)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|Particle_Update:pu0                                                      ; work         ;
;    |ColorSelector:cs0|                          ; 83 (60)           ; 81 (57)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|ColorSelector:cs0                                                                                                     ; work         ;
;       |ColorROM:colorROM|                       ; 23 (23)           ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|ColorSelector:cs0|ColorROM:colorROM                                                                                   ; work         ;
;    |Input_Controller:ic0|                       ; 135 (135)         ; 68 (68)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Input_Controller:ic0                                                                                                  ; work         ;
;    |Keyboard_Controller:kc0|                    ; 558 (77)          ; 108 (75)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Keyboard_Controller:kc0                                                                                               ; work         ;
;       |PS2_ScanCodeReader:PS2_SCR|              ; 26 (26)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Keyboard_Controller:kc0|PS2_ScanCodeReader:PS2_SCR                                                                    ; work         ;
;       |ScanCodeToEvent:scte|                    ; 455 (455)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Keyboard_Controller:kc0|ScanCodeToEvent:scte                                                                          ; work         ;
;    |RNG_4b:rng0|                                ; 640 (640)         ; 640 (640)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|RNG_4b:rng0                                                                                                           ; work         ;
;    |Reset_Delay:r0|                             ; 28 (28)           ; 21 (21)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Reset_Delay:r0                                                                                                        ; work         ;
;    |SRAM_Controller:sc0|                        ; 41 (41)           ; 68 (68)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|SRAM_Controller:sc0                                                                                                   ; work         ;
;    |Troll_Controller:tc0|                       ; 110 (70)          ; 39 (37)      ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Troll_Controller:tc0                                                                                                  ; work         ;
;       |TrollROM:tROM|                           ; 36 (0)            ; 2 (0)        ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Troll_Controller:tc0|TrollROM:tROM                                                                                    ; work         ;
;          |altsyncram:Ram0_rtl_0|                ; 36 (0)            ; 2 (0)        ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0                                                              ; work         ;
;             |altsyncram_l371:auto_generated|    ; 36 (0)            ; 2 (2)        ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0|altsyncram_l371:auto_generated                               ; work         ;
;                |decode_4oa:deep_decode|         ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0|altsyncram_l371:auto_generated|decode_4oa:deep_decode        ; work         ;
;                |mux_3kb:mux2|                   ; 32 (32)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0|altsyncram_l371:auto_generated|mux_3kb:mux2                  ; work         ;
;       |lpm_mult:Mult0|                          ; 4 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Troll_Controller:tc0|lpm_mult:Mult0                                                                                   ; work         ;
;          |multcore:mult_core|                   ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|Troll_Controller:tc0|lpm_mult:Mult0|multcore:mult_core                                                                ; work         ;
;    |VGA_Controller:u1|                          ; 180 (180)         ; 87 (87)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|VGA_Controller:u1                                                                                                     ; work         ;
;    |VGA_PLL:p1|                                 ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|VGA_PLL:p1                                                                                                            ; work         ;
;       |altpll:altpll_component|                 ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_TOP|VGA_PLL:p1|altpll:altpll_component                                                                                    ; work         ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                             ;
+----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+--------------------------------------------+
; Name                                                                                                                             ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                                        ;
+----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+--------------------------------------------+
; CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated|ALTSYNCRAM                        ; AUTO ; Simple Dual Port ; 256          ; 16           ; 256          ; 16           ; 4096   ; None                                       ;
; CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated|ALTSYNCRAM                        ; AUTO ; Simple Dual Port ; 256          ; 16           ; 256          ; 16           ; 4096   ; None                                       ;
; CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated|ALTSYNCRAM                        ; AUTO ; Simple Dual Port ; 256          ; 16           ; 256          ; 16           ; 4096   ; None                                       ;
; CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated|ALTSYNCRAM                        ; AUTO ; Simple Dual Port ; 256          ; 16           ; 256          ; 16           ; 4096   ; None                                       ;
; CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated|ALTSYNCRAM                        ; AUTO ; Simple Dual Port ; 256          ; 16           ; 256          ; 16           ; 4096   ; None                                       ;
; CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated|ALTSYNCRAM                        ; AUTO ; Simple Dual Port ; 256          ; 16           ; 256          ; 16           ; 4096   ; None                                       ;
; CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0|altsyncram_6071:auto_generated|ALTSYNCRAM ; AUTO ; ROM              ; 4096         ; 1            ; --           ; --           ; 4096   ; db/project.rom0_CircleROM_68958870.hdl.mif ;
; Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0|altsyncram_l371:auto_generated|ALTSYNCRAM                               ; AUTO ; ROM              ; 16384        ; 16           ; --           ; --           ; 262144 ; db/project.rom0_TrollROM_31c8eb6.hdl.mif   ;
+----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+--------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                             ;
+--------+--------------+---------+--------------+--------------+---------------------+-----------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance     ; IP Include File                                                             ;
+--------+--------------+---------+--------------+--------------+---------------------+-----------------------------------------------------------------------------+
; Altera ; ALTPLL       ; N/A     ; N/A          ; N/A          ; |DE2_TOP|VGA_PLL:p1 ; P:/Projects/FPGA_Falling_Sand_Game/ss868_FallingSandGame_restored/VGA_PLL.v ;
+--------+--------------+---------+--------------+--------------+---------------------+-----------------------------------------------------------------------------+


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; VGA_Controller:u1|oVGA_B[0,1]         ; Stuck at GND due to stuck port data_in ;
; VGA_Controller:u1|oVGA_G[0,1]         ; Stuck at GND due to stuck port data_in ;
; VGA_Controller:u1|oVGA_R[0,1]         ; Stuck at GND due to stuck port data_in ;
; VGA_Controller:u1|oSystemState[3,4]   ; Lost fanout                            ;
; Total Number of Removed Registers = 8 ;                                        ;
+---------------------------------------+----------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                     ;
+-----------------------------------+--------------------+----------------------------------------+
; Register name                     ; Reason for Removal ; Registers Removed due to This Register ;
+-----------------------------------+--------------------+----------------------------------------+
; VGA_Controller:u1|oSystemState[4] ; Lost Fanouts       ; VGA_Controller:u1|oSystemState[3]      ;
+-----------------------------------+--------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1513  ;
; Number of registers using Synchronous Clear  ; 97    ;
; Number of registers using Synchronous Load   ; 206   ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 578   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions                                                                                                                ;
+------------------------------------------------------------------------+-----------------------------------------------------------------------------+------+
; Register Name                                                          ; Megafunction                                                                ; Type ;
+------------------------------------------------------------------------+-----------------------------------------------------------------------------+------+
; CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|oData[0..15]                ; CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|RAM_rtl_0                        ; RAM  ;
; CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|oData[0..15]                ; CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|RAM_rtl_0                        ; RAM  ;
; CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|oData[0..15]                ; CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|RAM_rtl_0                        ; RAM  ;
; Troll_Controller:tc0|TrollROM:tROM|oData[0..15]                        ; Troll_Controller:tc0|TrollROM:tROM|Ram0_rtl_0                               ; RAM  ;
; CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|oData ; CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|Ram0_rtl_0 ; RAM  ;
; CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|oData[0..15]                ; CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|RAM_rtl_0                        ; RAM  ;
; CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|oData[0..15]                ; CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|RAM_rtl_0                        ; RAM  ;
; CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|oData[0..15]                ; CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|RAM_rtl_0                        ; RAM  ;
+------------------------------------------------------------------------+-----------------------------------------------------------------------------+------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_TOP|SRAM_Controller:sc0|VGA_datareg[15]                                       ;
; 3:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |DE2_TOP|SRAM_Controller:sc0|VGA_datareg[5]                                        ;
; 3:1                ; 37 bits   ; 74 LEs        ; 37 LEs               ; 37 LEs                 ; Yes        ; |DE2_TOP|VGA_Controller:u1|oAddress[12]                                            ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanByteCntr[2]                                   ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DE2_TOP|VGA_Controller:u1|oSystemState[1]                                         ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_TOP|Troll_Controller:tc0|TrollFrameCntr[0]                                    ;
; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE2_TOP|VGA_Controller:u1|H_Cont[5]                                               ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_TOP|SRAM_Controller:sc0|oSRAM_ADDR[7]                                         ;
; 9:1                ; 2 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |DE2_TOP|Troll_Controller:tc0|oTrollColor[0]                                       ;
; 5:1                ; 9 bits    ; 27 LEs        ; 18 LEs               ; 9 LEs                  ; Yes        ; |DE2_TOP|Troll_Controller:tc0|TrollCntr[1]                                         ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanBytes[7][6]                                   ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanBytes[6][2]                                   ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanBytes[5][4]                                   ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanBytes[4][4]                                   ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanBytes[3][0]                                   ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanBytes[2][1]                                   ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanBytes[1][7]                                   ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|ScanBytes[0][7]                                   ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |DE2_TOP|Keyboard_Controller:kc0|PS2_ScanCodeReader:PS2_SCR|BitCntr[0]             ;
; 5:1                ; 10 bits   ; 30 LEs        ; 10 LEs               ; 20 LEs                 ; Yes        ; |DE2_TOP|VGA_Controller:u1|V_Cont[4]                                               ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_TOP|Input_Controller:ic0|oCursorSize[0]                                       ;
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |DE2_TOP|Input_Controller:ic0|oFaucetSize_SALT[0]                                  ;
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |DE2_TOP|Input_Controller:ic0|oFaucetSize_WATER[2]                                 ;
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |DE2_TOP|Input_Controller:ic0|oFaucetSize_SAND[0]                                  ;
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |DE2_TOP|Input_Controller:ic0|oFaucetSize_OIL[0]                                   ;
; 11:1               ; 12 bits   ; 84 LEs        ; 24 LEs               ; 60 LEs                 ; Yes        ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|tempRegion[2][0][13]         ;
; 11:1               ; 12 bits   ; 84 LEs        ; 24 LEs               ; 60 LEs                 ; Yes        ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|tempRegion[0][2][1]          ;
; 7:1                ; 10 bits   ; 40 LEs        ; 10 LEs               ; 30 LEs                 ; Yes        ; |DE2_TOP|CA_Controller:cc0|yBlock[0]                                               ;
; 7:1                ; 9 bits    ; 36 LEs        ; 18 LEs               ; 18 LEs                 ; Yes        ; |DE2_TOP|CA_Controller:cc0|xBlock[4]                                               ;
; 7:1                ; 24 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; Yes        ; |DE2_TOP|VGA_Controller:u1|oVGA_B[9]                                               ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_TOP|CA_Controller:cc0|rowT[0]                                                 ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_TOP|CA_Controller:cc0|rowM[0]                                                 ;
; 8:1                ; 10 bits   ; 50 LEs        ; 10 LEs               ; 40 LEs                 ; Yes        ; |DE2_TOP|Input_Controller:ic0|oCursorY[2]                                          ;
; 8:1                ; 10 bits   ; 50 LEs        ; 10 LEs               ; 40 LEs                 ; Yes        ; |DE2_TOP|Input_Controller:ic0|oCursorX[5]                                          ;
; 7:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; Yes        ; |DE2_TOP|CA_Controller:cc0|rowB[0]                                                 ;
; 13:1               ; 12 bits   ; 96 LEs        ; 36 LEs               ; 60 LEs                 ; Yes        ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|tempRegion[1][1][12]         ;
; 13:1               ; 12 bits   ; 96 LEs        ; 36 LEs               ; 60 LEs                 ; Yes        ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|tempRegion[2][1][2]          ;
; 13:1               ; 12 bits   ; 96 LEs        ; 36 LEs               ; 60 LEs                 ; Yes        ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|tempRegion[1][1][4]          ;
; 13:1               ; 12 bits   ; 96 LEs        ; 36 LEs               ; 60 LEs                 ; Yes        ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|tempRegion[2][1][8]          ;
; 37:1               ; 4 bits    ; 96 LEs        ; 36 LEs               ; 60 LEs                 ; Yes        ; |DE2_TOP|Input_Controller:ic0|CHOSEN_COLOR[2]                                      ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |DE2_TOP|Troll_Controller:tc0|TrollFrame[1]                                        ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|Particle_Update:pu0|oMidL[1] ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|OLDoDataT[2]                                            ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|OLDoDataM[3]                                            ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|Particle_Update:pu0|oMidR[2] ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|RAMoDataB[10]                                           ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|RAMwen[0][0]                                            ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|OLDaddr[0][4]                                           ;
; 9:1                ; 7 bits    ; 42 LEs        ; 28 LEs               ; 14 LEs                 ; No         ; |DE2_TOP|CA_Controller:cc0|RAMaddr[0][6]                                           ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|Particle_Update:pu0|oBotM[1] ;
; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|Particle_Update:pu0|oBotL[1] ;
; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|pu_iOldMM[1]                 ;
; 7:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|Particle_Update:pu0|oBotR[3] ;
; 6:1                ; 8 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|comb                         ;
; 6:1                ; 8 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|comb                         ;
; 7:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|comb                         ;
; 7:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|comb                         ;
; 9:1                ; 16 bits   ; 96 LEs        ; 64 LEs               ; 32 LEs                 ; No         ; |DE2_TOP|CA_Controller:cc0|RAMiData[0][5]                                          ;
; 9:1                ; 16 bits   ; 96 LEs        ; 64 LEs               ; 32 LEs                 ; No         ; |DE2_TOP|CA_Controller:cc0|RAMiData[2][12]                                         ;
; 9:1                ; 16 bits   ; 96 LEs        ; 64 LEs               ; 32 LEs                 ; No         ; |DE2_TOP|CA_Controller:cc0|RAMiData[1][12]                                         ;
; 8:1                ; 8 bits    ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|comb                         ;
; 8:1                ; 8 bits    ; 40 LEs        ; 32 LEs               ; 8 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|comb                         ;
; 8:1                ; 8 bits    ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|comb                         ;
; 8:1                ; 8 bits    ; 40 LEs        ; 32 LEs               ; 8 LEs                  ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|comb                         ;
; 23:1               ; 4 bits    ; 60 LEs        ; 48 LEs               ; 12 LEs                 ; No         ; |DE2_TOP|CA_Controller:cc0|TempRegion_Controller:trc0|Particle_Update:pu0|oMidM[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                      ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                       ;
+---------------------------------+--------------------+------+---------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                      ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                       ;
+---------------------------------+--------------------+------+---------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                      ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                       ;
+---------------------------------+--------------------+------+---------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Source assignments for Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0|altsyncram_l371:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                               ;
+---------------------------------+--------------------+------+--------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                ;
+---------------------------------+--------------------+------+--------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0|altsyncram_6071:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                             ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                              ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                      ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                       ;
+---------------------------------+--------------------+------+---------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                      ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                       ;
+---------------------------------+--------------------+------+---------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|altsyncram:RAM_rtl_0|altsyncram_mrg1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                      ;
+---------------------------------+--------------------+------+---------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                       ;
+---------------------------------+--------------------+------+---------------------------------------------------------+


+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_PLL:p1|altpll:altpll_component ;
+-------------------------------+-------------------+-----------------------------+
; Parameter Name                ; Value             ; Type                        ;
+-------------------------------+-------------------+-----------------------------+
; OPERATION_MODE                ; NORMAL            ; Untyped                     ;
; PLL_TYPE                      ; AUTO              ; Untyped                     ;
; LPM_HINT                      ; UNUSED            ; Untyped                     ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                     ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                     ;
; SCAN_CHAIN                    ; LONG              ; Untyped                     ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                     ;
; INCLK0_INPUT_FREQUENCY        ; 37037             ; Signed Integer              ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                     ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                     ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                     ;
; LOCK_HIGH                     ; 1                 ; Untyped                     ;
; LOCK_LOW                      ; 1                 ; Untyped                     ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                     ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                     ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                     ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                     ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                     ;
; SKIP_VCO                      ; OFF               ; Untyped                     ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                     ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                     ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                     ;
; BANDWIDTH                     ; 0                 ; Untyped                     ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                     ;
; SPREAD_FREQUENCY              ; 0                 ; Untyped                     ;
; DOWN_SPREAD                   ; 0                 ; Untyped                     ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                     ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                     ;
; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                     ;
; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                     ;
; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                     ;
; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                     ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                     ;
; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                     ;
; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                     ;
; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                     ;
; CLK1_MULTIPLY_BY              ; 28                ; Signed Integer              ;
; CLK0_MULTIPLY_BY              ; 14                ; Signed Integer              ;
; CLK9_DIVIDE_BY                ; 0                 ; Untyped                     ;
; CLK8_DIVIDE_BY                ; 0                 ; Untyped                     ;
; CLK7_DIVIDE_BY                ; 0                 ; Untyped                     ;
; CLK6_DIVIDE_BY                ; 0                 ; Untyped                     ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                     ;
; CLK4_DIVIDE_BY                ; 1                 ; Untyped                     ;
; CLK3_DIVIDE_BY                ; 1                 ; Untyped                     ;
; CLK2_DIVIDE_BY                ; 1                 ; Untyped                     ;
; CLK1_DIVIDE_BY                ; 15                ; Signed Integer              ;
; CLK0_DIVIDE_BY                ; 15                ; Signed Integer              ;
; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK0_PHASE_SHIFT              ; -9921             ; Untyped                     ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK9_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK8_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK7_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK6_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK4_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK3_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK2_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer              ;
; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer              ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; LOCK_WINDOW_UI                ;  0.05             ; Untyped                     ;
; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                     ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                     ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                     ;
; DPA_MULTIPLY_BY               ; 0                 ; Untyped                     ;
; DPA_DIVIDE_BY                 ; 1                 ; Untyped                     ;
; DPA_DIVIDER                   ; 0                 ; Untyped                     ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                     ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                     ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                     ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                     ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                     ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                     ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                     ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                     ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                     ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                     ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                     ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                     ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                     ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                     ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                     ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                     ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                     ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                     ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                     ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                     ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                     ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                     ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                     ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                     ;
; VCO_MIN                       ; 0                 ; Untyped                     ;
; VCO_MAX                       ; 0                 ; Untyped                     ;
; VCO_CENTER                    ; 0                 ; Untyped                     ;
; PFD_MIN                       ; 0                 ; Untyped                     ;
; PFD_MAX                       ; 0                 ; Untyped                     ;
; M_INITIAL                     ; 0                 ; Untyped                     ;
; M                             ; 0                 ; Untyped                     ;
; N                             ; 1                 ; Untyped                     ;
; M2                            ; 1                 ; Untyped                     ;
; N2                            ; 1                 ; Untyped                     ;
; SS                            ; 1                 ; Untyped                     ;
; C0_HIGH                       ; 0                 ; Untyped                     ;
; C1_HIGH                       ; 0                 ; Untyped                     ;
; C2_HIGH                       ; 0                 ; Untyped                     ;
; C3_HIGH                       ; 0                 ; Untyped                     ;
; C4_HIGH                       ; 0                 ; Untyped                     ;
; C5_HIGH                       ; 0                 ; Untyped                     ;
; C6_HIGH                       ; 0                 ; Untyped                     ;
; C7_HIGH                       ; 0                 ; Untyped                     ;
; C8_HIGH                       ; 0                 ; Untyped                     ;
; C9_HIGH                       ; 0                 ; Untyped                     ;
; C0_LOW                        ; 0                 ; Untyped                     ;
; C1_LOW                        ; 0                 ; Untyped                     ;
; C2_LOW                        ; 0                 ; Untyped                     ;
; C3_LOW                        ; 0                 ; Untyped                     ;
; C4_LOW                        ; 0                 ; Untyped                     ;
; C5_LOW                        ; 0                 ; Untyped                     ;
; C6_LOW                        ; 0                 ; Untyped                     ;
; C7_LOW                        ; 0                 ; Untyped                     ;
; C8_LOW                        ; 0                 ; Untyped                     ;
; C9_LOW                        ; 0                 ; Untyped                     ;
; C0_INITIAL                    ; 0                 ; Untyped                     ;
; C1_INITIAL                    ; 0                 ; Untyped                     ;
; C2_INITIAL                    ; 0                 ; Untyped                     ;
; C3_INITIAL                    ; 0                 ; Untyped                     ;
; C4_INITIAL                    ; 0                 ; Untyped                     ;
; C5_INITIAL                    ; 0                 ; Untyped                     ;
; C6_INITIAL                    ; 0                 ; Untyped                     ;
; C7_INITIAL                    ; 0                 ; Untyped                     ;
; C8_INITIAL                    ; 0                 ; Untyped                     ;
; C9_INITIAL                    ; 0                 ; Untyped                     ;
; C0_MODE                       ; BYPASS            ; Untyped                     ;
; C1_MODE                       ; BYPASS            ; Untyped                     ;
; C2_MODE                       ; BYPASS            ; Untyped                     ;
; C3_MODE                       ; BYPASS            ; Untyped                     ;
; C4_MODE                       ; BYPASS            ; Untyped                     ;
; C5_MODE                       ; BYPASS            ; Untyped                     ;
; C6_MODE                       ; BYPASS            ; Untyped                     ;
; C7_MODE                       ; BYPASS            ; Untyped                     ;
; C8_MODE                       ; BYPASS            ; Untyped                     ;
; C9_MODE                       ; BYPASS            ; Untyped                     ;
; C0_PH                         ; 0                 ; Untyped                     ;
; C1_PH                         ; 0                 ; Untyped                     ;
; C2_PH                         ; 0                 ; Untyped                     ;
; C3_PH                         ; 0                 ; Untyped                     ;
; C4_PH                         ; 0                 ; Untyped                     ;
; C5_PH                         ; 0                 ; Untyped                     ;
; C6_PH                         ; 0                 ; Untyped                     ;
; C7_PH                         ; 0                 ; Untyped                     ;
; C8_PH                         ; 0                 ; Untyped                     ;
; C9_PH                         ; 0                 ; Untyped                     ;
; L0_HIGH                       ; 1                 ; Untyped                     ;
; L1_HIGH                       ; 1                 ; Untyped                     ;
; G0_HIGH                       ; 1                 ; Untyped                     ;
; G1_HIGH                       ; 1                 ; Untyped                     ;
; G2_HIGH                       ; 1                 ; Untyped                     ;
; G3_HIGH                       ; 1                 ; Untyped                     ;
; E0_HIGH                       ; 1                 ; Untyped                     ;
; E1_HIGH                       ; 1                 ; Untyped                     ;
; E2_HIGH                       ; 1                 ; Untyped                     ;
; E3_HIGH                       ; 1                 ; Untyped                     ;
; L0_LOW                        ; 1                 ; Untyped                     ;
; L1_LOW                        ; 1                 ; Untyped                     ;
; G0_LOW                        ; 1                 ; Untyped                     ;
; G1_LOW                        ; 1                 ; Untyped                     ;
; G2_LOW                        ; 1                 ; Untyped                     ;
; G3_LOW                        ; 1                 ; Untyped                     ;
; E0_LOW                        ; 1                 ; Untyped                     ;
; E1_LOW                        ; 1                 ; Untyped                     ;
; E2_LOW                        ; 1                 ; Untyped                     ;
; E3_LOW                        ; 1                 ; Untyped                     ;
; L0_INITIAL                    ; 1                 ; Untyped                     ;
; L1_INITIAL                    ; 1                 ; Untyped                     ;
; G0_INITIAL                    ; 1                 ; Untyped                     ;
; G1_INITIAL                    ; 1                 ; Untyped                     ;
; G2_INITIAL                    ; 1                 ; Untyped                     ;
; G3_INITIAL                    ; 1                 ; Untyped                     ;
; E0_INITIAL                    ; 1                 ; Untyped                     ;
; E1_INITIAL                    ; 1                 ; Untyped                     ;
; E2_INITIAL                    ; 1                 ; Untyped                     ;
; E3_INITIAL                    ; 1                 ; Untyped                     ;
; L0_MODE                       ; BYPASS            ; Untyped                     ;
; L1_MODE                       ; BYPASS            ; Untyped                     ;
; G0_MODE                       ; BYPASS            ; Untyped                     ;
; G1_MODE                       ; BYPASS            ; Untyped                     ;
; G2_MODE                       ; BYPASS            ; Untyped                     ;
; G3_MODE                       ; BYPASS            ; Untyped                     ;
; E0_MODE                       ; BYPASS            ; Untyped                     ;
; E1_MODE                       ; BYPASS            ; Untyped                     ;
; E2_MODE                       ; BYPASS            ; Untyped                     ;
; E3_MODE                       ; BYPASS            ; Untyped                     ;
; L0_PH                         ; 0                 ; Untyped                     ;
; L1_PH                         ; 0                 ; Untyped                     ;
; G0_PH                         ; 0                 ; Untyped                     ;
; G1_PH                         ; 0                 ; Untyped                     ;
; G2_PH                         ; 0                 ; Untyped                     ;
; G3_PH                         ; 0                 ; Untyped                     ;
; E0_PH                         ; 0                 ; Untyped                     ;
; E1_PH                         ; 0                 ; Untyped                     ;
; E2_PH                         ; 0                 ; Untyped                     ;
; E3_PH                         ; 0                 ; Untyped                     ;
; M_PH                          ; 0                 ; Untyped                     ;
; C1_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C2_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C3_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C4_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C5_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C6_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C7_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C8_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C9_USE_CASC_IN                ; OFF               ; Untyped                     ;
; CLK0_COUNTER                  ; G0                ; Untyped                     ;
; CLK1_COUNTER                  ; G0                ; Untyped                     ;
; CLK2_COUNTER                  ; G0                ; Untyped                     ;
; CLK3_COUNTER                  ; G0                ; Untyped                     ;
; CLK4_COUNTER                  ; G0                ; Untyped                     ;
; CLK5_COUNTER                  ; G0                ; Untyped                     ;
; CLK6_COUNTER                  ; E0                ; Untyped                     ;
; CLK7_COUNTER                  ; E1                ; Untyped                     ;
; CLK8_COUNTER                  ; E2                ; Untyped                     ;
; CLK9_COUNTER                  ; E3                ; Untyped                     ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                     ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                     ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                     ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                     ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                     ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                     ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                     ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                     ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                     ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                     ;
; M_TIME_DELAY                  ; 0                 ; Untyped                     ;
; N_TIME_DELAY                  ; 0                 ; Untyped                     ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                     ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                     ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                     ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                     ;
; ENABLE0_COUNTER               ; L0                ; Untyped                     ;
; ENABLE1_COUNTER               ; L0                ; Untyped                     ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                     ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                     ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                     ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                     ;
; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                     ;
; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                     ;
; VCO_POST_SCALE                ; 0                 ; Untyped                     ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                     ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                     ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                     ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II        ; Untyped                     ;
; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK0                     ; PORT_USED         ; Untyped                     ;
; PORT_CLK1                     ; PORT_USED         ; Untyped                     ;
; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_INCLK0                   ; PORT_USED         ; Untyped                     ;
; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                     ;
; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                     ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                     ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                     ;
; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                     ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                     ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                     ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                     ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                     ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C6_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C7_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C8_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C9_TEST_SOURCE                ; 5                 ; Untyped                     ;
; CBXI_PARAMETER                ; NOTHING           ; Untyped                     ;
; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                     ;
; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                     ;
; WIDTH_CLOCK                   ; 6                 ; Untyped                     ;
; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                     ;
; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                     ;
; DEVICE_FAMILY                 ; Cyclone II        ; Untyped                     ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                     ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                     ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                  ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE              ;
+-------------------------------+-------------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_Controller:u1 ;
+----------------+-------+---------------------------------------+
; Parameter Name ; Value ; Type                                  ;
+----------------+-------+---------------------------------------+
; H_SYNC_CYC     ; 95    ; Signed Integer                        ;
; H_SYNC_BACK    ; 60    ; Signed Integer                        ;
; H_SYNC_ACT     ; 640   ; Signed Integer                        ;
; H_SYNC_FRONT   ; 5     ; Signed Integer                        ;
; H_SYNC_MAX     ; 799   ; Signed Integer                        ;
; V_SYNC_CYC     ; 2     ; Signed Integer                        ;
; V_SYNC_BACK    ; 31    ; Signed Integer                        ;
; V_SYNC_ACT     ; 480   ; Signed Integer                        ;
; V_SYNC_FRONT   ; 12    ; Signed Integer                        ;
; V_SYNC_MAX     ; 524   ; Signed Integer                        ;
; X_START        ; 155   ; Signed Integer                        ;
; Y_START        ; 33    ; Signed Integer                        ;
; X_LATENCY      ; 3     ; Signed Integer                        ;
+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0 ;
+------------------------------------+----------------------+------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                 ;
+------------------------------------+----------------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                              ;
; WIDTH_A                            ; 16                   ; Untyped                                              ;
; WIDTHAD_A                          ; 8                    ; Untyped                                              ;
; NUMWORDS_A                         ; 256                  ; Untyped                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WIDTH_B                            ; 16                   ; Untyped                                              ;
; WIDTHAD_B                          ; 8                    ; Untyped                                              ;
; NUMWORDS_B                         ; 256                  ; Untyped                                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                              ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                              ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                              ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                              ;
; CBXI_PARAMETER                     ; altsyncram_mrg1      ; Untyped                                              ;
+------------------------------------+----------------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|altsyncram:RAM_rtl_0 ;
+------------------------------------+----------------------+------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                 ;
+------------------------------------+----------------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                              ;
; WIDTH_A                            ; 16                   ; Untyped                                              ;
; WIDTHAD_A                          ; 8                    ; Untyped                                              ;
; NUMWORDS_A                         ; 256                  ; Untyped                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WIDTH_B                            ; 16                   ; Untyped                                              ;
; WIDTHAD_B                          ; 8                    ; Untyped                                              ;
; NUMWORDS_B                         ; 256                  ; Untyped                                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                              ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                              ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                              ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                              ;
; CBXI_PARAMETER                     ; altsyncram_mrg1      ; Untyped                                              ;
+------------------------------------+----------------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|altsyncram:RAM_rtl_0 ;
+------------------------------------+----------------------+------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                 ;
+------------------------------------+----------------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                              ;
; WIDTH_A                            ; 16                   ; Untyped                                              ;
; WIDTHAD_A                          ; 8                    ; Untyped                                              ;
; NUMWORDS_A                         ; 256                  ; Untyped                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WIDTH_B                            ; 16                   ; Untyped                                              ;
; WIDTHAD_B                          ; 8                    ; Untyped                                              ;
; NUMWORDS_B                         ; 256                  ; Untyped                                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                              ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                              ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                              ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                              ;
; CBXI_PARAMETER                     ; altsyncram_mrg1      ; Untyped                                              ;
+------------------------------------+----------------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0 ;
+------------------------------------+------------------------------------------+---------------------------+
; Parameter Name                     ; Value                                    ; Type                      ;
+------------------------------------+------------------------------------------+---------------------------+
; BYTE_SIZE_BLOCK                    ; 8                                        ; Untyped                   ;
; AUTO_CARRY_CHAINS                  ; ON                                       ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS               ; OFF                                      ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS                ; ON                                       ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS             ; OFF                                      ; IGNORE_CASCADE            ;
; WIDTH_BYTEENA                      ; 1                                        ; Untyped                   ;
; OPERATION_MODE                     ; ROM                                      ; Untyped                   ;
; WIDTH_A                            ; 16                                       ; Untyped                   ;
; WIDTHAD_A                          ; 14                                       ; Untyped                   ;
; NUMWORDS_A                         ; 16384                                    ; Untyped                   ;
; OUTDATA_REG_A                      ; UNREGISTERED                             ; Untyped                   ;
; ADDRESS_ACLR_A                     ; NONE                                     ; Untyped                   ;
; OUTDATA_ACLR_A                     ; NONE                                     ; Untyped                   ;
; WRCONTROL_ACLR_A                   ; NONE                                     ; Untyped                   ;
; INDATA_ACLR_A                      ; NONE                                     ; Untyped                   ;
; BYTEENA_ACLR_A                     ; NONE                                     ; Untyped                   ;
; WIDTH_B                            ; 1                                        ; Untyped                   ;
; WIDTHAD_B                          ; 1                                        ; Untyped                   ;
; NUMWORDS_B                         ; 1                                        ; Untyped                   ;
; INDATA_REG_B                       ; CLOCK1                                   ; Untyped                   ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                                   ; Untyped                   ;
; RDCONTROL_REG_B                    ; CLOCK1                                   ; Untyped                   ;
; ADDRESS_REG_B                      ; CLOCK1                                   ; Untyped                   ;
; OUTDATA_REG_B                      ; UNREGISTERED                             ; Untyped                   ;
; BYTEENA_REG_B                      ; CLOCK1                                   ; Untyped                   ;
; INDATA_ACLR_B                      ; NONE                                     ; Untyped                   ;
; WRCONTROL_ACLR_B                   ; NONE                                     ; Untyped                   ;
; ADDRESS_ACLR_B                     ; NONE                                     ; Untyped                   ;
; OUTDATA_ACLR_B                     ; NONE                                     ; Untyped                   ;
; RDCONTROL_ACLR_B                   ; NONE                                     ; Untyped                   ;
; BYTEENA_ACLR_B                     ; NONE                                     ; Untyped                   ;
; WIDTH_BYTEENA_A                    ; 1                                        ; Untyped                   ;
; WIDTH_BYTEENA_B                    ; 1                                        ; Untyped                   ;
; RAM_BLOCK_TYPE                     ; AUTO                                     ; Untyped                   ;
; BYTE_SIZE                          ; 8                                        ; Untyped                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                ; Untyped                   ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                     ; Untyped                   ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                     ; Untyped                   ;
; INIT_FILE                          ; db/project.rom0_TrollROM_31c8eb6.hdl.mif ; Untyped                   ;
; INIT_FILE_LAYOUT                   ; PORT_A                                   ; Untyped                   ;
; MAXIMUM_DEPTH                      ; 0                                        ; Untyped                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                                   ; Untyped                   ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                                   ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                                   ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                                   ; Untyped                   ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                          ; Untyped                   ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                          ; Untyped                   ;
; ENABLE_ECC                         ; FALSE                                    ; Untyped                   ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                    ; Untyped                   ;
; WIDTH_ECCSTATUS                    ; 3                                        ; Untyped                   ;
; DEVICE_FAMILY                      ; Cyclone II                               ; Untyped                   ;
; CBXI_PARAMETER                     ; altsyncram_l371                          ; Untyped                   ;
+------------------------------------+------------------------------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0 ;
+------------------------------------+--------------------------------------------+-------------------------------------------------------+
; Parameter Name                     ; Value                                      ; Type                                                  ;
+------------------------------------+--------------------------------------------+-------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                                          ; Untyped                                               ;
; AUTO_CARRY_CHAINS                  ; ON                                         ; AUTO_CARRY                                            ;
; IGNORE_CARRY_BUFFERS               ; OFF                                        ; IGNORE_CARRY                                          ;
; AUTO_CASCADE_CHAINS                ; ON                                         ; AUTO_CASCADE                                          ;
; IGNORE_CASCADE_BUFFERS             ; OFF                                        ; IGNORE_CASCADE                                        ;
; WIDTH_BYTEENA                      ; 1                                          ; Untyped                                               ;
; OPERATION_MODE                     ; ROM                                        ; Untyped                                               ;
; WIDTH_A                            ; 1                                          ; Untyped                                               ;
; WIDTHAD_A                          ; 12                                         ; Untyped                                               ;
; NUMWORDS_A                         ; 4096                                       ; Untyped                                               ;
; OUTDATA_REG_A                      ; UNREGISTERED                               ; Untyped                                               ;
; ADDRESS_ACLR_A                     ; NONE                                       ; Untyped                                               ;
; OUTDATA_ACLR_A                     ; NONE                                       ; Untyped                                               ;
; WRCONTROL_ACLR_A                   ; NONE                                       ; Untyped                                               ;
; INDATA_ACLR_A                      ; NONE                                       ; Untyped                                               ;
; BYTEENA_ACLR_A                     ; NONE                                       ; Untyped                                               ;
; WIDTH_B                            ; 1                                          ; Untyped                                               ;
; WIDTHAD_B                          ; 1                                          ; Untyped                                               ;
; NUMWORDS_B                         ; 1                                          ; Untyped                                               ;
; INDATA_REG_B                       ; CLOCK1                                     ; Untyped                                               ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                                     ; Untyped                                               ;
; RDCONTROL_REG_B                    ; CLOCK1                                     ; Untyped                                               ;
; ADDRESS_REG_B                      ; CLOCK1                                     ; Untyped                                               ;
; OUTDATA_REG_B                      ; UNREGISTERED                               ; Untyped                                               ;
; BYTEENA_REG_B                      ; CLOCK1                                     ; Untyped                                               ;
; INDATA_ACLR_B                      ; NONE                                       ; Untyped                                               ;
; WRCONTROL_ACLR_B                   ; NONE                                       ; Untyped                                               ;
; ADDRESS_ACLR_B                     ; NONE                                       ; Untyped                                               ;
; OUTDATA_ACLR_B                     ; NONE                                       ; Untyped                                               ;
; RDCONTROL_ACLR_B                   ; NONE                                       ; Untyped                                               ;
; BYTEENA_ACLR_B                     ; NONE                                       ; Untyped                                               ;
; WIDTH_BYTEENA_A                    ; 1                                          ; Untyped                                               ;
; WIDTH_BYTEENA_B                    ; 1                                          ; Untyped                                               ;
; RAM_BLOCK_TYPE                     ; AUTO                                       ; Untyped                                               ;
; BYTE_SIZE                          ; 8                                          ; Untyped                                               ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                  ; Untyped                                               ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                       ; Untyped                                               ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                       ; Untyped                                               ;
; INIT_FILE                          ; db/project.rom0_CircleROM_68958870.hdl.mif ; Untyped                                               ;
; INIT_FILE_LAYOUT                   ; PORT_A                                     ; Untyped                                               ;
; MAXIMUM_DEPTH                      ; 0                                          ; Untyped                                               ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                                     ; Untyped                                               ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                                     ; Untyped                                               ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                                     ; Untyped                                               ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                                     ; Untyped                                               ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                            ; Untyped                                               ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                            ; Untyped                                               ;
; ENABLE_ECC                         ; FALSE                                      ; Untyped                                               ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                      ; Untyped                                               ;
; WIDTH_ECCSTATUS                    ; 3                                          ; Untyped                                               ;
; DEVICE_FAMILY                      ; Cyclone II                                 ; Untyped                                               ;
; CBXI_PARAMETER                     ; altsyncram_6071                            ; Untyped                                               ;
+------------------------------------+--------------------------------------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|altsyncram:RAM_rtl_0 ;
+------------------------------------+----------------------+------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                 ;
+------------------------------------+----------------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                              ;
; WIDTH_A                            ; 16                   ; Untyped                                              ;
; WIDTHAD_A                          ; 8                    ; Untyped                                              ;
; NUMWORDS_A                         ; 256                  ; Untyped                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WIDTH_B                            ; 16                   ; Untyped                                              ;
; WIDTHAD_B                          ; 8                    ; Untyped                                              ;
; NUMWORDS_B                         ; 256                  ; Untyped                                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                              ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                              ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                              ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                              ;
; CBXI_PARAMETER                     ; altsyncram_mrg1      ; Untyped                                              ;
+------------------------------------+----------------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|altsyncram:RAM_rtl_0 ;
+------------------------------------+----------------------+------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                 ;
+------------------------------------+----------------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                              ;
; WIDTH_A                            ; 16                   ; Untyped                                              ;
; WIDTHAD_A                          ; 8                    ; Untyped                                              ;
; NUMWORDS_A                         ; 256                  ; Untyped                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WIDTH_B                            ; 16                   ; Untyped                                              ;
; WIDTHAD_B                          ; 8                    ; Untyped                                              ;
; NUMWORDS_B                         ; 256                  ; Untyped                                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                              ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                              ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                              ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                              ;
; CBXI_PARAMETER                     ; altsyncram_mrg1      ; Untyped                                              ;
+------------------------------------+----------------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|altsyncram:RAM_rtl_0 ;
+------------------------------------+----------------------+------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                 ;
+------------------------------------+----------------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                              ;
; WIDTH_A                            ; 16                   ; Untyped                                              ;
; WIDTHAD_A                          ; 8                    ; Untyped                                              ;
; NUMWORDS_A                         ; 256                  ; Untyped                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                              ;
; WIDTH_B                            ; 16                   ; Untyped                                              ;
; WIDTHAD_B                          ; 8                    ; Untyped                                              ;
; NUMWORDS_B                         ; 256                  ; Untyped                                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                              ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                              ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                              ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                              ;
; CBXI_PARAMETER                     ; altsyncram_mrg1      ; Untyped                                              ;
+------------------------------------+----------------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Troll_Controller:tc0|lpm_mult:Mult0 ;
+------------------------------------------------+------------+------------------------+
; Parameter Name                                 ; Value      ; Type                   ;
+------------------------------------------------+------------+------------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE         ;
; LPM_WIDTHA                                     ; 12         ; Untyped                ;
; LPM_WIDTHB                                     ; 2          ; Untyped                ;
; LPM_WIDTHP                                     ; 14         ; Untyped                ;
; LPM_WIDTHR                                     ; 14         ; Untyped                ;
; LPM_WIDTHS                                     ; 1          ; Untyped                ;
; LPM_REPRESENTATION                             ; UNSIGNED   ; Untyped                ;
; LPM_PIPELINE                                   ; 0          ; Untyped                ;
; LATENCY                                        ; 0          ; Untyped                ;
; INPUT_A_IS_CONSTANT                            ; YES        ; Untyped                ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                ;
; USE_EAB                                        ; OFF        ; Untyped                ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped                ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K    ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped                ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                ;
; CBXI_PARAMETER                                 ; NOTHING    ; Untyped                ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped                ;
+------------------------------------------------+------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                       ;
+-------------------------------+------------------------------------+
; Name                          ; Value                              ;
+-------------------------------+------------------------------------+
; Number of entity instances    ; 1                                  ;
; Entity Instance               ; VGA_PLL:p1|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                             ;
;     -- PLL_TYPE               ; AUTO                               ;
;     -- PRIMARY_CLOCK          ; INCLK0                             ;
;     -- INCLK0_INPUT_FREQUENCY ; 37037                              ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                  ;
;     -- VCO_MULTIPLY_BY        ; 0                                  ;
;     -- VCO_DIVIDE_BY          ; 0                                  ;
+-------------------------------+------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                                                   ;
+-------------------------------------------+----------------------------------------------------------------------------------------+
; Name                                      ; Value                                                                                  ;
+-------------------------------------------+----------------------------------------------------------------------------------------+
; Number of entity instances                ; 8                                                                                      ;
; Entity Instance                           ; CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0                        ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                              ;
;     -- WIDTH_A                            ; 16                                                                                     ;
;     -- NUMWORDS_A                         ; 256                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                           ;
;     -- WIDTH_B                            ; 16                                                                                     ;
;     -- NUMWORDS_B                         ; 256                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                 ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                           ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                   ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                               ;
; Entity Instance                           ; CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|altsyncram:RAM_rtl_0                        ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                              ;
;     -- WIDTH_A                            ; 16                                                                                     ;
;     -- NUMWORDS_A                         ; 256                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                           ;
;     -- WIDTH_B                            ; 16                                                                                     ;
;     -- NUMWORDS_B                         ; 256                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                 ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                           ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                   ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                               ;
; Entity Instance                           ; CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|altsyncram:RAM_rtl_0                        ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                              ;
;     -- WIDTH_A                            ; 16                                                                                     ;
;     -- NUMWORDS_A                         ; 256                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                           ;
;     -- WIDTH_B                            ; 16                                                                                     ;
;     -- NUMWORDS_B                         ; 256                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                 ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                           ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                   ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                               ;
; Entity Instance                           ; Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0                               ;
;     -- OPERATION_MODE                     ; ROM                                                                                    ;
;     -- WIDTH_A                            ; 16                                                                                     ;
;     -- NUMWORDS_A                         ; 16384                                                                                  ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                           ;
;     -- WIDTH_B                            ; 1                                                                                      ;
;     -- NUMWORDS_B                         ; 1                                                                                      ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                 ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                           ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                   ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                              ;
; Entity Instance                           ; CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0 ;
;     -- OPERATION_MODE                     ; ROM                                                                                    ;
;     -- WIDTH_A                            ; 1                                                                                      ;
;     -- NUMWORDS_A                         ; 4096                                                                                   ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                           ;
;     -- WIDTH_B                            ; 1                                                                                      ;
;     -- NUMWORDS_B                         ; 1                                                                                      ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                 ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                           ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                   ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                              ;
; Entity Instance                           ; CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|altsyncram:RAM_rtl_0                        ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                              ;
;     -- WIDTH_A                            ; 16                                                                                     ;
;     -- NUMWORDS_A                         ; 256                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                           ;
;     -- WIDTH_B                            ; 16                                                                                     ;
;     -- NUMWORDS_B                         ; 256                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                 ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                           ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                   ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                               ;
; Entity Instance                           ; CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|altsyncram:RAM_rtl_0                        ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                              ;
;     -- WIDTH_A                            ; 16                                                                                     ;
;     -- NUMWORDS_A                         ; 256                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                           ;
;     -- WIDTH_B                            ; 16                                                                                     ;
;     -- NUMWORDS_B                         ; 256                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                 ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                           ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                   ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                               ;
; Entity Instance                           ; CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|altsyncram:RAM_rtl_0                        ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                              ;
;     -- WIDTH_A                            ; 16                                                                                     ;
;     -- NUMWORDS_A                         ; 256                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                           ;
;     -- WIDTH_B                            ; 16                                                                                     ;
;     -- NUMWORDS_B                         ; 256                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                 ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                           ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                   ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                               ;
+-------------------------------------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                              ;
+---------------------------------------+-------------------------------------+
; Name                                  ; Value                               ;
+---------------------------------------+-------------------------------------+
; Number of entity instances            ; 1                                   ;
; Entity Instance                       ; Troll_Controller:tc0|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 12                                  ;
;     -- LPM_WIDTHB                     ; 2                                   ;
;     -- LPM_WIDTHP                     ; 14                                  ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                            ;
;     -- INPUT_A_IS_CONSTANT            ; YES                                 ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                  ;
;     -- USE_EAB                        ; OFF                                 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                  ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                  ;
+---------------------------------------+-------------------------------------+


+------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CA_Controller:cc0|TempRegion_Controller:trc0"                                         ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; Port   ; Type   ; Severity ; Details                                                                             ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; oTR_TM ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; oTR_MM ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; oTR_BM ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD"                                                                                                                                       ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                            ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; iWen ; Input ; Warning  ; Input port expression (16 bits) is wider than the input port (1 bits) it drives.  The 15 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM"                                                                                                                                       ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                            ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; iWen ; Input ; Warning  ; Input port expression (16 bits) is wider than the input port (1 bits) it drives.  The 15 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD"                                                                                                                                       ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                            ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; iWen ; Input ; Warning  ; Input port expression (16 bits) is wider than the input port (1 bits) it drives.  The 15 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM"                                                                                                                                       ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                            ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; iWen ; Input ; Warning  ; Input port expression (16 bits) is wider than the input port (1 bits) it drives.  The 15 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD"                                                                                                                                       ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                            ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; iWen ; Input ; Warning  ; Input port expression (16 bits) is wider than the input port (1 bits) it drives.  The 15 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM"                                                                                                                                       ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                            ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; iWen ; Input ; Warning  ; Input port expression (16 bits) is wider than the input port (1 bits) it drives.  The 15 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "VGA_Controller:u1"                                                                                                                            ;
+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                         ;
+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------+
; oAddress           ; Output ; Warning  ; Output or bidir port (20 bits) is wider than the port expression (19 bits) it drives; bit(s) "oAddress[19..19]" have no fanouts ;
; oSystemState[4..3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                             ;
; oValidReq          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                        ;
+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:31     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun May 15 01:04:33 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off project -c DE2_TOP
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file vga_pll.v
    Info (12023): Found entity 1: VGA_PLL
Info (12021): Found 1 design units, including 1 entities, in source file vga_controller.v
    Info (12023): Found entity 1: VGA_Controller
Info (12021): Found 1 design units, including 1 entities, in source file colorrom.v
    Info (12023): Found entity 1: ColorROM
Info (12021): Found 1 design units, including 1 entities, in source file reset_delay.v
    Info (12023): Found entity 1: Reset_Delay
Info (12021): Found 1 design units, including 1 entities, in source file de2_top.v
    Info (12023): Found entity 1: DE2_TOP
Info (12021): Found 1 design units, including 1 entities, in source file sram_controller.v
    Info (12023): Found entity 1: SRAM_Controller
Info (12021): Found 1 design units, including 1 entities, in source file ca_controller.v
    Info (12023): Found entity 1: CA_Controller
Info (12021): Found 1 design units, including 1 entities, in source file input_controller.v
    Info (12023): Found entity 1: Input_Controller
Info (12021): Found 1 design units, including 1 entities, in source file colorselector.v
    Info (12023): Found entity 1: ColorSelector
Info (12021): Found 1 design units, including 1 entities, in source file ram_256_16.v
    Info (12023): Found entity 1: RAM_256_16
Info (12021): Found 1 design units, including 1 entities, in source file particle_update.v
    Info (12023): Found entity 1: Particle_Update
Info (12021): Found 1 design units, including 1 entities, in source file circlerom.v
    Info (12023): Found entity 1: CircleROM
Info (12021): Found 1 design units, including 1 entities, in source file tempregion_controller.v
    Info (12023): Found entity 1: TempRegion_Controller
Info (12021): Found 1 design units, including 1 entities, in source file rng_4b.v
    Info (12023): Found entity 1: RNG_4b
Info (12021): Found 1 design units, including 1 entities, in source file ps2_scancodereader.v
    Info (12023): Found entity 1: PS2_ScanCodeReader
Info (12021): Found 1 design units, including 1 entities, in source file keyboard_controller.v
    Info (12023): Found entity 1: Keyboard_Controller
Info (12021): Found 1 design units, including 1 entities, in source file scancodetoevent.v
    Info (12023): Found entity 1: ScanCodeToEvent
Info (12021): Found 1 design units, including 1 entities, in source file troll_controller.v
    Info (12023): Found entity 1: Troll_Controller
Info (12021): Found 1 design units, including 1 entities, in source file trollrom.v
    Info (12023): Found entity 1: TrollROM
Info (12127): Elaborating entity "DE2_TOP" for the top level hierarchy
Info (12128): Elaborating entity "VGA_PLL" for hierarchy "VGA_PLL:p1"
Info (12128): Elaborating entity "altpll" for hierarchy "VGA_PLL:p1|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "VGA_PLL:p1|altpll:altpll_component"
Info (12133): Instantiated megafunction "VGA_PLL:p1|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "clk0_divide_by" = "15"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "14"
    Info (12134): Parameter "clk0_phase_shift" = "-9921"
    Info (12134): Parameter "clk1_divide_by" = "15"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "28"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "37037"
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12128): Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:r0"
Info (12128): Elaborating entity "RNG_4b" for hierarchy "RNG_4b:rng0"
Info (12128): Elaborating entity "VGA_Controller" for hierarchy "VGA_Controller:u1"
Info (12128): Elaborating entity "ColorSelector" for hierarchy "ColorSelector:cs0"
Info (12128): Elaborating entity "ColorROM" for hierarchy "ColorSelector:cs0|ColorROM:colorROM"
Info (12128): Elaborating entity "SRAM_Controller" for hierarchy "SRAM_Controller:sc0"
Info (12128): Elaborating entity "CA_Controller" for hierarchy "CA_Controller:cc0"
Info (12128): Elaborating entity "RAM_256_16" for hierarchy "CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM"
Info (12128): Elaborating entity "TempRegion_Controller" for hierarchy "CA_Controller:cc0|TempRegion_Controller:trc0"
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "tempRegion" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "oldRegion" into its bus
Info (12128): Elaborating entity "CircleROM" for hierarchy "CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM"
Info (12128): Elaborating entity "Particle_Update" for hierarchy "CA_Controller:cc0|TempRegion_Controller:trc0|Particle_Update:pu0"
Info (12128): Elaborating entity "Keyboard_Controller" for hierarchy "Keyboard_Controller:kc0"
Info (12128): Elaborating entity "PS2_ScanCodeReader" for hierarchy "Keyboard_Controller:kc0|PS2_ScanCodeReader:PS2_SCR"
Info (12128): Elaborating entity "ScanCodeToEvent" for hierarchy "Keyboard_Controller:kc0|ScanCodeToEvent:scte"
Info (12128): Elaborating entity "Input_Controller" for hierarchy "Input_Controller:ic0"
Info (12128): Elaborating entity "Troll_Controller" for hierarchy "Troll_Controller:tc0"
Info (12128): Elaborating entity "TrollROM" for hierarchy "Troll_Controller:tc0|TrollROM:tROM"
Info (19000): Inferred 8 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|RAM_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 16
        Info (286033): Parameter WIDTHAD_A set to 8
        Info (286033): Parameter NUMWORDS_A set to 256
        Info (286033): Parameter WIDTH_B set to 16
        Info (286033): Parameter WIDTHAD_B set to 8
        Info (286033): Parameter NUMWORDS_B set to 256
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
    Info (276029): Inferred altsyncram megafunction from the following design logic: "CA_Controller:cc0|RAM_256_16:RAMgen[1].RAM|RAM_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 16
        Info (286033): Parameter WIDTHAD_A set to 8
        Info (286033): Parameter NUMWORDS_A set to 256
        Info (286033): Parameter WIDTH_B set to 16
        Info (286033): Parameter WIDTHAD_B set to 8
        Info (286033): Parameter NUMWORDS_B set to 256
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
    Info (276029): Inferred altsyncram megafunction from the following design logic: "CA_Controller:cc0|RAM_256_16:RAMgen[2].RAM|RAM_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 16
        Info (286033): Parameter WIDTHAD_A set to 8
        Info (286033): Parameter NUMWORDS_A set to 256
        Info (286033): Parameter WIDTH_B set to 16
        Info (286033): Parameter WIDTHAD_B set to 8
        Info (286033): Parameter NUMWORDS_B set to 256
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
    Info (276029): Inferred altsyncram megafunction from the following design logic: "Troll_Controller:tc0|TrollROM:tROM|Ram0_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 16
        Info (286033): Parameter WIDTHAD_A set to 14
        Info (286033): Parameter NUMWORDS_A set to 16384
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_ACLR_A set to NONE
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter INIT_FILE set to db/project.rom0_TrollROM_31c8eb6.hdl.mif
    Info (276029): Inferred altsyncram megafunction from the following design logic: "CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|Ram0_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 1
        Info (286033): Parameter WIDTHAD_A set to 12
        Info (286033): Parameter NUMWORDS_A set to 4096
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_ACLR_A set to NONE
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter INIT_FILE set to db/project.rom0_CircleROM_68958870.hdl.mif
    Info (276029): Inferred altsyncram megafunction from the following design logic: "CA_Controller:cc0|RAM_256_16:RAMgen[0].OLD|RAM_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 16
        Info (286033): Parameter WIDTHAD_A set to 8
        Info (286033): Parameter NUMWORDS_A set to 256
        Info (286033): Parameter WIDTH_B set to 16
        Info (286033): Parameter WIDTHAD_B set to 8
        Info (286033): Parameter NUMWORDS_B set to 256
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
    Info (276029): Inferred altsyncram megafunction from the following design logic: "CA_Controller:cc0|RAM_256_16:RAMgen[1].OLD|RAM_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 16
        Info (286033): Parameter WIDTHAD_A set to 8
        Info (286033): Parameter NUMWORDS_A set to 256
        Info (286033): Parameter WIDTH_B set to 16
        Info (286033): Parameter WIDTHAD_B set to 8
        Info (286033): Parameter NUMWORDS_B set to 256
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
    Info (276029): Inferred altsyncram megafunction from the following design logic: "CA_Controller:cc0|RAM_256_16:RAMgen[2].OLD|RAM_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 16
        Info (286033): Parameter WIDTHAD_A set to 8
        Info (286033): Parameter NUMWORDS_A set to 256
        Info (286033): Parameter WIDTH_B set to 16
        Info (286033): Parameter WIDTHAD_B set to 8
        Info (286033): Parameter NUMWORDS_B set to 256
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (278001): Inferred 1 megafunctions from design logic
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Troll_Controller:tc0|Mult0"
Info (12130): Elaborated megafunction instantiation "CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0"
Info (12133): Instantiated megafunction "CA_Controller:cc0|RAM_256_16:RAMgen[0].RAM|altsyncram:RAM_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
    Info (12134): Parameter "WIDTH_A" = "16"
    Info (12134): Parameter "WIDTHAD_A" = "8"
    Info (12134): Parameter "NUMWORDS_A" = "256"
    Info (12134): Parameter "WIDTH_B" = "16"
    Info (12134): Parameter "WIDTHAD_B" = "8"
    Info (12134): Parameter "NUMWORDS_B" = "256"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_mrg1.tdf
    Info (12023): Found entity 1: altsyncram_mrg1
Info (12130): Elaborated megafunction instantiation "Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0"
Info (12133): Instantiated megafunction "Troll_Controller:tc0|TrollROM:tROM|altsyncram:Ram0_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "16"
    Info (12134): Parameter "WIDTHAD_A" = "14"
    Info (12134): Parameter "NUMWORDS_A" = "16384"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info (12134): Parameter "INIT_FILE" = "db/project.rom0_TrollROM_31c8eb6.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_l371.tdf
    Info (12023): Found entity 1: altsyncram_l371
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_4oa.tdf
    Info (12023): Found entity 1: decode_4oa
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3kb.tdf
    Info (12023): Found entity 1: mux_3kb
Info (12130): Elaborated megafunction instantiation "CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0"
Info (12133): Instantiated megafunction "CA_Controller:cc0|TempRegion_Controller:trc0|CircleROM:circleROM|altsyncram:Ram0_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "1"
    Info (12134): Parameter "WIDTHAD_A" = "12"
    Info (12134): Parameter "NUMWORDS_A" = "4096"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info (12134): Parameter "INIT_FILE" = "db/project.rom0_CircleROM_68958870.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_6071.tdf
    Info (12023): Found entity 1: altsyncram_6071
Info (12130): Elaborated megafunction instantiation "Troll_Controller:tc0|lpm_mult:Mult0"
Info (12133): Instantiated megafunction "Troll_Controller:tc0|lpm_mult:Mult0" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHA" = "12"
    Info (12134): Parameter "LPM_WIDTHB" = "2"
    Info (12134): Parameter "LPM_WIDTHP" = "14"
    Info (12134): Parameter "LPM_WIDTHR" = "14"
    Info (12134): Parameter "LPM_WIDTHS" = "1"
    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "YES"
    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
Info (12131): Elaborated megafunction instantiation "Troll_Controller:tc0|lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "Troll_Controller:tc0|lpm_mult:Mult0"
Info (12131): Elaborated megafunction instantiation "Troll_Controller:tc0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "Troll_Controller:tc0|lpm_mult:Mult0"
Info (12131): Elaborated megafunction instantiation "Troll_Controller:tc0|lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "Troll_Controller:tc0|lpm_mult:Mult0"
Warning (12241): 7 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13039): The following bidir pins have no drivers
    Warning (13040): Bidir "SD_DAT3" has no driver
    Warning (13040): Bidir "SD_CMD" has no driver
    Warning (13040): Bidir "I2C_SDAT" has no driver
    Warning (13040): Bidir "AUD_ADCLRCK" has no driver
    Warning (13040): Bidir "AUD_DACLRCK" has no driver
    Warning (13040): Bidir "AUD_BCLK" has no driver
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "HEX0[0]" is stuck at VCC
    Warning (13410): Pin "HEX0[1]" is stuck at VCC
    Warning (13410): Pin "HEX0[2]" is stuck at VCC
    Warning (13410): Pin "HEX0[3]" is stuck at VCC
    Warning (13410): Pin "HEX0[4]" is stuck at VCC
    Warning (13410): Pin "HEX0[5]" is stuck at VCC
    Warning (13410): Pin "HEX0[6]" is stuck at VCC
    Warning (13410): Pin "HEX1[0]" is stuck at VCC
    Warning (13410): Pin "HEX1[1]" is stuck at VCC
    Warning (13410): Pin "HEX1[2]" is stuck at VCC
    Warning (13410): Pin "HEX1[3]" is stuck at VCC
    Warning (13410): Pin "HEX1[4]" is stuck at VCC
    Warning (13410): Pin "HEX1[5]" is stuck at VCC
    Warning (13410): Pin "HEX1[6]" is stuck at VCC
    Warning (13410): Pin "HEX2[0]" is stuck at VCC
    Warning (13410): Pin "HEX2[1]" is stuck at VCC
    Warning (13410): Pin "HEX2[2]" is stuck at VCC
    Warning (13410): Pin "HEX2[3]" is stuck at VCC
    Warning (13410): Pin "HEX2[4]" is stuck at VCC
    Warning (13410): Pin "HEX2[5]" is stuck at VCC
    Warning (13410): Pin "HEX2[6]" is stuck at VCC
    Warning (13410): Pin "HEX3[0]" is stuck at VCC
    Warning (13410): Pin "HEX3[1]" is stuck at VCC
    Warning (13410): Pin "HEX3[2]" is stuck at VCC
    Warning (13410): Pin "HEX3[3]" is stuck at VCC
    Warning (13410): Pin "HEX3[4]" is stuck at VCC
    Warning (13410): Pin "HEX3[5]" is stuck at VCC
    Warning (13410): Pin "HEX3[6]" is stuck at VCC
    Warning (13410): Pin "HEX4[0]" is stuck at VCC
    Warning (13410): Pin "HEX4[1]" is stuck at VCC
    Warning (13410): Pin "HEX4[2]" is stuck at VCC
    Warning (13410): Pin "HEX4[3]" is stuck at VCC
    Warning (13410): Pin "HEX4[4]" is stuck at VCC
    Warning (13410): Pin "HEX4[5]" is stuck at VCC
    Warning (13410): Pin "HEX4[6]" is stuck at VCC
    Warning (13410): Pin "HEX5[0]" is stuck at VCC
    Warning (13410): Pin "HEX5[1]" is stuck at VCC
    Warning (13410): Pin "HEX5[2]" is stuck at VCC
    Warning (13410): Pin "HEX5[3]" is stuck at VCC
    Warning (13410): Pin "HEX5[4]" is stuck at VCC
    Warning (13410): Pin "HEX5[5]" is stuck at VCC
    Warning (13410): Pin "HEX5[6]" is stuck at VCC
    Warning (13410): Pin "HEX6[0]" is stuck at VCC
    Warning (13410): Pin "HEX6[1]" is stuck at VCC
    Warning (13410): Pin "HEX6[2]" is stuck at VCC
    Warning (13410): Pin "HEX6[3]" is stuck at VCC
    Warning (13410): Pin "HEX6[4]" is stuck at VCC
    Warning (13410): Pin "HEX6[5]" is stuck at VCC
    Warning (13410): Pin "HEX6[6]" is stuck at VCC
    Warning (13410): Pin "HEX7[0]" is stuck at VCC
    Warning (13410): Pin "HEX7[1]" is stuck at VCC
    Warning (13410): Pin "HEX7[2]" is stuck at VCC
    Warning (13410): Pin "HEX7[3]" is stuck at VCC
    Warning (13410): Pin "HEX7[4]" is stuck at VCC
    Warning (13410): Pin "HEX7[5]" is stuck at VCC
    Warning (13410): Pin "HEX7[6]" is stuck at VCC
    Warning (13410): Pin "LEDG[0]" is stuck at GND
    Warning (13410): Pin "LEDG[1]" is stuck at GND
    Warning (13410): Pin "LEDG[2]" is stuck at GND
    Warning (13410): Pin "LEDG[3]" is stuck at GND
    Warning (13410): Pin "LEDG[4]" is stuck at GND
    Warning (13410): Pin "LEDG[5]" is stuck at GND
    Warning (13410): Pin "LEDG[6]" is stuck at GND
    Warning (13410): Pin "LEDG[7]" is stuck at GND
    Warning (13410): Pin "LEDG[8]" is stuck at GND
    Warning (13410): Pin "LEDR[0]" is stuck at GND
    Warning (13410): Pin "LEDR[1]" is stuck at GND
    Warning (13410): Pin "LEDR[2]" is stuck at GND
    Warning (13410): Pin "LEDR[3]" is stuck at GND
    Warning (13410): Pin "LEDR[4]" is stuck at GND
    Warning (13410): Pin "LEDR[5]" is stuck at GND
    Warning (13410): Pin "LEDR[6]" is stuck at GND
    Warning (13410): Pin "LEDR[7]" is stuck at GND
    Warning (13410): Pin "LEDR[8]" is stuck at GND
    Warning (13410): Pin "LEDR[9]" is stuck at GND
    Warning (13410): Pin "LEDR[10]" is stuck at GND
    Warning (13410): Pin "LEDR[11]" is stuck at GND
    Warning (13410): Pin "LEDR[12]" is stuck at GND
    Warning (13410): Pin "LEDR[13]" is stuck at GND
    Warning (13410): Pin "LEDR[14]" is stuck at GND
    Warning (13410): Pin "LEDR[15]" is stuck at GND
    Warning (13410): Pin "LEDR[16]" is stuck at GND
    Warning (13410): Pin "LEDR[17]" is stuck at GND
    Warning (13410): Pin "UART_TXD" is stuck at GND
    Warning (13410): Pin "IRDA_TXD" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[0]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[1]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[2]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[3]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[4]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[5]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[6]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[7]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[8]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[9]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[10]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[11]" is stuck at GND
    Warning (13410): Pin "DRAM_LDQM" is stuck at GND
    Warning (13410): Pin "DRAM_UDQM" is stuck at GND
    Warning (13410): Pin "DRAM_WE_N" is stuck at VCC
    Warning (13410): Pin "DRAM_CAS_N" is stuck at VCC
    Warning (13410): Pin "DRAM_RAS_N" is stuck at VCC
    Warning (13410): Pin "DRAM_CS_N" is stuck at VCC
    Warning (13410): Pin "DRAM_BA_0" is stuck at GND
    Warning (13410): Pin "DRAM_BA_1" is stuck at GND
    Warning (13410): Pin "DRAM_CLK" is stuck at GND
    Warning (13410): Pin "DRAM_CKE" is stuck at GND
    Warning (13410): Pin "FL_ADDR[0]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[1]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[2]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[3]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[4]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[5]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[6]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[7]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[8]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[9]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[10]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[11]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[12]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[13]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[14]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[15]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[16]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[17]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[18]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[19]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[20]" is stuck at GND
    Warning (13410): Pin "FL_ADDR[21]" is stuck at GND
    Warning (13410): Pin "FL_WE_N" is stuck at VCC
    Warning (13410): Pin "FL_RST_N" is stuck at VCC
    Warning (13410): Pin "FL_OE_N" is stuck at VCC
    Warning (13410): Pin "FL_CE_N" is stuck at VCC
    Warning (13410): Pin "SRAM_UB_N" is stuck at GND
    Warning (13410): Pin "SRAM_LB_N" is stuck at GND
    Warning (13410): Pin "SRAM_CE_N" is stuck at GND
    Warning (13410): Pin "SRAM_OE_N" is stuck at GND
    Warning (13410): Pin "OTG_ADDR[0]" is stuck at GND
    Warning (13410): Pin "OTG_ADDR[1]" is stuck at GND
    Warning (13410): Pin "OTG_CS_N" is stuck at VCC
    Warning (13410): Pin "OTG_RD_N" is stuck at VCC
    Warning (13410): Pin "OTG_WR_N" is stuck at VCC
    Warning (13410): Pin "OTG_RST_N" is stuck at VCC
    Warning (13410): Pin "OTG_FSPEED" is stuck at VCC
    Warning (13410): Pin "OTG_LSPEED" is stuck at VCC
    Warning (13410): Pin "OTG_DACK0_N" is stuck at VCC
    Warning (13410): Pin "OTG_DACK1_N" is stuck at VCC
    Warning (13410): Pin "LCD_ON" is stuck at GND
    Warning (13410): Pin "LCD_BLON" is stuck at GND
    Warning (13410): Pin "LCD_RW" is stuck at GND
    Warning (13410): Pin "LCD_EN" is stuck at GND
    Warning (13410): Pin "LCD_RS" is stuck at GND
    Warning (13410): Pin "SD_CLK" is stuck at GND
    Warning (13410): Pin "I2C_SCLK" is stuck at GND
    Warning (13410): Pin "TDO" is stuck at GND
    Warning (13410): Pin "VGA_SYNC" is stuck at GND
    Warning (13410): Pin "VGA_R[0]" is stuck at GND
    Warning (13410): Pin "VGA_R[1]" is stuck at GND
    Warning (13410): Pin "VGA_G[0]" is stuck at GND
    Warning (13410): Pin "VGA_G[1]" is stuck at GND
    Warning (13410): Pin "VGA_B[0]" is stuck at GND
    Warning (13410): Pin "VGA_B[1]" is stuck at GND
    Warning (13410): Pin "ENET_CMD" is stuck at GND
    Warning (13410): Pin "ENET_CS_N" is stuck at VCC
    Warning (13410): Pin "ENET_WR_N" is stuck at VCC
    Warning (13410): Pin "ENET_RD_N" is stuck at VCC
    Warning (13410): Pin "ENET_RST_N" is stuck at VCC
    Warning (13410): Pin "ENET_CLK" is stuck at GND
    Warning (13410): Pin "AUD_DACDAT" is stuck at GND
    Warning (13410): Pin "AUD_XCK" is stuck at GND
    Warning (13410): Pin "TD_RESET" is stuck at VCC
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 25 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLOCK_50"
    Warning (15610): No output dependent on input pin "EXT_CLOCK"
    Warning (15610): No output dependent on input pin "SW[7]"
    Warning (15610): No output dependent on input pin "SW[12]"
    Warning (15610): No output dependent on input pin "UART_RXD"
    Warning (15610): No output dependent on input pin "IRDA_RXD"
    Warning (15610): No output dependent on input pin "OTG_INT0"
    Warning (15610): No output dependent on input pin "OTG_INT1"
    Warning (15610): No output dependent on input pin "OTG_DREQ0"
    Warning (15610): No output dependent on input pin "OTG_DREQ1"
    Warning (15610): No output dependent on input pin "TDI"
    Warning (15610): No output dependent on input pin "TCK"
    Warning (15610): No output dependent on input pin "TCS"
    Warning (15610): No output dependent on input pin "ENET_INT"
    Warning (15610): No output dependent on input pin "AUD_ADCDAT"
    Warning (15610): No output dependent on input pin "TD_DATA[0]"
    Warning (15610): No output dependent on input pin "TD_DATA[1]"
    Warning (15610): No output dependent on input pin "TD_DATA[2]"
    Warning (15610): No output dependent on input pin "TD_DATA[3]"
    Warning (15610): No output dependent on input pin "TD_DATA[4]"
    Warning (15610): No output dependent on input pin "TD_DATA[5]"
    Warning (15610): No output dependent on input pin "TD_DATA[6]"
    Warning (15610): No output dependent on input pin "TD_DATA[7]"
    Warning (15610): No output dependent on input pin "TD_HS"
    Warning (15610): No output dependent on input pin "TD_VS"
Info (21057): Implemented 4305 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 48 input pins
    Info (21059): Implemented 218 output pins
    Info (21060): Implemented 159 bidirectional pins
    Info (21061): Implemented 3718 logic cells
    Info (21064): Implemented 161 RAM segments
    Info (21065): Implemented 1 PLLs
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 207 warnings
    Info: Peak virtual memory: 399 megabytes
    Info: Processing ended: Sun May 15 01:05:42 2016
    Info: Elapsed time: 00:01:09
    Info: Total CPU time (on all processors): 00:00:25


