| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| tc0|tROM |
15 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tc0 |
25 |
0 |
4 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ic0 |
37 |
0 |
6 |
0 |
44 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| kc0|scte |
64 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| kc0|PS2_SCR |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| kc0 |
4 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|trc0|pu0 |
94 |
0 |
4 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|trc0|circleROM |
13 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|trc0 |
174 |
0 |
0 |
0 |
144 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|RAMgen[2].OLD |
26 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|RAMgen[2].RAM |
26 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|RAMgen[1].OLD |
26 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|RAMgen[1].RAM |
26 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|RAMgen[0].OLD |
26 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0|RAMgen[0].RAM |
26 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cc0 |
69 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sc0 |
76 |
4 |
2 |
4 |
43 |
4 |
4 |
4 |
16 |
0 |
0 |
0 |
0 |
| cs0|colorROM |
5 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| cs0 |
54 |
6 |
3 |
6 |
30 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u1 |
32 |
2 |
0 |
2 |
80 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| rng0 |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| r0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p1 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |