Project Information                 c:\projects\hcs03\hardware\hcs03ioglue.rpt

MAX+plus II Compiler Report File
Version 9.6 3/22/2000
Compiled: 01/02/2003 16:53:28

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

hcs03ioglue
      EPM7064SLC44-10      7        5        16     23      0           35 %

User Pins:                 7        5        16 



Project Information                 c:\projects\hcs03\hardware\hcs03ioglue.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

hcs03ioglue@8                     A0
hcs03ioglue@9                     A1
hcs03ioglue@11                    A2
hcs03ioglue@12                    A3
hcs03ioglue@39                    DB0
hcs03ioglue@37                    DB1
hcs03ioglue@36                    DB2
hcs03ioglue@34                    DB3
hcs03ioglue@33                    DB4
hcs03ioglue@31                    DB5
hcs03ioglue@29                    DB6
hcs03ioglue@28                    DB7
hcs03ioglue@18                    D0
hcs03ioglue@19                    D1
hcs03ioglue@20                    D2
hcs03ioglue@21                    D3
hcs03ioglue@24                    D4
hcs03ioglue@25                    D5
hcs03ioglue@26                    D6
hcs03ioglue@27                    D7
hcs03ioglue@41                    nCLKkeyscan
hcs03ioglue@6                     nCLKrelline
hcs03ioglue@5                     nCLKrelplane
hcs03ioglue@4                     nOEkeyrethigh
hcs03ioglue@40                    nOEkeyretlow
hcs03ioglue@17                    nPCE0
hcs03ioglue@16                    nRD
hcs03ioglue@14                    nWR


Project Information                 c:\projects\hcs03\hardware\hcs03ioglue.rpt

** FILE HIERARCHY **



|16ndmux:50|


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

***** Logic for device 'hcs03ioglue' compiled without errors.




Device: EPM7064SLC44-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff

                         n                          
                      n  O                       n  
                   n  C  E                    n  O  
                   C  L  k                    C  E  
                   L  K  e                    L  k  
                   K  r  y                    K  e  
                   r  e  r                    k  y  
                   e  l  e                    e  r  
                   l  p  t                    y  e  
                   l  l  h                    s  t  
                   i  a  i  V  G  G  G  G  G  c  l  
                   n  n  g  C  N  N  N  N  N  a  o  
                   e  e  h  C  D  D  D  D  D  n  w  
                 -----------------------------------_ 
               /   6  5  4  3  2  1 44 43 42 41 40   | 
         #TDI |  7                                39 | DB0 
           A0 |  8                                38 | #TDO 
           A1 |  9                                37 | DB1 
          GND | 10                                36 | DB2 
           A2 | 11                                35 | VCC 
           A3 | 12        EPM7064SLC44-10         34 | DB3 
         #TMS | 13                                33 | DB4 
          nWR | 14                                32 | #TCK 
          VCC | 15                                31 | DB5 
          nRD | 16                                30 | GND 
        nPCE0 | 17                                29 | DB6 
              |_  18 19 20 21 22 23 24 25 26 27 28  _| 
                ------------------------------------ 
                   D  D  D  D  G  V  D  D  D  D  D  
                   0  1  2  3  N  C  4  5  6  7  B  
                               D  C              7  
                                                    
                                                    
                                                    
                                                    
                                                    
                                                    
                                                    
                                                    
                                                    
                                                    


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     5/16( 31%)   8/ 8(100%)   0/16(  0%)   7/36( 19%) 
B:    LC17 - LC32     4/16( 25%)   8/ 8(100%)   0/16(  0%)   4/36( 11%) 
C:    LC33 - LC48     7/16( 43%)   8/ 8(100%)   0/16(  0%)   7/36( 19%) 
D:    LC49 - LC64     7/16( 43%)   8/ 8(100%)   0/16(  0%)  12/36( 33%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            32/32     (100%)
Total logic cells used:                         23/64     ( 35%)
Total shareable expanders used:                  0/64     (  0%)
Total Turbo logic cells used:                   23/64     ( 35%)
Total shareable expanders not available (n/a):   0/64     (  0%)
Average fan-in:                                  2.86
Total fan-in:                                    66

Total input pins required:                       7
Total fast input logic cells required:           0
Total output pins required:                      5
Total bidirectional pins required:              16
Total reserved pins required                     4
Total logic cells required:                     23
Total flipflops required:                        0
Total product terms required:                   23
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         2/  64   (  3%)



Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   8    (5)  (A)      INPUT               0      0   0    0    0    5    0  A0
   9    (4)  (A)      INPUT               0      0   0    0    0    5    0  A1
  11    (3)  (A)      INPUT               0      0   0    0    0    5    0  A2
  12    (1)  (A)      INPUT               0      0   0    0    0    5    0  A3
  39     57    D      BIDIR               0      0   0    0    1    1    0  DB0
  37     53    D      BIDIR               0      0   0    0    1    1    0  DB1
  36     52    D      BIDIR               0      0   0    0    1    1    0  DB2
  34     51    D      BIDIR               0      0   0    0    1    1    0  DB3
  33     49    D      BIDIR               0      0   0    0    1    1    0  DB4
  31     46    C      BIDIR               0      0   0    0    1    1    0  DB5
  29     41    C      BIDIR               0      0   0    0    1    1    0  DB6
  28     40    C      BIDIR               0      0   0    0    1    1    0  DB7
  18     21    B      BIDIR               0      0   0    0    1    1    0  D0
  19     20    B      BIDIR               0      0   0    0    1    1    0  D1
  20     19    B      BIDIR               0      0   0    0    1    1    0  D2
  21     17    B      BIDIR               0      0   0    0    1    1    0  D3
  24     33    C      BIDIR               0      0   0    0    1    1    0  D4
  25     35    C      BIDIR               0      0   0    0    1    1    0  D5
  26     36    C      BIDIR               0      0   0    0    1    1    0  D6
  27     37    C      BIDIR               0      0   0    0    1    1    0  D7
  17   (24)  (B)      INPUT               0      0   0    0    0    5    2  nPCE0
  16   (25)  (B)      INPUT               0      0   0    0    0    2    1  nRD
  14   (30)  (B)      INPUT               0      0   0    0    0    3    1  nWR


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  39     57    D        TRI      t        0      0   0    0    1    1    0  DB0
  37     53    D        TRI      t        0      0   0    0    1    1    0  DB1
  36     52    D        TRI      t        0      0   0    0    1    1    0  DB2
  34     51    D        TRI      t        0      0   0    0    1    1    0  DB3
  33     49    D        TRI      t        0      0   0    0    1    1    0  DB4
  31     46    C        TRI      t        0      0   0    0    1    1    0  DB5
  29     41    C        TRI      t        0      0   0    0    1    1    0  DB6
  28     40    C        TRI      t        0      0   0    0    1    1    0  DB7
  18     21    B        TRI      t        0      0   0    0    1    1    0  D0
  19     20    B        TRI      t        0      0   0    0    1    1    0  D1
  20     19    B        TRI      t        0      0   0    0    1    1    0  D2
  21     17    B        TRI      t        0      0   0    0    1    1    0  D3
  24     33    C        TRI      t        0      0   0    0    1    1    0  D4
  25     35    C        TRI      t        0      0   0    0    1    1    0  D5
  26     36    C        TRI      t        0      0   0    0    1    1    0  D6
  27     37    C        TRI      t        0      0   0    0    1    1    0  D7
  41     64    D     OUTPUT      t        0      0   0    6    0    0    0  nCLKkeyscan
   6     11    A     OUTPUT      t        0      0   0    6    0    0    0  nCLKrelline
   5     14    A     OUTPUT      t        0      0   0    6    0    0    0  nCLKrelplane
   4     16    A     OUTPUT      t        0      0   0    6    0    0    0  nOEkeyrethigh
  40     62    D     OUTPUT      t        0      0   0    6    0    0    0  nOEkeyretlow


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (12)     1    A       SOFT    s t        0      0   0    2    0    0    0  DB7~1
  (9)     4    A       SOFT    s t        0      0   0    2    0    0    0  D7~1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                   Logic cells placed in LAB 'A'
        +--------- LC1 DB7~1
        | +------- LC4 D7~1
        | | +----- LC11 nCLKrelline
        | | | +--- LC14 nCLKrelplane
        | | | | +- LC16 nOEkeyrethigh
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'A'
LC      | | | | | | A B C D |     Logic cells that feed LAB 'A':

Pin
8    -> - - * * * | * - - * | <-- A0
9    -> - - * * * | * - - * | <-- A1
11   -> - - * * * | * - - * | <-- A2
12   -> - - * * * | * - - * | <-- A3
17   -> * * * * * | * - - * | <-- nPCE0
16   -> - * - - * | * - - * | <-- nRD
14   -> * - * * - | * - - * | <-- nWR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                 Logic cells placed in LAB 'B'
        +------- LC21 D0
        | +----- LC20 D1
        | | +--- LC19 D2
        | | | +- LC17 D3
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'B'
LC      | | | | | A B C D |     Logic cells that feed LAB 'B':

Pin
LC57 -> * - - - | - * - - | <-- DB0
LC53 -> - * - - | - * - - | <-- DB1
LC52 -> - - * - | - * - - | <-- DB2
LC51 -> - - - * | - * - - | <-- DB3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                       Logic cells placed in LAB 'C'
        +------------- LC46 DB5
        | +----------- LC41 DB6
        | | +--------- LC40 DB7
        | | | +------- LC33 D4
        | | | | +----- LC35 D5
        | | | | | +--- LC36 D6
        | | | | | | +- LC37 D7
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC46 -> - - - - * - - | - - * - | <-- DB5
LC41 -> - - - - - * - | - - * - | <-- DB6
LC40 -> - - - - - - * | - - * - | <-- DB7
LC35 -> * - - - - - - | - - * - | <-- D5
LC36 -> - * - - - - - | - - * - | <-- D6
LC37 -> - - * - - - - | - - * - | <-- D7

Pin
LC49 -> - - - * - - - | - - * - | <-- DB4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                       Logic cells placed in LAB 'D'
        +------------- LC57 DB0
        | +----------- LC53 DB1
        | | +--------- LC52 DB2
        | | | +------- LC51 DB3
        | | | | +----- LC49 DB4
        | | | | | +--- LC64 nCLKkeyscan
        | | | | | | +- LC62 nOEkeyretlow
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | A B C D |     Logic cells that feed LAB 'D':

Pin
8    -> - - - - - * * | * - - * | <-- A0
9    -> - - - - - * * | * - - * | <-- A1
11   -> - - - - - * * | * - - * | <-- A2
12   -> - - - - - * * | * - - * | <-- A3
17   -> - - - - - * * | * - - * | <-- nPCE0
16   -> - - - - - - * | * - - * | <-- nRD
14   -> - - - - - * - | * - - * | <-- nWR
LC21 -> * - - - - - - | - - - * | <-- D0
LC20 -> - * - - - - - | - - - * | <-- D1
LC19 -> - - * - - - - | - - - * | <-- D2
LC17 -> - - - * - - - | - - - * | <-- D3
LC33 -> - - - - * - - | - - - * | <-- D4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:        c:\projects\hcs03\hardware\hcs03ioglue.rpt
hcs03ioglue

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
nPCE0    : INPUT;
nRD      : INPUT;
nWR      : INPUT;

-- Node name is 'DB0' 
-- Equation name is 'DB0', location is LC057, type is bidir.
DB0      = TRI(_LC057,  _LC001);
_LC057   = LCELL( D0 $  GND);

-- Node name is 'DB1' 
-- Equation name is 'DB1', location is LC053, type is bidir.
DB1      = TRI(_LC053,  _LC001);
_LC053   = LCELL( D1 $  GND);

-- Node name is 'DB2' 
-- Equation name is 'DB2', location is LC052, type is bidir.
DB2      = TRI(_LC052,  _LC001);
_LC052   = LCELL( D2 $  GND);

-- Node name is 'DB3' 
-- Equation name is 'DB3', location is LC051, type is bidir.
DB3      = TRI(_LC051,  _LC001);
_LC051   = LCELL( D3 $  GND);

-- Node name is 'DB4' 
-- Equation name is 'DB4', location is LC049, type is bidir.
DB4      = TRI(_LC049,  _LC001);
_LC049   = LCELL( D4 $  GND);

-- Node name is 'DB5' 
-- Equation name is 'DB5', location is LC046, type is bidir.
DB5      = TRI(_LC046,  _LC001);
_LC046   = LCELL( D5 $  GND);

-- Node name is 'DB6' 
-- Equation name is 'DB6', location is LC041, type is bidir.
DB6      = TRI(_LC041,  _LC001);
_LC041   = LCELL( D6 $  GND);

-- Node name is 'DB7~1' 
-- Equation name is 'DB7~1', location is LC001, type is buried.
-- synthesized logic cell 
_LC001   = LCELL( _EQ001 $  GND);
  _EQ001 = !nPCE0 & !nWR;

-- Node name is 'DB7' 
-- Equation name is 'DB7', location is LC040, type is bidir.
DB7      = TRI(_LC040,  _LC001);
_LC040   = LCELL( D7 $  GND);

-- Node name is 'D0' 
-- Equation name is 'D0', location is LC021, type is bidir.
D0       = TRI(_LC021,  _LC004);
_LC021   = LCELL( DB0 $  GND);

-- Node name is 'D1' 
-- Equation name is 'D1', location is LC020, type is bidir.
D1       = TRI(_LC020,  _LC004);
_LC020   = LCELL( DB1 $  GND);

-- Node name is 'D2' 
-- Equation name is 'D2', location is LC019, type is bidir.
D2       = TRI(_LC019,  _LC004);
_LC019   = LCELL( DB2 $  GND);

-- Node name is 'D3' 
-- Equation name is 'D3', location is LC017, type is bidir.
D3       = TRI(_LC017,  _LC004);
_LC017   = LCELL( DB3 $  GND);

-- Node name is 'D4' 
-- Equation name is 'D4', location is LC033, type is bidir.
D4       = TRI(_LC033,  _LC004);
_LC033   = LCELL( DB4 $  GND);

-- Node name is 'D5' 
-- Equation name is 'D5', location is LC035, type is bidir.
D5       = TRI(_LC035,  _LC004);
_LC035   = LCELL( DB5 $  GND);

-- Node name is 'D6' 
-- Equation name is 'D6', location is LC036, type is bidir.
D6       = TRI(_LC036,  _LC004);
_LC036   = LCELL( DB6 $  GND);

-- Node name is 'D7~1' 
-- Equation name is 'D7~1', location is LC004, type is buried.
-- synthesized logic cell 
_LC004   = LCELL( _EQ002 $  GND);
  _EQ002 = !nPCE0 & !nRD;

-- Node name is 'D7' 
-- Equation name is 'D7', location is LC037, type is bidir.
D7       = TRI(_LC037,  _LC004);
_LC037   = LCELL( DB7 $  GND);

-- Node name is 'nCLKkeyscan' 
-- Equation name is 'nCLKkeyscan', location is LC064, type is output.
 nCLKkeyscan = LCELL( _EQ003 $  VCC);
  _EQ003 = !A0 &  A1 & !A2 & !A3 & !nPCE0 & !nWR;

-- Node name is 'nCLKrelline' 
-- Equation name is 'nCLKrelline', location is LC011, type is output.
 nCLKrelline = LCELL( _EQ004 $  VCC);
  _EQ004 = !A0 & !A1 & !A2 & !A3 & !nPCE0 & !nWR;

-- Node name is 'nCLKrelplane' 
-- Equation name is 'nCLKrelplane', location is LC014, type is output.
 nCLKrelplane = LCELL( _EQ005 $  VCC);
  _EQ005 =  A0 & !A1 & !A2 & !A3 & !nPCE0 & !nWR;

-- Node name is 'nOEkeyrethigh' 
-- Equation name is 'nOEkeyrethigh', location is LC016, type is output.
 nOEkeyrethigh = LCELL( _EQ006 $  VCC);
  _EQ006 =  A0 &  A1 & !A2 & !A3 & !nPCE0 & !nRD;

-- Node name is 'nOEkeyretlow' 
-- Equation name is 'nOEkeyretlow', location is LC062, type is output.
 nOEkeyretlow = LCELL( _EQ007 $  VCC);
  _EQ007 = !A0 &  A1 & !A2 & !A3 & !nPCE0 & !nRD;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                 c:\projects\hcs03\hardware\hcs03ioglue.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,850K
