nios

2012.05.04.09:30:44 Datasheet
Overview
  clk_0  nios
   spi_touch
 MISO  
 MOSI  
 SCLK  
 SS_n  
 MISO  
 MOSI  
 SCLK  
 SS_n  
   lcd_cs
 out_port  
 out_port  
 out_port  
 in_port  
 out_port  
Processor
   cpu Nios II 11.0
All Components
   cpu altera_nios2 11.0
   sysid altera_avalon_sysid 11.0
   rom altera_avalon_onchip_memory2 11.0
   ram altera_avalon_onchip_memory2 11.0
   spi_touch altera_avalon_spi 11.0
   spi_lcd22 altera_avalon_spi 11.0
   lcd_cs altera_avalon_pio 11.0
   touch_cs altera_avalon_pio 11.0
   lcd_rs altera_avalon_pio 11.0
   touch_irq altera_avalon_pio 11.0
   reset altera_avalon_pio 11.0
Memory Map
cpu
 instruction_master  data_master
  cpu
jtag_debug_module  0x00000000 0x00000000
  sysid
control_slave  0x00000890
  rom
s1  0x00018000 0x00018000
  ram
s1  0x00010000 0x00010000
  spi_touch
spi_control_port  0x00000800
  spi_lcd22
spi_control_port  0x00000820
  lcd_cs
s1  0x00000840
  touch_cs
s1  0x00000850
  lcd_rs
s1  0x00000860
  touch_irq
s1  0x00000870
  reset
s1  0x00000880

clk_0

clock_source v11.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2 v11.0
clk_0 clk   cpu
  clk
data_master   sysid
  control_slave
instruction_master   rom
  s1
data_master  
  s1
instruction_master   ram
  s1
data_master  
  s1
data_master   spi_touch
  spi_control_port
d_irq  
  irq
data_master   spi_lcd22
  spi_control_port
d_irq  
  irq
data_master   lcd_cs
  s1
data_master   touch_cs
  s1
data_master   lcd_rs
  s1
data_master   touch_irq
  s1
data_master   reset
  s1


Parameters

userDefinedSettings
tightlyCoupledInstructionMaster3MapParam
tightlyCoupledInstructionMaster3AddrWidth 1
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledDataMaster3MapParam
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster0AddrWidth 1
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave rom.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
internalIrqMaskSystemInfo 3
instSlaveMapParam <address-map><slave name='cpu.jtag_debug_module' start='0x0' end='0x800' /><slave name='ram.s1' start='0x10000' end='0x16890' /><slave name='rom.s1' start='0x18000' end='0x1BCB0' /></address-map>
instAddrWidth 17
impl Fast
icache_size _2048
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave rom.s1
exceptionOffset 32
deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
deviceFamilyName Cyclone III
debug_triggerArming true
debug_level Level2
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _0
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
dataSlaveMapParam <address-map><slave name='cpu.jtag_debug_module' start='0x0' end='0x800' /><slave name='spi_touch.spi_control_port' start='0x800' end='0x820' /><slave name='spi_lcd22.spi_control_port' start='0x820' end='0x840' /><slave name='lcd_cs.s1' start='0x840' end='0x850' /><slave name='touch_cs.s1' start='0x850' end='0x860' /><slave name='lcd_rs.s1' start='0x860' end='0x870' /><slave name='touch_irq.s1' start='0x870' end='0x880' /><slave name='reset.s1' start='0x880' end='0x890' /><slave name='sysid.control_slave' start='0x890' end='0x898' /><slave name='ram.s1' start='0x10000' end='0x16890' /><slave name='rom.s1' start='0x18000' end='0x1BCB0' /></address-map>
dataAddrWidth 17
customInstSlavesSystemInfo <info/>
cpuReset false
cpuID 0
clockFrequency 50000000
breakSlave cpu.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 50000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 2048
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x18020
RESET_ADDR 0x18000
BREAK_ADDR 0x20
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 17
DATA_ADDR_WIDTH 17
NUM_OF_SHADOW_REG_SETS 0

sysid

altera_avalon_sysid v11.0
clk_0 clk   sysid
  clk
cpu data_master  
  control_slave


Parameters

id 0
timestamp 1336095042
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 0u
TIMESTAMP 1336095042u

rom

altera_avalon_onchip_memory2 v11.0
clk_0 clk   rom
  clk1
cpu instruction_master  
  s1
data_master  
  s1


Parameters

allowInSystemMemoryContentEditor false
autoInitializationFileName rom
blockType AUTO
dataWidth 32
deviceFamily Cyclone III
dualPort false
initMemContent true
initializationFileName rom
instanceID NONE
memorySize 15536
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable false
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "rom"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 0
DUAL_PORT 0
SINGLE_CLOCK_OP 0
SIZE_VALUE 15536u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

ram

altera_avalon_onchip_memory2 v11.0
clk_0 clk   ram
  clk1
cpu instruction_master  
  s1
data_master  
  s1


Parameters

allowInSystemMemoryContentEditor false
autoInitializationFileName ram
blockType AUTO
dataWidth 32
deviceFamily Cyclone III
dualPort false
initMemContent true
initializationFileName ram
instanceID NONE
memorySize 26768
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "ram"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SINGLE_CLOCK_OP 0
SIZE_VALUE 26768u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

spi_touch

altera_avalon_spi v11.0
clk_0 clk   spi_touch
  clk
cpu data_master  
  spi_control_port
d_irq  
  irq


Parameters

actualClockRate 500000.0
actualSlaveSelectToSClkDelay 0.0
clockPhase 0
clockPolarity 0
dataWidth 8
disableAvalonFlowControl false
inputClockRate 50000000
insertDelayBetweenSlaveSelectAndSClk false
insertSync false
lsbOrderedFirst false
masterSPI true
numberOfSlaves 1
syncRegDepth 2
targetClockRate 500000
targetSlaveSelectToSClkDelay 0.0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DATABITS 8
DATAWIDTH 16
TARGETCLOCK 500000u
CLOCKUNITS "Hz"
CLOCKMULT 1
NUMSLAVES 1
ISMASTER 1
CLOCKPOLARITY 0
CLOCKPHASE 0
LSBFIRST 0
EXTRADELAY 0
INSERT_SYNC 0
SYNC_REG_DEPTH 2
TARGETSSDELAY "0.0"
DELAYUNITS "ns"
DELAYMULT "1.0E-9"
PREFIX "spi_"

spi_lcd22

altera_avalon_spi v11.0
clk_0 clk   spi_lcd22
  clk
cpu data_master  
  spi_control_port
d_irq  
  irq


Parameters

actualClockRate 5000000.0
actualSlaveSelectToSClkDelay 0.0
clockPhase 0
clockPolarity 0
dataWidth 8
disableAvalonFlowControl false
inputClockRate 50000000
insertDelayBetweenSlaveSelectAndSClk false
insertSync false
lsbOrderedFirst false
masterSPI true
numberOfSlaves 1
syncRegDepth 2
targetClockRate 5000000
targetSlaveSelectToSClkDelay 0.0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DATABITS 8
DATAWIDTH 16
TARGETCLOCK 5000000u
CLOCKUNITS "Hz"
CLOCKMULT 1
NUMSLAVES 1
ISMASTER 1
CLOCKPOLARITY 0
CLOCKPHASE 0
LSBFIRST 0
EXTRADELAY 0
INSERT_SYNC 0
SYNC_REG_DEPTH 2
TARGETSSDELAY "0.0"
DELAYUNITS "ns"
DELAYMULT "1.0E-9"
PREFIX "spi_"

lcd_cs

altera_avalon_pio v11.0
clk_0 clk   lcd_cs
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

touch_cs

altera_avalon_pio v11.0
clk_0 clk   touch_cs
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

lcd_rs

altera_avalon_pio v11.0
clk_0 clk   lcd_rs
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

touch_irq

altera_avalon_pio v11.0
cpu data_master   touch_irq
  s1
clk_0 clk  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

reset

altera_avalon_pio v11.0
clk_0 clk   reset
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u
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