Partition Merge report for nios
Thu May 03 17:33:19 2012
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Partition Merge Summary
  3. Partition Merge Netlist Types Used
  4. Partition Merge Partition Statistics
  5. Partition Merge Partition Pin Processing
  6. Partition Merge Resource Usage Summary
  7. Partition Merge RAM Summary
  8. Partition Merge DSP Block Usage Summary
  9. Partition Merge Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Partition Merge Summary                                                        ;
+------------------------------------+-------------------------------------------+
; Partition Merge Status             ; Successful - Thu May 03 17:33:19 2012     ;
; Quartus II Version                 ; 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name                      ; nios                                      ;
; Top-level Entity Name              ; nios                                      ;
; Family                             ; Cyclone III                               ;
; Total logic elements               ; 2,418                                     ;
;     Total combinational functions  ; 2,010                                     ;
;     Dedicated logic registers      ; 1,394                                     ;
; Total registers                    ; 1394                                      ;
; Total pins                         ; 10                                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 403,328                                   ;
; Embedded Multiplier 9-bit elements ; 4                                         ;
; Total PLLs                         ; 0                                         ;
+------------------------------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge Netlist Types Used                                                                                            ;
+--------------------------------+----------------+-------------------+------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Netlist Type Requested ; Partition Contents             ;
+--------------------------------+----------------+-------------------+------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; Post-Fit               ;                                ;
; sld_hub:auto_hub               ; Auto-generated ; Post-Synthesis    ; Post-Synthesis         ; sld_hub:auto_hub               ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; Source File            ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+------------------------+--------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Partition Merge Partition Statistics                                                                     ;
+---------------------------------------------+--------+------------------+--------------------------------+
; Statistic                                   ; Top    ; sld_hub:auto_hub ; hard_block:auto_generated_inst ;
+---------------------------------------------+--------+------------------+--------------------------------+
; Estimated Total logic elements              ; 2316   ; 102              ; 0                              ;
;                                             ;        ;                  ;                                ;
; Total combinational functions               ; 1918   ; 92               ; 0                              ;
; Logic element usage by number of LUT inputs ;        ;                  ;                                ;
;     -- 4 input functions                    ; 979    ; 40               ; 0                              ;
;     -- 3 input functions                    ; 728    ; 29               ; 0                              ;
;     -- <=2 input functions                  ; 211    ; 23               ; 0                              ;
;                                             ;        ;                  ;                                ;
; Logic elements by mode                      ;        ;                  ;                                ;
;     -- normal mode                          ; 1798   ; 88               ; 0                              ;
;     -- arithmetic mode                      ; 120    ; 4                ; 0                              ;
;                                             ;        ;                  ;                                ;
; Total registers                             ; 1333   ; 61               ; 0                              ;
;     -- Dedicated logic registers            ; 1333   ; 61               ; 0                              ;
;     -- I/O registers                        ; 0      ; 0                ; 0                              ;
;                                             ;        ;                  ;                                ;
; Virtual pins                                ; 0      ; 0                ; 0                              ;
; I/O pins                                    ; 10     ; 0                ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 4      ; 0                ; 0                              ;
; Total memory bits                           ; 403328 ; 0                ; 0                              ;
; Total RAM block bits                        ; 0      ; 0                ; 0                              ;
; JTAG                                        ; 1      ; 0                ; 0                              ;
;                                             ;        ;                  ;                                ;
; Connections                                 ;        ;                  ;                                ;
;     -- Input Connections                    ; 148    ; 95               ; 0                              ;
;     -- Registered Input Connections         ; 49     ; 70               ; 0                              ;
;     -- Output Connections                   ; 154    ; 89               ; 0                              ;
;     -- Registered Output Connections        ; 3      ; 88               ; 0                              ;
;                                             ;        ;                  ;                                ;
; Internal Connections                        ;        ;                  ;                                ;
;     -- Total Connections                    ; 16613  ; 580              ; 0                              ;
;     -- Registered Connections               ; 6716   ; 424              ; 0                              ;
;                                             ;        ;                  ;                                ;
; External Connections                        ;        ;                  ;                                ;
;     -- Top                                  ; 118    ; 184              ; 0                              ;
;     -- sld_hub:auto_hub                     ; 184    ; 0                ; 0                              ;
;     -- hard_block:auto_generated_inst       ; 0      ; 0                ; 0                              ;
;                                             ;        ;                  ;                                ;
; Partition Interface                         ;        ;                  ;                                ;
;     -- Input Ports                          ; 29     ; 14               ; 0                              ;
;     -- Output Ports                         ; 4      ; 32               ; 0                              ;
;     -- Bidir Ports                          ; 8      ; 0                ; 0                              ;
;                                             ;        ;                  ;                                ;
; Registered Ports                            ;        ;                  ;                                ;
;     -- Registered Input Ports               ; 0      ; 4                ; 0                              ;
;     -- Registered Output Ports              ; 0      ; 22               ; 0                              ;
;                                             ;        ;                  ;                                ;
; Port Connectivity                           ;        ;                  ;                                ;
;     -- Input Ports driven by GND            ; 0      ; 3                ; 0                              ;
;     -- Output Ports driven by GND           ; 0      ; 0                ; 0                              ;
;     -- Input Ports driven by VCC            ; 0      ; 0                ; 0                              ;
;     -- Output Ports driven by VCC           ; 0      ; 0                ; 0                              ;
;     -- Input Ports with no Source           ; 0      ; 0                ; 0                              ;
;     -- Output Ports with no Source          ; 0      ; 0                ; 0                              ;
;     -- Input Ports with no Fanout           ; 0      ; 1                ; 0                              ;
;     -- Output Ports with no Fanout          ; 0      ; 21               ; 0                              ;
+---------------------------------------------+--------+------------------+--------------------------------+
Note: Resource usage numbers presented for Partitions containing post-synthesis logic are estimates.  For Partitions containing post-fit logic, resource usage numbers are accurate based on previous placement information.  Actual Fitter results may vary depending on current Fitter Preservation Level assignments.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge Partition Pin Processing                                                                                                                                                                                     ;
+------------------------------------------------------------------------------------------------------------------------------------------+-----------+---------------+----------+--------------------------------------------+
; Name                                                                                                                                     ; Partition ; Type          ; Location ; Status                                     ;
+------------------------------------------------------------------------------------------------------------------------------------------+-----------+---------------+----------+--------------------------------------------+
; altera_reserved_tck                                                                                                                      ; Top       ; Input Port    ; n/a      ;                                            ;
;     -- altera_reserved_tck                                                                                                               ; Top       ; Input Pad     ; Unplaced ; Synthesized                                ;
;     -- altera_reserved_tck~input                                                                                                         ; Top       ; Input Buffer  ; Unplaced ; Synthesized                                ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; altera_reserved_tdi                                                                                                                      ; Top       ; Input Port    ; n/a      ;                                            ;
;     -- altera_reserved_tdi                                                                                                               ; Top       ; Input Pad     ; Unplaced ; Synthesized                                ;
;     -- altera_reserved_tdi~input                                                                                                         ; Top       ; Input Buffer  ; Unplaced ; Synthesized                                ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; altera_reserved_tdo                                                                                                                      ; Top       ; Output Port   ; n/a      ;                                            ;
;     -- altera_reserved_tdo                                                                                                               ; Top       ; Output Pad    ; Unplaced ; Synthesized                                ;
;     -- altera_reserved_tdo~output                                                                                                        ; Top       ; Output Buffer ; Unplaced ; Synthesized                                ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; altera_reserved_tms                                                                                                                      ; Top       ; Input Port    ; n/a      ;                                            ;
;     -- altera_reserved_tms                                                                                                               ; Top       ; Input Pad     ; Unplaced ; Synthesized                                ;
;     -- altera_reserved_tms~input                                                                                                         ; Top       ; Input Buffer  ; Unplaced ; Synthesized                                ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; bidir_port_to_and_from_the_pa[0]                                                                                                         ; Top       ; Bidir Port    ; n/a      ;                                            ;
;     -- bidir_port_to_and_from_the_pa[0]                                                                                                  ; Top       ; Bidir Pad     ; Unplaced ; Synthesized                                ;
;     -- bidir_port_to_and_from_the_pa[0]~output                                                                                           ; Top       ; Output Buffer ; Unplaced ; Preserved from Synthesis Netlist (WYSIWYG) ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; bidir_port_to_and_from_the_pa[1]                                                                                                         ; Top       ; Bidir Port    ; n/a      ;                                            ;
;     -- bidir_port_to_and_from_the_pa[1]                                                                                                  ; Top       ; Bidir Pad     ; Unplaced ; Synthesized                                ;
;     -- bidir_port_to_and_from_the_pa[1]~output                                                                                           ; Top       ; Output Buffer ; Unplaced ; Preserved from Synthesis Netlist (WYSIWYG) ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; bidir_port_to_and_from_the_pa[2]                                                                                                         ; Top       ; Bidir Port    ; n/a      ;                                            ;
;     -- bidir_port_to_and_from_the_pa[2]                                                                                                  ; Top       ; Bidir Pad     ; Unplaced ; Synthesized                                ;
;     -- bidir_port_to_and_from_the_pa[2]~output                                                                                           ; Top       ; Output Buffer ; Unplaced ; Preserved from Synthesis Netlist (WYSIWYG) ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; bidir_port_to_and_from_the_pa[3]                                                                                                         ; Top       ; Bidir Port    ; n/a      ;                                            ;
;     -- bidir_port_to_and_from_the_pa[3]                                                                                                  ; Top       ; Bidir Pad     ; Unplaced ; Synthesized                                ;
;     -- bidir_port_to_and_from_the_pa[3]~output                                                                                           ; Top       ; Output Buffer ; Unplaced ; Preserved from Synthesis Netlist (WYSIWYG) ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; bidir_port_to_and_from_the_pa[4]                                                                                                         ; Top       ; Bidir Port    ; n/a      ;                                            ;
;     -- bidir_port_to_and_from_the_pa[4]                                                                                                  ; Top       ; Bidir Pad     ; Unplaced ; Synthesized                                ;
;     -- bidir_port_to_and_from_the_pa[4]~output                                                                                           ; Top       ; Output Buffer ; Unplaced ; Preserved from Synthesis Netlist (WYSIWYG) ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; bidir_port_to_and_from_the_pa[5]                                                                                                         ; Top       ; Bidir Port    ; n/a      ;                                            ;
;     -- bidir_port_to_and_from_the_pa[5]                                                                                                  ; Top       ; Bidir Pad     ; Unplaced ; Synthesized                                ;
;     -- bidir_port_to_and_from_the_pa[5]~output                                                                                           ; Top       ; Output Buffer ; Unplaced ; Preserved from Synthesis Netlist (WYSIWYG) ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; bidir_port_to_and_from_the_pa[6]                                                                                                         ; Top       ; Bidir Port    ; n/a      ;                                            ;
;     -- bidir_port_to_and_from_the_pa[6]                                                                                                  ; Top       ; Bidir Pad     ; Unplaced ; Synthesized                                ;
;     -- bidir_port_to_and_from_the_pa[6]~output                                                                                           ; Top       ; Output Buffer ; Unplaced ; Preserved from Synthesis Netlist (WYSIWYG) ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; bidir_port_to_and_from_the_pa[7]                                                                                                         ; Top       ; Bidir Port    ; n/a      ;                                            ;
;     -- bidir_port_to_and_from_the_pa[7]                                                                                                  ; Top       ; Bidir Pad     ; Unplaced ; Synthesized                                ;
;     -- bidir_port_to_and_from_the_pa[7]~output                                                                                           ; Top       ; Output Buffer ; Unplaced ; Preserved from Synthesis Netlist (WYSIWYG) ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; clk_0                                                                                                                                    ; Top       ; Input Port    ; n/a      ;                                            ;
;     -- clk_0                                                                                                                             ; Top       ; Input Pad     ; Unplaced ; Synthesized                                ;
;     -- clk_0~input                                                                                                                       ; Top       ; Input Buffer  ; Unplaced ; Synthesized                                ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_clr             ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ena             ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_in_0_        ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_in_1_        ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_out_0_       ; Top       ; Output Port   ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_out_1_       ; Top       ; Output Port   ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_cdr  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_cir  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e1dr ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e1ir ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e2dr ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e2ir ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_pdr  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_pir  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_rti  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sdr  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sdrs ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sir  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sirs ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_tlr  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_udr  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_uir  ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_raw_tck         ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_raw_tms         ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_tdi             ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_tdo             ; Top       ; Output Port   ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; jtag.bp.the_cpu_the_cpu_nios2_oci_the_cpu_jtag_debug_module_wrapper_cpu_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_usr1            ; Top       ; Input Port    ; n/a      ;                                            ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
; reset_n                                                                                                                                  ; Top       ; Input Port    ; n/a      ;                                            ;
;     -- reset_n                                                                                                                           ; Top       ; Input Pad     ; Unplaced ; Synthesized                                ;
;     -- reset_n~input                                                                                                                     ; Top       ; Input Buffer  ; Unplaced ; Synthesized                                ;
;                                                                                                                                          ;           ;               ;          ;                                            ;
+------------------------------------------------------------------------------------------------------------------------------------------+-----------+---------------+----------+--------------------------------------------+


+-----------------------------------------------------------+
; Partition Merge Resource Usage Summary                    ;
+---------------------------------------------+-------------+
; Resource                                    ; Usage       ;
+---------------------------------------------+-------------+
; Estimated Total logic elements              ; 2,418       ;
;                                             ;             ;
; Total combinational functions               ; 2010        ;
; Logic element usage by number of LUT inputs ;             ;
;     -- 4 input functions                    ; 1019        ;
;     -- 3 input functions                    ; 757         ;
;     -- <=2 input functions                  ; 234         ;
;                                             ;             ;
; Logic elements by mode                      ;             ;
;     -- normal mode                          ; 1886        ;
;     -- arithmetic mode                      ; 124         ;
;                                             ;             ;
; Total registers                             ; 1394        ;
;     -- Dedicated logic registers            ; 1394        ;
;     -- I/O registers                        ; 0           ;
;                                             ;             ;
; I/O pins                                    ; 10          ;
; Total memory bits                           ; 403328      ;
; Embedded Multiplier 9-bit elements          ; 4           ;
; Maximum fan-out node                        ; clk_0~input ;
; Maximum fan-out                             ; 1559        ;
; Total fan-out                               ; 16874       ;
; Average fan-out                             ; 4.54        ;
+---------------------------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge RAM Summary                                                                                                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+---------------------------------+
; Name                                                                                                                                                                                                                             ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                             ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+---------------------------------+
; cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_2of1:auto_generated|ALTSYNCRAM                                                                                                                           ; AUTO ; Simple Dual Port ; 256          ; 2            ; 256          ; 2            ; 512    ; cpu_bht_ram.mif                 ;
; cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|ALTSYNCRAM                                                                                                                   ; AUTO ; Simple Dual Port ; 1024         ; 32           ; 1024         ; 32           ; 32768  ; None                            ;
; cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_94g1:auto_generated|ALTSYNCRAM                                                                                                                     ; AUTO ; Simple Dual Port ; 128          ; 13           ; 128          ; 13           ; 1664   ; cpu_ic_tag_ram.mif              ;
; cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_6472:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port   ; 256          ; 32           ; 256          ; 32           ; 8192   ; cpu_ociram_default_contents.mif ;
; cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_26f1:auto_generated|ALTSYNCRAM                                                                                                   ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; cpu_rf_ram_a.mif                ;
; cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_36f1:auto_generated|ALTSYNCRAM                                                                                                   ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; cpu_rf_ram_b.mif                ;
; ram:the_ram|altsyncram:the_altsyncram|altsyncram_oua1:auto_generated|altsyncram:ram_block1a0|altsyncram_f7a3:auto_generated|ALTSYNCRAM                                                                                           ; AUTO ; Single Port      ; 3000         ; 32           ; --           ; --           ; 96000  ; ram.hex                         ;
; rom:the_rom|altsyncram:the_altsyncram|altsyncram_90b1:auto_generated|ALTSYNCRAM                                                                                                                                                  ; AUTO ; Single Port      ; 8192         ; 32           ; --           ; --           ; 262144 ; rom.hex                         ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+---------------------------------+


+-----------------------------------------------------+
; Partition Merge DSP Block Usage Summary             ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 2           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 4           ;
; Signed Embedded Multipliers           ; 0           ;
; Unsigned Embedded Multipliers         ; 2           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+--------------------------+
; Partition Merge Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Partition Merge
    Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
    Info: Processing started: Thu May 03 17:33:17 2012
Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off nios -c nios --merge=on
Warning: Previously generated Fitter netlist for partition "Top" is older than current Synthesis netlist -- using the current Synthesis netlist instead to ensure that the latest source changes are included
    Info: Set the option to Ignore source file changes to force the Quartus II software to always use a previously generated Fitter netlist
Info: Using synthesis netlist for partition "Top"
Info: Using synthesis netlist for partition "sld_hub:auto_hub"
Info: Resolved and merged 2 partition(s)
Info: Generating hard_block partition "hard_block:auto_generated_inst"
Info: Implemented 2996 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 1 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 2706 logic cells
    Info: Implemented 271 RAM segments
    Info: Implemented 4 DSP elements
Info: Quartus II Partition Merge was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 261 megabytes
    Info: Processing ended: Thu May 03 17:33:19 2012
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


