Analysis & Synthesis report for sd
Thu Feb 09 16:29:44 2012
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize
 11. Registers Protected by Synthesis
 12. Registers Removed During Synthesis
 13. Removed Registers Triggering Further Register Optimizations
 14. General Register Statistics
 15. Inverted Register Statistics
 16. Multiplexer Restructuring Statistics (Restructuring Performed)
 17. Source assignments for sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated
 18. Source assignments for sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram|altsyncram_rva1:auto_generated
 19. Source assignments for sopc:inst|RS232_UART:the_RS232_UART
 20. Source assignments for sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer
 21. Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_8ef1:auto_generated
 22. Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_9ef1:auto_generated
 23. Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated
 24. Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated
 25. Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
 26. Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
 27. Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
 28. Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
 29. Source assignments for sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1
 30. Source assignments for sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1
 31. Source assignments for sopc:inst|sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch
 32. Parameter Settings for User Entity Instance: sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram
 33. Parameter Settings for User Entity Instance: sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram
 34. Parameter Settings for User Entity Instance: sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer
 35. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
 36. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
 37. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
 38. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
 39. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
 40. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 41. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
 42. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 43. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
 44. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
 45. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
 46. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
 47. Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy
 48. Parameter Settings for User Entity Instance: sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
 49. Parameter Settings for User Entity Instance: sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
 50. Parameter Settings for User Entity Instance: sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
 51. Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component
 52. Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub
 53. altsyncram Parameter Settings by Entity Instance
 54. scfifo Parameter Settings by Entity Instance
 55. altpll Parameter Settings by Entity Instance
 56. Port Connectivity Checks: "sopc:inst|sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch"
 57. Port Connectivity Checks: "sopc:inst|sysid:the_sysid"
 58. Port Connectivity Checks: "sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"
 59. Port Connectivity Checks: "sopc:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave"
 60. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy"
 61. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3"
 62. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2"
 63. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component"
 64. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib"
 65. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp"
 66. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode"
 67. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace"
 68. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk"
 69. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk"
 70. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component"
 71. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug"
 72. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci"
 73. Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench"
 74. Port Connectivity Checks: "sopc:inst|RS232_UART_s1_arbitrator:the_RS232_UART_s1"
 75. Elapsed Time Per Partition
 76. Analysis & Synthesis Messages
 77. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
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Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Feb 09 16:29:44 2012     ;
; Quartus II Version                 ; 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name                      ; sd                                        ;
; Top-level Entity Name              ; sd                                        ;
; Family                             ; Cyclone III                               ;
; Total logic elements               ; 1,900                                     ;
;     Total combinational functions  ; 1,722                                     ;
;     Dedicated logic registers      ; 935                                       ;
; Total registers                    ; 935                                       ;
; Total pins                         ; 8                                         ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 876,800                                   ;
; Embedded Multiplier 9-bit elements ; 0                                         ;
; Total PLLs                         ; 1                                         ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP3C40Q240C8       ;                    ;
; Top-level entity name                                                      ; sd                 ; sd                 ;
; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ; < 0.1%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                   ;
+-----------------------------------+-----------------+----------------------------------------+-----------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path  ; Used in Netlist ; File Type                              ; File Name with Absolute Path                                                                              ;
+-----------------------------------+-----------------+----------------------------------------+-----------------------------------------------------------------------------------------------------------+
; pll.vhd                           ; yes             ; User Wizard-Generated File             ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/pll.vhd                           ;
; sd.bdf                            ; yes             ; User Block Diagram/Schematic File      ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/sd.bdf                            ;
; sopc.v                            ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/sopc.v                            ;
; ram.v                             ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/ram.v                             ;
; altsyncram.tdf                    ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf                                             ;
; stratix_ram_block.inc             ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_ram_block.inc                                      ;
; lpm_mux.inc                       ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_mux.inc                                                ;
; lpm_decode.inc                    ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_decode.inc                                             ;
; aglobal110.inc                    ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/aglobal110.inc                                             ;
; a_rdenreg.inc                     ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_rdenreg.inc                                              ;
; altrom.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altrom.inc                                                 ;
; altram.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altram.inc                                                 ;
; altdpram.inc                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altdpram.inc                                               ;
; db/altsyncram_32b1.tdf            ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/altsyncram_32b1.tdf            ;
; RAM.hex                           ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/RAM.hex                           ;
; db/decode_dra.tdf                 ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/decode_dra.tdf                 ;
; db/mux_anb.tdf                    ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/mux_anb.tdf                    ;
; rom.v                             ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/rom.v                             ;
; db/altsyncram_rva1.tdf            ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/altsyncram_rva1.tdf            ;
; ROM.hex                           ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/ROM.hex                           ;
; rs232_uart.v                      ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/rs232_uart.v                      ;
; altera_std_synchronizer.v         ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altera_std_synchronizer.v                                  ;
; clk_spi.v                         ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/clk_spi.v                         ;
; cpu_0.v                           ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0.v                           ;
; cpu_0_test_bench.v                ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0_test_bench.v                ;
; db/altsyncram_8ef1.tdf            ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/altsyncram_8ef1.tdf            ;
; cpu_0_rf_ram_a.mif                ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0_rf_ram_a.mif                ;
; db/altsyncram_9ef1.tdf            ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/altsyncram_9ef1.tdf            ;
; cpu_0_rf_ram_b.mif                ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0_rf_ram_b.mif                ;
; db/altsyncram_l872.tdf            ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/altsyncram_l872.tdf            ;
; cpu_0_ociram_default_contents.mif ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0_ociram_default_contents.mif ;
; cpu_0_oci_test_bench.v            ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0_oci_test_bench.v            ;
; db/altsyncram_n802.tdf            ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/altsyncram_n802.tdf            ;
; cpu_0_jtag_debug_module_wrapper.v ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0_jtag_debug_module_wrapper.v ;
; cpu_0_jtag_debug_module_tck.v     ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0_jtag_debug_module_tck.v     ;
; cpu_0_jtag_debug_module_sysclk.v  ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cpu_0_jtag_debug_module_sysclk.v  ;
; sld_virtual_jtag_basic.v          ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v                                   ;
; cs_spi.v                          ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/cs_spi.v                          ;
; di_spi.v                          ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/di_spi.v                          ;
; do_spi.v                          ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/do_spi.v                          ;
; jtag_uart.v                       ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/jtag_uart.v                       ;
; scfifo.tdf                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/scfifo.tdf                                                 ;
; a_regfifo.inc                     ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_regfifo.inc                                              ;
; a_dpfifo.inc                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_dpfifo.inc                                               ;
; a_i2fifo.inc                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_i2fifo.inc                                               ;
; a_fffifo.inc                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_fffifo.inc                                               ;
; a_f2fifo.inc                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_f2fifo.inc                                               ;
; db/scfifo_aq21.tdf                ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/scfifo_aq21.tdf                ;
; db/a_dpfifo_h031.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/a_dpfifo_h031.tdf              ;
; db/a_fefifo_7cf.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/a_fefifo_7cf.tdf               ;
; db/cntr_4n7.tdf                   ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/cntr_4n7.tdf                   ;
; db/dpram_ek21.tdf                 ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/dpram_ek21.tdf                 ;
; db/altsyncram_i0m1.tdf            ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/altsyncram_i0m1.tdf            ;
; db/cntr_omb.tdf                   ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/cntr_omb.tdf                   ;
; alt_jtag_atlantic.v               ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/alt_jtag_atlantic.v                                        ;
; sysid.v                           ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/sysid.v                           ;
; timer.v                           ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/timer.v                           ;
; altpll.tdf                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altpll.tdf                                                 ;
; stratix_pll.inc                   ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_pll.inc                                            ;
; stratixii_pll.inc                 ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratixii_pll.inc                                          ;
; cycloneii_pll.inc                 ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/cycloneii_pll.inc                                          ;
; db/pll_altpll.v                   ; yes             ; Auto-Generated Megafunction            ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/db/pll_altpll.v                   ;
; sld_hub.vhd                       ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/sld_hub.vhd                                                ;
; sld_rom_sr.vhd                    ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/sld_rom_sr.vhd                                             ;
+-----------------------------------+-----------------+----------------------------------------+-----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                ;
+---------------------------------------------+------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                        ;
+---------------------------------------------+------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 1,900                                                                        ;
;                                             ;                                                                              ;
; Total combinational functions               ; 1722                                                                         ;
; Logic element usage by number of LUT inputs ;                                                                              ;
;     -- 4 input functions                    ; 925                                                                          ;
;     -- 3 input functions                    ; 503                                                                          ;
;     -- <=2 input functions                  ; 294                                                                          ;
;                                             ;                                                                              ;
; Logic elements by mode                      ;                                                                              ;
;     -- normal mode                          ; 1537                                                                         ;
;     -- arithmetic mode                      ; 185                                                                          ;
;                                             ;                                                                              ;
; Total registers                             ; 935                                                                          ;
;     -- Dedicated logic registers            ; 935                                                                          ;
;     -- I/O registers                        ; 0                                                                            ;
;                                             ;                                                                              ;
; I/O pins                                    ; 8                                                                            ;
; Total memory bits                           ; 876800                                                                       ;
; Total PLLs                                  ; 1                                                                            ;
;     -- PLLs                                 ; 1                                                                            ;
;                                             ;                                                                              ;
; Maximum fan-out node                        ; pll:inst1|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out                             ; 1050                                                                         ;
; Total fan-out                               ; 13598                                                                        ;
; Average fan-out                             ; 4.60                                                                         ;
+---------------------------------------------+------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                      ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                          ; Library Name ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |sd                                                                                             ; 1722 (2)          ; 935 (0)      ; 876800      ; 0            ; 0       ; 0         ; 8    ; 0            ; |sd                                                                                                                                                                                                                                                          ;              ;
;    |pll:inst1|                                                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|pll:inst1                                                                                                                                                                                                                                                ;              ;
;       |altpll:altpll_component|                                                                 ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|pll:inst1|altpll:altpll_component                                                                                                                                                                                                                        ;              ;
;          |pll_altpll:auto_generated|                                                            ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|pll:inst1|altpll:altpll_component|pll_altpll:auto_generated                                                                                                                                                                                              ;              ;
;    |sld_hub:auto_hub|                                                                           ; 122 (81)          ; 76 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sld_hub:auto_hub                                                                                                                                                                                                                                         ;              ;
;       |sld_rom_sr:hub_info_reg|                                                                 ; 24 (24)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sld_hub:auto_hub|sld_rom_sr:hub_info_reg                                                                                                                                                                                                                 ;              ;
;       |sld_shadow_jsm:shadow_jsm|                                                               ; 17 (17)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                                               ;              ;
;    |sopc:inst|                                                                                  ; 1598 (0)          ; 859 (0)      ; 876800      ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst                                                                                                                                                                                                                                                ;              ;
;       |RAM:the_RAM|                                                                             ; 68 (0)            ; 2 (0)        ; 800000      ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RAM:the_RAM                                                                                                                                                                                                                                    ;              ;
;          |altsyncram:the_altsyncram|                                                            ; 68 (0)            ; 2 (0)        ; 800000      ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram                                                                                                                                                                                                          ;              ;
;             |altsyncram_32b1:auto_generated|                                                    ; 68 (0)            ; 2 (2)        ; 800000      ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated                                                                                                                                                                           ;              ;
;                |decode_dra:decode3|                                                             ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated|decode_dra:decode3                                                                                                                                                        ;              ;
;                |mux_anb:mux2|                                                                   ; 64 (64)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated|mux_anb:mux2                                                                                                                                                              ;              ;
;       |RAM_s1_arbitrator:the_RAM_s1|                                                            ; 27 (27)           ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RAM_s1_arbitrator:the_RAM_s1                                                                                                                                                                                                                   ;              ;
;       |ROM:the_ROM|                                                                             ; 2 (2)             ; 0 (0)        ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|ROM:the_ROM                                                                                                                                                                                                                                    ;              ;
;          |altsyncram:the_altsyncram|                                                            ; 0 (0)             ; 0 (0)        ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram                                                                                                                                                                                                          ;              ;
;             |altsyncram_rva1:auto_generated|                                                    ; 0 (0)             ; 0 (0)        ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram|altsyncram_rva1:auto_generated                                                                                                                                                                           ;              ;
;       |ROM_s1_arbitrator:the_ROM_s1|                                                            ; 24 (24)           ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|ROM_s1_arbitrator:the_ROM_s1                                                                                                                                                                                                                   ;              ;
;       |RS232_UART:the_RS232_UART|                                                               ; 117 (0)           ; 92 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RS232_UART:the_RS232_UART                                                                                                                                                                                                                      ;              ;
;          |RS232_UART_regs:the_RS232_UART_regs|                                                  ; 34 (34)           ; 29 (29)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_regs:the_RS232_UART_regs                                                                                                                                                                                  ;              ;
;          |RS232_UART_rx:the_RS232_UART_rx|                                                      ; 46 (46)           ; 37 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx                                                                                                                                                                                      ;              ;
;             |altera_std_synchronizer:the_altera_std_synchronizer|                               ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer                                                                                                                                  ;              ;
;          |RS232_UART_tx:the_RS232_UART_tx|                                                      ; 37 (37)           ; 26 (26)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_tx:the_RS232_UART_tx                                                                                                                                                                                      ;              ;
;       |RS232_UART_s1_arbitrator:the_RS232_UART_s1|                                              ; 3 (3)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|RS232_UART_s1_arbitrator:the_RS232_UART_s1                                                                                                                                                                                                     ;              ;
;       |clk_spi:the_clk_spi|                                                                     ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|clk_spi:the_clk_spi                                                                                                                                                                                                                            ;              ;
;       |clk_spi_s1_arbitrator:the_clk_spi_s1|                                                    ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|clk_spi_s1_arbitrator:the_clk_spi_s1                                                                                                                                                                                                           ;              ;
;       |cpu_0:the_cpu_0|                                                                         ; 907 (687)         ; 496 (311)    ; 10240       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0                                                                                                                                                                                                                                ;              ;
;          |cpu_0_nios2_oci:the_cpu_0_nios2_oci|                                                  ; 220 (26)          ; 184 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci                                                                                                                                                                                            ;              ;
;             |cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|               ; 92 (0)            ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper                                                                                                                        ;              ;
;                |cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|              ; 7 (7)             ; 49 (45)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk                                                      ;              ;
;                   |altera_std_synchronizer:the_altera_std_synchronizer2|                        ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;              ;
;                   |altera_std_synchronizer:the_altera_std_synchronizer3|                        ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;              ;
;                |cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|                    ; 81 (81)           ; 47 (43)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck                                                            ;              ;
;                   |altera_std_synchronizer:the_altera_std_synchronizer1|                        ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1       ;              ;
;                   |altera_std_synchronizer:the_altera_std_synchronizer|                         ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer        ;              ;
;                |sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy|                             ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy                                                                     ;              ;
;             |cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|                                 ; 10 (10)           ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg                                                                                                                                          ;              ;
;             |cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|                                   ; 32 (32)           ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break                                                                                                                                            ;              ;
;             |cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|                                   ; 8 (8)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug                                                                                                                                            ;              ;
;             |cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|                                         ; 52 (52)           ; 44 (44)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem                                                                                                                                                  ;              ;
;                |cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component| ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component                                                                   ;              ;
;                   |altsyncram:the_altsyncram|                                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram                                         ;              ;
;                      |altsyncram_l872:auto_generated|                                           ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated          ;              ;
;          |cpu_0_register_bank_a_module:cpu_0_register_bank_a|                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a                                                                                                                                                                             ;              ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram                                                                                                                                                   ;              ;
;                |altsyncram_8ef1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_8ef1:auto_generated                                                                                                                    ;              ;
;          |cpu_0_register_bank_b_module:cpu_0_register_bank_b|                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b                                                                                                                                                                             ;              ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram                                                                                                                                                   ;              ;
;                |altsyncram_9ef1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_9ef1:auto_generated                                                                                                                    ;              ;
;          |cpu_0_test_bench:the_cpu_0_test_bench|                                                ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench                                                                                                                                                                                          ;              ;
;       |cpu_0_data_master_arbitrator:the_cpu_0_data_master|                                      ; 96 (96)           ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master                                                                                                                                                                                             ;              ;
;       |cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|                        ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master                                                                                                                                                                               ;              ;
;       |cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|                          ; 31 (31)           ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module                                                                                                                                                                                 ;              ;
;       |cs_spi:the_cs_spi|                                                                       ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cs_spi:the_cs_spi                                                                                                                                                                                                                              ;              ;
;       |cs_spi_s1_arbitrator:the_cs_spi_s1|                                                      ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|cs_spi_s1_arbitrator:the_cs_spi_s1                                                                                                                                                                                                             ;              ;
;       |di_spi:the_di_spi|                                                                       ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|di_spi:the_di_spi                                                                                                                                                                                                                              ;              ;
;       |di_spi_s1_arbitrator:the_di_spi_s1|                                                      ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|di_spi_s1_arbitrator:the_di_spi_s1                                                                                                                                                                                                             ;              ;
;       |do_spi:the_do_spi|                                                                       ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|do_spi:the_do_spi                                                                                                                                                                                                                              ;              ;
;       |do_spi_s1_arbitrator:the_do_spi_s1|                                                      ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|do_spi_s1_arbitrator:the_do_spi_s1                                                                                                                                                                                                             ;              ;
;       |jtag_uart:the_jtag_uart|                                                                 ; 142 (40)          ; 108 (13)     ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart                                                                                                                                                                                                                        ;              ;
;          |alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|                                        ; 51 (51)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic                                                                                                                                                                          ;              ;
;          |jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|                                            ; 26 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r                                                                                                                                                                              ;              ;
;             |scfifo:rfifo|                                                                      ; 26 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo                                                                                                                                                                 ;              ;
;                |scfifo_aq21:auto_generated|                                                     ; 26 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated                                                                                                                                      ;              ;
;                   |a_dpfifo_h031:dpfifo|                                                        ; 26 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo                                                                                                                 ;              ;
;                      |a_fefifo_7cf:fifo_state|                                                  ; 14 (8)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state                                                                                         ;              ;
;                         |cntr_4n7:count_usedw|                                                  ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw                                                                    ;              ;
;                      |cntr_omb:rd_ptr_count|                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:rd_ptr_count                                                                                           ;              ;
;                      |cntr_omb:wr_ptr|                                                          ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:wr_ptr                                                                                                 ;              ;
;                      |dpram_ek21:FIFOram|                                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram                                                                                              ;              ;
;                         |altsyncram_i0m1:altsyncram1|                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1                                                                  ;              ;
;          |jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|                                            ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w                                                                                                                                                                              ;              ;
;             |scfifo:wfifo|                                                                      ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo                                                                                                                                                                 ;              ;
;                |scfifo_aq21:auto_generated|                                                     ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated                                                                                                                                      ;              ;
;                   |a_dpfifo_h031:dpfifo|                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo                                                                                                                 ;              ;
;                      |a_fefifo_7cf:fifo_state|                                                  ; 13 (7)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state                                                                                         ;              ;
;                         |cntr_4n7:count_usedw|                                                  ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw                                                                    ;              ;
;                      |cntr_omb:rd_ptr_count|                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:rd_ptr_count                                                                                           ;              ;
;                      |cntr_omb:wr_ptr|                                                          ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:wr_ptr                                                                                                 ;              ;
;                      |dpram_ek21:FIFOram|                                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram                                                                                              ;              ;
;                         |altsyncram_i0m1:altsyncram1|                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1                                                                  ;              ;
;       |jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|                  ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave                                                                                                                                                                         ;              ;
;       |sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch|                      ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch                                                                                                                                                                             ;              ;
;       |sysid_control_slave_arbitrator:the_sysid_control_slave|                                  ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|sysid_control_slave_arbitrator:the_sysid_control_slave                                                                                                                                                                                         ;              ;
;       |timer:the_timer|                                                                         ; 145 (145)         ; 120 (120)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|timer:the_timer                                                                                                                                                                                                                                ;              ;
;       |timer_s1_arbitrator:the_timer_s1|                                                        ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sd|sopc:inst|timer_s1_arbitrator:the_timer_s1                                                                                                                                                                                                               ;              ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                                                              ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------------------------+
; Name                                                                                                                                                                                                                                                       ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                               ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------------------------+
; sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated|ALTSYNCRAM                                                                                                                                                                  ; AUTO ; Single Port      ; 25000        ; 32           ; --           ; --           ; 800000 ; RAM.hex                           ;
; sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram|altsyncram_rva1:auto_generated|ALTSYNCRAM                                                                                                                                                                  ; AUTO ; Single Port      ; 2048         ; 32           ; --           ; --           ; 65536  ; ROM.hex                           ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port   ; 256          ; 32           ; 256          ; 32           ; 8192   ; cpu_0_ociram_default_contents.mif ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_8ef1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; cpu_0_rf_ram_a.mif                ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_9ef1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; cpu_0_rf_ram_b.mif                ;
; sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|ALTSYNCRAM                                                         ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512    ; None                              ;
; sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|ALTSYNCRAM                                                         ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512    ; None                              ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------------------------+


The IP Core highlighted in red is outdated. Regenerate the outdated IP with the current version of the Quartus II software and the MegaWizard interface.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                             ;
+--------+--------------+---------+--------------+--------------+-----------------+---------------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File                                                                 ;
+--------+--------------+---------+--------------+--------------+-----------------+---------------------------------------------------------------------------------+
; Altera ; ALTPLL       ; 10.1    ; N/A          ; N/A          ; |sd|pll:inst1   ; E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/pll.vhd ;
+--------+--------------+---------+--------------+--------------+-----------------+---------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+
; Name       ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000                                                                                                                                 ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+
; DRsize.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0                                                                                                                                          ;
; DRsize.001 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1                                                                                                                                          ;
; DRsize.010 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1                                                                                                                                          ;
; DRsize.011 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1                                                                                                                                          ;
; DRsize.100 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1                                                                                                                                          ;
; DRsize.101 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1                                                                                                                                          ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                                                                                                                    ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[0]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch|data_out                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0]       ; yes                                                              ; yes                                        ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]        ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[1]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch|data_in_d1                                                                                                                                                                          ; yes                                                              ; yes                                        ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1        ; yes                                                              ; yes                                        ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[2]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[7]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[3]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[0]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_req                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_valid                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[4]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[1]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write                                                                                                                                                                       ; yes                                                              ; yes                                        ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; yes                                                              ; yes                                        ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[5]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[2]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ; yes                                                              ; yes                                        ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1  ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[6]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[3]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[7]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[6]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[5]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[4]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[3]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[2]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[4]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]                                                                                                                                  ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                          ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[5]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                                   ; yes                                                              ; yes                                        ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[6]                                                                                                                                                                         ; yes                                                              ; yes                                        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                                                              ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                            ; Reason for Removal                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[0..35]                                                                               ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|W_ienable_reg[3..31]                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|W_ipending_reg[3..31]                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|R_ctrl_custom                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[0..6]                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_wrap                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto1                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_break_pulse                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto0                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_break                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_regs:the_RS232_UART_regs|readdata[10..15]                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|d1_reasons_to_wait                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|d1_reasons_to_wait                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|W_control_rd_data[3..31]                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[0..16]                                                                             ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_slavearbiterlockenable                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_slavearbiterlockenable                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_slavearbiterlockenable                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter                                                                                       ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module                                                       ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module                                                              ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[1]                                                                           ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_reg_firsttransfer                                                                                       ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_arb_share_counter                                                                                                                                          ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|last_cycle_cpu_0_instruction_master_granted_slave_ROM_s1                                                                                                          ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|last_cycle_cpu_0_data_master_granted_slave_ROM_s1                                                                                                                 ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_saved_chosen_master_vector[1]                                                                                                                              ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_reg_firsttransfer                                                                                                                                          ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_arb_share_counter                                                                                                                                          ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|last_cycle_cpu_0_instruction_master_granted_slave_RAM_s1                                                                                                          ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|last_cycle_cpu_0_data_master_granted_slave_RAM_s1                                                                                                                 ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_saved_chosen_master_vector[1]                                                                                                                              ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_reg_firsttransfer                                                                                                                                          ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[3]                                                                           ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[4]                                                                           ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[4]                                                                           ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[5]                                                                           ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[5]                                                                           ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]                                                                           ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]                                                                           ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]                                                                           ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]                                                                           ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]                                                                           ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]                                                                           ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]                                                                           ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]                                                                           ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]                                                                          ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]                                                                          ;
; sopc:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[11,23..30]                                                                                            ; Merged with sopc:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31]                                                                                                   ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_cpu_0_jtag_debug_module_end_xfer                                                                                             ; Merged with sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait                                                                                                              ;
; sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|delayed_unxsync_rxdxx2                                                                                                               ; Merged with sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|delayed_unxsync_rxdxx1                                                                                                               ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_arb_addend[0]                                                                                                                                              ; Merged with sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_arb_addend[1]                                                                                                                                              ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_arb_addend[0]                                                                                                                                              ; Merged with sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_arb_addend[1]                                                                                                                                              ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|trigger_state                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_break                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|trigbrktype                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_saved_chosen_master_vector[0]                                                                                                                              ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_saved_chosen_master_vector[0]                                                                                                                              ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~3   ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~4   ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~5   ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.101 ; Lost fanout                                                                                                                                                                                                          ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.011 ; Merged with sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.001 ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.001 ; Stuck at GND due to stuck port data_in                                                                                                                                                                               ;
; Total Number of Removed Registers = 231                                                                                                                                                                  ;                                                                                                                                                                                                                      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                               ;
+-------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                           ; Reason for Removal        ; Registers Removed due to This Register                                                                                                              ;
+-------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|d1_reasons_to_wait                                                               ; Stuck at GND              ; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_slavearbiterlockenable,                                                                               ;
;                                                                                                                         ; due to stuck port data_in ; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|last_cycle_cpu_0_instruction_master_granted_slave_ROM_s1,                                                    ;
;                                                                                                                         ;                           ; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|last_cycle_cpu_0_data_master_granted_slave_ROM_s1,                                                           ;
;                                                                                                                         ;                           ; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_saved_chosen_master_vector[1],                                                                        ;
;                                                                                                                         ;                           ; sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_saved_chosen_master_vector[0]                                                                         ;
; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|d1_reasons_to_wait                                                               ; Stuck at GND              ; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_slavearbiterlockenable,                                                                               ;
;                                                                                                                         ; due to stuck port data_in ; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|last_cycle_cpu_0_instruction_master_granted_slave_RAM_s1,                                                    ;
;                                                                                                                         ;                           ; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|last_cycle_cpu_0_data_master_granted_slave_RAM_s1,                                                           ;
;                                                                                                                         ;                           ; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_saved_chosen_master_vector[1],                                                                        ;
;                                                                                                                         ;                           ; sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_saved_chosen_master_vector[0]                                                                         ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_slavearbiterlockenable ; Stuck at GND              ; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module, ;
;                                                                                                                         ; due to stuck port data_in ; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[1]                      ;
+-------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 935   ;
; Number of registers using Synchronous Clear  ; 60    ;
; Number of registers using Synchronous Load   ; 193   ;
; Number of registers using Asynchronous Clear ; 723   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 506   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                             ;
+--------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                              ; Fan out ;
+--------------------------------------------------------------------------------------------------------------------------------+---------+
; sopc:inst|timer:the_timer|internal_counter[0]                                                                                  ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[1]                                                                                  ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[2]                                                                                  ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[3]                                                                                  ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[4]                                                                                  ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[5]                                                                                  ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[6]                                                                                  ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[12]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[13]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[14]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[15]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[17]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[19]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[20]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[21]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[22]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[23]                                                                                 ; 3       ;
; sopc:inst|timer:the_timer|internal_counter[25]                                                                                 ; 3       ;
; sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_tx:the_RS232_UART_tx|txd                                                        ; 1       ;
; sopc:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest                                     ; 14      ;
; sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_tx:the_RS232_UART_tx|pre_txd                                                    ; 2       ;
; sopc:inst|jtag_uart:the_jtag_uart|t_dav                                                                                        ; 4       ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[9]                                       ; 11      ;
; sopc:inst|cpu_0:the_cpu_0|F_pc[16]                                                                                             ; 4       ;
; sopc:inst|cpu_0:the_cpu_0|i_read                                                                                               ; 7       ;
; sopc:inst|cpu_0:the_cpu_0|F_pc[11]                                                                                             ; 4       ;
; sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0]                 ; 5       ;
; sopc:inst|jtag_uart:the_jtag_uart|av_waitrequest                                                                               ; 2       ;
; sopc:inst|cpu_0:the_cpu_0|hbreak_enabled                                                                                       ; 12      ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rst2                                           ; 3       ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[0] ; 2       ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[1] ; 2       ;
; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[2] ; 2       ;
; sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_tx:the_RS232_UART_tx|tx_ready                                                   ; 6       ;
; sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rst1                                           ; 1       ;
; sopc:inst|timer:the_timer|period_l_register[0]                                                                                 ; 2       ;
; sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_tx:the_RS232_UART_tx|tx_shift_empty                                             ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[5]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_h_register[5]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[4]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_h_register[4]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[3]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_h_register[3]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[2]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[1]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_h_register[1]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[6]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_h_register[6]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[15]                                                                                ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[14]                                                                                ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[13]                                                                                ; 2       ;
; sopc:inst|timer:the_timer|period_l_register[12]                                                                                ; 2       ;
; sopc:inst|timer:the_timer|period_h_register[9]                                                                                 ; 2       ;
; sopc:inst|timer:the_timer|period_h_register[7]                                                                                 ; 2       ;
; sld_hub:auto_hub|tdo                                                                                                           ; 2       ;
; Total number of inverted registers = 55                                                                                        ;         ;
+--------------------------------------------------------------------------------------------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                                                                                                                                                                                               ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; |sd|sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[7]                                                                                                             ;                            ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|E_src2[4]                                                                                                                                                                  ;                            ;
; 3:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; |sd|sopc:inst|cpu_0:the_cpu_0|E_src1[28]                                                                                                                                                                 ;                            ;
; 3:1                ; 17 bits   ; 34 LEs        ; 34 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|E_src1[18]                                                                                                                                                                 ;                            ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|E_shift_rot_result[12]                                                                                                                                                     ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|av_ld_byte0_data[7]                                                                                                                                                        ;                            ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|av_ld_byte1_data[1]                                                                                                                                                        ;                            ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|D_iw[5]                                                                                                                                                                    ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|d_byteenable[1]                                                                                                                                                            ;                            ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; |sd|sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]                                                                           ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |sd|sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                          ;                            ;
; 4:1                ; 19 bits   ; 38 LEs        ; 38 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|W_alu_result[1]                                                                                                                                                            ;                            ;
; 4:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|E_src2[28]                                                                                                                                                                 ;                            ;
; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|W_control_rd_data[2]                                                                                                                                                       ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; |sd|sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_tx:the_RS232_UART_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]                                                                   ;                            ;
; 4:1                ; 21 bits   ; 42 LEs        ; 42 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[24]                                                                                  ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[17]                                                                                  ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|d_writedata[24]                                                                                                                                                            ;                            ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[4]                                                                                   ;                            ;
; 6:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[37] ;                            ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[33] ;                            ;
; 6:1                ; 13 bits   ; 52 LEs        ; 26 LEs               ; 26 LEs                 ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[11] ;                            ;
; 6:1                ; 16 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[30] ;                            ;
; 5:1                ; 13 bits   ; 39 LEs        ; 39 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|W_alu_result[21]                                                                                                                                                           ;                            ;
; 4:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|F_pc[5]                                                                                                                                                                    ;                            ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[3]                                                                                   ;                            ;
; 5:1                ; 32 bits   ; 96 LEs        ; 32 LEs               ; 64 LEs                 ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[6]                                                                       ;                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|d_byteenable[2]                                                                                                                                                            ;                            ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; |sd|sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                          ;                            ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; |sd|sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[6]                                                                                                          ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|F_pc[11]                                                                                                                                                                   ;                            ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|E_logic_result[18]                                                                                                                                                         ;                            ;
; 4:1                ; 29 bits   ; 58 LEs        ; 58 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|W_rf_wr_data[13]                                                                                                                                                           ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|W_rf_wr_data[2]                                                                                                                                                            ;                            ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[2]                                                                                                                            ;                            ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; |sd|sopc:inst|cpu_0:the_cpu_0|D_dst_regnum[2]                                                                                                                                                            ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+


+-------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------+
; Assignment                      ; Value              ; From ; To                                      ;
+---------------------------------+--------------------+------+-----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                       ;
+---------------------------------+--------------------+------+-----------------------------------------+


+-------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram|altsyncram_rva1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------+
; Assignment                      ; Value              ; From ; To                                      ;
+---------------------------------+--------------------+------+-----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                       ;
+---------------------------------+--------------------+------+-----------------------------------------+


+------------------------------------------------------------+
; Source assignments for sopc:inst|RS232_UART:the_RS232_UART ;
+-----------------------------+-------+------+---------------+
; Assignment                  ; Value ; From ; To            ;
+-----------------------------+-------+------+---------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -             ;
+-----------------------------+-------+------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                               ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                          ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                          ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                          ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                           ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_8ef1:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                             ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_9ef1:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                             ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                           ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                            ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                         ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                    ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                    ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                     ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                          ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                      ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                           ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                            ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                           ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                            ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                               ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                               ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Source assignments for sopc:inst|sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch ;
+-------------------+-------+------+------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                               ;
+-------------------+-------+------+------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                         ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                    ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                       ;
+-------------------+-------+------+------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------+
; Parameter Name                     ; Value                ; Type                             ;
+------------------------------------+----------------------+----------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                          ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                          ;
; WIDTH_A                            ; 32                   ; Signed Integer                   ;
; WIDTHAD_A                          ; 15                   ; Signed Integer                   ;
; NUMWORDS_A                         ; 25000                ; Signed Integer                   ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                          ;
; WIDTH_B                            ; 1                    ; Untyped                          ;
; WIDTHAD_B                          ; 1                    ; Untyped                          ;
; NUMWORDS_B                         ; 1                    ; Untyped                          ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                          ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                          ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                          ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                          ;
; WIDTH_BYTEENA_A                    ; 4                    ; Signed Integer                   ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                          ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                          ;
; INIT_FILE                          ; RAM.hex              ; Untyped                          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                          ;
; MAXIMUM_DEPTH                      ; 25000                ; Signed Integer                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                          ;
; ENABLE_ECC                         ; FALSE                ; Untyped                          ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                          ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                          ;
; CBXI_PARAMETER                     ; altsyncram_32b1      ; Untyped                          ;
+------------------------------------+----------------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------+
; Parameter Name                     ; Value                ; Type                             ;
+------------------------------------+----------------------+----------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                          ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                          ;
; WIDTH_A                            ; 32                   ; Signed Integer                   ;
; WIDTHAD_A                          ; 11                   ; Signed Integer                   ;
; NUMWORDS_A                         ; 2048                 ; Signed Integer                   ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                          ;
; WIDTH_B                            ; 1                    ; Untyped                          ;
; WIDTHAD_B                          ; 1                    ; Untyped                          ;
; NUMWORDS_B                         ; 1                    ; Untyped                          ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                          ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                          ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                          ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                          ;
; WIDTH_BYTEENA_A                    ; 4                    ; Signed Integer                   ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                          ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                          ;
; INIT_FILE                          ; ROM.hex              ; Untyped                          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                          ;
; MAXIMUM_DEPTH                      ; 2048                 ; Signed Integer                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                          ;
; ENABLE_ECC                         ; FALSE                ; Untyped                          ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                          ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                          ;
; CBXI_PARAMETER                     ; altsyncram_rva1      ; Untyped                          ;
+------------------------------------+----------------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                        ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a ;
+----------------+--------------------+-------------------------------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                                                ;
+----------------+--------------------+-------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_rf_ram_a.mif ; String                                                                              ;
+----------------+--------------------+-------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                    ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                 ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                            ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                          ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                 ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                 ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                          ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                          ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                          ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                 ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                 ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                 ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                 ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                 ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                 ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                          ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                          ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                          ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                 ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                                 ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                 ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                 ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                 ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                 ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                 ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                 ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                 ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                 ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                 ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                 ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                 ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                 ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                 ;
; INIT_FILE                          ; cpu_0_rf_ram_a.mif   ; Untyped                                                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                 ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                          ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                 ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                 ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                 ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                 ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                 ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                                 ;
; CBXI_PARAMETER                     ; altsyncram_8ef1      ; Untyped                                                                                 ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b ;
+----------------+--------------------+-------------------------------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                                                ;
+----------------+--------------------+-------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_rf_ram_b.mif ; String                                                                              ;
+----------------+--------------------+-------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                    ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                 ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                            ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                          ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                 ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                 ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                          ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                          ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                          ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                 ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                 ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                 ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                 ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                 ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                 ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                          ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                          ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                          ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                 ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                                 ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                 ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                 ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                 ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                 ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                 ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                 ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                 ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                 ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                 ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                 ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                 ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                 ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                 ;
; INIT_FILE                          ; cpu_0_rf_ram_b.mif   ; Untyped                                                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                 ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                          ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                 ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                 ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                 ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                 ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                 ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                                 ;
; CBXI_PARAMETER                     ; altsyncram_9ef1      ; Untyped                                                                                 ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component ;
+----------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value                             ; Type                                                                                                                                                                           ;
+----------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_ociram_default_contents.mif ; String                                                                                                                                                                         ;
+----------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                             ; Type                                                                                                                                                                                 ;
+------------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                                 ; Untyped                                                                                                                                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                                ; AUTO_CARRY                                                                                                                                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                               ; IGNORE_CARRY                                                                                                                                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                                ; AUTO_CASCADE                                                                                                                                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                               ; IGNORE_CASCADE                                                                                                                                                                       ;
; WIDTH_BYTEENA                      ; 1                                 ; Untyped                                                                                                                                                                              ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT                   ; Untyped                                                                                                                                                                              ;
; WIDTH_A                            ; 32                                ; Signed Integer                                                                                                                                                                       ;
; WIDTHAD_A                          ; 8                                 ; Signed Integer                                                                                                                                                                       ;
; NUMWORDS_A                         ; 256                               ; Signed Integer                                                                                                                                                                       ;
; OUTDATA_REG_A                      ; UNREGISTERED                      ; Untyped                                                                                                                                                                              ;
; ADDRESS_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                              ;
; OUTDATA_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                              ;
; WRCONTROL_ACLR_A                   ; NONE                              ; Untyped                                                                                                                                                                              ;
; INDATA_ACLR_A                      ; NONE                              ; Untyped                                                                                                                                                                              ;
; BYTEENA_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                              ;
; WIDTH_B                            ; 32                                ; Signed Integer                                                                                                                                                                       ;
; WIDTHAD_B                          ; 8                                 ; Signed Integer                                                                                                                                                                       ;
; NUMWORDS_B                         ; 256                               ; Signed Integer                                                                                                                                                                       ;
; INDATA_REG_B                       ; CLOCK1                            ; Untyped                                                                                                                                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                            ; Untyped                                                                                                                                                                              ;
; RDCONTROL_REG_B                    ; CLOCK1                            ; Untyped                                                                                                                                                                              ;
; ADDRESS_REG_B                      ; CLOCK1                            ; Untyped                                                                                                                                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED                      ; Untyped                                                                                                                                                                              ;
; BYTEENA_REG_B                      ; CLOCK1                            ; Untyped                                                                                                                                                                              ;
; INDATA_ACLR_B                      ; NONE                              ; Untyped                                                                                                                                                                              ;
; WRCONTROL_ACLR_B                   ; NONE                              ; Untyped                                                                                                                                                                              ;
; ADDRESS_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                              ;
; OUTDATA_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                              ;
; RDCONTROL_ACLR_B                   ; NONE                              ; Untyped                                                                                                                                                                              ;
; BYTEENA_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                              ;
; WIDTH_BYTEENA_A                    ; 4                                 ; Signed Integer                                                                                                                                                                       ;
; WIDTH_BYTEENA_B                    ; 1                                 ; Untyped                                                                                                                                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                              ; Untyped                                                                                                                                                                              ;
; BYTE_SIZE                          ; 8                                 ; Untyped                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                          ; Untyped                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ              ; Untyped                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ              ; Untyped                                                                                                                                                                              ;
; INIT_FILE                          ; cpu_0_ociram_default_contents.mif ; Untyped                                                                                                                                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A                            ; Untyped                                                                                                                                                                              ;
; MAXIMUM_DEPTH                      ; 0                                 ; Untyped                                                                                                                                                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                            ; Untyped                                                                                                                                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                            ; Untyped                                                                                                                                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                            ; Untyped                                                                                                                                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                            ; Untyped                                                                                                                                                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                   ; Untyped                                                                                                                                                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                   ; Untyped                                                                                                                                                                              ;
; ENABLE_ECC                         ; FALSE                             ; Untyped                                                                                                                                                                              ;
; WIDTH_ECCSTATUS                    ; 3                                 ; Untyped                                                                                                                                                                              ;
; DEVICE_FAMILY                      ; Cyclone III                       ; Untyped                                                                                                                                                                              ;
; CBXI_PARAMETER                     ; altsyncram_l872                   ; Untyped                                                                                                                                                                              ;
+------------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component ;
+----------------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                          ;
+----------------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                                        ;
+----------------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                  ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                               ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                            ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                          ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                          ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                        ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                               ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                                                                                                                                               ;
; WIDTH_A                            ; 36                   ; Signed Integer                                                                                                                                                                                        ;
; WIDTHAD_A                          ; 7                    ; Signed Integer                                                                                                                                                                                        ;
; NUMWORDS_A                         ; 128                  ; Signed Integer                                                                                                                                                                                        ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                               ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                               ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                               ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                               ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                               ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                               ;
; WIDTH_B                            ; 36                   ; Signed Integer                                                                                                                                                                                        ;
; WIDTHAD_B                          ; 7                    ; Signed Integer                                                                                                                                                                                        ;
; NUMWORDS_B                         ; 128                  ; Signed Integer                                                                                                                                                                                        ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                               ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                               ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                               ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                               ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                               ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                               ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                               ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                               ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                               ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                               ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                               ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                               ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                                                                                                                               ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                               ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                               ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                                                                                                                               ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                                                                                                                                               ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                               ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                               ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                               ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                               ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                               ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                               ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                               ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                               ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                               ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                               ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                               ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                               ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                               ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                                                                                                                                               ;
; CBXI_PARAMETER                     ; altsyncram_n802      ; Untyped                                                                                                                                                                                               ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                  ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                   ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                         ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                         ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                               ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                         ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                               ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy ;
+-------------------------+------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value                  ; Type                                                                                                                                                                           ;
+-------------------------+------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sld_mfg_id              ; 70                     ; Signed Integer                                                                                                                                                                 ;
; sld_type_id             ; 34                     ; Signed Integer                                                                                                                                                                 ;
; sld_version             ; 3                      ; Signed Integer                                                                                                                                                                 ;
; sld_instance_index      ; 0                      ; Signed Integer                                                                                                                                                                 ;
; sld_auto_instance_index ; YES                    ; String                                                                                                                                                                         ;
; sld_ir_width            ; 2                      ; Signed Integer                                                                                                                                                                 ;
; sld_sim_n_scan          ; 0                      ; Signed Integer                                                                                                                                                                 ;
; sld_sim_action          ;                        ; String                                                                                                                                                                         ;
; sld_sim_total_length    ; 0                      ; Signed Integer                                                                                                                                                                 ;
; lpm_type                ; sld_virtual_jtag_basic ; String                                                                                                                                                                         ;
; lpm_hint                ; UNUSED                 ; String                                                                                                                                                                         ;
+-------------------------+------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                          ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                    ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                  ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                  ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                ;
; lpm_width               ; 8           ; Signed Integer                                                                                ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                                ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                                ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                       ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                       ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                       ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                       ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                       ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                       ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                       ;
; USE_EAB                 ; ON          ; Untyped                                                                                       ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                       ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                       ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                       ;
; CBXI_PARAMETER          ; scfifo_aq21 ; Untyped                                                                                       ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                          ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                    ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                  ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                  ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                ;
; lpm_width               ; 8           ; Signed Integer                                                                                ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                                ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                                ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                       ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                       ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                       ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                       ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                       ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                       ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                       ;
; USE_EAB                 ; ON          ; Untyped                                                                                       ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                       ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                       ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                       ;
; CBXI_PARAMETER          ; scfifo_aq21 ; Untyped                                                                                       ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic ;
+-------------------------+----------------------------------+-----------------------------------------------------------------+
; Parameter Name          ; Value                            ; Type                                                            ;
+-------------------------+----------------------------------+-----------------------------------------------------------------+
; INSTANCE_ID             ; 0                                ; Signed Integer                                                  ;
; SLD_NODE_INFO           ; 00001100000000000110111000000000 ; Unsigned Binary                                                 ;
; SLD_AUTO_INSTANCE_INDEX ; YES                              ; String                                                          ;
; LOG2_TXFIFO_DEPTH       ; 6                                ; Signed Integer                                                  ;
; LOG2_RXFIFO_DEPTH       ; 6                                ; Signed Integer                                                  ;
; RESERVED                ; 0                                ; Signed Integer                                                  ;
; DATA_WIDTH              ; 8                                ; Signed Integer                                                  ;
; NODE_IR_WIDTH           ; 1                                ; Signed Integer                                                  ;
; SCAN_LENGTH             ; 11                               ; Signed Integer                                                  ;
+-------------------------+----------------------------------+-----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component ;
+-------------------------------+-----------------------+------------------------+
; Parameter Name                ; Value                 ; Type                   ;
+-------------------------------+-----------------------+------------------------+
; OPERATION_MODE                ; NORMAL                ; Untyped                ;
; PLL_TYPE                      ; AUTO                  ; Untyped                ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=pll ; Untyped                ;
; QUALIFY_CONF_DONE             ; OFF                   ; Untyped                ;
; COMPENSATE_CLOCK              ; CLK0                  ; Untyped                ;
; SCAN_CHAIN                    ; LONG                  ; Untyped                ;
; PRIMARY_CLOCK                 ; INCLK0                ; Untyped                ;
; INCLK0_INPUT_FREQUENCY        ; 20000                 ; Signed Integer         ;
; INCLK1_INPUT_FREQUENCY        ; 0                     ; Untyped                ;
; GATE_LOCK_SIGNAL              ; NO                    ; Untyped                ;
; GATE_LOCK_COUNTER             ; 0                     ; Untyped                ;
; LOCK_HIGH                     ; 1                     ; Untyped                ;
; LOCK_LOW                      ; 1                     ; Untyped                ;
; VALID_LOCK_MULTIPLIER         ; 1                     ; Untyped                ;
; INVALID_LOCK_MULTIPLIER       ; 5                     ; Untyped                ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                   ; Untyped                ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                   ; Untyped                ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                   ; Untyped                ;
; SKIP_VCO                      ; OFF                   ; Untyped                ;
; SWITCH_OVER_COUNTER           ; 0                     ; Untyped                ;
; SWITCH_OVER_TYPE              ; AUTO                  ; Untyped                ;
; FEEDBACK_SOURCE               ; EXTCLK0               ; Untyped                ;
; BANDWIDTH                     ; 0                     ; Untyped                ;
; BANDWIDTH_TYPE                ; AUTO                  ; Untyped                ;
; SPREAD_FREQUENCY              ; 0                     ; Untyped                ;
; DOWN_SPREAD                   ; 0                     ; Untyped                ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                   ; Untyped                ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                   ; Untyped                ;
; CLK9_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK8_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK7_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK6_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK5_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK4_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK3_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK2_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK1_MULTIPLY_BY              ; 1                     ; Signed Integer         ;
; CLK0_MULTIPLY_BY              ; 1                     ; Signed Integer         ;
; CLK9_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK8_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK7_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK6_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK5_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK4_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK3_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK2_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK1_DIVIDE_BY                ; 1                     ; Signed Integer         ;
; CLK0_DIVIDE_BY                ; 1                     ; Signed Integer         ;
; CLK9_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK8_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK7_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK6_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK5_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK4_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK3_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK2_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK1_PHASE_SHIFT              ; -3500                 ; Untyped                ;
; CLK0_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK5_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK4_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK3_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK2_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK1_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK0_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK9_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK8_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK7_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK6_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK5_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK4_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK3_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK2_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK1_DUTY_CYCLE               ; 50                    ; Signed Integer         ;
; CLK0_DUTY_CYCLE               ; 50                    ; Signed Integer         ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; LOCK_WINDOW_UI                ;  0.05                 ; Untyped                ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                ; Untyped                ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                ; Untyped                ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                ; Untyped                ;
; DPA_MULTIPLY_BY               ; 0                     ; Untyped                ;
; DPA_DIVIDE_BY                 ; 1                     ; Untyped                ;
; DPA_DIVIDER                   ; 0                     ; Untyped                ;
; EXTCLK3_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK2_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK1_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK0_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK3_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK2_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK1_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK0_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK3_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK2_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK1_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK0_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK3_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK2_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK1_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK0_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK3_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK2_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK1_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK0_DUTY_CYCLE            ; 50                    ; Untyped                ;
; VCO_MULTIPLY_BY               ; 0                     ; Untyped                ;
; VCO_DIVIDE_BY                 ; 0                     ; Untyped                ;
; SCLKOUT0_PHASE_SHIFT          ; 0                     ; Untyped                ;
; SCLKOUT1_PHASE_SHIFT          ; 0                     ; Untyped                ;
; VCO_MIN                       ; 0                     ; Untyped                ;
; VCO_MAX                       ; 0                     ; Untyped                ;
; VCO_CENTER                    ; 0                     ; Untyped                ;
; PFD_MIN                       ; 0                     ; Untyped                ;
; PFD_MAX                       ; 0                     ; Untyped                ;
; M_INITIAL                     ; 0                     ; Untyped                ;
; M                             ; 0                     ; Untyped                ;
; N                             ; 1                     ; Untyped                ;
; M2                            ; 1                     ; Untyped                ;
; N2                            ; 1                     ; Untyped                ;
; SS                            ; 1                     ; Untyped                ;
; C0_HIGH                       ; 0                     ; Untyped                ;
; C1_HIGH                       ; 0                     ; Untyped                ;
; C2_HIGH                       ; 0                     ; Untyped                ;
; C3_HIGH                       ; 0                     ; Untyped                ;
; C4_HIGH                       ; 0                     ; Untyped                ;
; C5_HIGH                       ; 0                     ; Untyped                ;
; C6_HIGH                       ; 0                     ; Untyped                ;
; C7_HIGH                       ; 0                     ; Untyped                ;
; C8_HIGH                       ; 0                     ; Untyped                ;
; C9_HIGH                       ; 0                     ; Untyped                ;
; C0_LOW                        ; 0                     ; Untyped                ;
; C1_LOW                        ; 0                     ; Untyped                ;
; C2_LOW                        ; 0                     ; Untyped                ;
; C3_LOW                        ; 0                     ; Untyped                ;
; C4_LOW                        ; 0                     ; Untyped                ;
; C5_LOW                        ; 0                     ; Untyped                ;
; C6_LOW                        ; 0                     ; Untyped                ;
; C7_LOW                        ; 0                     ; Untyped                ;
; C8_LOW                        ; 0                     ; Untyped                ;
; C9_LOW                        ; 0                     ; Untyped                ;
; C0_INITIAL                    ; 0                     ; Untyped                ;
; C1_INITIAL                    ; 0                     ; Untyped                ;
; C2_INITIAL                    ; 0                     ; Untyped                ;
; C3_INITIAL                    ; 0                     ; Untyped                ;
; C4_INITIAL                    ; 0                     ; Untyped                ;
; C5_INITIAL                    ; 0                     ; Untyped                ;
; C6_INITIAL                    ; 0                     ; Untyped                ;
; C7_INITIAL                    ; 0                     ; Untyped                ;
; C8_INITIAL                    ; 0                     ; Untyped                ;
; C9_INITIAL                    ; 0                     ; Untyped                ;
; C0_MODE                       ; BYPASS                ; Untyped                ;
; C1_MODE                       ; BYPASS                ; Untyped                ;
; C2_MODE                       ; BYPASS                ; Untyped                ;
; C3_MODE                       ; BYPASS                ; Untyped                ;
; C4_MODE                       ; BYPASS                ; Untyped                ;
; C5_MODE                       ; BYPASS                ; Untyped                ;
; C6_MODE                       ; BYPASS                ; Untyped                ;
; C7_MODE                       ; BYPASS                ; Untyped                ;
; C8_MODE                       ; BYPASS                ; Untyped                ;
; C9_MODE                       ; BYPASS                ; Untyped                ;
; C0_PH                         ; 0                     ; Untyped                ;
; C1_PH                         ; 0                     ; Untyped                ;
; C2_PH                         ; 0                     ; Untyped                ;
; C3_PH                         ; 0                     ; Untyped                ;
; C4_PH                         ; 0                     ; Untyped                ;
; C5_PH                         ; 0                     ; Untyped                ;
; C6_PH                         ; 0                     ; Untyped                ;
; C7_PH                         ; 0                     ; Untyped                ;
; C8_PH                         ; 0                     ; Untyped                ;
; C9_PH                         ; 0                     ; Untyped                ;
; L0_HIGH                       ; 1                     ; Untyped                ;
; L1_HIGH                       ; 1                     ; Untyped                ;
; G0_HIGH                       ; 1                     ; Untyped                ;
; G1_HIGH                       ; 1                     ; Untyped                ;
; G2_HIGH                       ; 1                     ; Untyped                ;
; G3_HIGH                       ; 1                     ; Untyped                ;
; E0_HIGH                       ; 1                     ; Untyped                ;
; E1_HIGH                       ; 1                     ; Untyped                ;
; E2_HIGH                       ; 1                     ; Untyped                ;
; E3_HIGH                       ; 1                     ; Untyped                ;
; L0_LOW                        ; 1                     ; Untyped                ;
; L1_LOW                        ; 1                     ; Untyped                ;
; G0_LOW                        ; 1                     ; Untyped                ;
; G1_LOW                        ; 1                     ; Untyped                ;
; G2_LOW                        ; 1                     ; Untyped                ;
; G3_LOW                        ; 1                     ; Untyped                ;
; E0_LOW                        ; 1                     ; Untyped                ;
; E1_LOW                        ; 1                     ; Untyped                ;
; E2_LOW                        ; 1                     ; Untyped                ;
; E3_LOW                        ; 1                     ; Untyped                ;
; L0_INITIAL                    ; 1                     ; Untyped                ;
; L1_INITIAL                    ; 1                     ; Untyped                ;
; G0_INITIAL                    ; 1                     ; Untyped                ;
; G1_INITIAL                    ; 1                     ; Untyped                ;
; G2_INITIAL                    ; 1                     ; Untyped                ;
; G3_INITIAL                    ; 1                     ; Untyped                ;
; E0_INITIAL                    ; 1                     ; Untyped                ;
; E1_INITIAL                    ; 1                     ; Untyped                ;
; E2_INITIAL                    ; 1                     ; Untyped                ;
; E3_INITIAL                    ; 1                     ; Untyped                ;
; L0_MODE                       ; BYPASS                ; Untyped                ;
; L1_MODE                       ; BYPASS                ; Untyped                ;
; G0_MODE                       ; BYPASS                ; Untyped                ;
; G1_MODE                       ; BYPASS                ; Untyped                ;
; G2_MODE                       ; BYPASS                ; Untyped                ;
; G3_MODE                       ; BYPASS                ; Untyped                ;
; E0_MODE                       ; BYPASS                ; Untyped                ;
; E1_MODE                       ; BYPASS                ; Untyped                ;
; E2_MODE                       ; BYPASS                ; Untyped                ;
; E3_MODE                       ; BYPASS                ; Untyped                ;
; L0_PH                         ; 0                     ; Untyped                ;
; L1_PH                         ; 0                     ; Untyped                ;
; G0_PH                         ; 0                     ; Untyped                ;
; G1_PH                         ; 0                     ; Untyped                ;
; G2_PH                         ; 0                     ; Untyped                ;
; G3_PH                         ; 0                     ; Untyped                ;
; E0_PH                         ; 0                     ; Untyped                ;
; E1_PH                         ; 0                     ; Untyped                ;
; E2_PH                         ; 0                     ; Untyped                ;
; E3_PH                         ; 0                     ; Untyped                ;
; M_PH                          ; 0                     ; Untyped                ;
; C1_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C2_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C3_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C4_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C5_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C6_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C7_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C8_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C9_USE_CASC_IN                ; OFF                   ; Untyped                ;
; CLK0_COUNTER                  ; G0                    ; Untyped                ;
; CLK1_COUNTER                  ; G0                    ; Untyped                ;
; CLK2_COUNTER                  ; G0                    ; Untyped                ;
; CLK3_COUNTER                  ; G0                    ; Untyped                ;
; CLK4_COUNTER                  ; G0                    ; Untyped                ;
; CLK5_COUNTER                  ; G0                    ; Untyped                ;
; CLK6_COUNTER                  ; E0                    ; Untyped                ;
; CLK7_COUNTER                  ; E1                    ; Untyped                ;
; CLK8_COUNTER                  ; E2                    ; Untyped                ;
; CLK9_COUNTER                  ; E3                    ; Untyped                ;
; L0_TIME_DELAY                 ; 0                     ; Untyped                ;
; L1_TIME_DELAY                 ; 0                     ; Untyped                ;
; G0_TIME_DELAY                 ; 0                     ; Untyped                ;
; G1_TIME_DELAY                 ; 0                     ; Untyped                ;
; G2_TIME_DELAY                 ; 0                     ; Untyped                ;
; G3_TIME_DELAY                 ; 0                     ; Untyped                ;
; E0_TIME_DELAY                 ; 0                     ; Untyped                ;
; E1_TIME_DELAY                 ; 0                     ; Untyped                ;
; E2_TIME_DELAY                 ; 0                     ; Untyped                ;
; E3_TIME_DELAY                 ; 0                     ; Untyped                ;
; M_TIME_DELAY                  ; 0                     ; Untyped                ;
; N_TIME_DELAY                  ; 0                     ; Untyped                ;
; EXTCLK3_COUNTER               ; E3                    ; Untyped                ;
; EXTCLK2_COUNTER               ; E2                    ; Untyped                ;
; EXTCLK1_COUNTER               ; E1                    ; Untyped                ;
; EXTCLK0_COUNTER               ; E0                    ; Untyped                ;
; ENABLE0_COUNTER               ; L0                    ; Untyped                ;
; ENABLE1_COUNTER               ; L0                    ; Untyped                ;
; CHARGE_PUMP_CURRENT           ; 2                     ; Untyped                ;
; LOOP_FILTER_R                 ;  1.000000             ; Untyped                ;
; LOOP_FILTER_C                 ; 5                     ; Untyped                ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                  ; Untyped                ;
; LOOP_FILTER_R_BITS            ; 9999                  ; Untyped                ;
; LOOP_FILTER_C_BITS            ; 9999                  ; Untyped                ;
; VCO_POST_SCALE                ; 0                     ; Untyped                ;
; CLK2_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; CLK1_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; CLK0_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; INTENDED_DEVICE_FAMILY        ; Cyclone III           ; Untyped                ;
; PORT_CLKENA0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA2                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA3                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA4                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA5                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLK0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK2                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK3                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKBAD0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKBAD1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK0                     ; PORT_USED             ; Untyped                ;
; PORT_CLK1                     ; PORT_USED             ; Untyped                ;
; PORT_CLK2                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK3                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK4                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK5                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK6                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK7                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK8                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK9                     ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDATA                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDATAOUT              ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDONE                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKLOSS                  ; PORT_UNUSED           ; Untyped                ;
; PORT_INCLK1                   ; PORT_UNUSED           ; Untyped                ;
; PORT_INCLK0                   ; PORT_USED             ; Untyped                ;
; PORT_FBIN                     ; PORT_UNUSED           ; Untyped                ;
; PORT_PLLENA                   ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKSWITCH                ; PORT_UNUSED           ; Untyped                ;
; PORT_ARESET                   ; PORT_UNUSED           ; Untyped                ;
; PORT_PFDENA                   ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANCLK                  ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANACLR                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANREAD                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANWRITE                ; PORT_UNUSED           ; Untyped                ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_LOCKED                   ; PORT_UNUSED           ; Untyped                ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED           ; Untyped                ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_PHASEDONE                ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASESTEP                ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANCLKENA               ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED           ; Untyped                ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY     ; Untyped                ;
; M_TEST_SOURCE                 ; 5                     ; Untyped                ;
; C0_TEST_SOURCE                ; 5                     ; Untyped                ;
; C1_TEST_SOURCE                ; 5                     ; Untyped                ;
; C2_TEST_SOURCE                ; 5                     ; Untyped                ;
; C3_TEST_SOURCE                ; 5                     ; Untyped                ;
; C4_TEST_SOURCE                ; 5                     ; Untyped                ;
; C5_TEST_SOURCE                ; 5                     ; Untyped                ;
; C6_TEST_SOURCE                ; 5                     ; Untyped                ;
; C7_TEST_SOURCE                ; 5                     ; Untyped                ;
; C8_TEST_SOURCE                ; 5                     ; Untyped                ;
; C9_TEST_SOURCE                ; 5                     ; Untyped                ;
; CBXI_PARAMETER                ; pll_altpll            ; Untyped                ;
; VCO_FREQUENCY_CONTROL         ; AUTO                  ; Untyped                ;
; VCO_PHASE_SHIFT_STEP          ; 0                     ; Untyped                ;
; WIDTH_CLOCK                   ; 5                     ; Signed Integer         ;
; WIDTH_PHASECOUNTERSELECT      ; 4                     ; Untyped                ;
; USING_FBMIMICBIDIR_PORT       ; OFF                   ; Untyped                ;
; DEVICE_FAMILY                 ; Cyclone III           ; Untyped                ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                ; Untyped                ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                   ; Untyped                ;
; AUTO_CARRY_CHAINS             ; ON                    ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS          ; OFF                   ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS           ; ON                    ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS        ; OFF                   ; IGNORE_CASCADE         ;
+-------------------------------+-----------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub                                             ;
+--------------------------+------------------------------------------------------------------+-----------------+
; Parameter Name           ; Value                                                            ; Type            ;
+--------------------------+------------------------------------------------------------------+-----------------+
; sld_hub_ip_version       ; 1                                                                ; Untyped         ;
; sld_hub_ip_minor_version ; 4                                                                ; Untyped         ;
; sld_common_ip_version    ; 0                                                                ; Untyped         ;
; device_family            ; Cyclone III                                                      ; Untyped         ;
; n_nodes                  ; 2                                                                ; Untyped         ;
; n_sel_bits               ; 2                                                                ; Untyped         ;
; n_node_ir_bits           ; 5                                                                ; Untyped         ;
; node_info                ; 0000110000000000011011100000000000011001000100000100011000000000 ; Unsigned Binary ;
; compilation_mode         ; 1                                                                ; Untyped         ;
; BROADCAST_FEATURE        ; 1                                                                ; Signed Integer  ;
; FORCE_IR_CAPTURE_FEATURE ; 1                                                                ; Signed Integer  ;
+--------------------------+------------------------------------------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                                                                                                                                                                                 ;
+-------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                                      ; Value                                                                                                                                                                                                                ;
+-------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances                ; 6                                                                                                                                                                                                                    ;
; Entity Instance                           ; sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram                                                                                                                                                                      ;
;     -- OPERATION_MODE                     ; SINGLE_PORT                                                                                                                                                                                                          ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 25000                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- WIDTH_B                            ; 1                                                                                                                                                                                                                    ;
;     -- NUMWORDS_B                         ; 1                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                               ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                 ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                            ;
; Entity Instance                           ; sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram                                                                                                                                                                      ;
;     -- OPERATION_MODE                     ; SINGLE_PORT                                                                                                                                                                                                          ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 2048                                                                                                                                                                                                                 ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- WIDTH_B                            ; 1                                                                                                                                                                                                                    ;
;     -- NUMWORDS_B                         ; 1                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                               ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                 ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                            ;
; Entity Instance                           ; sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram                                                                                                               ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                            ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 32                                                                                                                                                                                                                   ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                                   ;
;     -- NUMWORDS_B                         ; 32                                                                                                                                                                                                                   ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                               ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                 ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                            ;
; Entity Instance                           ; sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram                                                                                                               ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                            ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 32                                                                                                                                                                                                                   ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                                   ;
;     -- NUMWORDS_B                         ; 32                                                                                                                                                                                                                   ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                               ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                 ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                            ;
; Entity Instance                           ; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram     ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                                      ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 256                                                                                                                                                                                                                  ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                                   ;
;     -- NUMWORDS_B                         ; 256                                                                                                                                                                                                                  ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                               ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                 ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                             ;
; Entity Instance                           ; sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                                      ;
;     -- WIDTH_A                            ; 36                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 128                                                                                                                                                                                                                  ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- WIDTH_B                            ; 36                                                                                                                                                                                                                   ;
;     -- NUMWORDS_B                         ; 128                                                                                                                                                                                                                  ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                               ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                         ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                 ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                             ;
+-------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                          ;
+----------------------------+------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                    ;
+----------------------------+------------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                        ;
; Entity Instance            ; sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo ;
;     -- FIFO Type           ; Single Clock                                                                             ;
;     -- lpm_width           ; 8                                                                                        ;
;     -- LPM_NUMWORDS        ; 64                                                                                       ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                      ;
;     -- USE_EAB             ; ON                                                                                       ;
; Entity Instance            ; sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo ;
;     -- FIFO Type           ; Single Clock                                                                             ;
;     -- lpm_width           ; 8                                                                                        ;
;     -- LPM_NUMWORDS        ; 64                                                                                       ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                      ;
;     -- USE_EAB             ; ON                                                                                       ;
+----------------------------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                      ;
+-------------------------------+-----------------------------------+
; Name                          ; Value                             ;
+-------------------------------+-----------------------------------+
; Number of entity instances    ; 1                                 ;
; Entity Instance               ; pll:inst1|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                            ;
;     -- PLL_TYPE               ; AUTO                              ;
;     -- PRIMARY_CLOCK          ; INCLK0                            ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                             ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                 ;
;     -- VCO_MULTIPLY_BY        ; 0                                 ;
;     -- VCO_DIVIDE_BY          ; 0                                 ;
+-------------------------------+-----------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch" ;
+---------+-------+----------+-----------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                     ;
+---------+-------+----------+-----------------------------------------------------------------------------+
; data_in ; Input ; Info     ; Stuck at VCC                                                                ;
+---------+-------+----------+-----------------------------------------------------------------------------+


+-------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|sysid:the_sysid" ;
+-------+-------+----------+----------------------------+
; Port  ; Type  ; Severity ; Details                    ;
+-------+-------+----------+----------------------------+
; clock ; Input ; Info     ; Stuck at GND               ;
+-------+-------+----------+----------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"                                                                       ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                                                                                                                      ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; raw_tck        ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tck            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tdi            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; rti            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; shift          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; update         ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; usr1           ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; clr            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; ena            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; ir_in          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tdo            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; irq            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; ir_out         ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; jtag_state_cdr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; jtag_state_sdr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; jtag_state_udr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave"                                                ;
+---------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                              ; Type   ; Severity ; Details                                                                             ;
+---------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; jtag_uart_avalon_jtag_slave_dataavailable_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; jtag_uart_avalon_jtag_slave_readyfordata_from_sa  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy" ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                                 ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; virtual_state_e1dr ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; virtual_state_pdr  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; virtual_state_e2dr ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; virtual_state_cir  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; tms                ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_tlr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_sdrs    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_cdr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_sdr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_e1dr    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_pdr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_e2dr    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_udr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_sirs    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_cir     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_sir     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_e1ir    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_pir     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_e2ir    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
; jtag_state_uir     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3" ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                                                                                                                                                                                 ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_n ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                                            ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2" ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                                                                                                                                                                                 ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_n ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                                            ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component" ;
+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port      ; Type   ; Severity ; Details                                                                                                                                                                                ;
+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; address_b ; Input  ; Warning  ; Input port expression (17 bits) is wider than the input port (7 bits) it drives.  The 10 most-significant bit(s) in the expression will be dangling if they have no other fanouts.     ;
; clocken0  ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                           ;
; clocken1  ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                           ;
; q_a       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                    ;
; q_b       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                    ;
+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib" ;
+---------+--------+----------+---------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                 ;
+---------+--------+----------+---------------------------------------------------------------------------------------------------------+
; clkx2   ; Input  ; Info     ; Stuck at GND                                                                                            ;
; tr_clk  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                     ;
; tr_data ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                     ;
+---------+--------+----------+---------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp" ;
+------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                                                                                                             ;
+------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; fifowp_inc ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                 ;
+------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode" ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                                                                                ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; td_mode ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                    ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace"                                                                   ;
+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                             ;
+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; jdo  ; Input ; Warning  ; Input port expression (38 bits) is wider than the input port (16 bits) it drives.  The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk" ;
+--------------+--------+----------+------------------------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                                              ;
+--------------+--------+----------+------------------------------------------------------------------------------------------------------+
; dbrk_trigout ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                  ;
+--------------+--------+----------+------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk" ;
+--------------+--------+----------+------------------------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                                              ;
+--------------+--------+----------+------------------------------------------------------------------------------------------------------+
; xbrk_trigout ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                  ;
+--------------+--------+----------+------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component" ;
+----------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                                                                                                                              ;
+----------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; clocken0 ; Input ; Info     ; Stuck at VCC                                                                                                                                                                         ;
; clocken1 ; Input ; Info     ; Stuck at VCC                                                                                                                                                                         ;
+----------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug" ;
+----------+-------+----------+-------------------------------------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                                                     ;
+----------+-------+----------+-------------------------------------------------------------------------------------------------------------+
; debugreq ; Input ; Info     ; Stuck at GND                                                                                                ;
+----------+-------+----------+-------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci"                                    ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; oci_ienable[31..3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench" ;
+-----------------+-------+----------+--------------------------------------------------------+
; Port            ; Type  ; Severity ; Details                                                ;
+-----------------+-------+----------+--------------------------------------------------------+
; F_pcb[1..0]     ; Input ; Info     ; Stuck at GND                                           ;
; i_address[1..0] ; Input ; Info     ; Stuck at GND                                           ;
+-----------------+-------+----------+--------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sopc:inst|RS232_UART_s1_arbitrator:the_RS232_UART_s1"                                                              ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                ; Type   ; Severity ; Details                                                                             ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; RS232_UART_s1_dataavailable_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; RS232_UART_s1_readyfordata_from_sa  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:10     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
    Info: Processing started: Thu Feb 09 16:29:18 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sd -c sd
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 2 design units, including 1 entities, in source file pll.vhd
    Info: Found design unit 1: pll-SYN
    Info: Found entity 1: pll
Info: Found 1 design units, including 1 entities, in source file sd.bdf
    Info: Found entity 1: sd
Info: Elaborating entity "sd" for the top level hierarchy
Warning: Using design file sopc.v, which is not specified as a design file for the current project, but contains definitions for 15 design units and 15 entities in project
    Info: Found entity 1: RAM_s1_arbitrator
    Info: Found entity 2: ROM_s1_arbitrator
    Info: Found entity 3: RS232_UART_s1_arbitrator
    Info: Found entity 4: clk_spi_s1_arbitrator
    Info: Found entity 5: cpu_0_jtag_debug_module_arbitrator
    Info: Found entity 6: cpu_0_data_master_arbitrator
    Info: Found entity 7: cpu_0_instruction_master_arbitrator
    Info: Found entity 8: cs_spi_s1_arbitrator
    Info: Found entity 9: di_spi_s1_arbitrator
    Info: Found entity 10: do_spi_s1_arbitrator
    Info: Found entity 11: jtag_uart_avalon_jtag_slave_arbitrator
    Info: Found entity 12: sysid_control_slave_arbitrator
    Info: Found entity 13: timer_s1_arbitrator
    Info: Found entity 14: sopc_reset_clk_0_domain_synch_module
    Info: Found entity 15: sopc
Info: Elaborating entity "sopc" for hierarchy "sopc:inst"
Info: Elaborating entity "RAM_s1_arbitrator" for hierarchy "sopc:inst|RAM_s1_arbitrator:the_RAM_s1"
Warning: Using design file ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: RAM
Info: Elaborating entity "RAM" for hierarchy "sopc:inst|RAM:the_RAM"
Info: Elaborating entity "altsyncram" for hierarchy "sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram"
Info: Instantiated megafunction "sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "byte_size" = "8"
    Info: Parameter "init_file" = "RAM.hex"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "maximum_depth" = "25000"
    Info: Parameter "numwords_a" = "25000"
    Info: Parameter "operation_mode" = "SINGLE_PORT"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_byteena_a" = "4"
    Info: Parameter "widthad_a" = "15"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_32b1.tdf
    Info: Found entity 1: altsyncram_32b1
Info: Elaborating entity "altsyncram_32b1" for hierarchy "sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated"
Warning: Width of data items in "RAM.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 3125 warnings, reporting 10
    Warning: Data at line (2) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (3) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (4) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (5) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (6) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (7) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (8) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (9) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (10) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (11) of memory initialization file "RAM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Info: Found 1 design units, including 1 entities, in source file db/decode_dra.tdf
    Info: Found entity 1: decode_dra
Info: Elaborating entity "decode_dra" for hierarchy "sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated|decode_dra:decode3"
Info: Found 1 design units, including 1 entities, in source file db/mux_anb.tdf
    Info: Found entity 1: mux_anb
Info: Elaborating entity "mux_anb" for hierarchy "sopc:inst|RAM:the_RAM|altsyncram:the_altsyncram|altsyncram_32b1:auto_generated|mux_anb:mux2"
Info: Elaborating entity "ROM_s1_arbitrator" for hierarchy "sopc:inst|ROM_s1_arbitrator:the_ROM_s1"
Warning: Using design file rom.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ROM
Info: Elaborating entity "ROM" for hierarchy "sopc:inst|ROM:the_ROM"
Info: Elaborating entity "altsyncram" for hierarchy "sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram"
Info: Instantiated megafunction "sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "byte_size" = "8"
    Info: Parameter "init_file" = "ROM.hex"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "maximum_depth" = "2048"
    Info: Parameter "numwords_a" = "2048"
    Info: Parameter "operation_mode" = "SINGLE_PORT"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_byteena_a" = "4"
    Info: Parameter "widthad_a" = "11"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rva1.tdf
    Info: Found entity 1: altsyncram_rva1
Info: Elaborating entity "altsyncram_rva1" for hierarchy "sopc:inst|ROM:the_ROM|altsyncram:the_altsyncram|altsyncram_rva1:auto_generated"
Warning: Width of data items in "ROM.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 256 warnings, reporting 10
    Warning: Data at line (2) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (3) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (4) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (5) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (6) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (7) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (8) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (9) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (10) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
    Warning: Data at line (11) of memory initialization file "ROM.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
Info: Elaborating entity "RS232_UART_s1_arbitrator" for hierarchy "sopc:inst|RS232_UART_s1_arbitrator:the_RS232_UART_s1"
Warning: Using design file rs232_uart.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project
    Info: Found entity 1: RS232_UART_log_module
    Info: Found entity 2: RS232_UART_tx
    Info: Found entity 3: RS232_UART_rx_stimulus_source_character_source_rom_module
    Info: Found entity 4: RS232_UART_rx_stimulus_source
    Info: Found entity 5: RS232_UART_rx
    Info: Found entity 6: RS232_UART_regs
    Info: Found entity 7: RS232_UART
Info: Elaborating entity "RS232_UART" for hierarchy "sopc:inst|RS232_UART:the_RS232_UART"
Info: Elaborating entity "RS232_UART_tx" for hierarchy "sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_tx:the_RS232_UART_tx"
Info: Elaborating entity "RS232_UART_rx" for hierarchy "sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx"
Info: Elaborating entity "RS232_UART_rx_stimulus_source" for hierarchy "sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|RS232_UART_rx_stimulus_source:the_RS232_UART_rx_stimulus_source"
Info: Elaborating entity "altera_std_synchronizer" for hierarchy "sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer"
Info: Elaborated megafunction instantiation "sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer"
Info: Instantiated megafunction "sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_rx:the_RS232_UART_rx|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter:
    Info: Parameter "depth" = "2"
Info: Elaborating entity "RS232_UART_regs" for hierarchy "sopc:inst|RS232_UART:the_RS232_UART|RS232_UART_regs:the_RS232_UART_regs"
Info: Elaborating entity "clk_spi_s1_arbitrator" for hierarchy "sopc:inst|clk_spi_s1_arbitrator:the_clk_spi_s1"
Warning: Using design file clk_spi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: clk_spi
Info: Elaborating entity "clk_spi" for hierarchy "sopc:inst|clk_spi:the_clk_spi"
Info: Elaborating entity "cpu_0_jtag_debug_module_arbitrator" for hierarchy "sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module"
Info: Elaborating entity "cpu_0_data_master_arbitrator" for hierarchy "sopc:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master"
Info: Elaborating entity "cpu_0_instruction_master_arbitrator" for hierarchy "sopc:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master"
Warning: Using design file cpu_0.v, which is not specified as a design file for the current project, but contains definitions for 22 design units and 22 entities in project
    Info: Found entity 1: cpu_0_register_bank_a_module
    Info: Found entity 2: cpu_0_register_bank_b_module
    Info: Found entity 3: cpu_0_nios2_oci_debug
    Info: Found entity 4: cpu_0_ociram_lpm_dram_bdp_component_module
    Info: Found entity 5: cpu_0_nios2_ocimem
    Info: Found entity 6: cpu_0_nios2_avalon_reg
    Info: Found entity 7: cpu_0_nios2_oci_break
    Info: Found entity 8: cpu_0_nios2_oci_xbrk
    Info: Found entity 9: cpu_0_nios2_oci_dbrk
    Info: Found entity 10: cpu_0_nios2_oci_itrace
    Info: Found entity 11: cpu_0_nios2_oci_td_mode
    Info: Found entity 12: cpu_0_nios2_oci_dtrace
    Info: Found entity 13: cpu_0_nios2_oci_compute_tm_count
    Info: Found entity 14: cpu_0_nios2_oci_fifowp_inc
    Info: Found entity 15: cpu_0_nios2_oci_fifocount_inc
    Info: Found entity 16: cpu_0_nios2_oci_fifo
    Info: Found entity 17: cpu_0_nios2_oci_pib
    Info: Found entity 18: cpu_0_traceram_lpm_dram_bdp_component_module
    Info: Found entity 19: cpu_0_nios2_oci_im
    Info: Found entity 20: cpu_0_nios2_performance_monitors
    Info: Found entity 21: cpu_0_nios2_oci
    Info: Found entity 22: cpu_0
Info: Elaborating entity "cpu_0" for hierarchy "sopc:inst|cpu_0:the_cpu_0"
Warning: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_test_bench
Info: Elaborating entity "cpu_0_test_bench" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench"
Info: Elaborating entity "cpu_0_register_bank_a_module" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a"
Info: Elaborating entity "altsyncram" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram"
Info: Instantiated megafunction "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_0_rf_ram_a.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "32"
    Info: Parameter "numwords_b" = "32"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "widthad_a" = "5"
    Info: Parameter "widthad_b" = "5"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_8ef1.tdf
    Info: Found entity 1: altsyncram_8ef1
Info: Elaborating entity "altsyncram_8ef1" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_8ef1:auto_generated"
Info: Elaborating entity "cpu_0_register_bank_b_module" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b"
Info: Elaborating entity "altsyncram" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram"
Info: Instantiated megafunction "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_0_rf_ram_b.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "32"
    Info: Parameter "numwords_b" = "32"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "widthad_a" = "5"
    Info: Parameter "widthad_b" = "5"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9ef1.tdf
    Info: Found entity 1: altsyncram_9ef1
Info: Elaborating entity "altsyncram_9ef1" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_9ef1:auto_generated"
Info: Elaborating entity "cpu_0_nios2_oci" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci"
Info: Elaborating entity "cpu_0_nios2_oci_debug" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug"
Info: Elaborating entity "cpu_0_nios2_ocimem" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem"
Info: Elaborating entity "cpu_0_ociram_lpm_dram_bdp_component_module" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Instantiated megafunction "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_aclr_a" = "NONE"
    Info: Parameter "address_aclr_b" = "NONE"
    Info: Parameter "address_reg_b" = "CLOCK1"
    Info: Parameter "indata_aclr_a" = "NONE"
    Info: Parameter "indata_aclr_b" = "NONE"
    Info: Parameter "init_file" = "cpu_0_ociram_default_contents.mif"
    Info: Parameter "intended_device_family" = "CYCLONEIII"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "256"
    Info: Parameter "numwords_b" = "256"
    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    Info: Parameter "outdata_aclr_a" = "NONE"
    Info: Parameter "outdata_aclr_b" = "NONE"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "width_byteena_a" = "4"
    Info: Parameter "widthad_a" = "8"
    Info: Parameter "widthad_b" = "8"
    Info: Parameter "wrcontrol_aclr_a" = "NONE"
    Info: Parameter "wrcontrol_aclr_b" = "NONE"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l872.tdf
    Info: Found entity 1: altsyncram_l872
Info: Elaborating entity "altsyncram_l872" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated"
Info: Elaborating entity "cpu_0_nios2_avalon_reg" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg"
Info: Elaborating entity "cpu_0_nios2_oci_break" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break"
Info: Elaborating entity "cpu_0_nios2_oci_xbrk" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk"
Info: Elaborating entity "cpu_0_nios2_oci_dbrk" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk"
Info: Elaborating entity "cpu_0_nios2_oci_itrace" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace"
Info: Elaborating entity "cpu_0_nios2_oci_dtrace" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace"
Info: Elaborating entity "cpu_0_nios2_oci_td_mode" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode"
Info: Elaborating entity "cpu_0_nios2_oci_fifo" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo"
Info: Elaborating entity "cpu_0_nios2_oci_compute_tm_count" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count"
Info: Elaborating entity "cpu_0_nios2_oci_fifowp_inc" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp"
Info: Elaborating entity "cpu_0_nios2_oci_fifocount_inc" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount"
Warning: Using design file cpu_0_oci_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_oci_test_bench
Info: Elaborating entity "cpu_0_oci_test_bench" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_oci_test_bench:the_cpu_0_oci_test_bench"
Info: Elaborating entity "cpu_0_nios2_oci_pib" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib"
Info: Elaborating entity "cpu_0_nios2_oci_im" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im"
Info: Elaborating entity "cpu_0_traceram_lpm_dram_bdp_component_module" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Instantiated megafunction "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_aclr_a" = "NONE"
    Info: Parameter "address_aclr_b" = "NONE"
    Info: Parameter "address_reg_b" = "CLOCK1"
    Info: Parameter "indata_aclr_a" = "NONE"
    Info: Parameter "indata_aclr_b" = "NONE"
    Info: Parameter "init_file" = "UNUSED"
    Info: Parameter "intended_device_family" = "CYCLONEIII"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "128"
    Info: Parameter "numwords_b" = "128"
    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    Info: Parameter "outdata_aclr_a" = "NONE"
    Info: Parameter "outdata_aclr_b" = "NONE"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "36"
    Info: Parameter "width_b" = "36"
    Info: Parameter "widthad_a" = "7"
    Info: Parameter "widthad_b" = "7"
    Info: Parameter "wrcontrol_aclr_a" = "NONE"
    Info: Parameter "wrcontrol_aclr_b" = "NONE"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_n802.tdf
    Info: Found entity 1: altsyncram_n802
Info: Elaborating entity "altsyncram_n802" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated"
Warning: Using design file cpu_0_jtag_debug_module_wrapper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_jtag_debug_module_wrapper
Info: Elaborating entity "cpu_0_jtag_debug_module_wrapper" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper"
Warning: Using design file cpu_0_jtag_debug_module_tck.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_jtag_debug_module_tck
Info: Elaborating entity "cpu_0_jtag_debug_module_tck" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck"
Warning: Using design file cpu_0_jtag_debug_module_sysclk.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_jtag_debug_module_sysclk
Info: Elaborating entity "cpu_0_jtag_debug_module_sysclk" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk"
Info: Elaborating entity "sld_virtual_jtag_basic" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy"
Info: Elaborated megafunction instantiation "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy"
Info: Instantiated megafunction "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy" with the following parameter:
    Info: Parameter "sld_auto_instance_index" = "YES"
    Info: Parameter "sld_instance_index" = "0"
    Info: Parameter "sld_ir_width" = "2"
    Info: Parameter "sld_mfg_id" = "70"
    Info: Parameter "sld_sim_action" = ""
    Info: Parameter "sld_sim_n_scan" = "0"
    Info: Parameter "sld_sim_total_length" = "0"
    Info: Parameter "sld_type_id" = "34"
    Info: Parameter "sld_version" = "3"
Info: Elaborating entity "sld_virtual_jtag_impl" for hierarchy "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst"
Info: Elaborated megafunction instantiation "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy"
Info: Elaborating entity "cs_spi_s1_arbitrator" for hierarchy "sopc:inst|cs_spi_s1_arbitrator:the_cs_spi_s1"
Warning: Using design file cs_spi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cs_spi
Info: Elaborating entity "cs_spi" for hierarchy "sopc:inst|cs_spi:the_cs_spi"
Info: Elaborating entity "di_spi_s1_arbitrator" for hierarchy "sopc:inst|di_spi_s1_arbitrator:the_di_spi_s1"
Warning: Using design file di_spi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: di_spi
Info: Elaborating entity "di_spi" for hierarchy "sopc:inst|di_spi:the_di_spi"
Info: Elaborating entity "do_spi_s1_arbitrator" for hierarchy "sopc:inst|do_spi_s1_arbitrator:the_do_spi_s1"
Warning: Using design file do_spi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: do_spi
Info: Elaborating entity "do_spi" for hierarchy "sopc:inst|do_spi:the_do_spi"
Info: Elaborating entity "jtag_uart_avalon_jtag_slave_arbitrator" for hierarchy "sopc:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave"
Warning: Using design file jtag_uart.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project
    Info: Found entity 1: jtag_uart_log_module
    Info: Found entity 2: jtag_uart_sim_scfifo_w
    Info: Found entity 3: jtag_uart_scfifo_w
    Info: Found entity 4: jtag_uart_drom_module
    Info: Found entity 5: jtag_uart_sim_scfifo_r
    Info: Found entity 6: jtag_uart_scfifo_r
    Info: Found entity 7: jtag_uart
Info: Elaborating entity "jtag_uart" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart"
Info: Elaborating entity "jtag_uart_scfifo_w" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w"
Info: Elaborating entity "scfifo" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo"
Info: Elaborated megafunction instantiation "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo"
Info: Instantiated megafunction "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo" with the following parameter:
    Info: Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO"
    Info: Parameter "lpm_numwords" = "64"
    Info: Parameter "lpm_showahead" = "OFF"
    Info: Parameter "lpm_type" = "scfifo"
    Info: Parameter "lpm_width" = "8"
    Info: Parameter "lpm_widthu" = "6"
    Info: Parameter "overflow_checking" = "OFF"
    Info: Parameter "underflow_checking" = "OFF"
    Info: Parameter "use_eab" = "ON"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_aq21.tdf
    Info: Found entity 1: scfifo_aq21
Info: Elaborating entity "scfifo_aq21" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_h031.tdf
    Info: Found entity 1: a_dpfifo_h031
Info: Elaborating entity "a_dpfifo_h031" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf
    Info: Found entity 1: a_fefifo_7cf
Info: Elaborating entity "a_fefifo_7cf" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_4n7.tdf
    Info: Found entity 1: cntr_4n7
Info: Elaborating entity "cntr_4n7" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_ek21.tdf
    Info: Found entity 1: dpram_ek21
Info: Elaborating entity "dpram_ek21" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_i0m1.tdf
    Info: Found entity 1: altsyncram_i0m1
Info: Elaborating entity "altsyncram_i0m1" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1"
Info: Found 1 design units, including 1 entities, in source file db/cntr_omb.tdf
    Info: Found entity 1: cntr_omb
Info: Elaborating entity "cntr_omb" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:rd_ptr_count"
Info: Elaborating entity "jtag_uart_scfifo_r" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r"
Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"
Info: Elaborated megafunction instantiation "sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"
Info: Instantiated megafunction "sopc:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic" with the following parameter:
    Info: Parameter "INSTANCE_ID" = "0"
    Info: Parameter "LOG2_RXFIFO_DEPTH" = "6"
    Info: Parameter "LOG2_TXFIFO_DEPTH" = "6"
    Info: Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES"
Info: Elaborating entity "sysid_control_slave_arbitrator" for hierarchy "sopc:inst|sysid_control_slave_arbitrator:the_sysid_control_slave"
Warning: Using design file sysid.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sysid
Info: Elaborating entity "sysid" for hierarchy "sopc:inst|sysid:the_sysid"
Info: Elaborating entity "timer_s1_arbitrator" for hierarchy "sopc:inst|timer_s1_arbitrator:the_timer_s1"
Warning: Using design file timer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: timer
Info: Elaborating entity "timer" for hierarchy "sopc:inst|timer:the_timer"
Info: Elaborating entity "sopc_reset_clk_0_domain_synch_module" for hierarchy "sopc:inst|sopc_reset_clk_0_domain_synch_module:sopc_reset_clk_0_domain_synch"
Info: Elaborating entity "pll" for hierarchy "pll:inst1"
Info: Elaborating entity "altpll" for hierarchy "pll:inst1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "pll:inst1|altpll:altpll_component"
Info: Instantiated megafunction "pll:inst1|altpll:altpll_component" with the following parameter:
    Info: Parameter "bandwidth_type" = "AUTO"
    Info: Parameter "clk0_divide_by" = "1"
    Info: Parameter "clk0_duty_cycle" = "50"
    Info: Parameter "clk0_multiply_by" = "1"
    Info: Parameter "clk0_phase_shift" = "0"
    Info: Parameter "clk1_divide_by" = "1"
    Info: Parameter "clk1_duty_cycle" = "50"
    Info: Parameter "clk1_multiply_by" = "1"
    Info: Parameter "clk1_phase_shift" = "-3500"
    Info: Parameter "compensate_clock" = "CLK0"
    Info: Parameter "inclk0_input_frequency" = "20000"
    Info: Parameter "intended_device_family" = "Cyclone III"
    Info: Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll"
    Info: Parameter "lpm_type" = "altpll"
    Info: Parameter "operation_mode" = "NORMAL"
    Info: Parameter "pll_type" = "AUTO"
    Info: Parameter "port_activeclock" = "PORT_UNUSED"
    Info: Parameter "port_areset" = "PORT_UNUSED"
    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
    Info: Parameter "port_clkloss" = "PORT_UNUSED"
    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
    Info: Parameter "port_configupdate" = "PORT_UNUSED"
    Info: Parameter "port_fbin" = "PORT_UNUSED"
    Info: Parameter "port_inclk0" = "PORT_USED"
    Info: Parameter "port_inclk1" = "PORT_UNUSED"
    Info: Parameter "port_locked" = "PORT_UNUSED"
    Info: Parameter "port_pfdena" = "PORT_UNUSED"
    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info: Parameter "port_phasedone" = "PORT_UNUSED"
    Info: Parameter "port_phasestep" = "PORT_UNUSED"
    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info: Parameter "port_pllena" = "PORT_UNUSED"
    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
    Info: Parameter "port_scanclk" = "PORT_UNUSED"
    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
    Info: Parameter "port_scandata" = "PORT_UNUSED"
    Info: Parameter "port_scandataout" = "PORT_UNUSED"
    Info: Parameter "port_scandone" = "PORT_UNUSED"
    Info: Parameter "port_scanread" = "PORT_UNUSED"
    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
    Info: Parameter "port_clk0" = "PORT_USED"
    Info: Parameter "port_clk1" = "PORT_USED"
    Info: Parameter "port_clk2" = "PORT_UNUSED"
    Info: Parameter "port_clk3" = "PORT_UNUSED"
    Info: Parameter "port_clk4" = "PORT_UNUSED"
    Info: Parameter "port_clk5" = "PORT_UNUSED"
    Info: Parameter "port_clkena0" = "PORT_UNUSED"
    Info: Parameter "port_clkena1" = "PORT_UNUSED"
    Info: Parameter "port_clkena2" = "PORT_UNUSED"
    Info: Parameter "port_clkena3" = "PORT_UNUSED"
    Info: Parameter "port_clkena4" = "PORT_UNUSED"
    Info: Parameter "port_clkena5" = "PORT_UNUSED"
    Info: Parameter "port_extclk0" = "PORT_UNUSED"
    Info: Parameter "port_extclk1" = "PORT_UNUSED"
    Info: Parameter "port_extclk2" = "PORT_UNUSED"
    Info: Parameter "port_extclk3" = "PORT_UNUSED"
    Info: Parameter "width_clock" = "5"
Info: Found 1 design units, including 1 entities, in source file db/pll_altpll.v
    Info: Found entity 1: pll_altpll
Info: Elaborating entity "pll_altpll" for hierarchy "pll:inst1|altpll:altpll_component|pll_altpll:auto_generated"
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[0]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[1]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[2]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[3]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[4]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[5]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[6]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[7]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[8]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[9]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[10]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[11]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[12]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[13]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[14]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[15]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[16]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[17]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[18]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[19]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[20]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[21]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[22]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[23]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[24]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[25]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[26]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[27]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[28]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[29]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[30]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[31]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[32]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[33]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[34]"
        Warning (14320): Synthesized away node "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[35]"
Warning: 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning: The following nodes have both tri-state and non-tri-state drivers
    Warning: Inserted always-enabled tri-state buffer between "SDR_CLK" and its non-tri-state driver.
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "SDR_CLK~synth"
Info: Timing-Driven Synthesis is running on partition "Top"
Info: 74 registers lost all their fanouts during netlist optimizations. The first 74 are displayed below.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[0]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[1]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[2]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[3]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[4]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[5]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[6]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[7]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[8]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[9]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[10]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[11]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[12]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[13]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[14]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[15]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[16]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[17]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[18]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[19]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[20]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[21]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[22]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[23]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[24]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[25]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[26]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[27]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[28]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[29]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[30]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[31]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[34]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[33]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[32]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[35]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[0]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[16]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[15]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[14]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[13]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[12]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[11]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[10]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[9]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[8]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[7]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[6]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[5]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[4]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[3]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[2]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[1]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_reg_firsttransfer" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_arb_share_counter" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|ROM_s1_arbitrator:the_ROM_s1|last_cycle_cpu_0_instruction_master_granted_slave_ROM_s1" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|ROM_s1_arbitrator:the_ROM_s1|last_cycle_cpu_0_data_master_granted_slave_ROM_s1" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_reg_firsttransfer" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_arb_share_counter" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|RAM_s1_arbitrator:the_RAM_s1|last_cycle_cpu_0_instruction_master_granted_slave_RAM_s1" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|RAM_s1_arbitrator:the_RAM_s1|last_cycle_cpu_0_data_master_granted_slave_RAM_s1" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_reg_firsttransfer" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|RAM_s1_arbitrator:the_RAM_s1|RAM_s1_saved_chosen_master_vector[0]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|ROM_s1_arbitrator:the_ROM_s1|ROM_s1_saved_chosen_master_vector[0]" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~3" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~4" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~5" lost all its fanouts during netlist optimizations.
    Info: Register "sopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.101" lost all its fanouts during netlist optimizations.
Info: Generated suppressed messages file E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/sd.map.smsg
Info: Generating hard_block partition "hard_block:auto_generated_inst"
    Info: Adding node "pll:inst1|altpll:altpll_component|pll_altpll:auto_generated|pll1"
Info: Implemented 2234 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 5 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 1948 logic cells
    Info: Implemented 272 RAM segments
    Info: Implemented 1 PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 82 warnings
    Info: Peak virtual memory: 322 megabytes
    Info: Processing ended: Thu Feb 09 16:29:44 2012
    Info: Elapsed time: 00:00:26
    Info: Total CPU time (on all processors): 00:00:22


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/Program/CD_FPGA_CN/data/program/EP3C40/EP3C40/EP3C40/nios/sd_card_OK/sd.map.smsg.


