Analysis & Synthesis report for sdram_test
Thu May 03 11:15:01 2012
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis DSP Block Usage Summary
 10. Analysis & Synthesis IP Cores Summary
 11. State Machine - |NIOS|sdram_0:the_sdram_0|m_next
 12. State Machine - |NIOS|sdram_0:the_sdram_0|m_state
 13. State Machine - |NIOS|sdram_0:the_sdram_0|i_next
 14. State Machine - |NIOS|sdram_0:the_sdram_0|i_state
 15. State Machine - |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize
 16. State Machine - |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_master_FSM:master_FSM|master_state
 17. State Machine - |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_slave_FSM:slave_FSM|slave_state
 18. State Machine - |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_master_FSM:master_FSM|master_state
 19. State Machine - |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_slave_FSM:slave_FSM|slave_state
 20. State Machine - |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_master_FSM:master_FSM|master_state
 21. State Machine - |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_slave_FSM:slave_FSM|slave_state
 22. State Machine - |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_master_FSM:master_FSM|master_state
 23. State Machine - |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_slave_FSM:slave_FSM|slave_state
 24. Registers Protected by Synthesis
 25. Registers Removed During Synthesis
 26. Removed Registers Triggering Further Register Optimizations
 27. General Register Statistics
 28. Inverted Register Statistics
 29. Multiplexer Restructuring Statistics (Restructuring Performed)
 30. Source assignments for NIOS_clock_0:the_NIOS_clock_0
 31. Source assignments for NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer
 32. Source assignments for NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1
 33. Source assignments for NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2
 34. Source assignments for NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3
 35. Source assignments for NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_bit_pipe:endofpacket_bit_pipe
 36. Source assignments for NIOS_clock_1:the_NIOS_clock_1
 37. Source assignments for NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer
 38. Source assignments for NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer1
 39. Source assignments for NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer2
 40. Source assignments for NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer3
 41. Source assignments for NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_bit_pipe:endofpacket_bit_pipe
 42. Source assignments for NIOS_clock_2:the_NIOS_clock_2
 43. Source assignments for NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer
 44. Source assignments for NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer1
 45. Source assignments for NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer2
 46. Source assignments for NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer3
 47. Source assignments for NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_bit_pipe:endofpacket_bit_pipe
 48. Source assignments for NIOS_clock_3:the_NIOS_clock_3
 49. Source assignments for NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer
 50. Source assignments for NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer1
 51. Source assignments for NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer2
 52. Source assignments for NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer3
 53. Source assignments for NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_bit_pipe:endofpacket_bit_pipe
 54. Source assignments for altpll_0:the_altpll_0
 55. Source assignments for altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2|altpll_0_dffpipe_l2c:dffpipe3
 56. Source assignments for cpu_0_data_master_arbitrator:the_cpu_0_data_master|epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module:epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master
 57. Source assignments for cpu_0_data_master_arbitrator:the_cpu_0_data_master|jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module:jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master
 58. Source assignments for cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated
 59. Source assignments for cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_q8g1:auto_generated
 60. Source assignments for cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_hsf1:auto_generated
 61. Source assignments for cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_haf1:auto_generated
 62. Source assignments for cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_iaf1:auto_generated
 63. Source assignments for cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|dffpipe_93c:pre_result
 64. Source assignments for cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|dffpipe_93c:pre_result
 65. Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated
 66. Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated
 67. Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
 68. Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
 69. Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
 70. Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
 71. Source assignments for epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_tj41:auto_generated
 72. Source assignments for jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1
 73. Source assignments for jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1
 74. Source assignments for sdram_0:the_sdram_0
 75. Source assignments for NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch
 76. Source assignments for NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch
 77. Parameter Settings for User Entity Instance: NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer
 78. Parameter Settings for User Entity Instance: NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1
 79. Parameter Settings for User Entity Instance: NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2
 80. Parameter Settings for User Entity Instance: NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3
 81. Parameter Settings for User Entity Instance: NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer
 82. Parameter Settings for User Entity Instance: NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer1
 83. Parameter Settings for User Entity Instance: NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer2
 84. Parameter Settings for User Entity Instance: NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer3
 85. Parameter Settings for User Entity Instance: NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer
 86. Parameter Settings for User Entity Instance: NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer1
 87. Parameter Settings for User Entity Instance: NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer2
 88. Parameter Settings for User Entity Instance: NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer3
 89. Parameter Settings for User Entity Instance: NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer
 90. Parameter Settings for User Entity Instance: NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer1
 91. Parameter Settings for User Entity Instance: NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer2
 92. Parameter Settings for User Entity Instance: NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer3
 93. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
 94. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
 95. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
 96. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
 97. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht
 98. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram
 99. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
100. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
101. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
102. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
103. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1
104. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2
105. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
106. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
107. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
108. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
109. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
110. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
111. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
112. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
113. Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy
114. Parameter Settings for User Entity Instance: epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom
115. Parameter Settings for User Entity Instance: jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
116. Parameter Settings for User Entity Instance: jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
117. Parameter Settings for User Entity Instance: jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
118. Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub
119. altsyncram Parameter Settings by Entity Instance
120. altmult_add Parameter Settings by Entity Instance
121. scfifo Parameter Settings by Entity Instance
122. Port Connectivity Checks: "NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch"
123. Port Connectivity Checks: "NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch"
124. Port Connectivity Checks: "sysid:the_sysid"
125. Port Connectivity Checks: "sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module"
126. Port Connectivity Checks: "sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1"
127. Port Connectivity Checks: "sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1"
128. Port Connectivity Checks: "jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
129. Port Connectivity Checks: "jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave"
130. Port Connectivity Checks: "epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port"
131. Port Connectivity Checks: "altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1"
132. Port Connectivity Checks: "NIOS_clock_3:the_NIOS_clock_3"
133. Port Connectivity Checks: "NIOS_clock_3_in_arbitrator:the_NIOS_clock_3_in"
134. Port Connectivity Checks: "NIOS_clock_2:the_NIOS_clock_2"
135. Port Connectivity Checks: "NIOS_clock_2_in_arbitrator:the_NIOS_clock_2_in"
136. Port Connectivity Checks: "NIOS_clock_1:the_NIOS_clock_1"
137. Port Connectivity Checks: "NIOS_clock_1_in_arbitrator:the_NIOS_clock_1_in"
138. Port Connectivity Checks: "NIOS_clock_0:the_NIOS_clock_0"
139. Port Connectivity Checks: "NIOS_clock_0_in_arbitrator:the_NIOS_clock_0_in"
140. Elapsed Time Per Partition
141. Analysis & Synthesis Messages
142. Analysis & Synthesis Suppressed Messages



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+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu May 03 11:15:01 2012     ;
; Quartus II Version                 ; 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name                      ; sdram_test                                ;
; Top-level Entity Name              ; NIOS                                      ;
; Family                             ; Cyclone III                               ;
; Total logic elements               ; 4,385                                     ;
;     Total combinational functions  ; 3,276                                     ;
;     Dedicated logic registers      ; 2,664                                     ;
; Total registers                    ; 2664                                      ;
; Total pins                         ; 56                                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 55,680                                    ;
; Embedded Multiplier 9-bit elements ; 4                                         ;
; Total PLLs                         ; 1                                         ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP3C16Q240C8       ;                    ;
; Top-level entity name                                                      ; NIOS               ; sdram_test         ;
; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ; < 0.1%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                     ;
+--------------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path     ; Used in Netlist ; File Type                              ; File Name with Absolute Path                                             ;
+--------------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+
; altpll_0.v                           ; yes             ; User Verilog HDL File                  ; E:/Program/EP3C16/nios/sdram_test/altpll_0.v                             ;
; nios.v                               ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/nios.v                                 ;
; nios_clock_0.v                       ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/nios_clock_0.v                         ;
; altera_std_synchronizer.v            ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altera_std_synchronizer.v ;
; nios_clock_1.v                       ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/nios_clock_1.v                         ;
; nios_clock_2.v                       ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/nios_clock_2.v                         ;
; nios_clock_3.v                       ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/nios_clock_3.v                         ;
; cpu_0.v                              ; yes             ; Encrypted Auto-Found Verilog HDL File  ; E:/Program/EP3C16/nios/sdram_test/cpu_0.v                                ;
; cpu_0_test_bench.v                   ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/cpu_0_test_bench.v                     ;
; altsyncram.tdf                       ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf            ;
; stratix_ram_block.inc                ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_ram_block.inc     ;
; lpm_mux.inc                          ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_mux.inc               ;
; lpm_decode.inc                       ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_decode.inc            ;
; aglobal110.inc                       ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/aglobal110.inc            ;
; a_rdenreg.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_rdenreg.inc             ;
; altrom.inc                           ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altrom.inc                ;
; altram.inc                           ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altram.inc                ;
; altdpram.inc                         ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altdpram.inc              ;
; db/altsyncram_3id1.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_3id1.tdf                 ;
; db/altsyncram_q8g1.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_q8g1.tdf                 ;
; cpu_0_ic_tag_ram.mif                 ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP3C16/nios/sdram_test/cpu_0_ic_tag_ram.mif                   ;
; db/altsyncram_hsf1.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_hsf1.tdf                 ;
; cpu_0_bht_ram.mif                    ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP3C16/nios/sdram_test/cpu_0_bht_ram.mif                      ;
; db/altsyncram_haf1.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_haf1.tdf                 ;
; cpu_0_rf_ram_a.mif                   ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP3C16/nios/sdram_test/cpu_0_rf_ram_a.mif                     ;
; db/altsyncram_iaf1.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_iaf1.tdf                 ;
; cpu_0_rf_ram_b.mif                   ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP3C16/nios/sdram_test/cpu_0_rf_ram_b.mif                     ;
; cpu_0_mult_cell.v                    ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/cpu_0_mult_cell.v                      ;
; altmult_add.tdf                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altmult_add.tdf           ;
; stratix_mac_mult.inc                 ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_mac_mult.inc      ;
; stratix_mac_out.inc                  ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_mac_out.inc       ;
; db/mult_add_dfr2.tdf                 ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/mult_add_dfr2.tdf                   ;
; db/ded_mult_br81.tdf                 ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/ded_mult_br81.tdf                   ;
; db/dffpipe_93c.tdf                   ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/dffpipe_93c.tdf                     ;
; db/mult_add_ffr2.tdf                 ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/mult_add_ffr2.tdf                   ;
; db/altsyncram_l872.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_l872.tdf                 ;
; cpu_0_ociram_default_contents.mif    ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP3C16/nios/sdram_test/cpu_0_ociram_default_contents.mif      ;
; cpu_0_oci_test_bench.v               ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/cpu_0_oci_test_bench.v                 ;
; db/altsyncram_n802.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_n802.tdf                 ;
; cpu_0_jtag_debug_module_wrapper.v    ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/cpu_0_jtag_debug_module_wrapper.v      ;
; cpu_0_jtag_debug_module_tck.v        ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/cpu_0_jtag_debug_module_tck.v          ;
; cpu_0_jtag_debug_module_sysclk.v     ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/cpu_0_jtag_debug_module_sysclk.v       ;
; sld_virtual_jtag_basic.v             ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v  ;
; epcs_flash_controller_0.v            ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/epcs_flash_controller_0.v              ;
; db/altsyncram_tj41.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_tj41.tdf                 ;
; epcs_flash_controller_0_boot_rom.hex ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP3C16/nios/sdram_test/epcs_flash_controller_0_boot_rom.hex   ;
; jtag_uart_0.v                        ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/jtag_uart_0.v                          ;
; scfifo.tdf                           ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/scfifo.tdf                ;
; a_regfifo.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_regfifo.inc             ;
; a_dpfifo.inc                         ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_dpfifo.inc              ;
; a_i2fifo.inc                         ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_i2fifo.inc              ;
; a_fffifo.inc                         ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_fffifo.inc              ;
; a_f2fifo.inc                         ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_f2fifo.inc              ;
; db/scfifo_aq21.tdf                   ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/scfifo_aq21.tdf                     ;
; db/a_dpfifo_h031.tdf                 ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/a_dpfifo_h031.tdf                   ;
; db/a_fefifo_7cf.tdf                  ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/a_fefifo_7cf.tdf                    ;
; db/cntr_4n7.tdf                      ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/cntr_4n7.tdf                        ;
; db/dpram_ek21.tdf                    ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/dpram_ek21.tdf                      ;
; db/altsyncram_i0m1.tdf               ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/altsyncram_i0m1.tdf                 ;
; db/cntr_omb.tdf                      ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP3C16/nios/sdram_test/db/cntr_omb.tdf                        ;
; alt_jtag_atlantic.v                  ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/alt_jtag_atlantic.v       ;
; pio_0.v                              ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/pio_0.v                                ;
; sdram_0.v                            ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/sdram_0.v                              ;
; sysid.v                              ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP3C16/nios/sdram_test/sysid.v                                ;
; sld_hub.vhd                          ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/sld_hub.vhd               ;
; sld_rom_sr.vhd                       ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/sld_rom_sr.vhd            ;
+--------------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                   ;
+---------------------------------------------+-----------------------------------------------------------------+
; Resource                                    ; Usage                                                           ;
+---------------------------------------------+-----------------------------------------------------------------+
; Estimated Total logic elements              ; 4,385                                                           ;
;                                             ;                                                                 ;
; Total combinational functions               ; 3276                                                            ;
; Logic element usage by number of LUT inputs ;                                                                 ;
;     -- 4 input functions                    ; 1764                                                            ;
;     -- 3 input functions                    ; 1108                                                            ;
;     -- <=2 input functions                  ; 404                                                             ;
;                                             ;                                                                 ;
; Logic elements by mode                      ;                                                                 ;
;     -- normal mode                          ; 2985                                                            ;
;     -- arithmetic mode                      ; 291                                                             ;
;                                             ;                                                                 ;
; Total registers                             ; 2664                                                            ;
;     -- Dedicated logic registers            ; 2664                                                            ;
;     -- I/O registers                        ; 0                                                               ;
;                                             ;                                                                 ;
; I/O pins                                    ; 56                                                              ;
; Total memory bits                           ; 55680                                                           ;
; Embedded Multiplier 9-bit elements          ; 4                                                               ;
; Total PLLs                                  ; 1                                                               ;
;     -- PLLs                                 ; 1                                                               ;
;                                             ;                                                                 ;
; Maximum fan-out node                        ; altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|wire_pll7_clk[0] ;
; Maximum fan-out                             ; 2265                                                            ;
; Total fan-out                               ; 24347                                                           ;
; Average fan-out                             ; 3.88                                                            ;
+---------------------------------------------+-----------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                                                                                                                   ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                  ; Library Name ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |NIOS                                                                                                                                                                                        ; 3276 (3)          ; 2664 (0)     ; 55680       ; 4            ; 0       ; 2         ; 56   ; 0            ; |NIOS                                                                                                                                                                                                                                                ;              ;
;    |NIOS_clock_0:the_NIOS_clock_0|                                                                                                                                                           ; 15 (0)            ; 34 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0                                                                                                                                                                                                                  ;              ;
;       |NIOS_clock_0_edge_to_pulse:read_done_edge_to_pulse|                                                                                                                                   ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                               ;              ;
;       |NIOS_clock_0_edge_to_pulse:read_request_edge_to_pulse|                                                                                                                                ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                            ;              ;
;       |NIOS_clock_0_edge_to_pulse:write_done_edge_to_pulse|                                                                                                                                  ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_edge_to_pulse:write_done_edge_to_pulse                                                                                                                                                              ;              ;
;       |NIOS_clock_0_edge_to_pulse:write_request_edge_to_pulse|                                                                                                                               ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                           ;              ;
;       |NIOS_clock_0_master_FSM:master_FSM|                                                                                                                                                   ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_master_FSM:master_FSM                                                                                                                                                                               ;              ;
;       |NIOS_clock_0_slave_FSM:slave_FSM|                                                                                                                                                     ; 9 (9)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_slave_FSM:slave_FSM                                                                                                                                                                                 ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer1|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer2|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer3|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer|                                                                                                                                  ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer                                                                                                                                                              ;              ;
;    |NIOS_clock_0_in_arbitrator:the_NIOS_clock_0_in|                                                                                                                                          ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_0_in_arbitrator:the_NIOS_clock_0_in                                                                                                                                                                                                 ;              ;
;    |NIOS_clock_1:the_NIOS_clock_1|                                                                                                                                                           ; 30 (9)            ; 88 (64)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1                                                                                                                                                                                                                  ;              ;
;       |NIOS_clock_1_edge_to_pulse:read_done_edge_to_pulse|                                                                                                                                   ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                               ;              ;
;       |NIOS_clock_1_edge_to_pulse:read_request_edge_to_pulse|                                                                                                                                ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                            ;              ;
;       |NIOS_clock_1_edge_to_pulse:write_done_edge_to_pulse|                                                                                                                                  ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_edge_to_pulse:write_done_edge_to_pulse                                                                                                                                                              ;              ;
;       |NIOS_clock_1_edge_to_pulse:write_request_edge_to_pulse|                                                                                                                               ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                           ;              ;
;       |NIOS_clock_1_master_FSM:master_FSM|                                                                                                                                                   ; 11 (11)           ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_master_FSM:master_FSM                                                                                                                                                                               ;              ;
;       |NIOS_clock_1_slave_FSM:slave_FSM|                                                                                                                                                     ; 9 (9)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_slave_FSM:slave_FSM                                                                                                                                                                                 ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer1|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer1                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer2|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer2                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer3|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer3                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer|                                                                                                                                  ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer                                                                                                                                                              ;              ;
;    |NIOS_clock_1_in_arbitrator:the_NIOS_clock_1_in|                                                                                                                                          ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_1_in_arbitrator:the_NIOS_clock_1_in                                                                                                                                                                                                 ;              ;
;    |NIOS_clock_2:the_NIOS_clock_2|                                                                                                                                                           ; 34 (17)           ; 132 (114)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2                                                                                                                                                                                                                  ;              ;
;       |NIOS_clock_2_edge_to_pulse:read_done_edge_to_pulse|                                                                                                                                   ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                               ;              ;
;       |NIOS_clock_2_edge_to_pulse:read_request_edge_to_pulse|                                                                                                                                ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                            ;              ;
;       |NIOS_clock_2_edge_to_pulse:write_request_edge_to_pulse|                                                                                                                               ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                           ;              ;
;       |NIOS_clock_2_master_FSM:master_FSM|                                                                                                                                                   ; 8 (8)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_master_FSM:master_FSM                                                                                                                                                                               ;              ;
;       |NIOS_clock_2_slave_FSM:slave_FSM|                                                                                                                                                     ; 6 (6)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_slave_FSM:slave_FSM                                                                                                                                                                                 ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer2|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer2                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer3|                                                                                                                                 ; 1 (1)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer3                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer|                                                                                                                                  ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer                                                                                                                                                              ;              ;
;    |NIOS_clock_2_in_arbitrator:the_NIOS_clock_2_in|                                                                                                                                          ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2_in_arbitrator:the_NIOS_clock_2_in                                                                                                                                                                                                 ;              ;
;    |NIOS_clock_2_out_arbitrator:the_NIOS_clock_2_out|                                                                                                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_2_out_arbitrator:the_NIOS_clock_2_out                                                                                                                                                                                               ;              ;
;    |NIOS_clock_3:the_NIOS_clock_3|                                                                                                                                                           ; 24 (1)            ; 138 (114)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3                                                                                                                                                                                                                  ;              ;
;       |NIOS_clock_3_edge_to_pulse:read_done_edge_to_pulse|                                                                                                                                   ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                               ;              ;
;       |NIOS_clock_3_edge_to_pulse:read_request_edge_to_pulse|                                                                                                                                ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                            ;              ;
;       |NIOS_clock_3_edge_to_pulse:write_done_edge_to_pulse|                                                                                                                                  ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_edge_to_pulse:write_done_edge_to_pulse                                                                                                                                                              ;              ;
;       |NIOS_clock_3_edge_to_pulse:write_request_edge_to_pulse|                                                                                                                               ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                           ;              ;
;       |NIOS_clock_3_master_FSM:master_FSM|                                                                                                                                                   ; 9 (9)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_master_FSM:master_FSM                                                                                                                                                                               ;              ;
;       |NIOS_clock_3_slave_FSM:slave_FSM|                                                                                                                                                     ; 12 (12)           ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_slave_FSM:slave_FSM                                                                                                                                                                                 ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer1|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer1                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer2|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer2                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer3|                                                                                                                                 ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer3                                                                                                                                                             ;              ;
;       |altera_std_synchronizer:the_altera_std_synchronizer|                                                                                                                                  ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer                                                                                                                                                              ;              ;
;    |NIOS_clock_3_in_arbitrator:the_NIOS_clock_3_in|                                                                                                                                          ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3_in_arbitrator:the_NIOS_clock_3_in                                                                                                                                                                                                 ;              ;
;    |NIOS_clock_3_out_arbitrator:the_NIOS_clock_3_out|                                                                                                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_clock_3_out_arbitrator:the_NIOS_clock_3_out                                                                                                                                                                                               ;              ;
;    |NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch|                                                                                                  ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch                                                                                                                                                         ;              ;
;    |NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch|                                                                                                                    ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch                                                                                                                                                                           ;              ;
;    |altpll_0:the_altpll_0|                                                                                                                                                                   ; 6 (5)             ; 6 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|altpll_0:the_altpll_0                                                                                                                                                                                                                          ;              ;
;       |altpll_0_altpll_lpa2:sd1|                                                                                                                                                             ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1                                                                                                                                                                                                 ;              ;
;       |altpll_0_stdsync_sv6:stdsync2|                                                                                                                                                        ; 0 (0)             ; 3 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2                                                                                                                                                                                            ;              ;
;          |altpll_0_dffpipe_l2c:dffpipe3|                                                                                                                                                     ; 0 (0)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2|altpll_0_dffpipe_l2c:dffpipe3                                                                                                                                                              ;              ;
;    |cpu_0:the_cpu_0|                                                                                                                                                                         ; 2045 (1492)       ; 1586 (1192)  ; 46464       ; 4            ; 0       ; 2         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0                                                                                                                                                                                                                                ;              ;
;       |cpu_0_bht_module:cpu_0_bht|                                                                                                                                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht                                                                                                                                                                                                     ;              ;
;          |altsyncram:the_altsyncram|                                                                                                                                                         ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram                                                                                                                                                                           ;              ;
;             |altsyncram_hsf1:auto_generated|                                                                                                                                                 ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_hsf1:auto_generated                                                                                                                                            ;              ;
;       |cpu_0_ic_data_module:cpu_0_ic_data|                                                                                                                                                   ; 1 (0)             ; 1 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data                                                                                                                                                                                             ;              ;
;          |altsyncram:the_altsyncram|                                                                                                                                                         ; 1 (0)             ; 1 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram                                                                                                                                                                   ;              ;
;             |altsyncram_3id1:auto_generated|                                                                                                                                                 ; 1 (1)             ; 1 (1)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated                                                                                                                                    ;              ;
;       |cpu_0_ic_tag_module:cpu_0_ic_tag|                                                                                                                                                     ; 0 (0)             ; 0 (0)        ; 2944        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag                                                                                                                                                                                               ;              ;
;          |altsyncram:the_altsyncram|                                                                                                                                                         ; 0 (0)             ; 0 (0)        ; 2944        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram                                                                                                                                                                     ;              ;
;             |altsyncram_q8g1:auto_generated|                                                                                                                                                 ; 0 (0)             ; 0 (0)        ; 2944        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_q8g1:auto_generated                                                                                                                                      ;              ;
;       |cpu_0_mult_cell:the_cpu_0_mult_cell|                                                                                                                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 4            ; 0       ; 2         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell                                                                                                                                                                                            ;              ;
;          |altmult_add:the_altmult_add_part_1|                                                                                                                                                ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1                                                                                                                                                         ;              ;
;             |mult_add_dfr2:auto_generated|                                                                                                                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated                                                                                                                            ;              ;
;                |ded_mult_br81:ded_mult1|                                                                                                                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1                                                                                                    ;              ;
;          |altmult_add:the_altmult_add_part_2|                                                                                                                                                ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2                                                                                                                                                         ;              ;
;             |mult_add_ffr2:auto_generated|                                                                                                                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated                                                                                                                            ;              ;
;                |ded_mult_br81:ded_mult1|                                                                                                                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1                                                                                                    ;              ;
;       |cpu_0_nios2_oci:the_cpu_0_nios2_oci|                                                                                                                                                  ; 542 (39)          ; 393 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci                                                                                                                                                                                            ;              ;
;          |cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|                                                                                                               ; 96 (0)            ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper                                                                                                                        ;              ;
;             |cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|                                                                                                              ; 7 (7)             ; 49 (45)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk                                                      ;              ;
;                |altera_std_synchronizer:the_altera_std_synchronizer2|                                                                                                                        ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;              ;
;                |altera_std_synchronizer:the_altera_std_synchronizer3|                                                                                                                        ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;              ;
;             |cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|                                                                                                                    ; 85 (85)           ; 47 (43)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck                                                            ;              ;
;                |altera_std_synchronizer:the_altera_std_synchronizer1|                                                                                                                        ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1       ;              ;
;                |altera_std_synchronizer:the_altera_std_synchronizer|                                                                                                                         ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer        ;              ;
;             |sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy|                                                                                                                             ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy                                                                     ;              ;
;          |cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|                                                                                                                                 ; 8 (8)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg                                                                                                                                          ;              ;
;          |cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|                                                                                                                                   ; 85 (85)           ; 233 (233)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break                                                                                                                                            ;              ;
;          |cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|                                                                                                                                     ; 208 (45)          ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk                                                                                                                                              ;              ;
;             |cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit0_match_paired|                                                                                                            ; 75 (75)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit0_match_paired                                                                          ;              ;
;             |cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single|                                                                                                            ; 45 (45)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single                                                                          ;              ;
;             |cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit1_match_single|                                                                                                            ; 43 (43)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit1_match_single                                                                          ;              ;
;          |cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|                                                                                                                                   ; 8 (8)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug                                                                                                                                            ;              ;
;          |cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|                                                                                                                                     ; 41 (41)           ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk                                                                                                                                              ;              ;
;          |cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|                                                                                                                                         ; 57 (57)           ; 44 (44)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem                                                                                                                                                  ;              ;
;             |cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|                                                                                                 ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component                                                                   ;              ;
;                |altsyncram:the_altsyncram|                                                                                                                                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram                                         ;              ;
;                   |altsyncram_l872:auto_generated|                                                                                                                                           ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated          ;              ;
;       |cpu_0_register_bank_a_module:cpu_0_register_bank_a|                                                                                                                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a                                                                                                                                                                             ;              ;
;          |altsyncram:the_altsyncram|                                                                                                                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram                                                                                                                                                   ;              ;
;             |altsyncram_haf1:auto_generated|                                                                                                                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_haf1:auto_generated                                                                                                                    ;              ;
;       |cpu_0_register_bank_b_module:cpu_0_register_bank_b|                                                                                                                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b                                                                                                                                                                             ;              ;
;          |altsyncram:the_altsyncram|                                                                                                                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram                                                                                                                                                   ;              ;
;             |altsyncram_iaf1:auto_generated|                                                                                                                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_iaf1:auto_generated                                                                                                                    ;              ;
;       |cpu_0_test_bench:the_cpu_0_test_bench|                                                                                                                                                ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench                                                                                                                                                                                          ;              ;
;    |cpu_0_data_master_arbitrator:the_cpu_0_data_master|                                                                                                                                      ; 176 (176)         ; 55 (51)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0_data_master_arbitrator:the_cpu_0_data_master                                                                                                                                                                                             ;              ;
;       |epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module:epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master| ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0_data_master_arbitrator:the_cpu_0_data_master|epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module:epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master        ;              ;
;       |jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module:jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master|                         ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0_data_master_arbitrator:the_cpu_0_data_master|jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module:jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master                                ;              ;
;    |cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|                                                                                                                        ; 78 (78)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master                                                                                                                                                                               ;              ;
;    |cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|                                                                                                                          ; 33 (33)           ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module                                                                                                                                                                                 ;              ;
;    |epcs_flash_controller_0:the_epcs_flash_controller_0|                                                                                                                                     ; 138 (33)          ; 115 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0                                                                                                                                                                                            ;              ;
;       |altsyncram:the_boot_copier_rom|                                                                                                                                                       ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom                                                                                                                                                             ;              ;
;          |altsyncram_tj41:auto_generated|                                                                                                                                                    ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_tj41:auto_generated                                                                                                                              ;              ;
;       |epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|                                                                                                                          ; 105 (105)         ; 115 (115)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub                                                                                                                                ;              ;
;    |epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|                                                                                      ; 39 (39)           ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port                                                                                                                                             ;              ;
;    |jtag_uart_0:the_jtag_uart_0|                                                                                                                                                             ; 136 (35)          ; 108 (13)     ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0                                                                                                                                                                                                                    ;              ;
;       |alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|                                                                                                                                      ; 51 (51)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic                                                                                                                                                                    ;              ;
;       |jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|                                                                                                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r                                                                                                                                                                      ;              ;
;          |scfifo:rfifo|                                                                                                                                                                      ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo                                                                                                                                                         ;              ;
;             |scfifo_aq21:auto_generated|                                                                                                                                                     ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated                                                                                                                              ;              ;
;                |a_dpfifo_h031:dpfifo|                                                                                                                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo                                                                                                         ;              ;
;                   |a_fefifo_7cf:fifo_state|                                                                                                                                                  ; 13 (7)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state                                                                                 ;              ;
;                      |cntr_4n7:count_usedw|                                                                                                                                                  ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw                                                            ;              ;
;                   |cntr_omb:rd_ptr_count|                                                                                                                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:rd_ptr_count                                                                                   ;              ;
;                   |cntr_omb:wr_ptr|                                                                                                                                                          ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:wr_ptr                                                                                         ;              ;
;                   |dpram_ek21:FIFOram|                                                                                                                                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram                                                                                      ;              ;
;                      |altsyncram_i0m1:altsyncram1|                                                                                                                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1                                                          ;              ;
;       |jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|                                                                                                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w                                                                                                                                                                      ;              ;
;          |scfifo:wfifo|                                                                                                                                                                      ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo                                                                                                                                                         ;              ;
;             |scfifo_aq21:auto_generated|                                                                                                                                                     ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated                                                                                                                              ;              ;
;                |a_dpfifo_h031:dpfifo|                                                                                                                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo                                                                                                         ;              ;
;                   |a_fefifo_7cf:fifo_state|                                                                                                                                                  ; 13 (7)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state                                                                                 ;              ;
;                      |cntr_4n7:count_usedw|                                                                                                                                                  ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw                                                            ;              ;
;                   |cntr_omb:rd_ptr_count|                                                                                                                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:rd_ptr_count                                                                                   ;              ;
;                   |cntr_omb:wr_ptr|                                                                                                                                                          ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:wr_ptr                                                                                         ;              ;
;                   |dpram_ek21:FIFOram|                                                                                                                                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram                                                                                      ;              ;
;                      |altsyncram_i0m1:altsyncram1|                                                                                                                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1                                                          ;              ;
;    |pio_0:the_pio_0|                                                                                                                                                                         ; 3 (3)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|pio_0:the_pio_0                                                                                                                                                                                                                                ;              ;
;    |pio_0_s1_arbitrator:the_pio_0_s1|                                                                                                                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|pio_0_s1_arbitrator:the_pio_0_s1                                                                                                                                                                                                               ;              ;
;    |sdram_0:the_sdram_0|                                                                                                                                                                     ; 266 (213)         ; 245 (155)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sdram_0:the_sdram_0                                                                                                                                                                                                                            ;              ;
;       |sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|                                                                                                                            ; 53 (53)           ; 90 (90)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module                                                                                                                                                                  ;              ;
;    |sdram_0_s1_arbitrator:the_sdram_0_s1|                                                                                                                                                    ; 110 (60)          ; 42 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sdram_0_s1_arbitrator:the_sdram_0_s1                                                                                                                                                                                                           ;              ;
;       |rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|                                                                                     ; 32 (32)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1                                                                                                          ;              ;
;       |rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|                                                                       ; 18 (18)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1                                                                                            ;              ;
;    |sld_hub:auto_hub|                                                                                                                                                                        ; 122 (81)          ; 76 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sld_hub:auto_hub                                                                                                                                                                                                                               ;              ;
;       |sld_rom_sr:hub_info_reg|                                                                                                                                                              ; 24 (24)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sld_hub:auto_hub|sld_rom_sr:hub_info_reg                                                                                                                                                                                                       ;              ;
;       |sld_shadow_jsm:shadow_jsm|                                                                                                                                                            ; 17 (17)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                                     ;              ;
;    |sysid_control_slave_arbitrator:the_sysid_control_slave|                                                                                                                                  ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |NIOS|sysid_control_slave_arbitrator:the_sysid_control_slave                                                                                                                                                                                         ;              ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                                                      ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
; Name                                                                                                                                                                                                                                             ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                                  ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
; cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_hsf1:auto_generated|ALTSYNCRAM                                                                                                                                   ; AUTO ; Simple Dual Port ; 256          ; 2            ; 256          ; 2            ; 512   ; cpu_0_bht_ram.mif                    ;
; cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated|ALTSYNCRAM                                                                                                                           ; AUTO ; Simple Dual Port ; 1024         ; 32           ; 1024         ; 32           ; 32768 ; None                                 ;
; cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_q8g1:auto_generated|ALTSYNCRAM                                                                                                                             ; AUTO ; Simple Dual Port ; 128          ; 23           ; 128          ; 23           ; 2944  ; cpu_0_ic_tag_ram.mif                 ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port   ; 256          ; 32           ; 256          ; 32           ; 8192  ; cpu_0_ociram_default_contents.mif    ;
; cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_haf1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; cpu_0_rf_ram_a.mif                   ;
; cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_iaf1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; cpu_0_rf_ram_b.mif                   ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_tj41:auto_generated|ALTSYNCRAM                                                                                                                     ; AUTO ; ROM              ; 256          ; 32           ; --           ; --           ; 8192  ; epcs_flash_controller_0_boot_rom.hex ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|ALTSYNCRAM                                                 ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512   ; None                                 ;
; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1|ALTSYNCRAM                                                 ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512   ; None                                 ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 2           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 4           ;
; Signed Embedded Multipliers           ; 0           ;
; Unsigned Embedded Multipliers         ; 2           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                              ;
+--------+-------------------------------+---------+--------------+--------------+-----------------------+-------------------------------------------+
; Vendor ; IP Core Name                  ; Version ; Release Date ; License Type ; Entity Instance       ; IP Include File                           ;
+--------+-------------------------------+---------+--------------+--------------+-----------------------+-------------------------------------------+
; Altera ; Nios II Processor (6AF7_00A2) ; N/A     ; Apr 2004     ; Licensed     ; |NIOS|cpu_0:the_cpu_0 ; E:/Program/EP3C16/nios/sdram_test/cpu_0.v ;
+--------+-------------------------------+---------+--------------+--------------+-----------------------+-------------------------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------+
; State Machine - |NIOS|sdram_0:the_sdram_0|m_next                                             ;
+------------------+------------------+------------------+------------------+------------------+
; Name             ; m_next.010000000 ; m_next.000010000 ; m_next.000001000 ; m_next.000000001 ;
+------------------+------------------+------------------+------------------+------------------+
; m_next.000000001 ; 0                ; 0                ; 0                ; 0                ;
; m_next.000001000 ; 0                ; 0                ; 1                ; 1                ;
; m_next.000010000 ; 0                ; 1                ; 0                ; 1                ;
; m_next.010000000 ; 1                ; 0                ; 0                ; 1                ;
+------------------+------------------+------------------+------------------+------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|sdram_0:the_sdram_0|m_state                                                                                                                                                     ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; m_state.100000000 ; m_state.010000000 ; m_state.001000000 ; m_state.000100000 ; m_state.000010000 ; m_state.000001000 ; m_state.000000100 ; m_state.000000010 ; m_state.000000001 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; m_state.000000001 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; m_state.000000010 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; m_state.000000100 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; m_state.000001000 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; m_state.000010000 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000100000 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.001000000 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.010000000 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.100000000 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------+
; State Machine - |NIOS|sdram_0:the_sdram_0|i_next               ;
+------------+------------+------------+------------+------------+
; Name       ; i_next.111 ; i_next.101 ; i_next.010 ; i_next.000 ;
+------------+------------+------------+------------+------------+
; i_next.000 ; 0          ; 0          ; 0          ; 0          ;
; i_next.010 ; 0          ; 0          ; 1          ; 1          ;
; i_next.101 ; 0          ; 1          ; 0          ; 1          ;
; i_next.111 ; 1          ; 0          ; 0          ; 1          ;
+------------+------------+------------+------------+------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|sdram_0:the_sdram_0|i_state                                               ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; Name        ; i_state.111 ; i_state.101 ; i_state.011 ; i_state.010 ; i_state.001 ; i_state.000 ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; i_state.000 ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ;
; i_state.001 ; 0           ; 0           ; 0           ; 0           ; 1           ; 1           ;
; i_state.010 ; 0           ; 0           ; 0           ; 1           ; 0           ; 1           ;
; i_state.011 ; 0           ; 0           ; 1           ; 0           ; 0           ; 1           ;
; i_state.101 ; 0           ; 1           ; 0           ; 0           ; 0           ; 1           ;
; i_state.111 ; 1           ; 0           ; 0           ; 0           ; 0           ; 1           ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize ;
+------------+------------+------------+------------+------------+------------+------------------------------------------------------------------------------------------------------------------------------------+
; Name       ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000                                                                                                                         ;
+------------+------------+------------+------------+------------+------------+------------------------------------------------------------------------------------------------------------------------------------+
; DRsize.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0                                                                                                                                  ;
; DRsize.001 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1                                                                                                                                  ;
; DRsize.010 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1                                                                                                                                  ;
; DRsize.011 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1                                                                                                                                  ;
; DRsize.100 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1                                                                                                                                  ;
; DRsize.101 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1                                                                                                                                  ;
+------------+------------+------------+------------+------------+------------+------------------------------------------------------------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+--------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                           ;
+------------------+------------------+------------------+--------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                          ;
; master_state.010 ; 0                ; 1                ; 1                                          ;
; master_state.100 ; 1                ; 0                ; 1                                          ;
+------------------+------------------+------------------+--------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                            ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                          ;
; slave_state.010 ; 0               ; 1               ; 1                                          ;
; slave_state.100 ; 1               ; 0               ; 1                                          ;
+-----------------+-----------------+-----------------+--------------------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+--------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                           ;
+------------------+------------------+------------------+--------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                          ;
; master_state.010 ; 0                ; 1                ; 1                                          ;
; master_state.100 ; 1                ; 0                ; 1                                          ;
+------------------+------------------+------------------+--------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                            ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                          ;
; slave_state.010 ; 0               ; 1               ; 1                                          ;
; slave_state.100 ; 1               ; 0               ; 1                                          ;
+-----------------+-----------------+-----------------+--------------------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+--------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                           ;
+------------------+------------------+------------------+--------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                          ;
; master_state.010 ; 0                ; 1                ; 1                                          ;
; master_state.100 ; 1                ; 0                ; 1                                          ;
+------------------+------------------+------------------+--------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                            ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                          ;
; slave_state.010 ; 0               ; 1               ; 1                                          ;
; slave_state.100 ; 1               ; 0               ; 1                                          ;
+-----------------+-----------------+-----------------+--------------------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+--------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                           ;
+------------------+------------------+------------------+--------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                          ;
; master_state.010 ; 0                ; 1                ; 1                                          ;
; master_state.100 ; 1                ; 0                ; 1                                          ;
+------------------+------------------+------------------+--------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------+
; State Machine - |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                            ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                          ;
; slave_state.010 ; 0               ; 1               ; 1                                          ;
; slave_state.100 ; 1               ; 0               ; 1                                          ;
+-----------------+-----------------+-----------------+--------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                                                                                                       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                                                                                                          ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch|data_out                                                                                                                                                                          ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[4]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[4]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[3]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[3]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[2]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[2]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[10]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[10]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch|data_out                                                                                                                                                        ; yes                                                              ; yes                                        ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0]       ; yes                                                              ; yes                                        ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]        ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[1]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                            ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|master_writedata[0]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|master_address[3]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|master_address[2]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch|data_in_d1                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[0]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[0]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[10]                                                                                                                                                                                                       ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[10]                                                                                                                                                                                                       ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[4]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[4]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[3]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[3]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[2]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[2]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[10]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[10]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[7]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[7]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch|data_in_d1                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1        ; yes                                                              ; yes                                        ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1         ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[2]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled                                                                                                                                                              ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[10]                                                                                                                                                               ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[7]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|slave_writedata_d1[0]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|slave_address_d1[3]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|slave_address_d1[2]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[0]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[0]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[10]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[10]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[6]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[6]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[7]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[7]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                                                               ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                                                               ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                                                               ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_nativeaddress                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[3]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[0]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_req                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[5]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[5]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[6]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[6]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                                                               ; yes                                                              ; yes                                        ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; yes                                                              ; yes                                        ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_valid                                                                                                                                                                ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_nativeaddress_d1                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[1]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[7]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[4]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[4]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[5]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[5]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1  ; yes                                                              ; yes                                        ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0]                                                                                                                                                             ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[5]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[2]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[0]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[7]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[3]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[3]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[4]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[4]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; cpu_0_data_master_arbitrator:the_cpu_0_data_master|jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module:jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master|data_out                               ; yes                                                              ; yes                                        ;
; cpu_0_data_master_arbitrator:the_cpu_0_data_master|epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module:epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master|data_out       ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1                                                                                                                                                              ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[6]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[3]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[1]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[0]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[2]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[2]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[3]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[3]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; cpu_0_data_master_arbitrator:the_cpu_0_data_master|jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module:jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master|data_in_d1                             ; yes                                                              ; yes                                        ;
; cpu_0_data_master_arbitrator:the_cpu_0_data_master|epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module:epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master|data_in_d1     ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[4]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[2]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[1]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[1]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[1]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[2]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[2]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[5]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[3]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[2]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[1]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[1]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[5]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[5]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[6]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[6]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[7]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[7]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[8]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[8]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_address[9]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_address[9]                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|master_writedata[1]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[1]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[10]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[6]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[5]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[4]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[3]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[2]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[6]                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[4]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[3]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[9]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[9]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[8]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[8]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[5]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[5]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[6]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[6]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[7]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[7]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[8]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[8]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_address_d1[9]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_address_d1[9]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_0:the_NIOS_clock_0|slave_writedata_d1[1]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[15]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[15]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[14]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[14]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[13]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[13]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[12]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[12]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|master_writedata[11]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|master_writedata[11]                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[10]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[5]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[4]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[9]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[9]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[8]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[8]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[15]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[15]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[14]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[14]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[13]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[13]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[12]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[12]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_3:the_NIOS_clock_3|slave_writedata_d1[11]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_2:the_NIOS_clock_2|slave_writedata_d1[11]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|master_writedata[6]                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[5]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; NIOS_clock_1:the_NIOS_clock_1|slave_writedata_d1[6]                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                  ; Reason for Removal                                                                                                                                                                                         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[0..35]                                                                               ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|i_addr[4,5]                                                                                                                                                                ; Stuck at VCC due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|E_control_reg_rddata[2..31]                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|M_control_reg_rddata[2..31]                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|E_ctrl_br_always_pred_taken                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|M_ctrl_br_always_pred_taken                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[0..6]                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_wrap                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto1                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto0                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[11,23..31]                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[11,23..31]                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[2..31]                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[2..31]                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[0..16]                                                                             ; Lost fanout                                                                                                                                                                                                ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_slavearbiterlockenable                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_latency_counter                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_arb_share_counter                                 ; Lost fanout                                                                                                                                                                                                ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|last_cycle_NIOS_clock_3_out_granted_slave_epcs_flash_controller_0_epcs_control_port         ; Lost fanout                                                                                                                                                                                                ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|last_cycle_NIOS_clock_2_out_granted_slave_epcs_flash_controller_0_epcs_control_port         ; Lost fanout                                                                                                                                                                                                ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_saved_chosen_master_vector[1]                     ; Lost fanout                                                                                                                                                                                                ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_reg_firsttransfer                                 ; Lost fanout                                                                                                                                                                                                ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[3]                                                                           ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[4]                                                                           ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[4]                                                                           ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[5]                                                                           ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[5]                                                                           ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]                                                                           ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]                                                                           ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]                                                                           ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]                                                                           ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]                                                                           ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]                                                                           ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]                                                                           ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]                                                                           ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]                                                                          ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]                                                                          ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[2]                                                                           ;
; sdram_0:the_sdram_0|i_addr[0..3,6..11]                                                                                                                                                         ; Merged with sdram_0:the_sdram_0|i_addr[12]                                                                                                                                                                 ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|d1_epcs_flash_controller_0_epcs_control_port_end_xfer                                       ; Merged with epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|d1_reasons_to_wait                                                                          ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_cpu_0_jtag_debug_module_end_xfer                                                                                             ; Merged with cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait                                                                                                              ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_6                                     ; Merged with sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_6                                                   ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_5                                     ; Merged with sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_5                                                   ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_4                                     ; Merged with sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_4                                                   ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_3                                     ; Merged with sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_3                                                   ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_2                                     ; Merged with sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_2                                                   ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_1                                     ; Merged with sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_1                                                   ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_0                                     ; Merged with sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_0                                                   ;
; cpu_0:the_cpu_0|D_ctrl_jmp_direct                                                                                                                                                              ; Merged with cpu_0:the_cpu_0|D_ctrl_a_not_src                                                                                                                                                               ;
; cpu_0:the_cpu_0|D_ctrl_b_not_src                                                                                                                                                               ; Merged with cpu_0:the_cpu_0|D_ctrl_b_is_dst                                                                                                                                                                ;
; cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_rdv_counter[0]                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[0]                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[0]                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_slave_FSM:slave_FSM|slave_write_request                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter[1]                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_slavearbiterlockenable                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module                                                       ; Lost fanout                                                                                                                                                                                                ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module                                                              ; Lost fanout                                                                                                                                                                                                ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter[0]                                                                                    ; Lost fanout                                                                                                                                                                                                ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_reg_firsttransfer                                                                                       ; Lost fanout                                                                                                                                                                                                ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[1]                                                                           ; Lost fanout                                                                                                                                                                                                ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|slowcount[1]                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; sdram_0:the_sdram_0|m_next~9                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|m_next~10                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|m_next~13                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|m_next~14                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|m_next~16                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|i_next~4                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|i_next~5                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|i_next~6                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|i_state~14                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|i_state~15                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                ;
; sdram_0:the_sdram_0|i_state~16                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~3   ; Lost fanout                                                                                                                                                                                                ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~4   ; Lost fanout                                                                                                                                                                                                ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~5   ; Lost fanout                                                                                                                                                                                                ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.101 ; Lost fanout                                                                                                                                                                                                ;
; NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_master_FSM:master_FSM|master_write                                                                                                                  ; Merged with NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_master_FSM:master_FSM|master_state.100                                                                                                              ;
; NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_master_FSM:master_FSM|master_state.010                                                                                                              ; Merged with NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_master_FSM:master_FSM|master_read                                                                                                                   ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.011 ; Merged with cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.001 ;
; NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_slave_FSM:slave_FSM|slave_state.100                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.001 ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; sdram_0:the_sdram_0|m_count[2]                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                     ;
; Total Number of Removed Registers = 297                                                                                                                                                        ;                                                                                                                                                                                                            ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                       ; Reason for Removal        ; Registers Removed due to This Register                                                                                                                                                  ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_slavearbiterlockenable                                                       ; Stuck at GND              ; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module,                                               ;
;                                                                                                                                                                     ; due to stuck port data_in ; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module,                                                      ;
;                                                                                                                                                                     ;                           ; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[1]                                                                    ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_slavearbiterlockenable ; Stuck at GND              ; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|last_cycle_NIOS_clock_3_out_granted_slave_epcs_flash_controller_0_epcs_control_port, ;
;                                                                                                                                                                     ; due to stuck port data_in ; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|last_cycle_NIOS_clock_2_out_granted_slave_epcs_flash_controller_0_epcs_control_port, ;
;                                                                                                                                                                     ;                           ; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_saved_chosen_master_vector[1]              ;
; cpu_0:the_cpu_0|E_control_reg_rddata[29]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[29]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[28]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[28]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[27]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[27]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[26]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[26]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[25]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[25]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[24]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[24]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[23]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[23]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[22]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[22]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[21]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[21]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[20]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[20]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[19]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[19]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[18]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[18]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[17]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[17]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[16]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[16]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[15]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[15]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[14]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[14]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[13]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[13]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[12]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[12]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[11]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[11]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[10]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[10]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[9]                                                                                                                             ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[9]                                                                                                                                                 ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[8]                                                                                                                             ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[8]                                                                                                                                                 ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[7]                                                                                                                             ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[7]                                                                                                                                                 ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[6]                                                                                                                             ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[6]                                                                                                                                                 ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[5]                                                                                                                             ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[5]                                                                                                                                                 ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[4]                                                                                                                             ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[4]                                                                                                                                                 ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[3]                                                                                                                             ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[3]                                                                                                                                                 ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[2]                                                                                                                             ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[2]                                                                                                                                                 ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_ctrl_br_always_pred_taken                                                                                                                         ; Stuck at GND              ; cpu_0:the_cpu_0|M_ctrl_br_always_pred_taken                                                                                                                                             ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[31]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[31]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[30]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[30]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[29]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[29]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[28]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[28]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[27]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[27]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[26]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[26]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[25]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[25]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[24]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[24]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[23]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[23]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_1:the_NIOS_clock_1|slave_readdata_p1[11]                                                                                                                 ; Stuck at GND              ; NIOS_clock_1:the_NIOS_clock_1|slave_readdata[11]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[31]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[31]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[30]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[30]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[29]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[29]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[28]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[28]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[27]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[27]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[26]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[26]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[25]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[25]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[24]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[24]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[23]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[23]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[22]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[22]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[21]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[21]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[20]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[20]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[19]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[19]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[18]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[18]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[31]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[31]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[16]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[16]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[15]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[15]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[14]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[14]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[13]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[13]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[12]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[12]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[11]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[11]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[10]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[10]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[9]                                                                                                                  ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[9]                                                                                                                                         ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[17]                                                                                                                 ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[17]                                                                                                                                        ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[7]                                                                                                                  ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[7]                                                                                                                                         ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[6]                                                                                                                  ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[6]                                                                                                                                         ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[5]                                                                                                                  ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[5]                                                                                                                                         ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[4]                                                                                                                  ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[4]                                                                                                                                         ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[3]                                                                                                                  ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[3]                                                                                                                                         ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[2]                                                                                                                  ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[2]                                                                                                                                         ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0:the_cpu_0|E_control_reg_rddata[30]                                                                                                                            ; Stuck at GND              ; cpu_0:the_cpu_0|M_control_reg_rddata[30]                                                                                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter[1]                                                         ; Stuck at GND              ; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_reg_firsttransfer                                                                                ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
; NIOS_clock_0:the_NIOS_clock_0|slave_readdata_p1[8]                                                                                                                  ; Stuck at GND              ; NIOS_clock_0:the_NIOS_clock_0|slave_readdata[8]                                                                                                                                         ;
;                                                                                                                                                                     ; due to stuck port data_in ;                                                                                                                                                                                         ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 2664  ;
; Number of registers using Synchronous Clear  ; 26    ;
; Number of registers using Synchronous Load   ; 245   ;
; Number of registers using Asynchronous Clear ; 2120  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1746  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                        ; Fan out ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|epcs_slave_select_reg[0]                                 ; 2       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|stateZero                                                ; 1       ;
; sdram_0:the_sdram_0|m_cmd[1]                                                                                                                                             ; 2       ;
; sdram_0:the_sdram_0|m_cmd[3]                                                                                                                                             ; 1       ;
; sdram_0:the_sdram_0|m_cmd[2]                                                                                                                                             ; 2       ;
; sdram_0:the_sdram_0|m_cmd[0]                                                                                                                                             ; 2       ;
; epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|epcs_slave_select_holding_reg[0]                         ; 1       ;
; epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_arb_addend[0]               ; 5       ;
; cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest                                                                                         ; 14      ;
; sdram_0:the_sdram_0|i_addr[12]                                                                                                                                           ; 11      ;
; sdram_0:the_sdram_0|i_cmd[1]                                                                                                                                             ; 2       ;
; sdram_0:the_sdram_0|i_cmd[3]                                                                                                                                             ; 2       ;
; sdram_0:the_sdram_0|i_cmd[2]                                                                                                                                             ; 2       ;
; sdram_0:the_sdram_0|i_cmd[0]                                                                                                                                             ; 2       ;
; jtag_uart_0:the_jtag_uart_0|t_dav                                                                                                                                        ; 4       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9]                                                                                     ; 11      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|fifo_contains_ones_n               ; 2       ;
; cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0]                                                                     ; 5       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n ; 8       ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[0]                                                                                                            ; 6       ;
; sdram_0:the_sdram_0|refresh_counter[12]                                                                                                                                  ; 2       ;
; sdram_0:the_sdram_0|refresh_counter[9]                                                                                                                                   ; 2       ;
; sdram_0:the_sdram_0|refresh_counter[8]                                                                                                                                   ; 2       ;
; sdram_0:the_sdram_0|refresh_counter[7]                                                                                                                                   ; 2       ;
; sdram_0:the_sdram_0|refresh_counter[3]                                                                                                                                   ; 2       ;
; cpu_0:the_cpu_0|M_pipe_flush                                                                                                                                             ; 56      ;
; cpu_0:the_cpu_0|hbreak_enabled                                                                                                                                           ; 41      ;
; sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_reg_firsttransfer                                                                                                        ; 1       ;
; jtag_uart_0:the_jtag_uart_0|av_waitrequest                                                                                                                               ; 10      ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rst2                                                                                         ; 3       ;
; jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rst1                                                                                         ; 1       ;
; cpu_0:the_cpu_0|A_wr_dst_reg_from_M                                                                                                                                      ; 66      ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[0]                                                     ; 2       ;
; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[1]                                                     ; 2       ;
; cpu_0:the_cpu_0|M_pipe_flush_waddr[10]                                                                                                                                   ; 1       ;
; cpu_0:the_cpu_0|ic_tag_clr_valid_bits                                                                                                                                    ; 1       ;
; cpu_0:the_cpu_0|ic_tag_wraddress[6]                                                                                                                                      ; 1       ;
; cpu_0:the_cpu_0|M_pipe_flush_waddr[9]                                                                                                                                    ; 1       ;
; cpu_0:the_cpu_0|M_pipe_flush_waddr[24]                                                                                                                                   ; 1       ;
; cpu_0:the_cpu_0|clr_break_line                                                                                                                                           ; 5       ;
; altpll_0:the_altpll_0|pfdena_reg                                                                                                                                         ; 2       ;
; sld_hub:auto_hub|tdo                                                                                                                                                     ; 2       ;
; Total number of inverted registers = 42                                                                                                                                  ;         ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                                                                                                                                                                                       ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; |NIOS|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[4]                                                                                                       ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|M_mem_byte_en[0]                                                                                                                                                           ;                            ;
; 3:1                ; 26 bits   ; 52 LEs        ; 52 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|D_iw[14]                                                                                                                                                                   ;                            ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|A_slow_inst_result[26]                                                                                                                                                     ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|A_slow_inst_result[11]                                                                                                                                                     ;                            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |NIOS|cpu_0:the_cpu_0|ic_fill_ap_cnt[0]                                                                                                                                                          ;                            ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; |NIOS|cpu_0:the_cpu_0|ic_fill_ap_offset[0]                                                                                                                                                       ;                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; |NIOS|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[1]                                                                                                   ;                            ;
; 8:1                ; 5 bits    ; 25 LEs        ; 10 LEs               ; 15 LEs                 ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|data_to_cpu[14]                                                            ;                            ;
; 8:1                ; 2 bits    ; 10 LEs        ; 8 LEs                ; 2 LEs                  ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|data_to_cpu[9]                                                             ;                            ;
; 8:1                ; 3 bits    ; 15 LEs        ; 6 LEs                ; 9 LEs                  ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|data_to_cpu[1]                                                             ;                            ;
; 8:1                ; 4 bits    ; 20 LEs        ; 12 LEs               ; 8 LEs                  ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|data_to_cpu[4]                                                             ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; |NIOS|epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub|shift_reg[0]                                                               ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |NIOS|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[8]                                                                                                    ;                            ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|ic_tag_wraddress[0]                                                                                                                                                        ;                            ;
; 4:1                ; 17 bits   ; 34 LEs        ; 34 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[27]                                                                                  ;                            ;
; 4:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|E_src2[17]                                                                                                                                                                 ;                            ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|A_slow_inst_result[0]                                                                                                                                                      ;                            ;
; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[29]                                                                                  ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|M_st_data[24]                                                                                                                                                              ;                            ;
; 6:1                ; 13 bits   ; 52 LEs        ; 26 LEs               ; 26 LEs                 ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[2]  ;                            ;
; 6:1                ; 18 bits   ; 72 LEs        ; 36 LEs               ; 36 LEs                 ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[29] ;                            ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|E_src1[11]                                                                                                                                                                 ;                            ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[8]                                                                                   ;                            ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |NIOS|sdram_0:the_sdram_0|m_dqm[0]                                                                                                                                                               ;                            ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[27]                                                                      ;                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|M_mem_byte_en[3]                                                                                                                                                           ;                            ;
; 6:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[8]                                                                                   ;                            ;
; 6:1                ; 15 bits   ; 60 LEs        ; 60 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|F_pc[13]                                                                                                                                                                   ;                            ;
; 6:1                ; 22 bits   ; 88 LEs        ; 88 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|M_pipe_flush_waddr[1]                                                                                                                                                      ;                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; |NIOS|sdram_0:the_sdram_0|i_count[1]                                                                                                                                                             ;                            ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; |NIOS|sdram_0:the_sdram_0|m_addr[9]                                                                                                                                                              ;                            ;
; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; |NIOS|sdram_0:the_sdram_0|m_addr[4]                                                                                                                                                              ;                            ;
; 7:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; |NIOS|sdram_0:the_sdram_0|m_addr[1]                                                                                                                                                              ;                            ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; |NIOS|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4]                                                                                                    ;                            ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; |NIOS|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[5]                                                                                                    ;                            ;
; 9:1                ; 26 bits   ; 156 LEs       ; 52 LEs               ; 104 LEs                ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[26]                                                                      ;                            ;
; 12:1               ; 43 bits   ; 344 LEs       ; 0 LEs                ; 344 LEs                ; |NIOS|sdram_0:the_sdram_0|active_data[15]                                                                                                                                                        ;                            ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; |NIOS|sdram_0:the_sdram_0|m_data[6]                                                                                                                                                              ;                            ;
; 6:1                ; 3 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|M_pipe_flush_waddr[24]                                                                                                                                                     ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |NIOS|sdram_0:the_sdram_0|comb                                                                                                                                                                   ;                            ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|E_logic_result[13]                                                                                                                                                         ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |NIOS|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter_next_value[1]                                                                     ;                            ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; |NIOS|cpu_0:the_cpu_0|F_iw[0]                                                                                                                                                                    ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[3]                                                                                                                            ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |NIOS|NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_slave_FSM:slave_FSM|Selector0                                                                                                                   ;                            ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |NIOS|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|updated_one_count                      ;                            ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |NIOS|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|updated_one_count                                    ;                            ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|D_dst_regnum[0]                                                                                                                                                            ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[1]                                                                                                                            ;                            ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|A_wr_data_unfiltered[30]                                                                                                                                                   ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |NIOS|NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_slave_FSM:slave_FSM|Selector0                                                                                                                   ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |NIOS|NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_slave_FSM:slave_FSM|Selector0                                                                                                                   ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |NIOS|NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_slave_FSM:slave_FSM|Selector0                                                                                                                   ;                            ;
; 5:1                ; 5 bits    ; 15 LEs        ; 15 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|E_alu_result[29]                                                                                                                                                           ;                            ;
; 5:1                ; 25 bits   ; 75 LEs        ; 75 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|E_alu_result[2]                                                                                                                                                            ;                            ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|D_src2_reg[22]                                                                                                                                                             ;                            ;
; 6:1                ; 10 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; |NIOS|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[5]                                                                                                                                                    ;                            ;
; 11:1               ; 2 bits    ; 14 LEs        ; 4 LEs                ; 10 LEs                 ; |NIOS|sdram_0:the_sdram_0|Selector35                                                                                                                                                             ;                            ;
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; |NIOS|sdram_0:the_sdram_0|Selector28                                                                                                                                                             ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+


+-----------------------------------------------------------------+
; Source assignments for NIOS_clock_0:the_NIOS_clock_0            ;
+-------------------+-------+------+------------------------------+
; Assignment        ; Value ; From ; To                           ;
+-------------------+-------+------+------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; master_address[3]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[2]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[1]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[0]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[3]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[2]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[1]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[0]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[1]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[0]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[31]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[30]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[29]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[28]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[27]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[26]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[25]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[24]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[23]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[22]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[21]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[20]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[19]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[18]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[17]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[16]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[15]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[14]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[13]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[12]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[11]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[10]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[9]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[8]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[7]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[6]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[5]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[4]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[3]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[2]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[1]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[0]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[31]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[30]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[29]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[28]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[27]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[26]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[25]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[24]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[23]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[22]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[21]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[20]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[19]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[18]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[17]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[16]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[15]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[14]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[13]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[12]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[11]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[10]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[9]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[8]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[7]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[6]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[5]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[4]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[3]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[2]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[1]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[31]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[30]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[29]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[28]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[27]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[26]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[25]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[24]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[23]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[22]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[21]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[20]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[19]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[18]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[17]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[16]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[15]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[14]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[13]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[12]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[11]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[10]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[9]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[8]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[7]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[6]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[5]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[4]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[3]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[2]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[1]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[0]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[3]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[2]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[1]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[0]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[3]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[2]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[1]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[0]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[1]    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[0]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[0]    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[1]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[0]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[3]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[2]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[1]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[0]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[3]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[2]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[1]~reg0    ;
+-------------------+-------+------+------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+--------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                         ;
+-----------------------------+------------------------+------+--------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                    ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                    ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                    ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                     ;
+-----------------------------+------------------------+------+--------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------+--------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                           ;
+-------------------+-------+------+--------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                   ;
+-------------------+-------+------+--------------------------------------------------------------+


+--------------------------------------------------------------+
; Source assignments for NIOS_clock_1:the_NIOS_clock_1         ;
+-------------------+-------+------+---------------------------+
; Assignment        ; Value ; From ; To                        ;
+-------------------+-------+------+---------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; master_address[2]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[1]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[0]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[3]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[2]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[1]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[0]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[31]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[30]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[29]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[28]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[27]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[26]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[25]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[24]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[23]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[22]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[21]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[20]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[19]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[18]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[17]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[16]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[15]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[14]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[13]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[12]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[11]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[10]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[9]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[8]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[7]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[6]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[5]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[4]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[3]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[2]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[1]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[0]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[31]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[30]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[29]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[28]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[27]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[26]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[25]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[24]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[23]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[22]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[21]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[20]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[19]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[18]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[17]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[16]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[15]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[14]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[13]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[12]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[11]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[10]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[9]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[8]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[7]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[6]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[5]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[4]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[3]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[2]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[1]     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[0]     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[31]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[30]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[29]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[28]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[27]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[26]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[25]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[24]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[23]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[22]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[21]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[20]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[19]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[18]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[17]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[16]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[15]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[14]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[13]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[12]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[11]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[10]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[9]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[8]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[7]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[6]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[5]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[4]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[3]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[2]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[1]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[0]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[2]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[1]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[0]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[2]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[1]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[0]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[0]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[3]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[2]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[1]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[0]    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[3]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[2]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[1]~reg0 ;
+-------------------+-------+------+---------------------------+


+----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+--------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                         ;
+-----------------------------+------------------------+------+--------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                    ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                    ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                    ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                     ;
+-----------------------------+------------------------+------+--------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------+--------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                           ;
+-------------------+-------+------+--------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                   ;
+-------------------+-------+------+--------------------------------------------------------------+


+-----------------------------------------------------------------+
; Source assignments for NIOS_clock_2:the_NIOS_clock_2            ;
+-------------------+-------+------+------------------------------+
; Assignment        ; Value ; From ; To                           ;
+-------------------+-------+------+------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; master_address[10]           ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[9]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[8]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[7]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[6]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[5]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[4]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[3]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[2]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[1]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[0]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[3]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[2]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[1]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[0]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[8]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[7]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[6]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[5]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[4]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[3]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[2]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[1]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[0]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[31]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[30]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[29]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[28]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[27]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[26]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[25]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[24]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[23]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[22]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[21]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[20]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[19]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[18]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[17]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[16]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[15]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[14]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[13]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[12]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[11]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[10]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[9]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[8]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[7]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[6]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[5]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[4]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[3]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[2]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[1]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[0]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[31]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[30]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[29]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[28]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[27]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[26]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[25]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[24]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[23]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[22]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[21]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[20]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[19]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[18]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[17]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[16]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[15]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[14]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[13]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[12]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[11]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[10]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[9]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[8]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[7]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[6]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[5]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[4]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[3]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[2]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[1]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[31]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[30]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[29]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[28]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[27]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[26]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[25]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[24]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[23]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[22]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[21]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[20]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[19]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[18]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[17]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[16]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[15]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[14]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[13]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[12]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[11]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[10]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[9]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[8]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[7]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[6]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[5]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[4]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[3]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[2]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[1]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[0]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[10]         ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[9]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[8]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[7]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[6]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[5]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[4]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[3]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[2]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[1]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[0]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[10]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[9]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[8]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[7]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[6]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[5]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[4]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[3]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[2]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[1]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[0]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[8]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[7]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[6]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[5]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[4]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[3]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[2]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[1]    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[0]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[0]    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[8]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[7]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[6]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[5]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[4]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[3]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[2]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[1]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[0]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[3]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[2]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[1]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[0]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[3]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[2]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[1]~reg0    ;
+-------------------+-------+------+------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+--------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                         ;
+-----------------------------+------------------------+------+--------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                    ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                    ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                    ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                     ;
+-----------------------------+------------------------+------+--------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------+--------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                           ;
+-------------------+-------+------+--------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                   ;
+-------------------+-------+------+--------------------------------------------------------------+


+-----------------------------------------------------------------+
; Source assignments for NIOS_clock_3:the_NIOS_clock_3            ;
+-------------------+-------+------+------------------------------+
; Assignment        ; Value ; From ; To                           ;
+-------------------+-------+------+------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; master_address[10]           ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[9]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[8]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[7]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[6]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[5]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[4]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[3]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[2]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[1]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[0]            ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[3]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[2]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[1]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[0]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[8]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[7]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[6]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[5]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[4]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[3]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[2]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[1]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[0]      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[31]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[30]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[29]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[28]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[27]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[26]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[25]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[24]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[23]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[22]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[21]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[20]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[19]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[18]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[17]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[16]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[15]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[14]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[13]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[12]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[11]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[10]         ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[9]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[8]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[7]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[6]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[5]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[4]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[3]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[2]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[1]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[0]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[31]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[30]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[29]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[28]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[27]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[26]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[25]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[24]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[23]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[22]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[21]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[20]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[19]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[18]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[17]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[16]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[15]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[14]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[13]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[12]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[11]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[10]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[9]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[8]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[7]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[6]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[5]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[4]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[3]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[2]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[1]        ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_writedata_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[31]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[30]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[29]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[28]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[27]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[26]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[25]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[24]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[23]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[22]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[21]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[20]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[19]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[18]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[17]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[16]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[15]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[14]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[13]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[12]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[11]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[10]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[9]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[8]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[7]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[6]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[5]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[4]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[3]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[2]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[1]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; master_writedata[0]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[10]         ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[9]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[8]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[7]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[6]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[5]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[4]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[3]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[2]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[1]          ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_address_d1[0]          ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[10]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[9]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[8]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[7]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[6]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[5]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[4]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[3]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[2]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[1]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_address[0]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[8]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[7]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[6]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[5]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[4]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[3]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[2]    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[1]    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[0]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_nativeaddress_d1[0]    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[8]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[7]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[6]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[5]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[4]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[3]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[2]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[1]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; master_nativeaddress[0]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[3]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[2]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[1]       ;
; PRESERVE_REGISTER ; ON    ; -    ; slave_byteenable_d1[0]       ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[3]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[2]~reg0    ;
; PRESERVE_REGISTER ; ON    ; -    ; master_byteenable[1]~reg0    ;
+-------------------+-------+------+------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+--------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                         ;
+-----------------------------+------------------------+------+--------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                    ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                    ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                    ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                     ;
+-----------------------------+------------------------+------+--------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+-----------------------------+------------------------+------+---------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                          ;
+-----------------------------+------------------------+------+---------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                      ;
+-----------------------------+------------------------+------+---------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------+--------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                           ;
+-------------------+-------+------+--------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                   ;
+-------------------+-------+------+--------------------------------------------------------------+


+----------------------------------------------+
; Source assignments for altpll_0:the_altpll_0 ;
+----------------+-------+------+--------------+
; Assignment     ; Value ; From ; To           ;
+----------------+-------+------+--------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; pfdena_reg   ;
+----------------+-------+------+--------------+


+----------------------------------------------------------------------------------------------------------+
; Source assignments for altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2|altpll_0_dffpipe_l2c:dffpipe3 ;
+---------------------------------+-------+------+---------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                      ;
+---------------------------------+-------+------+---------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
+---------------------------------+-------+------+---------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0_data_master_arbitrator:the_cpu_0_data_master|epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module:epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                                                                                          ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                                                                                                                                                    ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                                                                                                                                                  ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0_data_master_arbitrator:the_cpu_0_data_master|jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module:jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                                                                  ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                                                                                                                            ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                                                                                                                                       ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                                                                                                                          ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                   ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                    ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_q8g1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                  ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_hsf1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                           ;
+---------------------------------+--------------------+------+--------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                            ;
+---------------------------------+--------------------+------+--------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_haf1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_iaf1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated|ded_mult_br81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                             ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                              ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                  ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                               ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                          ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                          ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                          ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                           ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                           ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                            ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                      ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                 ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                 ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                 ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                  ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                  ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                      ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                 ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                 ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                 ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                  ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                  ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_tj41:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                         ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                          ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                             ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                              ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                             ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                              ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------+
; Source assignments for sdram_0:the_sdram_0                    ;
+-----------------------------+-------+------+------------------+
; Assignment                  ; Value ; From ; To               ;
+-----------------------------+-------+------+------------------+
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[3]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[2]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[0]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[12]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[0]         ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; oe               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]~reg0  ;
+-----------------------------+-------+------+------------------+


+---------------------------------------------------------------------------------------------------------------+
; Source assignments for NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch ;
+-------------------+-------+------+----------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                         ;
+-------------------+-------+------+----------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                              ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                 ;
+-------------------+-------+------+----------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Source assignments for NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch ;
+-------------------+-------+------+----------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                       ;
+-------------------+-------+------+----------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                            ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                               ;
+-------------------+-------+------+----------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_1:the_NIOS_clock_1|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_2:the_NIOS_clock_2|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: NIOS_clock_3:the_NIOS_clock_3|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data ;
+----------------+--------+-----------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                  ;
+----------------+--------+-----------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                ;
+----------------+--------+-----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+---------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                          ;
+------------------------------------+----------------------+---------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                       ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                    ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                  ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                  ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                       ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                       ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                ;
; WIDTHAD_A                          ; 10                   ; Signed Integer                                                ;
; NUMWORDS_A                         ; 1024                 ; Signed Integer                                                ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                       ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                       ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                       ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                       ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                       ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                       ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                ;
; WIDTHAD_B                          ; 10                   ; Signed Integer                                                ;
; NUMWORDS_B                         ; 1024                 ; Signed Integer                                                ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                       ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                       ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                       ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                       ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                       ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                       ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                       ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                       ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                       ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                       ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                       ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                       ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                       ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                       ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                       ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                       ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                       ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                       ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                       ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                       ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                       ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                       ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                       ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                       ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                       ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                       ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                       ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                       ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                       ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                       ;
; CBXI_PARAMETER                     ; altsyncram_3id1      ; Untyped                                                       ;
+------------------------------------+----------------------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag ;
+----------------+----------------------+-------------------------------------------------------+
; Parameter Name ; Value                ; Type                                                  ;
+----------------+----------------------+-------------------------------------------------------+
; lpm_file       ; cpu_0_ic_tag_ram.mif ; String                                                ;
+----------------+----------------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                        ;
+------------------------------------+----------------------+-------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                     ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                              ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                     ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                     ;
; WIDTH_A                            ; 23                   ; Signed Integer                                              ;
; WIDTHAD_A                          ; 7                    ; Signed Integer                                              ;
; NUMWORDS_A                         ; 128                  ; Signed Integer                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                     ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                     ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                     ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                     ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                     ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                     ;
; WIDTH_B                            ; 23                   ; Signed Integer                                              ;
; WIDTHAD_B                          ; 7                    ; Signed Integer                                              ;
; NUMWORDS_B                         ; 128                  ; Signed Integer                                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                     ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                     ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                     ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                     ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                     ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                     ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                     ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                     ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                     ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                     ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                     ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                     ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                     ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                     ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                     ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                     ;
; INIT_FILE                          ; cpu_0_ic_tag_ram.mif ; Untyped                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                     ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                     ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                     ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                     ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                     ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                     ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                     ;
; CBXI_PARAMETER                     ; altsyncram_q8g1      ; Untyped                                                     ;
+------------------------------------+----------------------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht ;
+----------------+-------------------+----------------------------------------------------+
; Parameter Name ; Value             ; Type                                               ;
+----------------+-------------------+----------------------------------------------------+
; lpm_file       ; cpu_0_bht_ram.mif ; String                                             ;
+----------------+-------------------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                  ;
+------------------------------------+----------------------+-------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                               ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                            ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                          ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                          ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                        ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                               ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                               ;
; WIDTH_A                            ; 2                    ; Signed Integer                                        ;
; WIDTHAD_A                          ; 8                    ; Signed Integer                                        ;
; NUMWORDS_A                         ; 256                  ; Signed Integer                                        ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                               ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                               ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                               ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                               ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                               ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                               ;
; WIDTH_B                            ; 2                    ; Signed Integer                                        ;
; WIDTHAD_B                          ; 8                    ; Signed Integer                                        ;
; NUMWORDS_B                         ; 256                  ; Signed Integer                                        ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                               ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                               ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                               ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                               ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                               ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                               ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                               ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                               ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                               ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                               ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                               ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                               ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                               ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                               ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                               ;
; BYTE_SIZE                          ; 8                    ; Untyped                                               ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                               ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                               ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                               ;
; INIT_FILE                          ; cpu_0_bht_ram.mif    ; Untyped                                               ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                               ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                               ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                               ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                               ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                               ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                               ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                               ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                               ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                               ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                               ;
; CBXI_PARAMETER                     ; altsyncram_hsf1      ; Untyped                                               ;
+------------------------------------+----------------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a ;
+----------------+--------------------+---------------------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                                      ;
+----------------+--------------------+---------------------------------------------------------------------------+
; lpm_file       ; cpu_0_rf_ram_a.mif ; String                                                                    ;
+----------------+--------------------+---------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                          ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                       ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                    ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                  ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                  ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                       ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                       ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                       ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                       ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                       ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                       ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                       ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                       ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                       ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                       ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                       ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                       ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                       ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                       ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                       ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                       ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                       ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                       ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                       ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                       ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                       ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                       ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                       ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                       ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                       ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                       ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                       ;
; INIT_FILE                          ; cpu_0_rf_ram_a.mif   ; Untyped                                                                       ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                       ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                       ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                       ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                       ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                       ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                       ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                       ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                       ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                       ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                       ;
; CBXI_PARAMETER                     ; altsyncram_haf1      ; Untyped                                                                       ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b ;
+----------------+--------------------+---------------------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                                      ;
+----------------+--------------------+---------------------------------------------------------------------------+
; lpm_file       ; cpu_0_rf_ram_b.mif ; String                                                                    ;
+----------------+--------------------+---------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                          ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                       ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                    ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                  ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                  ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                       ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                       ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                       ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                       ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                       ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                       ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                       ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                       ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                       ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                       ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                       ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                       ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                       ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                       ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                       ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                       ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                       ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                       ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                       ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                       ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                       ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                       ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                       ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                       ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                       ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                       ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                       ;
; INIT_FILE                          ; cpu_0_rf_ram_b.mif   ; Untyped                                                                       ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                       ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                       ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                       ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                       ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                       ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                       ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                       ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                       ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                       ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                       ;
; CBXI_PARAMETER                     ; altsyncram_iaf1      ; Untyped                                                                       ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ;
+---------------------------------------+-------------------+-------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                    ;
+---------------------------------------+-------------------+-------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                              ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                            ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                            ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                          ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                 ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                 ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                 ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                 ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                 ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                 ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                 ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                 ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0             ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED      ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                 ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                 ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                 ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES               ; Untyped                                                                 ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                 ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                 ;
; INPUT_ACLR_A0                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_B0                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_REGISTER_A0                     ; UNREGISTERED      ; Untyped                                                                 ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_B0                     ; UNREGISTERED      ; Untyped                                                                 ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                 ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                 ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                 ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                 ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                 ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                 ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                 ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                 ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                 ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                 ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                 ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                 ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                 ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                 ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                 ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                 ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                 ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                 ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                 ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                 ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                 ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                 ;
; MULTIPLIER_ACLR0                      ; ACLR0             ; Untyped                                                                 ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                 ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                 ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                 ;
; MULTIPLIER_REGISTER0                  ; CLOCK0            ; Untyped                                                                 ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                 ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                 ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                 ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                          ;
; OUTPUT_ACLR                           ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_REGISTER                       ; UNREGISTERED      ; Untyped                                                                 ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                 ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                 ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                 ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                 ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                 ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                 ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                 ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                 ;
; port_addnsub1                         ; PORT_UNUSED       ; Untyped                                                                 ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                 ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                 ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                 ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                 ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                 ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                 ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                 ;
; port_signa                            ; PORT_UNUSED       ; Untyped                                                                 ;
; port_signb                            ; PORT_UNUSED       ; Untyped                                                                 ;
; REPRESENTATION_A                      ; UNSIGNED          ; Untyped                                                                 ;
; REPRESENTATION_B                      ; UNSIGNED          ; Untyped                                                                 ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                 ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                 ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                 ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                 ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                 ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                 ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                 ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                 ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                 ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                 ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                 ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                 ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                 ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                 ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                 ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                 ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                 ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                 ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                 ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0             ; Untyped                                                                 ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0             ; Untyped                                                                 ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                 ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                 ;
; SIGNED_REGISTER_A                     ; UNREGISTERED      ; Untyped                                                                 ;
; SIGNED_REGISTER_B                     ; UNREGISTERED      ; Untyped                                                                 ;
; WIDTH_A                               ; 16                ; Signed Integer                                                          ;
; WIDTH_B                               ; 16                ; Signed Integer                                                          ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                 ;
; WIDTH_RESULT                          ; 32                ; Signed Integer                                                          ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                 ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                 ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                 ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                 ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                 ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                 ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                 ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                 ;
; CBXI_PARAMETER                        ; mult_add_dfr2     ; Untyped                                                                 ;
; DEVICE_FAMILY                         ; Cyclone III       ; Untyped                                                                 ;
; WIDTH_C                               ; 22                ; Untyped                                                                 ;
; LOADCONST_VALUE                       ; 64                ; Untyped                                                                 ;
; PREADDER_MODE                         ; SIMPLE            ; Untyped                                                                 ;
; PREADDER_DIRECTION_0                  ; ADD               ; Untyped                                                                 ;
; PREADDER_DIRECTION_1                  ; ADD               ; Untyped                                                                 ;
; PREADDER_DIRECTION_2                  ; ADD               ; Untyped                                                                 ;
; PREADDER_DIRECTION_3                  ; ADD               ; Untyped                                                                 ;
; INPUT_REGISTER_C0                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_ACLR_C0                         ; ACLR0             ; Untyped                                                                 ;
; COEFSEL0_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; COEFSEL1_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; COEFSEL2_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; COEFSEL3_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; COEFSEL0_ACLR                         ; ACLR0             ; Untyped                                                                 ;
; COEFSEL1_ACLR                         ; ACLR0             ; Untyped                                                                 ;
; COEFSEL2_ACLR                         ; ACLR0             ; Untyped                                                                 ;
; COEFSEL3_ACLR                         ; ACLR0             ; Untyped                                                                 ;
; SYSTOLIC_DELAY1                       ; CLOCK0            ; Untyped                                                                 ;
; SYSTOLIC_DELAY3                       ; CLOCK0            ; Untyped                                                                 ;
; SYSTOLIC_ACLR1                        ; ACLR0             ; Untyped                                                                 ;
; SYSTOLIC_ACLR3                        ; ACLR0             ; Untyped                                                                 ;
; COEF0_0                               ; 0                 ; Untyped                                                                 ;
; COEF0_1                               ; 0                 ; Untyped                                                                 ;
; COEF0_2                               ; 0                 ; Untyped                                                                 ;
; COEF0_3                               ; 0                 ; Untyped                                                                 ;
; COEF0_4                               ; 0                 ; Untyped                                                                 ;
; COEF0_5                               ; 0                 ; Untyped                                                                 ;
; COEF0_6                               ; 0                 ; Untyped                                                                 ;
; COEF0_7                               ; 0                 ; Untyped                                                                 ;
; COEF1_0                               ; 0                 ; Untyped                                                                 ;
; COEF1_1                               ; 0                 ; Untyped                                                                 ;
; COEF1_2                               ; 0                 ; Untyped                                                                 ;
; COEF1_3                               ; 0                 ; Untyped                                                                 ;
; COEF1_4                               ; 0                 ; Untyped                                                                 ;
; COEF1_5                               ; 0                 ; Untyped                                                                 ;
; COEF1_6                               ; 0                 ; Untyped                                                                 ;
; COEF1_7                               ; 0                 ; Untyped                                                                 ;
; COEF2_0                               ; 0                 ; Untyped                                                                 ;
; COEF2_1                               ; 0                 ; Untyped                                                                 ;
; COEF2_2                               ; 0                 ; Untyped                                                                 ;
; COEF2_3                               ; 0                 ; Untyped                                                                 ;
; COEF2_4                               ; 0                 ; Untyped                                                                 ;
; COEF2_5                               ; 0                 ; Untyped                                                                 ;
; COEF2_6                               ; 0                 ; Untyped                                                                 ;
; COEF2_7                               ; 0                 ; Untyped                                                                 ;
; COEF3_0                               ; 0                 ; Untyped                                                                 ;
; COEF3_1                               ; 0                 ; Untyped                                                                 ;
; COEF3_2                               ; 0                 ; Untyped                                                                 ;
; COEF3_3                               ; 0                 ; Untyped                                                                 ;
; COEF3_4                               ; 0                 ; Untyped                                                                 ;
; COEF3_5                               ; 0                 ; Untyped                                                                 ;
; COEF3_6                               ; 0                 ; Untyped                                                                 ;
; COEF3_7                               ; 0                 ; Untyped                                                                 ;
; WIDTH_COEF                            ; 18                ; Untyped                                                                 ;
+---------------------------------------+-------------------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ;
+---------------------------------------+-------------------+-------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                    ;
+---------------------------------------+-------------------+-------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                              ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                            ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                            ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                          ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                 ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                 ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                 ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                 ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                 ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                 ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                 ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                 ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0             ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED      ; Untyped                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                 ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                 ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                 ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                 ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                 ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES               ; Untyped                                                                 ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                 ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                 ;
; INPUT_ACLR_A0                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_B0                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                 ;
; INPUT_REGISTER_A0                     ; UNREGISTERED      ; Untyped                                                                 ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_B0                     ; UNREGISTERED      ; Untyped                                                                 ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                 ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                 ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                 ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                 ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                 ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                 ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                 ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                 ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                 ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                 ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                 ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                 ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                 ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                 ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                 ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                 ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                 ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                 ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                 ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                 ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                 ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                 ;
; MULTIPLIER_ACLR0                      ; ACLR0             ; Untyped                                                                 ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                 ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                 ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                 ;
; MULTIPLIER_REGISTER0                  ; CLOCK0            ; Untyped                                                                 ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                 ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                 ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                 ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                          ;
; OUTPUT_ACLR                           ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_REGISTER                       ; UNREGISTERED      ; Untyped                                                                 ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                 ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                 ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                 ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                 ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                 ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                 ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                 ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                 ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                 ;
; port_addnsub1                         ; PORT_UNUSED       ; Untyped                                                                 ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                 ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                 ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                 ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                 ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                 ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                 ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                 ;
; port_signa                            ; PORT_UNUSED       ; Untyped                                                                 ;
; port_signb                            ; PORT_UNUSED       ; Untyped                                                                 ;
; REPRESENTATION_A                      ; UNSIGNED          ; Untyped                                                                 ;
; REPRESENTATION_B                      ; UNSIGNED          ; Untyped                                                                 ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                 ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                 ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                 ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                 ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                 ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                 ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                 ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                 ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                 ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                 ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                 ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                 ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                 ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                 ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                 ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                 ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                 ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                 ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                 ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0             ; Untyped                                                                 ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0             ; Untyped                                                                 ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                 ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                 ;
; SIGNED_REGISTER_A                     ; UNREGISTERED      ; Untyped                                                                 ;
; SIGNED_REGISTER_B                     ; UNREGISTERED      ; Untyped                                                                 ;
; WIDTH_A                               ; 16                ; Signed Integer                                                          ;
; WIDTH_B                               ; 16                ; Signed Integer                                                          ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                 ;
; WIDTH_RESULT                          ; 16                ; Signed Integer                                                          ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                 ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                 ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                 ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                 ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                 ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                 ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                 ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                 ;
; CBXI_PARAMETER                        ; mult_add_ffr2     ; Untyped                                                                 ;
; DEVICE_FAMILY                         ; Cyclone III       ; Untyped                                                                 ;
; WIDTH_C                               ; 22                ; Untyped                                                                 ;
; LOADCONST_VALUE                       ; 64                ; Untyped                                                                 ;
; PREADDER_MODE                         ; SIMPLE            ; Untyped                                                                 ;
; PREADDER_DIRECTION_0                  ; ADD               ; Untyped                                                                 ;
; PREADDER_DIRECTION_1                  ; ADD               ; Untyped                                                                 ;
; PREADDER_DIRECTION_2                  ; ADD               ; Untyped                                                                 ;
; PREADDER_DIRECTION_3                  ; ADD               ; Untyped                                                                 ;
; INPUT_REGISTER_C0                     ; CLOCK0            ; Untyped                                                                 ;
; INPUT_ACLR_C0                         ; ACLR0             ; Untyped                                                                 ;
; COEFSEL0_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; COEFSEL1_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; COEFSEL2_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; COEFSEL3_REGISTER                     ; CLOCK0            ; Untyped                                                                 ;
; COEFSEL0_ACLR                         ; ACLR0             ; Untyped                                                                 ;
; COEFSEL1_ACLR                         ; ACLR0             ; Untyped                                                                 ;
; COEFSEL2_ACLR                         ; ACLR0             ; Untyped                                                                 ;
; COEFSEL3_ACLR                         ; ACLR0             ; Untyped                                                                 ;
; SYSTOLIC_DELAY1                       ; CLOCK0            ; Untyped                                                                 ;
; SYSTOLIC_DELAY3                       ; CLOCK0            ; Untyped                                                                 ;
; SYSTOLIC_ACLR1                        ; ACLR0             ; Untyped                                                                 ;
; SYSTOLIC_ACLR3                        ; ACLR0             ; Untyped                                                                 ;
; COEF0_0                               ; 0                 ; Untyped                                                                 ;
; COEF0_1                               ; 0                 ; Untyped                                                                 ;
; COEF0_2                               ; 0                 ; Untyped                                                                 ;
; COEF0_3                               ; 0                 ; Untyped                                                                 ;
; COEF0_4                               ; 0                 ; Untyped                                                                 ;
; COEF0_5                               ; 0                 ; Untyped                                                                 ;
; COEF0_6                               ; 0                 ; Untyped                                                                 ;
; COEF0_7                               ; 0                 ; Untyped                                                                 ;
; COEF1_0                               ; 0                 ; Untyped                                                                 ;
; COEF1_1                               ; 0                 ; Untyped                                                                 ;
; COEF1_2                               ; 0                 ; Untyped                                                                 ;
; COEF1_3                               ; 0                 ; Untyped                                                                 ;
; COEF1_4                               ; 0                 ; Untyped                                                                 ;
; COEF1_5                               ; 0                 ; Untyped                                                                 ;
; COEF1_6                               ; 0                 ; Untyped                                                                 ;
; COEF1_7                               ; 0                 ; Untyped                                                                 ;
; COEF2_0                               ; 0                 ; Untyped                                                                 ;
; COEF2_1                               ; 0                 ; Untyped                                                                 ;
; COEF2_2                               ; 0                 ; Untyped                                                                 ;
; COEF2_3                               ; 0                 ; Untyped                                                                 ;
; COEF2_4                               ; 0                 ; Untyped                                                                 ;
; COEF2_5                               ; 0                 ; Untyped                                                                 ;
; COEF2_6                               ; 0                 ; Untyped                                                                 ;
; COEF2_7                               ; 0                 ; Untyped                                                                 ;
; COEF3_0                               ; 0                 ; Untyped                                                                 ;
; COEF3_1                               ; 0                 ; Untyped                                                                 ;
; COEF3_2                               ; 0                 ; Untyped                                                                 ;
; COEF3_3                               ; 0                 ; Untyped                                                                 ;
; COEF3_4                               ; 0                 ; Untyped                                                                 ;
; COEF3_5                               ; 0                 ; Untyped                                                                 ;
; COEF3_6                               ; 0                 ; Untyped                                                                 ;
; COEF3_7                               ; 0                 ; Untyped                                                                 ;
; WIDTH_COEF                            ; 18                ; Untyped                                                                 ;
+---------------------------------------+-------------------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value                             ; Type                                                                                                                                                                 ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_ociram_default_contents.mif ; String                                                                                                                                                               ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                             ; Type                                                                                                                                                                       ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                                 ; Untyped                                                                                                                                                                    ;
; AUTO_CARRY_CHAINS                  ; ON                                ; AUTO_CARRY                                                                                                                                                                 ;
; IGNORE_CARRY_BUFFERS               ; OFF                               ; IGNORE_CARRY                                                                                                                                                               ;
; AUTO_CASCADE_CHAINS                ; ON                                ; AUTO_CASCADE                                                                                                                                                               ;
; IGNORE_CASCADE_BUFFERS             ; OFF                               ; IGNORE_CASCADE                                                                                                                                                             ;
; WIDTH_BYTEENA                      ; 1                                 ; Untyped                                                                                                                                                                    ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT                   ; Untyped                                                                                                                                                                    ;
; WIDTH_A                            ; 32                                ; Signed Integer                                                                                                                                                             ;
; WIDTHAD_A                          ; 8                                 ; Signed Integer                                                                                                                                                             ;
; NUMWORDS_A                         ; 256                               ; Signed Integer                                                                                                                                                             ;
; OUTDATA_REG_A                      ; UNREGISTERED                      ; Untyped                                                                                                                                                                    ;
; ADDRESS_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                    ;
; OUTDATA_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                    ;
; WRCONTROL_ACLR_A                   ; NONE                              ; Untyped                                                                                                                                                                    ;
; INDATA_ACLR_A                      ; NONE                              ; Untyped                                                                                                                                                                    ;
; BYTEENA_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                    ;
; WIDTH_B                            ; 32                                ; Signed Integer                                                                                                                                                             ;
; WIDTHAD_B                          ; 8                                 ; Signed Integer                                                                                                                                                             ;
; NUMWORDS_B                         ; 256                               ; Signed Integer                                                                                                                                                             ;
; INDATA_REG_B                       ; CLOCK1                            ; Untyped                                                                                                                                                                    ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                            ; Untyped                                                                                                                                                                    ;
; RDCONTROL_REG_B                    ; CLOCK1                            ; Untyped                                                                                                                                                                    ;
; ADDRESS_REG_B                      ; CLOCK1                            ; Untyped                                                                                                                                                                    ;
; OUTDATA_REG_B                      ; UNREGISTERED                      ; Untyped                                                                                                                                                                    ;
; BYTEENA_REG_B                      ; CLOCK1                            ; Untyped                                                                                                                                                                    ;
; INDATA_ACLR_B                      ; NONE                              ; Untyped                                                                                                                                                                    ;
; WRCONTROL_ACLR_B                   ; NONE                              ; Untyped                                                                                                                                                                    ;
; ADDRESS_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                    ;
; OUTDATA_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                    ;
; RDCONTROL_ACLR_B                   ; NONE                              ; Untyped                                                                                                                                                                    ;
; BYTEENA_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                    ;
; WIDTH_BYTEENA_A                    ; 4                                 ; Signed Integer                                                                                                                                                             ;
; WIDTH_BYTEENA_B                    ; 1                                 ; Untyped                                                                                                                                                                    ;
; RAM_BLOCK_TYPE                     ; AUTO                              ; Untyped                                                                                                                                                                    ;
; BYTE_SIZE                          ; 8                                 ; Untyped                                                                                                                                                                    ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                          ; Untyped                                                                                                                                                                    ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ              ; Untyped                                                                                                                                                                    ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ              ; Untyped                                                                                                                                                                    ;
; INIT_FILE                          ; cpu_0_ociram_default_contents.mif ; Untyped                                                                                                                                                                    ;
; INIT_FILE_LAYOUT                   ; PORT_A                            ; Untyped                                                                                                                                                                    ;
; MAXIMUM_DEPTH                      ; 0                                 ; Untyped                                                                                                                                                                    ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                            ; Untyped                                                                                                                                                                    ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                            ; Untyped                                                                                                                                                                    ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                            ; Untyped                                                                                                                                                                    ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                            ; Untyped                                                                                                                                                                    ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                   ; Untyped                                                                                                                                                                    ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                   ; Untyped                                                                                                                                                                    ;
; ENABLE_ECC                         ; FALSE                             ; Untyped                                                                                                                                                                    ;
; WIDTH_ECCSTATUS                    ; 3                                 ; Untyped                                                                                                                                                                    ;
; DEVICE_FAMILY                      ; Cyclone III                       ; Untyped                                                                                                                                                                    ;
; CBXI_PARAMETER                     ; altsyncram_l872                   ; Untyped                                                                                                                                                                    ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                              ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                        ;
+------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                     ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                              ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                     ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                                                                                                                                     ;
; WIDTH_A                            ; 36                   ; Signed Integer                                                                                                                                                                              ;
; WIDTHAD_A                          ; 7                    ; Signed Integer                                                                                                                                                                              ;
; NUMWORDS_A                         ; 128                  ; Signed Integer                                                                                                                                                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                     ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                     ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                     ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                     ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                     ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                     ;
; WIDTH_B                            ; 36                   ; Signed Integer                                                                                                                                                                              ;
; WIDTHAD_B                          ; 7                    ; Signed Integer                                                                                                                                                                              ;
; NUMWORDS_B                         ; 128                  ; Signed Integer                                                                                                                                                                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                     ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                     ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                     ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                     ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                     ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                     ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                     ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                     ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                     ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                                                                                                                     ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                     ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                     ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                                                                                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                                                                                                                                     ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                     ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                     ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                     ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                     ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                     ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                     ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                     ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                     ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                     ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                                                                                                                                     ;
; CBXI_PARAMETER                     ; altsyncram_n802      ; Untyped                                                                                                                                                                                     ;
+------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                              ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                               ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                               ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                     ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                               ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                     ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy ;
+-------------------------+------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value                  ; Type                                                                                                                                                                 ;
+-------------------------+------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sld_mfg_id              ; 70                     ; Signed Integer                                                                                                                                                       ;
; sld_type_id             ; 34                     ; Signed Integer                                                                                                                                                       ;
; sld_version             ; 3                      ; Signed Integer                                                                                                                                                       ;
; sld_instance_index      ; 0                      ; Signed Integer                                                                                                                                                       ;
; sld_auto_instance_index ; YES                    ; String                                                                                                                                                               ;
; sld_ir_width            ; 2                      ; Signed Integer                                                                                                                                                       ;
; sld_sim_n_scan          ; 0                      ; Signed Integer                                                                                                                                                       ;
; sld_sim_action          ;                        ; String                                                                                                                                                               ;
; sld_sim_total_length    ; 0                      ; Signed Integer                                                                                                                                                       ;
; lpm_type                ; sld_virtual_jtag_basic ; String                                                                                                                                                               ;
; lpm_hint                ; UNUSED                 ; String                                                                                                                                                               ;
+-------------------------+------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom ;
+------------------------------------+--------------------------------------+-----------------------------------------------------+
; Parameter Name                     ; Value                                ; Type                                                ;
+------------------------------------+--------------------------------------+-----------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                                    ; Untyped                                             ;
; AUTO_CARRY_CHAINS                  ; ON                                   ; AUTO_CARRY                                          ;
; IGNORE_CARRY_BUFFERS               ; OFF                                  ; IGNORE_CARRY                                        ;
; AUTO_CASCADE_CHAINS                ; ON                                   ; AUTO_CASCADE                                        ;
; IGNORE_CASCADE_BUFFERS             ; OFF                                  ; IGNORE_CASCADE                                      ;
; WIDTH_BYTEENA                      ; 1                                    ; Untyped                                             ;
; OPERATION_MODE                     ; ROM                                  ; Untyped                                             ;
; WIDTH_A                            ; 32                                   ; Signed Integer                                      ;
; WIDTHAD_A                          ; 8                                    ; Signed Integer                                      ;
; NUMWORDS_A                         ; 256                                  ; Signed Integer                                      ;
; OUTDATA_REG_A                      ; UNREGISTERED                         ; Untyped                                             ;
; ADDRESS_ACLR_A                     ; NONE                                 ; Untyped                                             ;
; OUTDATA_ACLR_A                     ; NONE                                 ; Untyped                                             ;
; WRCONTROL_ACLR_A                   ; NONE                                 ; Untyped                                             ;
; INDATA_ACLR_A                      ; NONE                                 ; Untyped                                             ;
; BYTEENA_ACLR_A                     ; NONE                                 ; Untyped                                             ;
; WIDTH_B                            ; 1                                    ; Untyped                                             ;
; WIDTHAD_B                          ; 1                                    ; Untyped                                             ;
; NUMWORDS_B                         ; 1                                    ; Untyped                                             ;
; INDATA_REG_B                       ; CLOCK1                               ; Untyped                                             ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                               ; Untyped                                             ;
; RDCONTROL_REG_B                    ; CLOCK1                               ; Untyped                                             ;
; ADDRESS_REG_B                      ; CLOCK1                               ; Untyped                                             ;
; OUTDATA_REG_B                      ; UNREGISTERED                         ; Untyped                                             ;
; BYTEENA_REG_B                      ; CLOCK1                               ; Untyped                                             ;
; INDATA_ACLR_B                      ; NONE                                 ; Untyped                                             ;
; WRCONTROL_ACLR_B                   ; NONE                                 ; Untyped                                             ;
; ADDRESS_ACLR_B                     ; NONE                                 ; Untyped                                             ;
; OUTDATA_ACLR_B                     ; NONE                                 ; Untyped                                             ;
; RDCONTROL_ACLR_B                   ; NONE                                 ; Untyped                                             ;
; BYTEENA_ACLR_B                     ; NONE                                 ; Untyped                                             ;
; WIDTH_BYTEENA_A                    ; 1                                    ; Untyped                                             ;
; WIDTH_BYTEENA_B                    ; 1                                    ; Untyped                                             ;
; RAM_BLOCK_TYPE                     ; AUTO                                 ; Untyped                                             ;
; BYTE_SIZE                          ; 8                                    ; Signed Integer                                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                            ; Untyped                                             ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                 ; Untyped                                             ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                 ; Untyped                                             ;
; INIT_FILE                          ; epcs_flash_controller_0_boot_rom.hex ; Untyped                                             ;
; INIT_FILE_LAYOUT                   ; PORT_A                               ; Untyped                                             ;
; MAXIMUM_DEPTH                      ; 0                                    ; Untyped                                             ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                               ; Untyped                                             ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                               ; Untyped                                             ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                               ; Untyped                                             ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                               ; Untyped                                             ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                      ; Untyped                                             ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                      ; Untyped                                             ;
; ENABLE_ECC                         ; FALSE                                ; Untyped                                             ;
; WIDTH_ECCSTATUS                    ; 3                                    ; Untyped                                             ;
; DEVICE_FAMILY                      ; Cyclone III                          ; Untyped                                             ;
; CBXI_PARAMETER                     ; altsyncram_tj41                      ; Untyped                                             ;
+------------------------------------+--------------------------------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                        ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                  ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                              ;
; lpm_width               ; 8           ; Signed Integer                                                                              ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                              ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                              ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                     ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                     ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                     ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                     ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                     ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                     ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                     ;
; USE_EAB                 ; ON          ; Untyped                                                                                     ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                     ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                     ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                     ;
; CBXI_PARAMETER          ; scfifo_aq21 ; Untyped                                                                                     ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                        ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                  ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                              ;
; lpm_width               ; 8           ; Signed Integer                                                                              ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                              ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                              ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                     ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                     ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                     ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                     ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                     ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                     ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                     ;
; USE_EAB                 ; ON          ; Untyped                                                                                     ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                     ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                     ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                     ;
; CBXI_PARAMETER          ; scfifo_aq21 ; Untyped                                                                                     ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic ;
+-------------------------+----------------------------------+-------------------------------------------------------------+
; Parameter Name          ; Value                            ; Type                                                        ;
+-------------------------+----------------------------------+-------------------------------------------------------------+
; INSTANCE_ID             ; 0                                ; Signed Integer                                              ;
; SLD_NODE_INFO           ; 00001100000000000110111000000000 ; Unsigned Binary                                             ;
; SLD_AUTO_INSTANCE_INDEX ; YES                              ; String                                                      ;
; LOG2_TXFIFO_DEPTH       ; 6                                ; Signed Integer                                              ;
; LOG2_RXFIFO_DEPTH       ; 6                                ; Signed Integer                                              ;
; RESERVED                ; 0                                ; Signed Integer                                              ;
; DATA_WIDTH              ; 8                                ; Signed Integer                                              ;
; NODE_IR_WIDTH           ; 1                                ; Signed Integer                                              ;
; SCAN_LENGTH             ; 11                               ; Signed Integer                                              ;
+-------------------------+----------------------------------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub                                             ;
+--------------------------+------------------------------------------------------------------+-----------------+
; Parameter Name           ; Value                                                            ; Type            ;
+--------------------------+------------------------------------------------------------------+-----------------+
; sld_hub_ip_version       ; 1                                                                ; Untyped         ;
; sld_hub_ip_minor_version ; 4                                                                ; Untyped         ;
; sld_common_ip_version    ; 0                                                                ; Untyped         ;
; device_family            ; Cyclone III                                                      ; Untyped         ;
; n_nodes                  ; 2                                                                ; Untyped         ;
; n_sel_bits               ; 2                                                                ; Untyped         ;
; n_node_ir_bits           ; 5                                                                ; Untyped         ;
; node_info                ; 0000110000000000011011100000000000011001000100000100011000000000 ; Unsigned Binary ;
; compilation_mode         ; 1                                                                ; Untyped         ;
; BROADCAST_FEATURE        ; 1                                                                ; Signed Integer  ;
; FORCE_IR_CAPTURE_FEATURE ; 1                                                                ; Signed Integer  ;
+--------------------------+------------------------------------------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                                                                                                                                                                       ;
+-------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                                      ; Value                                                                                                                                                                                                      ;
+-------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances                ; 8                                                                                                                                                                                                          ;
; Entity Instance                           ; cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram                                                                                                                               ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                  ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_A                         ; 1024                                                                                                                                                                                                       ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_B                         ; 1024                                                                                                                                                                                                       ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                       ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                  ;
; Entity Instance                           ; cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram                                                                                                                                 ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                  ;
;     -- WIDTH_A                            ; 23                                                                                                                                                                                                         ;
;     -- NUMWORDS_A                         ; 128                                                                                                                                                                                                        ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- WIDTH_B                            ; 23                                                                                                                                                                                                         ;
;     -- NUMWORDS_B                         ; 128                                                                                                                                                                                                        ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                       ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                   ;
; Entity Instance                           ; cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram                                                                                                                                       ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                  ;
;     -- WIDTH_A                            ; 2                                                                                                                                                                                                          ;
;     -- NUMWORDS_A                         ; 256                                                                                                                                                                                                        ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- WIDTH_B                            ; 2                                                                                                                                                                                                          ;
;     -- NUMWORDS_B                         ; 256                                                                                                                                                                                                        ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                       ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                   ;
; Entity Instance                           ; cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram                                                                                                               ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                  ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_A                         ; 32                                                                                                                                                                                                         ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_B                         ; 32                                                                                                                                                                                                         ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                       ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                   ;
; Entity Instance                           ; cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram                                                                                                               ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                  ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_A                         ; 32                                                                                                                                                                                                         ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_B                         ; 32                                                                                                                                                                                                         ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                       ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                   ;
; Entity Instance                           ; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram     ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                            ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_A                         ; 256                                                                                                                                                                                                        ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_B                         ; 256                                                                                                                                                                                                        ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                       ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                   ;
; Entity Instance                           ; cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                            ;
;     -- WIDTH_A                            ; 36                                                                                                                                                                                                         ;
;     -- NUMWORDS_A                         ; 128                                                                                                                                                                                                        ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- WIDTH_B                            ; 36                                                                                                                                                                                                         ;
;     -- NUMWORDS_B                         ; 128                                                                                                                                                                                                        ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                       ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                   ;
; Entity Instance                           ; epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom                                                                                                                         ;
;     -- OPERATION_MODE                     ; ROM                                                                                                                                                                                                        ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                         ;
;     -- NUMWORDS_A                         ; 256                                                                                                                                                                                                        ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- WIDTH_B                            ; 1                                                                                                                                                                                                          ;
;     -- NUMWORDS_B                         ; 1                                                                                                                                                                                                          ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                               ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                       ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                  ;
+-------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; altmult_add Parameter Settings by Entity Instance                                                                              ;
+---------------------------------------+----------------------------------------------------------------------------------------+
; Name                                  ; Value                                                                                  ;
+---------------------------------------+----------------------------------------------------------------------------------------+
; Number of entity instances            ; 2                                                                                      ;
; Entity Instance                       ; cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                    ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                      ;
;     -- port_signa                     ; PORT_UNUSED                                                                            ;
;     -- port_signb                     ; PORT_UNUSED                                                                            ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                               ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                               ;
;     -- WIDTH_A                        ; 16                                                                                     ;
;     -- WIDTH_B                        ; 16                                                                                     ;
;     -- WIDTH_RESULT                   ; 32                                                                                     ;
; Entity Instance                       ; cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                    ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                      ;
;     -- port_signa                     ; PORT_UNUSED                                                                            ;
;     -- port_signb                     ; PORT_UNUSED                                                                            ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                               ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                               ;
;     -- WIDTH_A                        ; 16                                                                                     ;
;     -- WIDTH_B                        ; 16                                                                                     ;
;     -- WIDTH_RESULT                   ; 16                                                                                     ;
+---------------------------------------+----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                        ;
+----------------------------+----------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                  ;
+----------------------------+----------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                      ;
; Entity Instance            ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
;     -- FIFO Type           ; Single Clock                                                                           ;
;     -- lpm_width           ; 8                                                                                      ;
;     -- LPM_NUMWORDS        ; 64                                                                                     ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                    ;
;     -- USE_EAB             ; ON                                                                                     ;
; Entity Instance            ; jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ;
;     -- FIFO Type           ; Single Clock                                                                           ;
;     -- lpm_width           ; 8                                                                                      ;
;     -- LPM_NUMWORDS        ; 64                                                                                     ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                    ;
;     -- USE_EAB             ; ON                                                                                     ;
+----------------------------+----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch" ;
+---------+-------+----------+---------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                             ;
+---------+-------+----------+---------------------------------------------------------------------+
; data_in ; Input ; Info     ; Stuck at VCC                                                        ;
+---------+-------+----------+---------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch" ;
+---------+-------+----------+---------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                               ;
+---------+-------+----------+---------------------------------------------------------------------------------------+
; data_in ; Input ; Info     ; Stuck at VCC                                                                          ;
+---------+-------+----------+---------------------------------------------------------------------------------------+


+---------------------------------------------+
; Port Connectivity Checks: "sysid:the_sysid" ;
+-------+-------+----------+------------------+
; Port  ; Type  ; Severity ; Details          ;
+-------+-------+----------+------------------+
; clock ; Input ; Info     ; Stuck at GND     ;
+-------+-------+----------+------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module"              ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                             ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; almost_empty ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; almost_full  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1" ;
+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                                                                                        ;
+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+
; clear_fifo ; Input  ; Info     ; Stuck at GND                                                                                                                                   ;
; empty      ; Output ; Info     ; Explicitly unconnected                                                                                                                         ;
; full       ; Output ; Info     ; Explicitly unconnected                                                                                                                         ;
; sync_reset ; Input  ; Info     ; Stuck at GND                                                                                                                                   ;
+------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1" ;
+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                                                                          ;
+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------+
; clear_fifo ; Input  ; Info     ; Stuck at GND                                                                                                                     ;
; empty      ; Output ; Info     ; Explicitly unconnected                                                                                                           ;
; full       ; Output ; Info     ; Explicitly unconnected                                                                                                           ;
; sync_reset ; Input  ; Info     ; Stuck at GND                                                                                                                     ;
+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"                                                                           ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                                                                                                                      ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; raw_tck        ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tck            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tdi            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; rti            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; shift          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; update         ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; usr1           ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; clr            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; ena            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; ir_in          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tdo            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; irq            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; ir_out         ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; jtag_state_cdr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; jtag_state_sdr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; jtag_state_udr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave"                                                        ;
+-----------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                                ; Type   ; Severity ; Details                                                                             ;
+-----------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-----------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port"                                            ;
+-----------------------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                                            ; Type   ; Severity ; Details                                                                             ;
+-----------------------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; epcs_flash_controller_0_epcs_control_port_dataavailable_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; epcs_flash_controller_0_epcs_control_port_readyfordata_from_sa  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-----------------------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1"                                          ;
+-----------+--------+----------+-------------------------------------------------------------------------------------+
; Port      ; Type   ; Severity ; Details                                                                             ;
+-----------+--------+----------+-------------------------------------------------------------------------------------+
; clk[4..2] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; inclk[1]  ; Input  ; Info     ; Stuck at GND                                                                        ;
+-----------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_clock_3:the_NIOS_clock_3"                                                                      ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                 ; Type   ; Severity ; Details                                                                             ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; master_nativeaddress ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_clock_3_in_arbitrator:the_NIOS_clock_3_in"                                                                    ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                ; Type   ; Severity ; Details                                                                             ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; NIOS_clock_3_in_endofpacket_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_clock_2:the_NIOS_clock_2"                                                                      ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                 ; Type   ; Severity ; Details                                                                             ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; master_nativeaddress ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; slave_writedata      ; Input  ; Info     ; Stuck at GND                                                                        ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_clock_2_in_arbitrator:the_NIOS_clock_2_in"                                                                    ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                ; Type   ; Severity ; Details                                                                             ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; NIOS_clock_2_in_endofpacket_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------+
; Port Connectivity Checks: "NIOS_clock_1:the_NIOS_clock_1" ;
+--------------------+-------+----------+-------------------+
; Port               ; Type  ; Severity ; Details           ;
+--------------------+-------+----------+-------------------+
; master_endofpacket ; Input ; Info     ; Stuck at GND      ;
+--------------------+-------+----------+-------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_clock_1_in_arbitrator:the_NIOS_clock_1_in"                                                                    ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                ; Type   ; Severity ; Details                                                                             ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; NIOS_clock_1_in_endofpacket_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_clock_0:the_NIOS_clock_0"                                                                      ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                 ; Type   ; Severity ; Details                                                                             ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; master_endofpacket   ; Input  ; Info     ; Stuck at GND                                                                        ;
; master_nativeaddress ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "NIOS_clock_0_in_arbitrator:the_NIOS_clock_0_in"                                                                    ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                ; Type   ; Severity ; Details                                                                             ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; NIOS_clock_0_in_endofpacket_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:15     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
    Info: Processing started: Thu May 03 11:14:34 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sdram_test -c sdram_test
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 4 design units, including 4 entities, in source file altpll_0.v
    Info: Found entity 1: altpll_0_dffpipe_l2c
    Info: Found entity 2: altpll_0_stdsync_sv6
    Info: Found entity 3: altpll_0_altpll_lpa2
    Info: Found entity 4: altpll_0
Info: Found 1 design units, including 1 entities, in source file software/sdram_test.bdf
    Info: Found entity 1: sdram_test
Info: Found 1 design units, including 1 entities, in source file software/fengpin.v
    Info: Found entity 1: fengpin
Warning: Using design file nios.v, which is not specified as a design file for the current project, but contains definitions for 24 design units and 24 entities in project
    Info: Found entity 1: NIOS_clock_0_in_arbitrator
    Info: Found entity 2: NIOS_clock_0_out_arbitrator
    Info: Found entity 3: NIOS_clock_1_in_arbitrator
    Info: Found entity 4: NIOS_clock_1_out_arbitrator
    Info: Found entity 5: NIOS_clock_2_in_arbitrator
    Info: Found entity 6: NIOS_clock_2_out_arbitrator
    Info: Found entity 7: NIOS_clock_3_in_arbitrator
    Info: Found entity 8: NIOS_clock_3_out_arbitrator
    Info: Found entity 9: altpll_0_pll_slave_arbitrator
    Info: Found entity 10: cpu_0_jtag_debug_module_arbitrator
    Info: Found entity 11: epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module
    Info: Found entity 12: jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module
    Info: Found entity 13: cpu_0_data_master_arbitrator
    Info: Found entity 14: cpu_0_instruction_master_arbitrator
    Info: Found entity 15: epcs_flash_controller_0_epcs_control_port_arbitrator
    Info: Found entity 16: jtag_uart_0_avalon_jtag_slave_arbitrator
    Info: Found entity 17: pio_0_s1_arbitrator
    Info: Found entity 18: rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module
    Info: Found entity 19: rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module
    Info: Found entity 20: sdram_0_s1_arbitrator
    Info: Found entity 21: sysid_control_slave_arbitrator
    Info: Found entity 22: NIOS_reset_altpll_0_c0_out_domain_synch_module
    Info: Found entity 23: NIOS_reset_clk_ex_domain_synch_module
    Info: Found entity 24: NIOS
Info: Elaborating entity "NIOS" for the top level hierarchy
Info: Elaborating entity "NIOS_clock_0_in_arbitrator" for hierarchy "NIOS_clock_0_in_arbitrator:the_NIOS_clock_0_in"
Info: Elaborating entity "NIOS_clock_0_out_arbitrator" for hierarchy "NIOS_clock_0_out_arbitrator:the_NIOS_clock_0_out"
Warning: Using design file nios_clock_0.v, which is not specified as a design file for the current project, but contains definitions for 5 design units and 5 entities in project
    Info: Found entity 1: NIOS_clock_0_edge_to_pulse
    Info: Found entity 2: NIOS_clock_0_slave_FSM
    Info: Found entity 3: NIOS_clock_0_master_FSM
    Info: Found entity 4: NIOS_clock_0_bit_pipe
    Info: Found entity 5: NIOS_clock_0
Info: Elaborating entity "NIOS_clock_0" for hierarchy "NIOS_clock_0:the_NIOS_clock_0"
Info: Elaborating entity "altera_std_synchronizer" for hierarchy "NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer"
Info: Elaborated megafunction instantiation "NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer"
Info: Instantiated megafunction "NIOS_clock_0:the_NIOS_clock_0|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter:
    Info: Parameter "depth" = "2"
Info: Elaborating entity "NIOS_clock_0_edge_to_pulse" for hierarchy "NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "NIOS_clock_0_slave_FSM" for hierarchy "NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_slave_FSM:slave_FSM"
Info: Elaborating entity "NIOS_clock_0_master_FSM" for hierarchy "NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_master_FSM:master_FSM"
Info: Elaborating entity "NIOS_clock_0_bit_pipe" for hierarchy "NIOS_clock_0:the_NIOS_clock_0|NIOS_clock_0_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "NIOS_clock_1_in_arbitrator" for hierarchy "NIOS_clock_1_in_arbitrator:the_NIOS_clock_1_in"
Info: Elaborating entity "NIOS_clock_1_out_arbitrator" for hierarchy "NIOS_clock_1_out_arbitrator:the_NIOS_clock_1_out"
Warning: Using design file nios_clock_1.v, which is not specified as a design file for the current project, but contains definitions for 5 design units and 5 entities in project
    Info: Found entity 1: NIOS_clock_1_edge_to_pulse
    Info: Found entity 2: NIOS_clock_1_slave_FSM
    Info: Found entity 3: NIOS_clock_1_master_FSM
    Info: Found entity 4: NIOS_clock_1_bit_pipe
    Info: Found entity 5: NIOS_clock_1
Info: Elaborating entity "NIOS_clock_1" for hierarchy "NIOS_clock_1:the_NIOS_clock_1"
Info: Elaborating entity "NIOS_clock_1_edge_to_pulse" for hierarchy "NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "NIOS_clock_1_slave_FSM" for hierarchy "NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_slave_FSM:slave_FSM"
Info: Elaborating entity "NIOS_clock_1_master_FSM" for hierarchy "NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_master_FSM:master_FSM"
Info: Elaborating entity "NIOS_clock_1_bit_pipe" for hierarchy "NIOS_clock_1:the_NIOS_clock_1|NIOS_clock_1_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "NIOS_clock_2_in_arbitrator" for hierarchy "NIOS_clock_2_in_arbitrator:the_NIOS_clock_2_in"
Info: Elaborating entity "NIOS_clock_2_out_arbitrator" for hierarchy "NIOS_clock_2_out_arbitrator:the_NIOS_clock_2_out"
Warning: Using design file nios_clock_2.v, which is not specified as a design file for the current project, but contains definitions for 5 design units and 5 entities in project
    Info: Found entity 1: NIOS_clock_2_edge_to_pulse
    Info: Found entity 2: NIOS_clock_2_slave_FSM
    Info: Found entity 3: NIOS_clock_2_master_FSM
    Info: Found entity 4: NIOS_clock_2_bit_pipe
    Info: Found entity 5: NIOS_clock_2
Info: Elaborating entity "NIOS_clock_2" for hierarchy "NIOS_clock_2:the_NIOS_clock_2"
Info: Elaborating entity "NIOS_clock_2_edge_to_pulse" for hierarchy "NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "NIOS_clock_2_slave_FSM" for hierarchy "NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_slave_FSM:slave_FSM"
Info: Elaborating entity "NIOS_clock_2_master_FSM" for hierarchy "NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_master_FSM:master_FSM"
Info: Elaborating entity "NIOS_clock_2_bit_pipe" for hierarchy "NIOS_clock_2:the_NIOS_clock_2|NIOS_clock_2_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "NIOS_clock_3_in_arbitrator" for hierarchy "NIOS_clock_3_in_arbitrator:the_NIOS_clock_3_in"
Info: Elaborating entity "NIOS_clock_3_out_arbitrator" for hierarchy "NIOS_clock_3_out_arbitrator:the_NIOS_clock_3_out"
Warning: Using design file nios_clock_3.v, which is not specified as a design file for the current project, but contains definitions for 5 design units and 5 entities in project
    Info: Found entity 1: NIOS_clock_3_edge_to_pulse
    Info: Found entity 2: NIOS_clock_3_slave_FSM
    Info: Found entity 3: NIOS_clock_3_master_FSM
    Info: Found entity 4: NIOS_clock_3_bit_pipe
    Info: Found entity 5: NIOS_clock_3
Info: Elaborating entity "NIOS_clock_3" for hierarchy "NIOS_clock_3:the_NIOS_clock_3"
Info: Elaborating entity "NIOS_clock_3_edge_to_pulse" for hierarchy "NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "NIOS_clock_3_slave_FSM" for hierarchy "NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_slave_FSM:slave_FSM"
Info: Elaborating entity "NIOS_clock_3_master_FSM" for hierarchy "NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_master_FSM:master_FSM"
Info: Elaborating entity "NIOS_clock_3_bit_pipe" for hierarchy "NIOS_clock_3:the_NIOS_clock_3|NIOS_clock_3_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "altpll_0_pll_slave_arbitrator" for hierarchy "altpll_0_pll_slave_arbitrator:the_altpll_0_pll_slave"
Info: Elaborating entity "altpll_0" for hierarchy "altpll_0:the_altpll_0"
Info: Elaborating entity "altpll_0_stdsync_sv6" for hierarchy "altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2"
Info: Elaborating entity "altpll_0_dffpipe_l2c" for hierarchy "altpll_0:the_altpll_0|altpll_0_stdsync_sv6:stdsync2|altpll_0_dffpipe_l2c:dffpipe3"
Info: Elaborating entity "altpll_0_altpll_lpa2" for hierarchy "altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1"
Info: Elaborating entity "cpu_0_jtag_debug_module_arbitrator" for hierarchy "cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module"
Info: Elaborating entity "cpu_0_data_master_arbitrator" for hierarchy "cpu_0_data_master_arbitrator:the_cpu_0_data_master"
Info: Elaborating entity "epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module" for hierarchy "cpu_0_data_master_arbitrator:the_cpu_0_data_master|epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master_module:epcs_flash_controller_0_epcs_control_port_irq_from_sa_clock_crossing_cpu_0_data_master"
Info: Elaborating entity "jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module" for hierarchy "cpu_0_data_master_arbitrator:the_cpu_0_data_master|jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master_module:jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_cpu_0_data_master"
Info: Elaborating entity "cpu_0_instruction_master_arbitrator" for hierarchy "cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master"
Info: Found 27 design units, including 27 entities, in source file cpu_0.v
    Info: Found entity 1: cpu_0_ic_data_module
    Info: Found entity 2: cpu_0_ic_tag_module
    Info: Found entity 3: cpu_0_bht_module
    Info: Found entity 4: cpu_0_register_bank_a_module
    Info: Found entity 5: cpu_0_register_bank_b_module
    Info: Found entity 6: cpu_0_nios2_oci_debug
    Info: Found entity 7: cpu_0_ociram_lpm_dram_bdp_component_module
    Info: Found entity 8: cpu_0_nios2_ocimem
    Info: Found entity 9: cpu_0_nios2_avalon_reg
    Info: Found entity 10: cpu_0_nios2_oci_break
    Info: Found entity 11: cpu_0_nios2_oci_xbrk
    Info: Found entity 12: cpu_0_nios2_oci_match_single
    Info: Found entity 13: cpu_0_nios2_oci_match_paired
    Info: Found entity 14: cpu_0_nios2_oci_dbrk
    Info: Found entity 15: cpu_0_nios2_oci_itrace
    Info: Found entity 16: cpu_0_nios2_oci_td_mode
    Info: Found entity 17: cpu_0_nios2_oci_dtrace
    Info: Found entity 18: cpu_0_nios2_oci_compute_tm_count
    Info: Found entity 19: cpu_0_nios2_oci_fifowp_inc
    Info: Found entity 20: cpu_0_nios2_oci_fifocount_inc
    Info: Found entity 21: cpu_0_nios2_oci_fifo
    Info: Found entity 22: cpu_0_nios2_oci_pib
    Info: Found entity 23: cpu_0_traceram_lpm_dram_bdp_component_module
    Info: Found entity 24: cpu_0_nios2_oci_im
    Info: Found entity 25: cpu_0_nios2_performance_monitors
    Info: Found entity 26: cpu_0_nios2_oci
    Info: Found entity 27: cpu_0
Info: Elaborating entity "cpu_0" for hierarchy "cpu_0:the_cpu_0"
Warning: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_test_bench
Info: Elaborating entity "cpu_0_test_bench" for hierarchy "cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench"
Info: Elaborating entity "cpu_0_ic_data_module" for hierarchy "cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data"
Info: Elaborating entity "altsyncram" for hierarchy "cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "1024"
    Info: Parameter "numwords_b" = "1024"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "widthad_a" = "10"
    Info: Parameter "widthad_b" = "10"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3id1.tdf
    Info: Found entity 1: altsyncram_3id1
Info: Elaborating entity "altsyncram_3id1" for hierarchy "cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_3id1:auto_generated"
Info: Elaborating entity "cpu_0_ic_tag_module" for hierarchy "cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag"
Info: Elaborating entity "altsyncram" for hierarchy "cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_0_ic_tag_ram.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "128"
    Info: Parameter "numwords_b" = "128"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "23"
    Info: Parameter "width_b" = "23"
    Info: Parameter "widthad_a" = "7"
    Info: Parameter "widthad_b" = "7"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_q8g1.tdf
    Info: Found entity 1: altsyncram_q8g1
Info: Elaborating entity "altsyncram_q8g1" for hierarchy "cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_q8g1:auto_generated"
Info: Elaborating entity "cpu_0_bht_module" for hierarchy "cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht"
Info: Elaborating entity "altsyncram" for hierarchy "cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_0_bht_ram.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "256"
    Info: Parameter "numwords_b" = "256"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "2"
    Info: Parameter "width_b" = "2"
    Info: Parameter "widthad_a" = "8"
    Info: Parameter "widthad_b" = "8"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hsf1.tdf
    Info: Found entity 1: altsyncram_hsf1
Info: Elaborating entity "altsyncram_hsf1" for hierarchy "cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_hsf1:auto_generated"
Info: Elaborating entity "cpu_0_register_bank_a_module" for hierarchy "cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a"
Info: Elaborating entity "altsyncram" for hierarchy "cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_0_rf_ram_a.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "32"
    Info: Parameter "numwords_b" = "32"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "widthad_a" = "5"
    Info: Parameter "widthad_b" = "5"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_haf1.tdf
    Info: Found entity 1: altsyncram_haf1
Info: Elaborating entity "altsyncram_haf1" for hierarchy "cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_haf1:auto_generated"
Info: Elaborating entity "cpu_0_register_bank_b_module" for hierarchy "cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b"
Info: Elaborating entity "altsyncram" for hierarchy "cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_0_rf_ram_b.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "32"
    Info: Parameter "numwords_b" = "32"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "widthad_a" = "5"
    Info: Parameter "widthad_b" = "5"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_iaf1.tdf
    Info: Found entity 1: altsyncram_iaf1
Info: Elaborating entity "altsyncram_iaf1" for hierarchy "cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_iaf1:auto_generated"
Warning: Using design file cpu_0_mult_cell.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_mult_cell
Info: Elaborating entity "cpu_0_mult_cell" for hierarchy "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell"
Info: Elaborating entity "altmult_add" for hierarchy "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1" with the following parameter:
    Info: Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0"
    Info: Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0"
    Info: Parameter "addnsub_multiplier_register1" = "UNREGISTERED"
    Info: Parameter "dedicated_multiplier_circuitry" = "YES"
    Info: Parameter "input_register_a0" = "UNREGISTERED"
    Info: Parameter "input_register_b0" = "UNREGISTERED"
    Info: Parameter "input_source_a0" = "DATAA"
    Info: Parameter "input_source_b0" = "DATAB"
    Info: Parameter "intended_device_family" = "CYCLONEIII"
    Info: Parameter "lpm_type" = "altmult_add"
    Info: Parameter "multiplier1_direction" = "ADD"
    Info: Parameter "multiplier_aclr0" = "ACLR0"
    Info: Parameter "multiplier_register0" = "CLOCK0"
    Info: Parameter "number_of_multipliers" = "1"
    Info: Parameter "output_register" = "UNREGISTERED"
    Info: Parameter "port_addnsub1" = "PORT_UNUSED"
    Info: Parameter "port_signa" = "PORT_UNUSED"
    Info: Parameter "port_signb" = "PORT_UNUSED"
    Info: Parameter "representation_a" = "UNSIGNED"
    Info: Parameter "representation_b" = "UNSIGNED"
    Info: Parameter "signed_pipeline_aclr_a" = "ACLR0"
    Info: Parameter "signed_pipeline_aclr_b" = "ACLR0"
    Info: Parameter "signed_pipeline_register_a" = "CLOCK0"
    Info: Parameter "signed_pipeline_register_b" = "CLOCK0"
    Info: Parameter "signed_register_a" = "UNREGISTERED"
    Info: Parameter "signed_register_b" = "UNREGISTERED"
    Info: Parameter "width_a" = "16"
    Info: Parameter "width_b" = "16"
    Info: Parameter "width_result" = "32"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_dfr2.tdf
    Info: Found entity 1: mult_add_dfr2
Info: Elaborating entity "mult_add_dfr2" for hierarchy "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_br81.tdf
    Info: Found entity 1: ded_mult_br81
Info: Elaborating entity "ded_mult_br81" for hierarchy "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf
    Info: Found entity 1: dffpipe_93c
Info: Elaborating entity "dffpipe_93c" for hierarchy "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_dfr2:auto_generated|ded_mult_br81:ded_mult1|dffpipe_93c:pre_result"
Info: Elaborating entity "altmult_add" for hierarchy "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2" with the following parameter:
    Info: Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0"
    Info: Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0"
    Info: Parameter "addnsub_multiplier_register1" = "UNREGISTERED"
    Info: Parameter "dedicated_multiplier_circuitry" = "YES"
    Info: Parameter "input_register_a0" = "UNREGISTERED"
    Info: Parameter "input_register_b0" = "UNREGISTERED"
    Info: Parameter "input_source_a0" = "DATAA"
    Info: Parameter "input_source_b0" = "DATAB"
    Info: Parameter "intended_device_family" = "CYCLONEIII"
    Info: Parameter "lpm_type" = "altmult_add"
    Info: Parameter "multiplier1_direction" = "ADD"
    Info: Parameter "multiplier_aclr0" = "ACLR0"
    Info: Parameter "multiplier_register0" = "CLOCK0"
    Info: Parameter "number_of_multipliers" = "1"
    Info: Parameter "output_register" = "UNREGISTERED"
    Info: Parameter "port_addnsub1" = "PORT_UNUSED"
    Info: Parameter "port_signa" = "PORT_UNUSED"
    Info: Parameter "port_signb" = "PORT_UNUSED"
    Info: Parameter "representation_a" = "UNSIGNED"
    Info: Parameter "representation_b" = "UNSIGNED"
    Info: Parameter "signed_pipeline_aclr_a" = "ACLR0"
    Info: Parameter "signed_pipeline_aclr_b" = "ACLR0"
    Info: Parameter "signed_pipeline_register_a" = "CLOCK0"
    Info: Parameter "signed_pipeline_register_b" = "CLOCK0"
    Info: Parameter "signed_register_a" = "UNREGISTERED"
    Info: Parameter "signed_register_b" = "UNREGISTERED"
    Info: Parameter "width_a" = "16"
    Info: Parameter "width_b" = "16"
    Info: Parameter "width_result" = "16"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_ffr2.tdf
    Info: Found entity 1: mult_add_ffr2
Info: Elaborating entity "mult_add_ffr2" for hierarchy "cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ffr2:auto_generated"
Info: Elaborating entity "cpu_0_nios2_oci" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci"
Info: Elaborating entity "cpu_0_nios2_oci_debug" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug"
Info: Elaborating entity "cpu_0_nios2_ocimem" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem"
Info: Elaborating entity "cpu_0_ociram_lpm_dram_bdp_component_module" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_aclr_a" = "NONE"
    Info: Parameter "address_aclr_b" = "NONE"
    Info: Parameter "address_reg_b" = "CLOCK1"
    Info: Parameter "indata_aclr_a" = "NONE"
    Info: Parameter "indata_aclr_b" = "NONE"
    Info: Parameter "init_file" = "cpu_0_ociram_default_contents.mif"
    Info: Parameter "intended_device_family" = "CYCLONEIII"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "256"
    Info: Parameter "numwords_b" = "256"
    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    Info: Parameter "outdata_aclr_a" = "NONE"
    Info: Parameter "outdata_aclr_b" = "NONE"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "width_byteena_a" = "4"
    Info: Parameter "widthad_a" = "8"
    Info: Parameter "widthad_b" = "8"
    Info: Parameter "wrcontrol_aclr_a" = "NONE"
    Info: Parameter "wrcontrol_aclr_b" = "NONE"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l872.tdf
    Info: Found entity 1: altsyncram_l872
Info: Elaborating entity "altsyncram_l872" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_l872:auto_generated"
Info: Elaborating entity "cpu_0_nios2_avalon_reg" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg"
Info: Elaborating entity "cpu_0_nios2_oci_break" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break"
Info: Elaborating entity "cpu_0_nios2_oci_xbrk" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk"
Info: Elaborating entity "cpu_0_nios2_oci_dbrk" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk"
Info: Elaborating entity "cpu_0_nios2_oci_match_single" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single"
Info: Elaborating entity "cpu_0_nios2_oci_match_paired" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit0_match_paired"
Info: Elaborating entity "cpu_0_nios2_oci_itrace" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace"
Info: Elaborating entity "cpu_0_nios2_oci_dtrace" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace"
Info: Elaborating entity "cpu_0_nios2_oci_td_mode" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode"
Info: Elaborating entity "cpu_0_nios2_oci_fifo" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo"
Info: Elaborating entity "cpu_0_nios2_oci_compute_tm_count" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count"
Info: Elaborating entity "cpu_0_nios2_oci_fifowp_inc" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp"
Info: Elaborating entity "cpu_0_nios2_oci_fifocount_inc" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount"
Warning: Using design file cpu_0_oci_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_oci_test_bench
Info: Elaborating entity "cpu_0_oci_test_bench" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_oci_test_bench:the_cpu_0_oci_test_bench"
Warning: Entity "cpu_0_oci_test_bench" contains only dangling pins
Info: Elaborating entity "cpu_0_nios2_oci_pib" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib"
Info: Elaborating entity "cpu_0_nios2_oci_im" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im"
Info: Elaborating entity "cpu_0_traceram_lpm_dram_bdp_component_module" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_aclr_a" = "NONE"
    Info: Parameter "address_aclr_b" = "NONE"
    Info: Parameter "address_reg_b" = "CLOCK1"
    Info: Parameter "indata_aclr_a" = "NONE"
    Info: Parameter "indata_aclr_b" = "NONE"
    Info: Parameter "init_file" = "UNUSED"
    Info: Parameter "intended_device_family" = "CYCLONEIII"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "128"
    Info: Parameter "numwords_b" = "128"
    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    Info: Parameter "outdata_aclr_a" = "NONE"
    Info: Parameter "outdata_aclr_b" = "NONE"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "36"
    Info: Parameter "width_b" = "36"
    Info: Parameter "widthad_a" = "7"
    Info: Parameter "widthad_b" = "7"
    Info: Parameter "wrcontrol_aclr_a" = "NONE"
    Info: Parameter "wrcontrol_aclr_b" = "NONE"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_n802.tdf
    Info: Found entity 1: altsyncram_n802
Info: Elaborating entity "altsyncram_n802" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated"
Warning: Using design file cpu_0_jtag_debug_module_wrapper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_jtag_debug_module_wrapper
Info: Elaborating entity "cpu_0_jtag_debug_module_wrapper" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper"
Warning: Using design file cpu_0_jtag_debug_module_tck.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_jtag_debug_module_tck
Info: Elaborating entity "cpu_0_jtag_debug_module_tck" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck"
Warning: Using design file cpu_0_jtag_debug_module_sysclk.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_jtag_debug_module_sysclk
Info: Elaborating entity "cpu_0_jtag_debug_module_sysclk" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk"
Info: Elaborating entity "sld_virtual_jtag_basic" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy"
Info: Instantiated megafunction "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy" with the following parameter:
    Info: Parameter "sld_auto_instance_index" = "YES"
    Info: Parameter "sld_instance_index" = "0"
    Info: Parameter "sld_ir_width" = "2"
    Info: Parameter "sld_mfg_id" = "70"
    Info: Parameter "sld_sim_action" = ""
    Info: Parameter "sld_sim_n_scan" = "0"
    Info: Parameter "sld_sim_total_length" = "0"
    Info: Parameter "sld_type_id" = "34"
    Info: Parameter "sld_version" = "3"
Info: Elaborating entity "sld_virtual_jtag_impl" for hierarchy "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst"
Info: Elaborated megafunction instantiation "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_0_jtag_debug_module_phy"
Info: Elaborating entity "epcs_flash_controller_0_epcs_control_port_arbitrator" for hierarchy "epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port"
Warning: Using design file epcs_flash_controller_0.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: epcs_flash_controller_0_sub
    Info: Found entity 2: epcs_flash_controller_0
Info: Elaborating entity "epcs_flash_controller_0" for hierarchy "epcs_flash_controller_0:the_epcs_flash_controller_0"
Info: Elaborating entity "epcs_flash_controller_0_sub" for hierarchy "epcs_flash_controller_0:the_epcs_flash_controller_0|epcs_flash_controller_0_sub:the_epcs_flash_controller_0_sub"
Info: Elaborating entity "altsyncram" for hierarchy "epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom"
Info: Elaborated megafunction instantiation "epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom"
Info: Instantiated megafunction "epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom" with the following parameter:
    Info: Parameter "byte_size" = "8"
    Info: Parameter "init_file" = "epcs_flash_controller_0_boot_rom.hex"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "256"
    Info: Parameter "operation_mode" = "ROM"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info: Parameter "width_a" = "32"
    Info: Parameter "widthad_a" = "8"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tj41.tdf
    Info: Found entity 1: altsyncram_tj41
Info: Elaborating entity "altsyncram_tj41" for hierarchy "epcs_flash_controller_0:the_epcs_flash_controller_0|altsyncram:the_boot_copier_rom|altsyncram_tj41:auto_generated"
Info: Elaborating entity "jtag_uart_0_avalon_jtag_slave_arbitrator" for hierarchy "jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave"
Warning: Using design file jtag_uart_0.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project
    Info: Found entity 1: jtag_uart_0_log_module
    Info: Found entity 2: jtag_uart_0_sim_scfifo_w
    Info: Found entity 3: jtag_uart_0_scfifo_w
    Info: Found entity 4: jtag_uart_0_drom_module
    Info: Found entity 5: jtag_uart_0_sim_scfifo_r
    Info: Found entity 6: jtag_uart_0_scfifo_r
    Info: Found entity 7: jtag_uart_0
Info: Elaborating entity "jtag_uart_0" for hierarchy "jtag_uart_0:the_jtag_uart_0"
Info: Elaborating entity "jtag_uart_0_scfifo_w" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w"
Info: Elaborating entity "scfifo" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Elaborated megafunction instantiation "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Instantiated megafunction "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo" with the following parameter:
    Info: Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO"
    Info: Parameter "lpm_numwords" = "64"
    Info: Parameter "lpm_showahead" = "OFF"
    Info: Parameter "lpm_type" = "scfifo"
    Info: Parameter "lpm_width" = "8"
    Info: Parameter "lpm_widthu" = "6"
    Info: Parameter "overflow_checking" = "OFF"
    Info: Parameter "underflow_checking" = "OFF"
    Info: Parameter "use_eab" = "ON"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_aq21.tdf
    Info: Found entity 1: scfifo_aq21
Info: Elaborating entity "scfifo_aq21" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_h031.tdf
    Info: Found entity 1: a_dpfifo_h031
Info: Elaborating entity "a_dpfifo_h031" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf
    Info: Found entity 1: a_fefifo_7cf
Info: Elaborating entity "a_fefifo_7cf" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_4n7.tdf
    Info: Found entity 1: cntr_4n7
Info: Elaborating entity "cntr_4n7" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|a_fefifo_7cf:fifo_state|cntr_4n7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_ek21.tdf
    Info: Found entity 1: dpram_ek21
Info: Elaborating entity "dpram_ek21" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_i0m1.tdf
    Info: Found entity 1: altsyncram_i0m1
Info: Elaborating entity "altsyncram_i0m1" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|dpram_ek21:FIFOram|altsyncram_i0m1:altsyncram1"
Info: Found 1 design units, including 1 entities, in source file db/cntr_omb.tdf
    Info: Found entity 1: cntr_omb
Info: Elaborating entity "cntr_omb" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_aq21:auto_generated|a_dpfifo_h031:dpfifo|cntr_omb:rd_ptr_count"
Info: Elaborating entity "jtag_uart_0_scfifo_r" for hierarchy "jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r"
Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Elaborated megafunction instantiation "jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Instantiated megafunction "jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic" with the following parameter:
    Info: Parameter "INSTANCE_ID" = "0"
    Info: Parameter "LOG2_RXFIFO_DEPTH" = "6"
    Info: Parameter "LOG2_TXFIFO_DEPTH" = "6"
    Info: Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES"
Info: Elaborating entity "pio_0_s1_arbitrator" for hierarchy "pio_0_s1_arbitrator:the_pio_0_s1"
Warning: Using design file pio_0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: pio_0
Info: Elaborating entity "pio_0" for hierarchy "pio_0:the_pio_0"
Info: Elaborating entity "sdram_0_s1_arbitrator" for hierarchy "sdram_0_s1_arbitrator:the_sdram_0_s1"
Info: Elaborating entity "rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module" for hierarchy "sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1"
Info: Elaborating entity "rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module" for hierarchy "sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1"
Warning: Using design file sdram_0.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: sdram_0_input_efifo_module
    Info: Found entity 2: sdram_0
Info: Elaborating entity "sdram_0" for hierarchy "sdram_0:the_sdram_0"
Info: Elaborating entity "sdram_0_input_efifo_module" for hierarchy "sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module"
Info: Elaborating entity "sysid_control_slave_arbitrator" for hierarchy "sysid_control_slave_arbitrator:the_sysid_control_slave"
Warning: Using design file sysid.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sysid
Info: Elaborating entity "sysid" for hierarchy "sysid:the_sysid"
Info: Elaborating entity "NIOS_reset_altpll_0_c0_out_domain_synch_module" for hierarchy "NIOS_reset_altpll_0_c0_out_domain_synch_module:NIOS_reset_altpll_0_c0_out_domain_synch"
Info: Elaborating entity "NIOS_reset_clk_ex_domain_synch_module" for hierarchy "NIOS_reset_clk_ex_domain_synch_module:NIOS_reset_clk_ex_domain_synch"
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[0]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[1]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[2]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[3]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[4]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[5]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[6]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[7]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[8]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[9]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[10]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[11]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[12]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[13]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[14]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[15]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[16]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[17]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[18]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[19]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[20]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[21]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[22]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[23]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[24]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[25]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[26]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[27]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[28]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[29]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[30]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[31]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[32]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[33]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[34]"
        Warning (14320): Synthesized away node "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_n802:auto_generated|q_a[35]"
Warning: 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "phasedone_from_the_altpll_0" is stuck at GND
    Warning (13410): Pin "zs_cke_from_the_sdram_0" is stuck at VCC
Info: Timing-Driven Synthesis is running on partition "Top"
Info: 78 registers lost all their fanouts during netlist optimizations. The first 78 are displayed below.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[0]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[1]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[2]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[3]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[4]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[5]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[6]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[7]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[8]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[9]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[10]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[11]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[12]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[13]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[14]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[15]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[16]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[17]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[18]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[19]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[20]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[21]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[22]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[23]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[24]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[25]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[26]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[27]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[28]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[29]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[30]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[31]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[34]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[33]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[32]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace|itm[35]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[0]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[16]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[15]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[14]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[13]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[12]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[11]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[10]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[9]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[8]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[7]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[6]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[5]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[4]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[3]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[2]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_jtag_addr[1]" lost all its fanouts during netlist optimizations.
    Info: Register "epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_arb_share_counter" lost all its fanouts during netlist optimizations.
    Info: Register "epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|last_cycle_NIOS_clock_3_out_granted_slave_epcs_flash_controller_0_epcs_control_port" lost all its fanouts during netlist optimizations.
    Info: Register "epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|last_cycle_NIOS_clock_2_out_granted_slave_epcs_flash_controller_0_epcs_control_port" lost all its fanouts during netlist optimizations.
    Info: Register "epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations.
    Info: Register "epcs_flash_controller_0_epcs_control_port_arbitrator:the_epcs_flash_controller_0_epcs_control_port|epcs_flash_controller_0_epcs_control_port_reg_firsttransfer" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter[0]" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_reg_firsttransfer" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|m_next~9" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|m_next~10" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|m_next~13" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|m_next~14" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|m_next~16" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|i_next~4" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|i_next~5" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|i_next~6" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|i_state~14" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|i_state~15" lost all its fanouts during netlist optimizations.
    Info: Register "sdram_0:the_sdram_0|i_state~16" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~3" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~4" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize~5" lost all its fanouts during netlist optimizations.
    Info: Register "cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|DRsize.101" lost all its fanouts during netlist optimizations.
Warning: Ignored assignments for entity "sdram_test" -- entity does not exist in design
    Warning: Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity sdram_test -section_id Top was ignored
    Warning: Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity sdram_test -section_id Top was ignored
Info: Generated suppressed messages file E:/Program/EP3C16/nios/sdram_test/sdram_test.map.smsg
Info: Generating hard_block partition "hard_block:auto_generated_inst"
    Info: Adding node "altpll_0:the_altpll_0|altpll_0_altpll_lpa2:sd1|pll7"
Info: Implemented 5088 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 38 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 4821 logic cells
    Info: Implemented 201 RAM segments
    Info: Implemented 1 PLLs
    Info: Implemented 4 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 74 warnings
    Info: Peak virtual memory: 337 megabytes
    Info: Processing ended: Thu May 03 11:15:01 2012
    Info: Elapsed time: 00:00:27
    Info: Total CPU time (on all processors): 00:00:27


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/Program/EP3C16/nios/sdram_test/sdram_test.map.smsg.


