Analysis & Synthesis report for lcd
Wed Aug 12 22:39:31 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |lcd|current
  8. State Machine - |lcd|next
  9. General Register Statistics
 10. Parameter Settings for User Entity Instance: Top-level Entity: |lcd
 11. Analysis & Synthesis Messages
 12. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Wed Aug 12 22:39:31 2009    ;
; Quartus II Version                 ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name                      ; lcd                                      ;
; Top-level Entity Name              ; lcd                                      ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 45                                       ;
; Total registers                    ; 45                                       ;
; Total pins                         ; 12                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0                                        ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C8Q208C8        ;                    ;
; Top-level entity name                                              ; lcd                ; lcd                ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                         ;
+----------------------------------+-----------------+------------------------+----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path     ;
+----------------------------------+-----------------+------------------------+----------------------------------+
; lcd.v                            ; yes             ; User Verilog HDL File  ; F:/EP2C5Q208/350/LCD1602_B/lcd.v ;
+----------------------------------+-----------------+------------------------+----------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 45    ;
; Total combinational functions               ; 42    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 16    ;
;     -- 3 input functions                    ; 4     ;
;     -- <=2 input functions                  ; 22    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 27    ;
;     -- arithmetic mode                      ; 15    ;
; Total registers                             ; 45    ;
; I/O pins                                    ; 12    ;
; Maximum fan-out node                        ; clkr  ;
; Maximum fan-out                             ; 30    ;
; Total fan-out                               ; 217   ;
; Average fan-out                             ; 2.19  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |lcd                       ; 42 (42)           ; 45 (45)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 12   ; 0            ; |lcd                ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |lcd|current                                                                                                                                                                                                                                                  ;
+---------------+-------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+---------------+--------------+---------------+
; Name          ; current.nul ; current.set1 ; current.set2 ; current.set3 ; current.dat0 ; current.dat1 ; current.dat2 ; current.dat3 ; current.dat4 ; current.dat5 ; current.dat6 ; current.dat7 ; current.dat8 ; current.dat9 ; current.dat10 ; current.set0 ; current.dat11 ;
+---------------+-------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+---------------+--------------+---------------+
; current.set0  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 0            ; 0             ;
; current.dat11 ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 1             ;
; current.dat10 ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 1             ; 1            ; 0             ;
; current.dat9  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 1            ; 0             ; 1            ; 0             ;
; current.dat8  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0             ; 1            ; 0             ;
; current.dat7  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.dat6  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.dat5  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.dat4  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.dat3  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.dat2  ; 0           ; 0            ; 0            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.dat1  ; 0           ; 0            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.dat0  ; 0           ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.set3  ; 0           ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.set2  ; 0           ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.set1  ; 0           ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
; current.nul   ; 1           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0             ; 1            ; 0             ;
+---------------+-------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+---------------+--------------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |lcd|next                                                                                                                                                                                               ;
+------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+------------+----------+-----------+------------+
; Name       ; next.set1 ; next.set2 ; next.set3 ; next.dat0 ; next.dat1 ; next.dat2 ; next.dat3 ; next.dat4 ; next.dat5 ; next.dat6 ; next.dat7 ; next.dat8 ; next.dat9 ; next.dat10 ; next.nul ; next.set0 ; next.dat11 ;
+------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+------------+----------+-----------+------------+
; next.set0  ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 0         ; 0          ;
; next.nul   ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 1        ; 1         ; 0          ;
; next.dat11 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 1          ;
; next.dat10 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1          ; 0        ; 1         ; 0          ;
; next.dat9  ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0          ; 0        ; 1         ; 0          ;
; next.dat8  ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.dat7  ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.dat6  ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.dat5  ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.dat4  ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.dat3  ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.dat2  ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.dat1  ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.dat0  ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.set3  ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.set2  ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
; next.set1  ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0        ; 1         ; 0          ;
+------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+------------+----------+-----------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 45    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |lcd ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; set0           ; 0000  ; Binary                                     ;
; set1           ; 0001  ; Binary                                     ;
; set2           ; 0010  ; Binary                                     ;
; set3           ; 0011  ; Binary                                     ;
; dat0           ; 0100  ; Binary                                     ;
; dat1           ; 0101  ; Binary                                     ;
; dat2           ; 0110  ; Binary                                     ;
; dat3           ; 0111  ; Binary                                     ;
; dat4           ; 1000  ; Binary                                     ;
; dat5           ; 1001  ; Binary                                     ;
; dat6           ; 1010  ; Binary                                     ;
; dat7           ; 1011  ; Binary                                     ;
; dat8           ; 1100  ; Binary                                     ;
; dat9           ; 1101  ; Binary                                     ;
; dat10          ; 1110  ; Binary                                     ;
; dat11          ; 10000 ; Binary                                     ;
; nul            ; 1111  ; Binary                                     ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Aug 12 22:39:29 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd
Info: Found 1 design units, including 1 entities, in source file lcd.v
    Info: Found entity 1: lcd
Info: Elaborating entity "lcd" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at lcd.v(34): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at lcd.v(62): truncated value with size 32 to match size of target (2)
Warning: Reduced register "dat[7]~reg0" with stuck data_in port to stuck value GND
Info: State machine "|lcd|current" contains 17 states
Info: State machine "|lcd|next" contains 17 states
Info: Selected Auto state machine encoding method for state machine "|lcd|current"
Info: Encoding result for state machine "|lcd|current"
    Info: Completed encoding using 17 state bits
        Info: Encoded state bit "current.nul"
        Info: Encoded state bit "current.set1"
        Info: Encoded state bit "current.set2"
        Info: Encoded state bit "current.set3"
        Info: Encoded state bit "current.dat0"
        Info: Encoded state bit "current.dat1"
        Info: Encoded state bit "current.dat2"
        Info: Encoded state bit "current.dat3"
        Info: Encoded state bit "current.dat4"
        Info: Encoded state bit "current.dat5"
        Info: Encoded state bit "current.dat6"
        Info: Encoded state bit "current.dat7"
        Info: Encoded state bit "current.dat8"
        Info: Encoded state bit "current.dat9"
        Info: Encoded state bit "current.dat10"
        Info: Encoded state bit "current.set0"
        Info: Encoded state bit "current.dat11"
    Info: State "|lcd|current.set0" uses code string "00000000000000000"
    Info: State "|lcd|current.dat11" uses code string "00000000000000011"
    Info: State "|lcd|current.dat10" uses code string "00000000000000110"
    Info: State "|lcd|current.dat9" uses code string "00000000000001010"
    Info: State "|lcd|current.dat8" uses code string "00000000000010010"
    Info: State "|lcd|current.dat7" uses code string "00000000000100010"
    Info: State "|lcd|current.dat6" uses code string "00000000001000010"
    Info: State "|lcd|current.dat5" uses code string "00000000010000010"
    Info: State "|lcd|current.dat4" uses code string "00000000100000010"
    Info: State "|lcd|current.dat3" uses code string "00000001000000010"
    Info: State "|lcd|current.dat2" uses code string "00000010000000010"
    Info: State "|lcd|current.dat1" uses code string "00000100000000010"
    Info: State "|lcd|current.dat0" uses code string "00001000000000010"
    Info: State "|lcd|current.set3" uses code string "00010000000000010"
    Info: State "|lcd|current.set2" uses code string "00100000000000010"
    Info: State "|lcd|current.set1" uses code string "01000000000000010"
    Info: State "|lcd|current.nul" uses code string "10000000000000010"
Info: Selected Auto state machine encoding method for state machine "|lcd|next"
Info: Encoding result for state machine "|lcd|next"
    Info: Completed encoding using 17 state bits
        Info: Encoded state bit "next.set1"
        Info: Encoded state bit "next.set2"
        Info: Encoded state bit "next.set3"
        Info: Encoded state bit "next.dat0"
        Info: Encoded state bit "next.dat1"
        Info: Encoded state bit "next.dat2"
        Info: Encoded state bit "next.dat3"
        Info: Encoded state bit "next.dat4"
        Info: Encoded state bit "next.dat5"
        Info: Encoded state bit "next.dat6"
        Info: Encoded state bit "next.dat7"
        Info: Encoded state bit "next.dat8"
        Info: Encoded state bit "next.dat9"
        Info: Encoded state bit "next.dat10"
        Info: Encoded state bit "next.nul"
        Info: Encoded state bit "next.set0"
        Info: Encoded state bit "next.dat11"
    Info: State "|lcd|next.set0" uses code string "00000000000000000"
    Info: State "|lcd|next.nul" uses code string "00000000000000110"
    Info: State "|lcd|next.dat11" uses code string "00000000000000011"
    Info: State "|lcd|next.dat10" uses code string "00000000000001010"
    Info: State "|lcd|next.dat9" uses code string "00000000000010010"
    Info: State "|lcd|next.dat8" uses code string "00000000000100010"
    Info: State "|lcd|next.dat7" uses code string "00000000001000010"
    Info: State "|lcd|next.dat6" uses code string "00000000010000010"
    Info: State "|lcd|next.dat5" uses code string "00000000100000010"
    Info: State "|lcd|next.dat4" uses code string "00000001000000010"
    Info: State "|lcd|next.dat3" uses code string "00000010000000010"
    Info: State "|lcd|next.dat2" uses code string "00000100000000010"
    Info: State "|lcd|next.dat1" uses code string "00001000000000010"
    Info: State "|lcd|next.dat0" uses code string "00010000000000010"
    Info: State "|lcd|next.set3" uses code string "00100000000000010"
    Info: State "|lcd|next.set2" uses code string "01000000000000010"
    Info: State "|lcd|next.set1" uses code string "10000000000000010"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "rw" stuck at GND
    Warning: Pin "dat[7]" stuck at GND
Info: Implemented 84 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 11 output pins
    Info: Implemented 72 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Wed Aug 12 22:39:31 2009
    Info: Elapsed time: 00:00:03


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/EP2C5Q208/350/LCD1602_B/lcd.map.smsg.


