TimeQuest Timing Analyzer report for pwm_test
Tue Feb 14 18:30:28 2012
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Slow 1200mV 85C Model Setup Summary
  7. Slow 1200mV 85C Model Hold Summary
  8. Slow 1200mV 85C Model Recovery Summary
  9. Slow 1200mV 85C Model Removal Summary
 10. Slow 1200mV 85C Model Minimum Pulse Width Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width: 'clk'
 12. Clock to Output Times
 13. Minimum Clock to Output Times
 14. Slow 1200mV 85C Model Metastability Report
 15. Slow 1200mV 0C Model Fmax Summary
 16. Slow 1200mV 0C Model Setup Summary
 17. Slow 1200mV 0C Model Hold Summary
 18. Slow 1200mV 0C Model Recovery Summary
 19. Slow 1200mV 0C Model Removal Summary
 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
 21. Slow 1200mV 0C Model Minimum Pulse Width: 'clk'
 22. Clock to Output Times
 23. Minimum Clock to Output Times
 24. Slow 1200mV 0C Model Metastability Report
 25. Fast 1200mV 0C Model Setup Summary
 26. Fast 1200mV 0C Model Hold Summary
 27. Fast 1200mV 0C Model Recovery Summary
 28. Fast 1200mV 0C Model Removal Summary
 29. Fast 1200mV 0C Model Minimum Pulse Width Summary
 30. Fast 1200mV 0C Model Minimum Pulse Width: 'clk'
 31. Clock to Output Times
 32. Minimum Clock to Output Times
 33. Fast 1200mV 0C Model Metastability Report
 34. Multicorner Timing Analysis Summary
 35. Clock to Output Times
 36. Minimum Clock to Output Times
 37. Board Trace Model Assignments
 38. Input Transition Times
 39. Slow Corner Signal Integrity Metrics
 40. Fast Corner Signal Integrity Metrics
 41. Clock Transfers
 42. Report TCCS
 43. Report RSKM
 44. Unconstrained Paths
 45. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                      ;
+--------------------+---------------------------------------------------+
; Quartus II Version ; Version 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name      ; pwm_test                                          ;
; Device Family      ; Cyclone III                                       ;
; Device Name        ; EP3C40Q240C8                                      ;
; Timing Models      ; Final                                             ;
; Delay Model        ; Combined                                          ;
; Rise/Fall Delays   ; Enabled                                           ;
+--------------------+---------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ; < 0.1%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                              ;
+--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------+------------------------------------------------------+
; Clock Name                                       ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source                                             ; Targets                                              ;
+--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------+------------------------------------------------------+
; clk                                              ; Base      ; 20.000 ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                    ; { clk }                                              ;
; pll0|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 30.303 ; 33.0 MHz  ; 0.000 ; 15.151 ; 50.00      ; 50        ; 33          ;       ;        ;           ;            ; false    ; clk    ; pll0|altpll_component|auto_generated|pll1|inclk[0] ; { pll0|altpll_component|auto_generated|pll1|clk[0] } ;
; pll0|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 40.000 ; 25.0 MHz  ; 0.000 ; 20.000 ; 50.00      ; 2         ; 1           ;       ;        ;           ;            ; false    ; clk    ; pll0|altpll_component|auto_generated|pll1|inclk[0] ; { pll0|altpll_component|auto_generated|pll1|clk[1] } ;
+--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------+------------------------------------------------------+


--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.


---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.


--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+---------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-------+-------+-----------------------------------+
; Clock ; Slack ; End Point TNS                     ;
+-------+-------+-----------------------------------+
; clk   ; 9.866 ; 0.000                             ;
+-------+-------+-----------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk'                                                                                            ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+
; 9.866  ; 9.866        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.866  ; 9.866        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 9.866  ; 9.866        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.891  ; 9.891        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                                                ;
; 9.921  ; 9.921        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                                                ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                                                ;
; 10.078 ; 10.078       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.109 ; 10.109       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o                                                ;
; 10.132 ; 10.132       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0]           ;
; 10.132 ; 10.132       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 10.132 ; 10.132       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                                        ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; clk0      ; clk        ; 2.880 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk0      ; clk        ;       ; 2.688 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk1      ; clk        ; 2.868 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; clk1      ; clk        ;       ; 2.678 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                          ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; clk0      ; clk        ; 2.398 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk0      ; clk        ;       ; 2.209 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk1      ; clk        ; 2.386 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; clk1      ; clk        ;       ; 2.200 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.


--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.


-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+-------+-------+----------------------------------+
; Clock ; Slack ; End Point TNS                    ;
+-------+-------+----------------------------------+
; clk   ; 9.843 ; 0.000                            ;
+-------+-------+----------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk'                                                                                             ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+
; 9.843  ; 9.843        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.843  ; 9.843        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 9.843  ; 9.843        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.891  ; 9.891        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                                                ;
; 9.913  ; 9.913        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                                                ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                                                ;
; 10.086 ; 10.086       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.109 ; 10.109       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o                                                ;
; 10.153 ; 10.153       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0]           ;
; 10.153 ; 10.153       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 10.153 ; 10.153       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                                        ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; clk0      ; clk        ; 3.031 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk0      ; clk        ;       ; 2.811 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk1      ; clk        ; 3.020 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; clk1      ; clk        ;       ; 2.802 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                          ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; clk0      ; clk        ; 2.611 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk0      ; clk        ;       ; 2.396 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk1      ; clk        ; 2.601 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; clk1      ; clk        ;       ; 2.387 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.


-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+-------+-------+----------------------------------+
; Clock ; Slack ; End Point TNS                    ;
+-------+-------+----------------------------------+
; clk   ; 9.405 ; 0.000                            ;
+-------+-------+----------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk'                                                                                             ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+
; 9.405  ; 9.405        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.405  ; 9.405        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 9.405  ; 9.405        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.441  ; 9.441        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                                                ;
; 9.447  ; 9.447        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                                                ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                                                ;
; 10.552 ; 10.552       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.559 ; 10.559       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o                                                ;
; 10.593 ; 10.593       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0]           ;
; 10.593 ; 10.593       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 10.593 ; 10.593       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                                        ;
+--------+--------------+----------------+------------------+-------+------------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; clk0      ; clk        ; 1.390 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk0      ; clk        ;       ; 1.398 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk1      ; clk        ; 1.390 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; clk1      ; clk        ;       ; 1.396 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                          ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; clk0      ; clk        ; 1.158 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk0      ; clk        ;       ; 1.164 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk1      ; clk        ; 1.158 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; clk1      ; clk        ;       ; 1.162 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                        ;
+------------------+-------+------+----------+---------+---------------------+
; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; 9.405               ;
;  clk             ; N/A   ; N/A  ; N/A      ; N/A     ; 9.405               ;
; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
;  clk             ; N/A   ; N/A  ; N/A      ; N/A     ; 0.000               ;
+------------------+-------+------+----------+---------+---------------------+


+--------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; clk0      ; clk        ; 3.031 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk0      ; clk        ;       ; 2.811 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk1      ; clk        ; 3.020 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; clk1      ; clk        ;       ; 2.802 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                          ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; clk0      ; clk        ; 1.158 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk0      ; clk        ;       ; 1.164 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[0] ;
; clk1      ; clk        ; 1.158 ;       ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; clk1      ; clk        ;       ; 1.162 ; Fall       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; clk0          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; clk1          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_nCEO~ ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; clk                     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; clk0          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; clk1          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.58e-07 V                   ; 3.13 V              ; -0.0396 V           ; 0.18 V                               ; 0.073 V                              ; 4.81e-10 s                  ; 4.67e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.58e-07 V                  ; 3.13 V             ; -0.0396 V          ; 0.18 V                              ; 0.073 V                             ; 4.81e-10 s                 ; 4.67e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; clk0          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; clk1          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.0651 V           ; 0.234 V                              ; 0.087 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.0651 V          ; 0.234 V                             ; 0.087 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


-------------------
; Clock Transfers ;
-------------------
Nothing to report.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 0     ; 0    ;
; Unconstrained Input Port Paths  ; 0     ; 0    ;
; Unconstrained Output Ports      ; 2     ; 2    ;
; Unconstrained Output Port Paths ; 2     ; 2    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
    Info: Processing started: Tue Feb 14 18:30:22 2012
Info: Command: quartus_sta pwm_test -c pwm_test
Info: qsta_default_script.tcl version: #1
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Critical Warning: Synopsys Design Constraints File file not found: 'pwm_test.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info: Deriving PLL Clocks
    Info: create_clock -period 20.000 -waveform {0.000 10.000} -name clk clk
    Info: create_generated_clock -source {pll0|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 50 -multiply_by 33 -duty_cycle 50.00 -name {pll0|altpll_component|auto_generated|pll1|clk[0]} {pll0|altpll_component|auto_generated|pll1|clk[0]}
    Info: create_generated_clock -source {pll0|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -duty_cycle 50.00 -name {pll0|altpll_component|auto_generated|pll1|clk[1]} {pll0|altpll_component|auto_generated|pll1|clk[1]}
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Info: No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Analyzing Slow 1200mV 85C Model
Info: No fmax paths to report
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 9.866
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     9.866         0.000 clk 
Info: Analyzing Slow 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: No fmax paths to report
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 9.843
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     9.843         0.000 clk 
Info: Analyzing Fast 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 9.405
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     9.405         0.000 clk 
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 282 megabytes
    Info: Processing ended: Tue Feb 14 18:30:28 2012
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:04


