TimeQuest Timing Analyzer report for vga_red
Fri May 04 16:52:18 2012
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Slow 1200mV 85C Model Setup Summary
  7. Slow 1200mV 85C Model Hold Summary
  8. Slow 1200mV 85C Model Recovery Summary
  9. Slow 1200mV 85C Model Removal Summary
 10. Slow 1200mV 85C Model Minimum Pulse Width Summary
 11. Slow 1200mV 85C Model Setup: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 12. Slow 1200mV 85C Model Hold: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 13. Slow 1200mV 85C Model Minimum Pulse Width: 'clk'
 14. Slow 1200mV 85C Model Minimum Pulse Width: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 15. Clock to Output Times
 16. Minimum Clock to Output Times
 17. Slow 1200mV 85C Model Metastability Report
 18. Slow 1200mV 0C Model Fmax Summary
 19. Slow 1200mV 0C Model Setup Summary
 20. Slow 1200mV 0C Model Hold Summary
 21. Slow 1200mV 0C Model Recovery Summary
 22. Slow 1200mV 0C Model Removal Summary
 23. Slow 1200mV 0C Model Minimum Pulse Width Summary
 24. Slow 1200mV 0C Model Setup: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 25. Slow 1200mV 0C Model Hold: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 0C Model Minimum Pulse Width: 'clk'
 27. Slow 1200mV 0C Model Minimum Pulse Width: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 28. Clock to Output Times
 29. Minimum Clock to Output Times
 30. Slow 1200mV 0C Model Metastability Report
 31. Fast 1200mV 0C Model Setup Summary
 32. Fast 1200mV 0C Model Hold Summary
 33. Fast 1200mV 0C Model Recovery Summary
 34. Fast 1200mV 0C Model Removal Summary
 35. Fast 1200mV 0C Model Minimum Pulse Width Summary
 36. Fast 1200mV 0C Model Setup: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 37. Fast 1200mV 0C Model Hold: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 38. Fast 1200mV 0C Model Minimum Pulse Width: 'clk'
 39. Fast 1200mV 0C Model Minimum Pulse Width: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
 40. Clock to Output Times
 41. Minimum Clock to Output Times
 42. Fast 1200mV 0C Model Metastability Report
 43. Multicorner Timing Analysis Summary
 44. Clock to Output Times
 45. Minimum Clock to Output Times
 46. Board Trace Model Assignments
 47. Input Transition Times
 48. Slow Corner Signal Integrity Metrics
 49. Fast Corner Signal Integrity Metrics
 50. Setup Transfers
 51. Hold Transfers
 52. Report TCCS
 53. Report RSKM
 54. Unconstrained Paths
 55. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                      ;
+--------------------+---------------------------------------------------+
; Quartus II Version ; Version 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name      ; vga_red                                           ;
; Device Family      ; Cyclone III                                       ;
; Device Name        ; EP3C16Q240C8                                      ;
; Timing Models      ; Final                                             ;
; Delay Model        ; Combined                                          ;
; Rise/Fall Delays   ; Enabled                                           ;
+--------------------+---------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ; < 0.1%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                      ;
+----------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+------------------------------------------------------------+--------------------------------------------------------------+
; Clock Name                                               ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source                                                     ; Targets                                                      ;
+----------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+------------------------------------------------------------+--------------------------------------------------------------+
; clk                                                      ; Base      ; 20.000 ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                            ; { clk }                                                      ;
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 40.000 ; 25.0 MHz  ; 0.000 ; 20.000 ; 50.00      ; 2         ; 1           ;       ;        ;           ;            ; false    ; clk    ; vga_pll_inst|altpll_component|auto_generated|pll1|inclk[0] ; { vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] } ;
+----------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+------------------------------------------------------------+--------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                            ;
+-----------+-----------------+----------------------------------------------------------+------+
; Fmax      ; Restricted Fmax ; Clock Name                                               ; Note ;
+-----------+-----------------+----------------------------------------------------------+------+
; 208.2 MHz ; 208.2 MHz       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;      ;
+-----------+-----------------+----------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-----------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                               ;
+----------------------------------------------------------+--------+---------------+
; Clock                                                    ; Slack  ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 35.197 ; 0.000         ;
+----------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                               ;
+----------------------------------------------------------+-------+---------------+
; Clock                                                    ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.455 ; 0.000         ;
+----------------------------------------------------------+-------+---------------+


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+-----------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                 ;
+----------------------------------------------------------+--------+---------------+
; Clock                                                    ; Slack  ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; clk                                                      ; 9.860  ; 0.000         ;
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 19.699 ; 0.000         ;
+----------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                      ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node  ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 35.197 ; h_cnt[7]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.726      ;
; 35.255 ; h_cnt[3]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.668      ;
; 35.343 ; h_cnt[7]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.580      ;
; 35.351 ; h_cnt[7]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.572      ;
; 35.401 ; h_cnt[3]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.522      ;
; 35.407 ; h_cnt[3]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.516      ;
; 35.427 ; h_cnt[5]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.496      ;
; 35.433 ; h_cnt[8]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.490      ;
; 35.489 ; h_cnt[7]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.434      ;
; 35.497 ; h_cnt[7]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.426      ;
; 35.519 ; h_cnt[2]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.404      ;
; 35.547 ; h_cnt[3]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.376      ;
; 35.553 ; h_cnt[3]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.370      ;
; 35.573 ; h_cnt[5]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.350      ;
; 35.579 ; h_cnt[8]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.344      ;
; 35.603 ; h_cnt[5]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.320      ;
; 35.609 ; h_cnt[8]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.314      ;
; 35.618 ; h_cnt[9]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.305      ;
; 35.635 ; h_cnt[7]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.288      ;
; 35.643 ; h_cnt[7]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.280      ;
; 35.665 ; h_cnt[4]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.258      ;
; 35.665 ; h_cnt[2]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.258      ;
; 35.693 ; h_cnt[3]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.230      ;
; 35.695 ; h_cnt[2]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.228      ;
; 35.699 ; h_cnt[3]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.224      ;
; 35.719 ; h_cnt[5]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.204      ;
; 35.725 ; h_cnt[8]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.198      ;
; 35.749 ; h_cnt[5]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.174      ;
; 35.755 ; h_cnt[8]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.168      ;
; 35.764 ; h_cnt[9]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.159      ;
; 35.773 ; h_cnt[6]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.150      ;
; 35.781 ; h_cnt[7]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.142      ;
; 35.789 ; h_cnt[7]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.134      ;
; 35.794 ; h_cnt[9]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.129      ;
; 35.811 ; h_cnt[4]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.112      ;
; 35.811 ; h_cnt[2]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.112      ;
; 35.839 ; h_cnt[3]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.084      ;
; 35.841 ; h_cnt[4]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.082      ;
; 35.841 ; h_cnt[2]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.082      ;
; 35.845 ; h_cnt[3]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.078      ;
; 35.865 ; h_cnt[5]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.058      ;
; 35.871 ; h_cnt[8]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.052      ;
; 35.895 ; h_cnt[5]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.028      ;
; 35.901 ; h_cnt[8]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.022      ;
; 35.910 ; h_cnt[9]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.013      ;
; 35.919 ; h_cnt[6]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 4.004      ;
; 35.940 ; h_cnt[9]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.983      ;
; 35.949 ; h_cnt[6]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.974      ;
; 35.957 ; h_cnt[4]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.966      ;
; 35.957 ; h_cnt[2]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.966      ;
; 35.987 ; h_cnt[4]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.936      ;
; 35.987 ; h_cnt[2]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.936      ;
; 36.011 ; h_cnt[5]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.912      ;
; 36.017 ; h_cnt[8]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.906      ;
; 36.041 ; h_cnt[5]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.882      ;
; 36.047 ; h_cnt[8]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.876      ;
; 36.056 ; h_cnt[9]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.867      ;
; 36.060 ; h_cnt[1]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.863      ;
; 36.065 ; h_cnt[6]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.858      ;
; 36.086 ; h_cnt[9]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.837      ;
; 36.095 ; h_cnt[6]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.828      ;
; 36.103 ; h_cnt[4]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.820      ;
; 36.103 ; h_cnt[2]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.820      ;
; 36.111 ; h_cnt[7]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.811      ;
; 36.111 ; h_cnt[7]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.811      ;
; 36.133 ; h_cnt[4]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.790      ;
; 36.133 ; h_cnt[2]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.790      ;
; 36.169 ; h_cnt[3]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.753      ;
; 36.169 ; h_cnt[3]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.753      ;
; 36.202 ; h_cnt[9]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.721      ;
; 36.206 ; h_cnt[1]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.717      ;
; 36.211 ; h_cnt[6]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.712      ;
; 36.232 ; h_cnt[9]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.691      ;
; 36.236 ; h_cnt[1]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.687      ;
; 36.241 ; h_cnt[6]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.682      ;
; 36.249 ; h_cnt[4]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.674      ;
; 36.279 ; h_cnt[4]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.644      ;
; 36.341 ; h_cnt[5]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.581      ;
; 36.341 ; h_cnt[5]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.581      ;
; 36.347 ; h_cnt[8]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.575      ;
; 36.347 ; h_cnt[8]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.575      ;
; 36.352 ; h_cnt[1]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.571      ;
; 36.353 ; h_cnt[0]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.570      ;
; 36.357 ; h_cnt[6]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.566      ;
; 36.373 ; h_cnt[7]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.550      ;
; 36.382 ; h_cnt[1]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.541      ;
; 36.387 ; h_cnt[6]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.536      ;
; 36.424 ; h_cnt[7]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.498      ;
; 36.428 ; h_cnt[7]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.494      ;
; 36.429 ; h_cnt[3]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.494      ;
; 36.430 ; v_cnt[8]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.492      ;
; 36.433 ; h_cnt[2]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.489      ;
; 36.433 ; h_cnt[2]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.489      ;
; 36.482 ; h_cnt[3]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.440      ;
; 36.486 ; h_cnt[3]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.436      ;
; 36.498 ; h_cnt[1]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.425      ;
; 36.499 ; h_cnt[0]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.424      ;
; 36.528 ; h_cnt[1]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.395      ;
; 36.529 ; h_cnt[0]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.078     ; 3.394      ;
; 36.532 ; h_cnt[9]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.079     ; 3.390      ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                      ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node  ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.455 ; hys_r     ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.762 ; h_cnt[7]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.053      ;
; 0.765 ; h_cnt[3]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.766 ; v_cnt[9]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.056      ;
; 0.766 ; h_cnt[6]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.057      ;
; 0.767 ; v_cnt[3]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.057      ;
; 0.772 ; v_cnt[1]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.062      ;
; 0.772 ; v_cnt[7]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.062      ;
; 0.775 ; v_cnt[8]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.065      ;
; 0.775 ; h_cnt[4]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.066      ;
; 0.777 ; v_cnt[6]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.067      ;
; 0.777 ; v_cnt[4]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.067      ;
; 0.785 ; v_cnt[0]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.075      ;
; 0.787 ; h_cnt[1]  ; h_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.078      ;
; 0.951 ; h_cnt[2]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.242      ;
; 0.956 ; v_cnt[9]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.246      ;
; 0.957 ; v_cnt[5]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.247      ;
; 0.982 ; v_cnt[0]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.272      ;
; 0.986 ; h_cnt[6]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.277      ;
; 1.025 ; h_cnt[5]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.316      ;
; 1.102 ; h_cnt[0]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.393      ;
; 1.119 ; h_cnt[3]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.121 ; v_cnt[3]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.411      ;
; 1.127 ; v_cnt[1]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.417      ;
; 1.127 ; v_cnt[7]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.417      ;
; 1.127 ; h_cnt[6]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.418      ;
; 1.128 ; v_cnt[0]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.418      ;
; 1.129 ; h_cnt[5]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.420      ;
; 1.129 ; h_cnt[0]  ; h_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.420      ;
; 1.130 ; v_cnt[1]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.420      ;
; 1.136 ; v_cnt[8]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.426      ;
; 1.137 ; v_cnt[0]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.427      ;
; 1.138 ; v_cnt[6]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.428      ;
; 1.138 ; h_cnt[0]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.429      ;
; 1.138 ; v_cnt[4]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.428      ;
; 1.142 ; h_cnt[1]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.433      ;
; 1.145 ; h_cnt[4]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.436      ;
; 1.147 ; v_cnt[4]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.437      ;
; 1.147 ; v_cnt[6]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.437      ;
; 1.168 ; vys_r     ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.459      ;
; 1.175 ; h_cnt[5]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.466      ;
; 1.191 ; h_cnt[8]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.482      ;
; 1.226 ; v_cnt[2]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.516      ;
; 1.252 ; v_cnt[3]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.542      ;
; 1.258 ; v_cnt[1]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.548      ;
; 1.258 ; v_cnt[7]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.548      ;
; 1.259 ; h_cnt[3]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.550      ;
; 1.260 ; h_cnt[5]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.551      ;
; 1.261 ; v_cnt[3]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.551      ;
; 1.263 ; h_cnt[1]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.554      ;
; 1.267 ; v_cnt[1]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.557      ;
; 1.268 ; v_cnt[0]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.558      ;
; 1.269 ; h_cnt[0]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.560      ;
; 1.273 ; h_cnt[1]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.564      ;
; 1.276 ; h_cnt[4]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.567      ;
; 1.277 ; v_cnt[0]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.567      ;
; 1.278 ; h_cnt[0]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.569      ;
; 1.278 ; v_cnt[4]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.568      ;
; 1.278 ; v_cnt[6]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.568      ;
; 1.282 ; h_cnt[1]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.573      ;
; 1.287 ; v_cnt[4]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.577      ;
; 1.291 ; h_cnt[2]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.582      ;
; 1.311 ; h_cnt[9]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.602      ;
; 1.312 ; v_cnt[5]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.602      ;
; 1.321 ; h_cnt[2]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.612      ;
; 1.349 ; h_cnt[0]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.640      ;
; 1.390 ; h_cnt[3]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.681      ;
; 1.392 ; v_cnt[3]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.682      ;
; 1.398 ; v_cnt[1]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.688      ;
; 1.401 ; v_cnt[3]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.691      ;
; 1.402 ; v_cnt[5]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.692      ;
; 1.407 ; v_cnt[1]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.697      ;
; 1.408 ; v_cnt[0]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.698      ;
; 1.417 ; v_cnt[0]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.707      ;
; 1.418 ; h_cnt[0]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.709      ;
; 1.418 ; v_cnt[4]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.708      ;
; 1.420 ; v_cnt[3]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.710      ;
; 1.422 ; h_cnt[1]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.713      ;
; 1.452 ; v_cnt[5]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.742      ;
; 1.461 ; h_cnt[2]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.752      ;
; 1.517 ; h_cnt[4]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.808      ;
; 1.517 ; h_cnt[7]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.808      ;
; 1.532 ; v_cnt[3]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.822      ;
; 1.536 ; h_cnt[6]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.827      ;
; 1.538 ; v_cnt[1]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.828      ;
; 1.542 ; v_cnt[5]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.832      ;
; 1.547 ; v_cnt[1]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.837      ;
; 1.548 ; v_cnt[0]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.838      ;
; 1.549 ; h_cnt[0]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.840      ;
; 1.553 ; v_cnt[2]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.843      ;
; 1.553 ; h_cnt[1]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.844      ;
; 1.557 ; v_cnt[0]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.847      ;
; 1.571 ; h_cnt[2]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.862      ;
; 1.630 ; v_cnt[2]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.920      ;
; 1.631 ; h_cnt[3]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.922      ;
; 1.669 ; h_cnt[5]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.960      ;
; 1.678 ; v_cnt[1]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.968      ;
; 1.685 ; h_cnt[4]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.976      ;
; 1.688 ; v_cnt[0]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.978      ;
; 1.693 ; v_cnt[2]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.983      ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk'                                                                                                    ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                             ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+
; 9.860  ; 9.860        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.860  ; 9.860        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.891  ; 9.891        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                                                        ;
; 9.923  ; 9.923        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                                                        ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                                                        ;
; 10.075 ; 10.075       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.109 ; 10.109       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o                                                        ;
; 10.138 ; 10.138       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]           ;
; 10.138 ; 10.138       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|observablevcoout ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                                                ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]                                                                       ;
; 19.699 ; 19.919       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r                                                                          ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]                                                                       ;
; 19.700 ; 19.920       ; 0.220          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r                                                                          ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]                                                                       ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r                                                                          ;
; 19.890 ; 20.078       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r                                                                          ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]                                                                       ;
; 19.891 ; 20.079       ; 0.188          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]                                                                       ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]|clk                                                                   ;
; 19.968 ; 19.968       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r|clk                                                                      ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r|clk                                                                      ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r|clk                                                                      ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r|clk                                                                      ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]|clk                                                                   ;
; 20.031 ; 20.031       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]|clk                                                                   ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; hys       ; clk        ; 7.224 ; 6.745 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_b     ; clk        ; 8.166 ; 8.381 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_g     ; clk        ; 8.797 ; 9.107 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_r     ; clk        ; 9.011 ; 8.454 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; vys       ; clk        ; 5.435 ; 5.118 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                  ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; hys       ; clk        ; 6.660 ; 6.183 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_b     ; clk        ; 5.131 ; 5.408 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_g     ; clk        ; 5.737 ; 6.105 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_r     ; clk        ; 6.472 ; 6.037 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; vys       ; clk        ; 4.860 ; 4.548 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                              ;
+------------+-----------------+----------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                               ; Note ;
+------------+-----------------+----------------------------------------------------------+------+
; 229.57 MHz ; 229.57 MHz      ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+----------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-----------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                ;
+----------------------------------------------------------+--------+---------------+
; Clock                                                    ; Slack  ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 35.644 ; 0.000         ;
+----------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                ;
+----------------------------------------------------------+-------+---------------+
; Clock                                                    ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.403 ; 0.000         ;
+----------------------------------------------------------+-------+---------------+


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+-----------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                  ;
+----------------------------------------------------------+--------+---------------+
; Clock                                                    ; Slack  ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; clk                                                      ; 9.840  ; 0.000         ;
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 19.699 ; 0.000         ;
+----------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                       ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node  ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 35.644 ; h_cnt[7]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.288      ;
; 35.694 ; h_cnt[3]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.238      ;
; 35.746 ; h_cnt[7]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.186      ;
; 35.759 ; h_cnt[5]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.173      ;
; 35.766 ; h_cnt[8]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.166      ;
; 35.770 ; h_cnt[7]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.162      ;
; 35.803 ; h_cnt[3]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.129      ;
; 35.820 ; h_cnt[3]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.112      ;
; 35.872 ; h_cnt[7]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.060      ;
; 35.885 ; h_cnt[5]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.047      ;
; 35.892 ; h_cnt[8]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.040      ;
; 35.896 ; h_cnt[7]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.036      ;
; 35.923 ; h_cnt[2]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.009      ;
; 35.924 ; h_cnt[5]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.008      ;
; 35.929 ; h_cnt[3]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.003      ;
; 35.931 ; h_cnt[8]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 4.001      ;
; 35.941 ; h_cnt[9]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.991      ;
; 35.946 ; h_cnt[3]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.986      ;
; 35.998 ; h_cnt[7]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.934      ;
; 36.011 ; h_cnt[5]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.921      ;
; 36.018 ; h_cnt[8]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.914      ;
; 36.022 ; h_cnt[7]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.910      ;
; 36.049 ; h_cnt[2]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.883      ;
; 36.050 ; h_cnt[5]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.882      ;
; 36.054 ; h_cnt[4]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.878      ;
; 36.055 ; h_cnt[3]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.877      ;
; 36.057 ; h_cnt[8]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.875      ;
; 36.067 ; h_cnt[9]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.865      ;
; 36.072 ; h_cnt[3]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.860      ;
; 36.088 ; h_cnt[2]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.844      ;
; 36.106 ; h_cnt[9]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.826      ;
; 36.124 ; h_cnt[7]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.808      ;
; 36.137 ; h_cnt[5]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.795      ;
; 36.144 ; h_cnt[8]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.788      ;
; 36.148 ; h_cnt[7]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.784      ;
; 36.164 ; h_cnt[6]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.768      ;
; 36.175 ; h_cnt[2]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.757      ;
; 36.176 ; h_cnt[5]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.756      ;
; 36.180 ; h_cnt[4]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.752      ;
; 36.181 ; h_cnt[3]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.751      ;
; 36.183 ; h_cnt[8]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.749      ;
; 36.193 ; h_cnt[9]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.739      ;
; 36.198 ; h_cnt[3]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.734      ;
; 36.214 ; h_cnt[2]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.718      ;
; 36.219 ; h_cnt[4]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.713      ;
; 36.232 ; h_cnt[9]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.700      ;
; 36.263 ; h_cnt[5]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.669      ;
; 36.270 ; h_cnt[8]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.662      ;
; 36.290 ; h_cnt[6]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.642      ;
; 36.301 ; h_cnt[2]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.631      ;
; 36.302 ; h_cnt[5]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.630      ;
; 36.306 ; h_cnt[4]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.626      ;
; 36.309 ; h_cnt[8]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.623      ;
; 36.319 ; h_cnt[9]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.613      ;
; 36.321 ; h_cnt[6]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.611      ;
; 36.340 ; h_cnt[2]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.592      ;
; 36.345 ; h_cnt[4]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.587      ;
; 36.358 ; h_cnt[9]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.574      ;
; 36.416 ; h_cnt[6]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.516      ;
; 36.421 ; h_cnt[7]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.510      ;
; 36.421 ; h_cnt[7]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.510      ;
; 36.427 ; h_cnt[2]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.505      ;
; 36.432 ; h_cnt[4]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.500      ;
; 36.437 ; h_cnt[1]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.495      ;
; 36.445 ; h_cnt[9]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.487      ;
; 36.447 ; h_cnt[6]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.485      ;
; 36.466 ; h_cnt[2]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.466      ;
; 36.471 ; h_cnt[4]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.461      ;
; 36.471 ; h_cnt[3]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.460      ;
; 36.471 ; h_cnt[3]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.460      ;
; 36.484 ; h_cnt[9]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.448      ;
; 36.536 ; h_cnt[5]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.395      ;
; 36.536 ; h_cnt[5]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.395      ;
; 36.542 ; h_cnt[6]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.390      ;
; 36.543 ; h_cnt[8]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.388      ;
; 36.543 ; h_cnt[8]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.388      ;
; 36.558 ; h_cnt[4]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.374      ;
; 36.563 ; h_cnt[1]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.369      ;
; 36.563 ; h_cnt[1]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.369      ;
; 36.573 ; h_cnt[6]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.359      ;
; 36.597 ; h_cnt[4]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.335      ;
; 36.644 ; h_cnt[7]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.288      ;
; 36.668 ; h_cnt[6]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.264      ;
; 36.684 ; v_cnt[8]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.247      ;
; 36.689 ; h_cnt[1]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.243      ;
; 36.689 ; h_cnt[1]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.243      ;
; 36.696 ; h_cnt[7]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.235      ;
; 36.699 ; h_cnt[6]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.233      ;
; 36.700 ; h_cnt[7]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.231      ;
; 36.700 ; h_cnt[2]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.231      ;
; 36.700 ; h_cnt[2]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.231      ;
; 36.701 ; h_cnt[3]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.231      ;
; 36.703 ; h_cnt[0]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.229      ;
; 36.718 ; h_cnt[9]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.213      ;
; 36.718 ; h_cnt[9]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.213      ;
; 36.753 ; h_cnt[3]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.178      ;
; 36.757 ; h_cnt[3]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.174      ;
; 36.815 ; h_cnt[1]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.117      ;
; 36.815 ; h_cnt[1]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.070     ; 3.117      ;
; 36.824 ; h_cnt[5]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.071     ; 3.107      ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                       ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node  ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.403 ; hys_r     ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.707 ; h_cnt[7]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.973      ;
; 0.710 ; v_cnt[9]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.975      ;
; 0.710 ; h_cnt[3]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.976      ;
; 0.712 ; v_cnt[3]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.977      ;
; 0.713 ; h_cnt[6]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.979      ;
; 0.717 ; v_cnt[7]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.982      ;
; 0.719 ; v_cnt[1]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.984      ;
; 0.722 ; v_cnt[6]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.987      ;
; 0.722 ; v_cnt[8]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.987      ;
; 0.722 ; h_cnt[4]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.988      ;
; 0.723 ; v_cnt[4]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.988      ;
; 0.729 ; h_cnt[1]  ; h_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.995      ;
; 0.733 ; v_cnt[0]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.998      ;
; 0.859 ; h_cnt[2]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.125      ;
; 0.880 ; v_cnt[5]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.145      ;
; 0.882 ; v_cnt[9]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.147      ;
; 0.901 ; h_cnt[6]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.167      ;
; 0.912 ; h_cnt[5]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.178      ;
; 0.920 ; v_cnt[0]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.185      ;
; 1.005 ; v_cnt[1]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.270      ;
; 1.024 ; h_cnt[0]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.290      ;
; 1.031 ; h_cnt[6]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.297      ;
; 1.031 ; v_cnt[0]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.296      ;
; 1.031 ; h_cnt[0]  ; h_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.297      ;
; 1.034 ; h_cnt[3]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.300      ;
; 1.036 ; v_cnt[3]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.301      ;
; 1.039 ; v_cnt[7]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.304      ;
; 1.041 ; v_cnt[1]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.306      ;
; 1.041 ; v_cnt[8]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.306      ;
; 1.041 ; v_cnt[6]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.306      ;
; 1.042 ; v_cnt[4]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.307      ;
; 1.043 ; h_cnt[5]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.309      ;
; 1.048 ; h_cnt[0]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.314      ;
; 1.048 ; v_cnt[0]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.313      ;
; 1.051 ; h_cnt[1]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.317      ;
; 1.056 ; v_cnt[6]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.321      ;
; 1.056 ; h_cnt[4]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.322      ;
; 1.057 ; v_cnt[4]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.322      ;
; 1.080 ; vys_r     ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.346      ;
; 1.088 ; h_cnt[5]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.354      ;
; 1.092 ; v_cnt[2]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.357      ;
; 1.100 ; h_cnt[8]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.366      ;
; 1.130 ; v_cnt[3]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.395      ;
; 1.134 ; v_cnt[7]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.399      ;
; 1.138 ; v_cnt[1]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.403      ;
; 1.139 ; h_cnt[5]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.405      ;
; 1.145 ; h_cnt[1]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.411      ;
; 1.153 ; v_cnt[0]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.418      ;
; 1.153 ; h_cnt[0]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.419      ;
; 1.155 ; h_cnt[2]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.421      ;
; 1.156 ; h_cnt[3]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.422      ;
; 1.158 ; v_cnt[3]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.423      ;
; 1.163 ; v_cnt[1]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.428      ;
; 1.163 ; v_cnt[6]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.428      ;
; 1.163 ; h_cnt[4]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.429      ;
; 1.164 ; v_cnt[4]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.429      ;
; 1.169 ; h_cnt[1]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.435      ;
; 1.170 ; h_cnt[0]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.436      ;
; 1.170 ; v_cnt[0]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.435      ;
; 1.173 ; h_cnt[1]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.439      ;
; 1.179 ; v_cnt[4]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.444      ;
; 1.222 ; h_cnt[9]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.488      ;
; 1.227 ; v_cnt[5]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.492      ;
; 1.234 ; h_cnt[2]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.500      ;
; 1.244 ; h_cnt[0]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.510      ;
; 1.250 ; h_cnt[3]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.516      ;
; 1.252 ; v_cnt[3]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.517      ;
; 1.255 ; v_cnt[5]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.520      ;
; 1.260 ; v_cnt[1]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.525      ;
; 1.275 ; v_cnt[0]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.540      ;
; 1.280 ; v_cnt[3]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.545      ;
; 1.285 ; v_cnt[1]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.550      ;
; 1.286 ; v_cnt[4]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.551      ;
; 1.292 ; h_cnt[0]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.558      ;
; 1.292 ; v_cnt[0]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.557      ;
; 1.295 ; h_cnt[1]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.561      ;
; 1.308 ; v_cnt[3]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.573      ;
; 1.349 ; v_cnt[5]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.614      ;
; 1.356 ; h_cnt[2]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.622      ;
; 1.374 ; v_cnt[3]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.639      ;
; 1.377 ; v_cnt[5]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.642      ;
; 1.382 ; v_cnt[1]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.647      ;
; 1.383 ; h_cnt[4]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.649      ;
; 1.386 ; h_cnt[7]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.652      ;
; 1.388 ; v_cnt[2]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.653      ;
; 1.389 ; h_cnt[1]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.655      ;
; 1.397 ; v_cnt[0]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.662      ;
; 1.397 ; h_cnt[0]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.663      ;
; 1.399 ; h_cnt[2]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.665      ;
; 1.404 ; h_cnt[6]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.670      ;
; 1.407 ; v_cnt[1]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.672      ;
; 1.414 ; v_cnt[0]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.679      ;
; 1.483 ; h_cnt[3]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.749      ;
; 1.495 ; v_cnt[2]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.760      ;
; 1.504 ; v_cnt[1]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.769      ;
; 1.510 ; v_cnt[2]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.775      ;
; 1.519 ; v_cnt[0]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.784      ;
; 1.522 ; h_cnt[5]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.788      ;
; 1.535 ; h_cnt[4]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.801      ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk'                                                                                                     ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                             ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+
; 9.840  ; 9.840        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.840  ; 9.840        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.891  ; 9.891        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                                                        ;
; 9.916  ; 9.916        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                                                        ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                                                        ;
; 10.083 ; 10.083       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.109 ; 10.109       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o                                                        ;
; 10.159 ; 10.159       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]           ;
; 10.159 ; 10.159       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|observablevcoout ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                                                ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]                                                                       ;
; 19.699 ; 19.915       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r                                                                          ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]                                                                       ;
; 19.700 ; 19.916       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r                                                                          ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]                                                                       ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r                                                                          ;
; 19.896 ; 20.080       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r                                                                          ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]                                                                       ;
; 19.897 ; 20.081       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]                                                                       ;
; 19.967 ; 19.967       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.967 ; 19.967       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]|clk                                                                   ;
; 19.969 ; 19.969       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r|clk                                                                      ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]|clk                                                                   ;
; 19.970 ; 19.970       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r|clk                                                                      ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]|clk                                                                   ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r|clk                                                                      ;
; 20.029 ; 20.029       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r|clk                                                                      ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]|clk                                                                   ;
; 20.030 ; 20.030       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]|clk                                                                   ;
; 20.032 ; 20.032       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 20.032 ; 20.032       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 37.513 ; 40.000       ; 2.487          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; hys       ; clk        ; 7.244 ; 6.655 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_b     ; clk        ; 7.858 ; 8.102 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_g     ; clk        ; 8.438 ; 8.801 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_r     ; clk        ; 8.803 ; 8.044 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; vys       ; clk        ; 5.442 ; 5.018 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                  ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; hys       ; clk        ; 6.746 ; 6.163 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_b     ; clk        ; 5.027 ; 5.466 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_g     ; clk        ; 5.583 ; 6.137 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_r     ; clk        ; 6.418 ; 5.919 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; vys       ; clk        ; 4.934 ; 4.519 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                ;
+----------------------------------------------------------+--------+---------------+
; Clock                                                    ; Slack  ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 37.947 ; 0.000         ;
+----------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                ;
+----------------------------------------------------------+-------+---------------+
; Clock                                                    ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.188 ; 0.000         ;
+----------------------------------------------------------+-------+---------------+


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+-----------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                  ;
+----------------------------------------------------------+--------+---------------+
; Clock                                                    ; Slack  ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; clk                                                      ; 9.407  ; 0.000         ;
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 19.786 ; 0.000         ;
+----------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                       ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node ; To Node  ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 37.947 ; h_cnt[7]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 2.005      ;
; 37.971 ; h_cnt[3]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.981      ;
; 38.011 ; h_cnt[7]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.941      ;
; 38.015 ; h_cnt[7]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.937      ;
; 38.035 ; h_cnt[3]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.917      ;
; 38.039 ; h_cnt[3]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.913      ;
; 38.078 ; h_cnt[8]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.874      ;
; 38.079 ; h_cnt[7]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.873      ;
; 38.081 ; h_cnt[5]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.871      ;
; 38.082 ; h_cnt[8]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.870      ;
; 38.083 ; h_cnt[7]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.869      ;
; 38.085 ; h_cnt[5]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.867      ;
; 38.096 ; h_cnt[2]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.856      ;
; 38.103 ; h_cnt[3]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.849      ;
; 38.107 ; h_cnt[3]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.845      ;
; 38.146 ; h_cnt[8]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.806      ;
; 38.147 ; h_cnt[7]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.805      ;
; 38.149 ; h_cnt[5]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.803      ;
; 38.150 ; h_cnt[8]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.802      ;
; 38.151 ; h_cnt[7]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.801      ;
; 38.153 ; h_cnt[5]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.799      ;
; 38.156 ; h_cnt[4]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.796      ;
; 38.160 ; h_cnt[2]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.792      ;
; 38.164 ; h_cnt[2]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.788      ;
; 38.171 ; h_cnt[3]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.781      ;
; 38.172 ; h_cnt[9]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.780      ;
; 38.175 ; h_cnt[3]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.777      ;
; 38.176 ; h_cnt[9]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.776      ;
; 38.201 ; h_cnt[6]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.751      ;
; 38.214 ; h_cnt[8]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.738      ;
; 38.215 ; h_cnt[7]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.737      ;
; 38.217 ; h_cnt[5]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.735      ;
; 38.218 ; h_cnt[8]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.734      ;
; 38.219 ; h_cnt[7]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.733      ;
; 38.220 ; h_cnt[4]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.732      ;
; 38.221 ; h_cnt[5]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.731      ;
; 38.224 ; h_cnt[4]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.728      ;
; 38.228 ; h_cnt[2]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.724      ;
; 38.232 ; h_cnt[2]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.720      ;
; 38.239 ; h_cnt[3]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.713      ;
; 38.240 ; h_cnt[9]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.712      ;
; 38.243 ; h_cnt[3]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.709      ;
; 38.244 ; h_cnt[9]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.708      ;
; 38.265 ; h_cnt[6]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.687      ;
; 38.269 ; h_cnt[6]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.683      ;
; 38.282 ; h_cnt[8]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.670      ;
; 38.285 ; h_cnt[5]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.667      ;
; 38.286 ; h_cnt[8]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.666      ;
; 38.288 ; h_cnt[4]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.664      ;
; 38.289 ; h_cnt[5]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.663      ;
; 38.292 ; h_cnt[4]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.660      ;
; 38.294 ; h_cnt[1]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.658      ;
; 38.296 ; h_cnt[2]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.656      ;
; 38.300 ; h_cnt[2]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.652      ;
; 38.308 ; h_cnt[9]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.644      ;
; 38.312 ; h_cnt[9]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.640      ;
; 38.333 ; h_cnt[6]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.619      ;
; 38.337 ; h_cnt[6]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.615      ;
; 38.350 ; h_cnt[8]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.602      ;
; 38.353 ; h_cnt[5]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.599      ;
; 38.356 ; h_cnt[4]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.596      ;
; 38.358 ; h_cnt[1]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.594      ;
; 38.360 ; h_cnt[4]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.592      ;
; 38.362 ; h_cnt[1]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.590      ;
; 38.363 ; h_cnt[7]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.589      ;
; 38.363 ; h_cnt[7]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.589      ;
; 38.364 ; h_cnt[2]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.588      ;
; 38.368 ; h_cnt[2]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.584      ;
; 38.376 ; h_cnt[9]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.576      ;
; 38.380 ; h_cnt[9]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.572      ;
; 38.387 ; h_cnt[3]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.565      ;
; 38.387 ; h_cnt[3]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.565      ;
; 38.401 ; h_cnt[6]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.551      ;
; 38.402 ; h_cnt[8]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.550      ;
; 38.403 ; h_cnt[8]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.549      ;
; 38.405 ; h_cnt[6]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.547      ;
; 38.405 ; h_cnt[5]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.547      ;
; 38.406 ; h_cnt[5]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.546      ;
; 38.424 ; h_cnt[4]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.528      ;
; 38.426 ; h_cnt[1]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.526      ;
; 38.428 ; h_cnt[0]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.524      ;
; 38.428 ; h_cnt[4]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.524      ;
; 38.430 ; h_cnt[1]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.522      ;
; 38.444 ; h_cnt[9]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.508      ;
; 38.469 ; h_cnt[6]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.483      ;
; 38.473 ; h_cnt[6]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.479      ;
; 38.488 ; h_cnt[7]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.464      ;
; 38.491 ; h_cnt[7]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.461      ;
; 38.492 ; h_cnt[0]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.460      ;
; 38.494 ; h_cnt[7]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.458      ;
; 38.494 ; h_cnt[1]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.458      ;
; 38.496 ; h_cnt[0]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.456      ;
; 38.496 ; h_cnt[9]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.456      ;
; 38.497 ; h_cnt[9]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.455      ;
; 38.498 ; h_cnt[1]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.454      ;
; 38.505 ; h_cnt[2]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.447      ;
; 38.506 ; h_cnt[2]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.446      ;
; 38.509 ; h_cnt[3]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.443      ;
; 38.512 ; h_cnt[3]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.440      ;
; 38.515 ; h_cnt[3]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 40.000       ; -0.035     ; 1.437      ;
+--------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                       ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node  ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.188 ; hys_r     ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.304 ; v_cnt[9]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.306 ; v_cnt[3]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; h_cnt[7]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.425      ;
; 0.307 ; h_cnt[3]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.426      ;
; 0.308 ; h_cnt[6]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.427      ;
; 0.310 ; v_cnt[1]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.430      ;
; 0.310 ; v_cnt[7]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.430      ;
; 0.311 ; v_cnt[6]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; v_cnt[4]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; v_cnt[8]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.431      ;
; 0.312 ; v_cnt[0]  ; v_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.312 ; h_cnt[4]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.431      ;
; 0.317 ; h_cnt[1]  ; h_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.436      ;
; 0.368 ; v_cnt[5]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.488      ;
; 0.368 ; h_cnt[2]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.487      ;
; 0.372 ; v_cnt[9]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.491      ;
; 0.382 ; v_cnt[0]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.501      ;
; 0.383 ; h_cnt[6]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.502      ;
; 0.396 ; h_cnt[5]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.515      ;
; 0.438 ; v_cnt[1]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.557      ;
; 0.448 ; h_cnt[0]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.567      ;
; 0.455 ; v_cnt[3]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.456 ; h_cnt[3]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.459 ; v_cnt[1]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.459 ; v_cnt[7]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.462 ; h_cnt[5]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.581      ;
; 0.464 ; vys_r     ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.583      ;
; 0.465 ; v_cnt[0]  ; v_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.585      ;
; 0.466 ; h_cnt[6]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.585      ;
; 0.466 ; h_cnt[1]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.585      ;
; 0.467 ; h_cnt[5]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.586      ;
; 0.468 ; h_cnt[0]  ; h_cnt[1] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.587      ;
; 0.468 ; v_cnt[0]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.588      ;
; 0.469 ; v_cnt[8]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.589      ;
; 0.469 ; v_cnt[6]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.589      ;
; 0.469 ; v_cnt[4]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.589      ;
; 0.471 ; h_cnt[0]  ; h_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.590      ;
; 0.472 ; v_cnt[4]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.592      ;
; 0.472 ; v_cnt[6]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.592      ;
; 0.473 ; h_cnt[4]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.592      ;
; 0.475 ; h_cnt[8]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.594      ;
; 0.482 ; v_cnt[2]  ; v_cnt[2] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.602      ;
; 0.511 ; h_cnt[1]  ; hys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.630      ;
; 0.517 ; v_cnt[5]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.637      ;
; 0.518 ; v_cnt[3]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.638      ;
; 0.521 ; v_cnt[3]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.641      ;
; 0.522 ; v_cnt[1]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.522 ; v_cnt[7]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.522 ; h_cnt[3]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.641      ;
; 0.523 ; h_cnt[9]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.642      ;
; 0.525 ; v_cnt[1]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.645      ;
; 0.525 ; h_cnt[5]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.644      ;
; 0.526 ; h_cnt[2]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.645      ;
; 0.529 ; h_cnt[2]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.648      ;
; 0.529 ; h_cnt[1]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.648      ;
; 0.531 ; v_cnt[0]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.651      ;
; 0.532 ; h_cnt[1]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.651      ;
; 0.534 ; v_cnt[0]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.654      ;
; 0.534 ; h_cnt[0]  ; h_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.653      ;
; 0.535 ; v_cnt[4]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.655      ;
; 0.535 ; v_cnt[6]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.655      ;
; 0.536 ; h_cnt[4]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.655      ;
; 0.537 ; h_cnt[0]  ; h_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.656      ;
; 0.538 ; v_cnt[4]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.658      ;
; 0.544 ; h_cnt[0]  ; h_cnt[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.663      ;
; 0.578 ; v_cnt[3]  ; vys_r    ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.697      ;
; 0.580 ; v_cnt[5]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.700      ;
; 0.583 ; v_cnt[5]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.703      ;
; 0.584 ; v_cnt[3]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.704      ;
; 0.585 ; h_cnt[3]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.704      ;
; 0.587 ; v_cnt[3]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.707      ;
; 0.588 ; v_cnt[1]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.708      ;
; 0.591 ; v_cnt[1]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.711      ;
; 0.595 ; h_cnt[2]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.714      ;
; 0.597 ; v_cnt[0]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.717      ;
; 0.598 ; h_cnt[1]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.717      ;
; 0.600 ; v_cnt[0]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.720      ;
; 0.601 ; v_cnt[4]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.721      ;
; 0.603 ; h_cnt[0]  ; h_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.722      ;
; 0.609 ; h_cnt[7]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.728      ;
; 0.623 ; h_cnt[6]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.742      ;
; 0.624 ; h_cnt[4]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.743      ;
; 0.640 ; v_cnt[2]  ; v_cnt[3] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.760      ;
; 0.643 ; v_cnt[2]  ; v_cnt[4] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.763      ;
; 0.646 ; v_cnt[5]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.766      ;
; 0.650 ; v_cnt[3]  ; v_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.770      ;
; 0.654 ; v_cnt[1]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.774      ;
; 0.657 ; v_cnt[1]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.777      ;
; 0.658 ; h_cnt[2]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.777      ;
; 0.661 ; h_cnt[1]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.780      ;
; 0.663 ; v_cnt[0]  ; v_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.783      ;
; 0.666 ; v_cnt[0]  ; v_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.786      ;
; 0.666 ; h_cnt[0]  ; h_cnt[7] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.785      ;
; 0.673 ; h_cnt[3]  ; h_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.792      ;
; 0.682 ; h_cnt[5]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.801      ;
; 0.692 ; h_cnt[8]  ; h_cnt[9] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.811      ;
; 0.693 ; h_cnt[4]  ; h_cnt[8] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.812      ;
; 0.706 ; v_cnt[2]  ; v_cnt[5] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.826      ;
; 0.709 ; v_cnt[2]  ; v_cnt[6] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.829      ;
+-------+-----------+----------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk'                                                                                                     ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                             ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+
; 9.407  ; 9.407        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]           ;
; 9.407  ; 9.407        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|observablevcoout ;
; 9.441  ; 9.441        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                                                        ;
; 9.450  ; 9.450        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                                                        ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                                                        ;
; 10.550 ; 10.550       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|inclk[0]         ;
; 10.559 ; 10.559       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o                                                        ;
; 10.591 ; 10.591       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]           ;
; 10.591 ; 10.591       ; 0.000          ; High Pulse Width ; clk   ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|observablevcoout ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                                                ;
+--------+--------------+----------------+------------------+-------+------------+--------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]                                                                       ;
; 19.786 ; 20.002       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r                                                                          ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]                                                                       ;
; 19.787 ; 20.003       ; 0.216          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r                                                                          ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r                                                                          ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]                                                                       ;
; 19.811 ; 19.995       ; 0.184          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r                                                                          ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r|clk                                                                      ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]|clk                                                                   ;
; 19.991 ; 19.991       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r|clk                                                                      ;
; 19.999 ; 19.999       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.999 ; 19.999       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 20.001 ; 20.001       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 20.001 ; 20.001       ; 0.000          ; Low Pulse Width  ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vga_pll_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[8]|clk                                                                   ;
; 20.008 ; 20.008       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[9]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; hys_r|clk                                                                      ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[0]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[1]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[2]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[3]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[4]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[5]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[6]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[7]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[8]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; v_cnt[9]|clk                                                                   ;
; 20.009 ; 20.009       ; 0.000          ; High Pulse Width ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; vys_r|clk                                                                      ;
; 38.000 ; 40.000       ; 2.000          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[0]                                                                       ;
; 38.000 ; 40.000       ; 2.000          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[1]                                                                       ;
; 38.000 ; 40.000       ; 2.000          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[2]                                                                       ;
; 38.000 ; 40.000       ; 2.000          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[3]                                                                       ;
; 38.000 ; 40.000       ; 2.000          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[4]                                                                       ;
; 38.000 ; 40.000       ; 2.000          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[5]                                                                       ;
; 38.000 ; 40.000       ; 2.000          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[6]                                                                       ;
; 38.000 ; 40.000       ; 2.000          ; Min Period       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; h_cnt[7]                                                                       ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; hys       ; clk        ; 3.890 ; 3.731 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_b     ; clk        ; 3.749 ; 3.782 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_g     ; clk        ; 4.079 ; 4.076 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_r     ; clk        ; 3.968 ; 4.026 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; vys       ; clk        ; 2.514 ; 2.536 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                  ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; hys       ; clk        ; 3.623 ; 3.459 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_b     ; clk        ; 2.520 ; 2.449 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_g     ; clk        ; 2.837 ; 2.732 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_r     ; clk        ; 2.957 ; 2.922 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; vys       ; clk        ; 2.243 ; 2.262 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                   ;
+-----------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                     ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+-----------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                          ; 35.197 ; 0.188 ; N/A      ; N/A     ; 9.407               ;
;  clk                                                      ; N/A    ; N/A   ; N/A      ; N/A     ; 9.407               ;
;  vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 35.197 ; 0.188 ; N/A      ; N/A     ; 19.699              ;
; Design-wide TNS                                           ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  clk                                                      ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+-----------------------------------------------------------+--------+-------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; hys       ; clk        ; 7.244 ; 6.745 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_b     ; clk        ; 8.166 ; 8.381 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_g     ; clk        ; 8.797 ; 9.107 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_r     ; clk        ; 9.011 ; 8.454 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; vys       ; clk        ; 5.442 ; 5.118 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                  ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                          ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+
; hys       ; clk        ; 3.623 ; 3.459 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_b     ; clk        ; 2.520 ; 2.449 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_g     ; clk        ; 2.837 ; 2.732 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; rgb_r     ; clk        ; 2.957 ; 2.922 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
; vys       ; clk        ; 2.243 ; 2.262 ; Rise       ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; hys           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; vys           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rgb_r         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rgb_g         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rgb_b         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; reset                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; clk                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; hys           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; vys           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; rgb_r         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; rgb_g         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; rgb_b         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.58e-07 V                   ; 3.13 V              ; -0.0396 V           ; 0.18 V                               ; 0.073 V                              ; 4.81e-10 s                  ; 4.67e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.58e-07 V                  ; 3.13 V             ; -0.0396 V          ; 0.18 V                              ; 0.073 V                             ; 4.81e-10 s                 ; 4.67e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; hys           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; vys           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; rgb_r         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; rgb_g         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; rgb_b         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.0651 V           ; 0.234 V                              ; 0.087 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.0651 V          ; 0.234 V                             ; 0.087 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                 ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                               ; To Clock                                                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 382      ; 0        ; 0        ; 0        ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                  ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                               ; To Clock                                                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 382      ; 0        ; 0        ; 0        ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 1     ; 1    ;
; Unconstrained Input Port Paths  ; 22    ; 22   ;
; Unconstrained Output Ports      ; 5     ; 5    ;
; Unconstrained Output Port Paths ; 47    ; 47   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
    Info: Processing started: Fri May 04 16:52:15 2012
Info: Command: quartus_sta vga_red -c vga_red
Info: qsta_default_script.tcl version: #1
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Critical Warning: Synopsys Design Constraints File file not found: 'vga_red.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info: Deriving PLL Clocks
    Info: create_clock -period 20.000 -waveform {0.000 10.000} -name clk clk
    Info: create_generated_clock -source {vga_pll_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -duty_cycle 50.00 -name {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]} {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Info: No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
Info: Analyzing Slow 1200mV 85C Model
Info: Worst-case setup slack is 35.197
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    35.197         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: Worst-case hold slack is 0.455
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.455         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 9.860
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     9.860         0.000 clk 
    Info:    19.699         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Slow 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
Info: Worst-case setup slack is 35.644
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    35.644         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: Worst-case hold slack is 0.403
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.403         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 9.840
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     9.840         0.000 clk 
    Info:    19.699         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Fast 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {vga_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.020
Info: Worst-case setup slack is 37.947
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    37.947         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: Worst-case hold slack is 0.188
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.188         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 9.407
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     9.407         0.000 clk 
    Info:    19.786         0.000 vga_pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 270 megabytes
    Info: Processing ended: Fri May 04 16:52:18 2012
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02


