Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  cycloneiii
Quartus root          :  d:/altera/quartus/bin/
Quartus sim root      :  d:/altera/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :  vga_red.vo
Sim SDF file          :  vga_red__verilog.sdo
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script d:/altera/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File vga_red_run_msim_rtl_verilog.do already exists - backing up current file as vga_red_run_msim_rtl_verilog.do.bak1
Info: Spawning ModelSim-Altera Simulation software 
