Analysis & Synthesis report for DS18B20_LCD1602
Wed Jun 20 11:04:06 2012
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis IP Cores Summary
  9. User-Specified and Inferred Latches
 10. Registers Removed During Synthesis
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Parameter Settings for User Entity Instance: cont:inst1|lpm_counter:lpm_counter_component
 15. Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Div1
 16. Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Mod0
 17. Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Mod1
 18. Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Div0
 19. Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Mod2
 20. Elapsed Time Per Partition
 21. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Wed Jun 20 11:04:06 2012     ;
; Quartus II Version                 ; 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name                      ; DS18B20_LCD1602                           ;
; Top-level Entity Name              ; DS18B20_LCD1602                           ;
; Family                             ; Cyclone III                               ;
; Total logic elements               ; 734                                       ;
;     Total combinational functions  ; 726                                       ;
;     Dedicated logic registers      ; 146                                       ;
; Total registers                    ; 146                                       ;
; Total pins                         ; 29                                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 0                                         ;
; Embedded Multiplier 9-bit elements ; 0                                         ;
; Total PLLs                         ; 0                                         ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP3C16Q240C8       ;                    ;
; Top-level entity name                                                      ; DS18B20_LCD1602    ; DS18B20_LCD1602    ;
; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; lcdm_data.VHD                    ; yes             ; User VHDL File                     ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/lcdm_data.VHD                   ;
; CLK_DIV.v                        ; yes             ; User Verilog HDL File              ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/CLK_DIV.v                       ;
; BO.vhd                           ; yes             ; User VHDL File                     ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/BO.vhd                          ;
; DS18B20_LCD1602.bdf              ; yes             ; User Block Diagram/Schematic File  ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/DS18B20_LCD1602.bdf             ;
; cont.v                           ; yes             ; Auto-Found Wizard-Generated File   ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/cont.v                          ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/dffeea.inc              ;
; alt_counter_stratix.inc          ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal110.inc                   ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/aglobal110.inc          ;
; db/cntr_2si.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/cntr_2si.tdf                 ;
; lpm_divide.tdf                   ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_divide.tdf          ;
; abs_divider.inc                  ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/abs_divider.inc         ;
; sign_div_unsign.inc              ; yes             ; Megafunction                       ; c:/altera/11.0/quartus/libraries/megafunctions/sign_div_unsign.inc     ;
; db/lpm_divide_ohm.tdf            ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/lpm_divide_ohm.tdf           ;
; db/sign_div_unsign_plh.tdf       ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/sign_div_unsign_plh.tdf      ;
; db/alt_u_div_t5f.tdf             ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/alt_u_div_t5f.tdf            ;
; db/add_sub_unc.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/add_sub_unc.tdf              ;
; db/add_sub_vnc.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/add_sub_vnc.tdf              ;
; db/lpm_divide_5bm.tdf            ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/lpm_divide_5bm.tdf           ;
; db/sign_div_unsign_3nh.tdf       ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/sign_div_unsign_3nh.tdf      ;
; db/alt_u_div_h8f.tdf             ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/alt_u_div_h8f.tdf            ;
; db/lpm_divide_f8m.tdf            ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/lpm_divide_f8m.tdf           ;
; db/sign_div_unsign_dkh.tdf       ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/sign_div_unsign_dkh.tdf      ;
; db/alt_u_div_53f.tdf             ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/alt_u_div_53f.tdf            ;
; db/lpm_divide_2jm.tdf            ; yes             ; Auto-Generated Megafunction        ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/db/lpm_divide_2jm.tdf           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+


+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                ;
+---------------------------------------------+--------------+
; Resource                                    ; Usage        ;
+---------------------------------------------+--------------+
; Estimated Total logic elements              ; 734          ;
;                                             ;              ;
; Total combinational functions               ; 726          ;
; Logic element usage by number of LUT inputs ;              ;
;     -- 4 input functions                    ; 282          ;
;     -- 3 input functions                    ; 145          ;
;     -- <=2 input functions                  ; 299          ;
;                                             ;              ;
; Logic elements by mode                      ;              ;
;     -- normal mode                          ; 527          ;
;     -- arithmetic mode                      ; 199          ;
;                                             ;              ;
; Total registers                             ; 146          ;
;     -- Dedicated logic registers            ; 146          ;
;     -- I/O registers                        ; 0            ;
;                                             ;              ;
; I/O pins                                    ; 29           ;
; Maximum fan-out node                        ; BO:inst8|clk ;
; Maximum fan-out                             ; 107          ;
; Total fan-out                               ; 2540         ;
; Average fan-out                             ; 2.73         ;
+---------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                     ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                              ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
; |DS18B20_LCD1602                          ; 726 (2)           ; 146 (1)      ; 0           ; 0            ; 0       ; 0         ; 29   ; 0            ; |DS18B20_LCD1602                                                                                                                 ;              ;
;    |BO:inst8|                             ; 258 (258)         ; 112 (112)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|BO:inst8                                                                                                        ;              ;
;    |CLK_DIV:inst|                         ; 25 (25)           ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|CLK_DIV:inst                                                                                                    ;              ;
;    |cont:inst1|                           ; 6 (0)             ; 6 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|cont:inst1                                                                                                      ;              ;
;       |lpm_counter:lpm_counter_component| ; 6 (0)             ; 6 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|cont:inst1|lpm_counter:lpm_counter_component                                                                    ;              ;
;          |cntr_2si:auto_generated|        ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated                                            ;              ;
;    |lcdm_data:inst7|                      ; 435 (142)         ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7                                                                                                 ;              ;
;       |lpm_divide:Div0|                   ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Div0                                                                                 ;              ;
;          |lpm_divide_2jm:auto_generated|  ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Div0|lpm_divide_2jm:auto_generated                                                   ;              ;
;             |sign_div_unsign_3nh:divider| ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Div0|lpm_divide_2jm:auto_generated|sign_div_unsign_3nh:divider                       ;              ;
;                |alt_u_div_h8f:divider|    ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Div0|lpm_divide_2jm:auto_generated|sign_div_unsign_3nh:divider|alt_u_div_h8f:divider ;              ;
;       |lpm_divide:Div1|                   ; 52 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Div1                                                                                 ;              ;
;          |lpm_divide_ohm:auto_generated|  ; 52 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Div1|lpm_divide_ohm:auto_generated                                                   ;              ;
;             |sign_div_unsign_plh:divider| ; 52 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Div1|lpm_divide_ohm:auto_generated|sign_div_unsign_plh:divider                       ;              ;
;                |alt_u_div_t5f:divider|    ; 52 (52)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Div1|lpm_divide_ohm:auto_generated|sign_div_unsign_plh:divider|alt_u_div_t5f:divider ;              ;
;       |lpm_divide:Mod0|                   ; 16 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod0                                                                                 ;              ;
;          |lpm_divide_5bm:auto_generated|  ; 16 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod0|lpm_divide_5bm:auto_generated                                                   ;              ;
;             |sign_div_unsign_3nh:divider| ; 16 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod0|lpm_divide_5bm:auto_generated|sign_div_unsign_3nh:divider                       ;              ;
;                |alt_u_div_h8f:divider|    ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod0|lpm_divide_5bm:auto_generated|sign_div_unsign_3nh:divider|alt_u_div_h8f:divider ;              ;
;       |lpm_divide:Mod1|                   ; 56 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod1                                                                                 ;              ;
;          |lpm_divide_f8m:auto_generated|  ; 56 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod1|lpm_divide_f8m:auto_generated                                                   ;              ;
;             |sign_div_unsign_dkh:divider| ; 56 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod1|lpm_divide_f8m:auto_generated|sign_div_unsign_dkh:divider                       ;              ;
;                |alt_u_div_53f:divider|    ; 56 (56)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod1|lpm_divide_f8m:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_53f:divider ;              ;
;       |lpm_divide:Mod2|                   ; 163 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod2                                                                                 ;              ;
;          |lpm_divide_5bm:auto_generated|  ; 163 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod2|lpm_divide_5bm:auto_generated                                                   ;              ;
;             |sign_div_unsign_3nh:divider| ; 163 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod2|lpm_divide_5bm:auto_generated|sign_div_unsign_3nh:divider                       ;              ;
;                |alt_u_div_h8f:divider|    ; 163 (163)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DS18B20_LCD1602|lcdm_data:inst7|lpm_divide:Mod2|lpm_divide_5bm:auto_generated|sign_div_unsign_3nh:divider|alt_u_div_h8f:divider ;              ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                       ;
+--------+--------------+---------+--------------+--------------+-----------------------------+-----------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance             ; IP Include File                               ;
+--------+--------------+---------+--------------+--------------+-----------------------------+-----------------------------------------------+
; Altera ; LPM_COUNTER  ; N/A     ; N/A          ; N/A          ; |DS18B20_LCD1602|cont:inst1 ; E:/Program/EP3C16/vhdl/DS18B20_LCD1602/cont.v ;
+--------+--------------+---------+--------------+--------------+-----------------------------+-----------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; BO:inst8|var4[0]                                   ; BO:inst8|ng         ; yes                    ;
; Number of user-specified and inferred latches = 1  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                   ;
+---------------------------------------------------------------------------------------------+----------------------------------------+
; Register name                                                                               ; Reason for Removal                     ;
+---------------------------------------------------------------------------------------------+----------------------------------------+
; BO:inst8|sel[0..3]                                                                          ; Stuck at GND due to stuck port data_in ;
; cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[6..15] ; Lost fanout                            ;
; Total Number of Removed Registers = 14                                                      ;                                        ;
+---------------------------------------------------------------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 146   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 10    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 76    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; BO:inst8|i[3]                          ; 6       ;
; BO:inst8|i[2]                          ; 5       ;
; BO:inst8|i[0]                          ; 8       ;
; BO:inst8|i[1]                          ; 6       ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+---------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                            ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+---------------------------------------+----------------------------+
; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; |DS18B20_LCD1602|BO:inst8|seg[6]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 8 LEs                ; 24 LEs                 ; |DS18B20_LCD1602|BO:inst8|count3[6]   ;                            ;
; 64:1               ; 4 bits    ; 168 LEs       ; 124 LEs              ; 44 LEs                 ; |DS18B20_LCD1602|lcdm_data:inst7|Q[0] ;                            ;
; 9:1                ; 11 bits   ; 66 LEs        ; 11 LEs               ; 55 LEs                 ; |DS18B20_LCD1602|BO:inst8|count1[3]   ;                            ;
; 13:1               ; 10 bits   ; 80 LEs        ; 10 LEs               ; 70 LEs                 ; |DS18B20_LCD1602|BO:inst8|count2[9]   ;                            ;
; 15:1               ; 8 bits    ; 80 LEs        ; 8 LEs                ; 72 LEs                 ; |DS18B20_LCD1602|BO:inst8|templ1[0]   ;                            ;
; 22:1               ; 2 bits    ; 28 LEs        ; 4 LEs                ; 24 LEs                 ; |DS18B20_LCD1602|BO:inst8|state[1]    ;                            ;
; 13:1               ; 4 bits    ; 32 LEs        ; 4 LEs                ; 28 LEs                 ; |DS18B20_LCD1602|BO:inst8|i[2]        ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+---------------------------------------+----------------------------+


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cont:inst1|lpm_counter:lpm_counter_component ;
+------------------------+-------------+----------------------------------------------------+
; Parameter Name         ; Value       ; Type                                               ;
+------------------------+-------------+----------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                         ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                       ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                       ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                     ;
; LPM_WIDTH              ; 16          ; Signed Integer                                     ;
; LPM_DIRECTION          ; UP          ; Untyped                                            ;
; LPM_MODULUS            ; 0           ; Untyped                                            ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                            ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                            ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                            ;
; DEVICE_FAMILY          ; Cyclone III ; Untyped                                            ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                            ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                 ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                 ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                            ;
; LABWIDE_SCLR           ; ON          ; Untyped                                            ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                            ;
; CBXI_PARAMETER         ; cntr_2si    ; Untyped                                            ;
+------------------------+-------------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Div1 ;
+------------------------+----------------+----------------------------------------+
; Parameter Name         ; Value          ; Type                                   ;
+------------------------+----------------+----------------------------------------+
; LPM_WIDTHN             ; 11             ; Untyped                                ;
; LPM_WIDTHD             ; 8              ; Untyped                                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_PIPELINE           ; 0              ; Untyped                                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                ;
; CBXI_PARAMETER         ; lpm_divide_ohm ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                         ;
+------------------------+----------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Mod0 ;
+------------------------+----------------+----------------------------------------+
; Parameter Name         ; Value          ; Type                                   ;
+------------------------+----------------+----------------------------------------+
; LPM_WIDTHN             ; 11             ; Untyped                                ;
; LPM_WIDTHD             ; 11             ; Untyped                                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_PIPELINE           ; 0              ; Untyped                                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                ;
; CBXI_PARAMETER         ; lpm_divide_5bm ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                         ;
+------------------------+----------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Mod1 ;
+------------------------+----------------+----------------------------------------+
; Parameter Name         ; Value          ; Type                                   ;
+------------------------+----------------+----------------------------------------+
; LPM_WIDTHN             ; 7              ; Untyped                                ;
; LPM_WIDTHD             ; 7              ; Untyped                                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_PIPELINE           ; 0              ; Untyped                                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                ;
; CBXI_PARAMETER         ; lpm_divide_f8m ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                         ;
+------------------------+----------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Div0 ;
+------------------------+----------------+----------------------------------------+
; Parameter Name         ; Value          ; Type                                   ;
+------------------------+----------------+----------------------------------------+
; LPM_WIDTHN             ; 11             ; Untyped                                ;
; LPM_WIDTHD             ; 11             ; Untyped                                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_PIPELINE           ; 0              ; Untyped                                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                ;
; CBXI_PARAMETER         ; lpm_divide_2jm ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                         ;
+------------------------+----------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lcdm_data:inst7|lpm_divide:Mod2 ;
+------------------------+----------------+----------------------------------------+
; Parameter Name         ; Value          ; Type                                   ;
+------------------------+----------------+----------------------------------------+
; LPM_WIDTHN             ; 11             ; Untyped                                ;
; LPM_WIDTHD             ; 11             ; Untyped                                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                ;
; LPM_PIPELINE           ; 0              ; Untyped                                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                ;
; CBXI_PARAMETER         ; lpm_divide_5bm ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                         ;
+------------------------+----------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:03     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
    Info: Processing started: Wed Jun 20 11:04:01 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DS18B20_LCD1602 -c DS18B20_LCD1602
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 2 design units, including 1 entities, in source file shizhong.vhd
    Info: Found design unit 1: shizhong-behave
    Info: Found entity 1: shizhong
Info: Found 2 design units, including 1 entities, in source file lcdm_data.vhd
    Info: Found design unit 1: lcdm_data-a
    Info: Found entity 1: lcdm_data
Info: Found 1 design units, including 1 entities, in source file clk_div.v
    Info: Found entity 1: CLK_DIV
Info: Found 2 design units, including 1 entities, in source file bo.vhd
    Info: Found design unit 1: BO-bhv
    Info: Found entity 1: BO
Info: Found 1 design units, including 1 entities, in source file ds18b20_lcd1602.bdf
    Info: Found entity 1: DS18B20_LCD1602
Info: Elaborating entity "DS18B20_LCD1602" for the top level hierarchy
Info: Elaborating entity "CLK_DIV" for hierarchy "CLK_DIV:inst"
Warning (10230): Verilog HDL assignment warning at CLK_DIV.v(23): truncated value with size 32 to match size of target (17)
Info: Elaborating entity "lcdm_data" for hierarchy "lcdm_data:inst7"
Warning (10492): VHDL Process Statement warning at lcdm_data.VHD(107): signal "var4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lcdm_data.VHD(120): signal "var3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lcdm_data.VHD(134): signal "var2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lcdm_data.VHD(148): signal "var1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file cont.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cont
Info: Elaborating entity "cont" for hierarchy "cont:inst1"
Info: Elaborating entity "lpm_counter" for hierarchy "cont:inst1|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "cont:inst1|lpm_counter:lpm_counter_component"
Info: Instantiated megafunction "cont:inst1|lpm_counter:lpm_counter_component" with the following parameter:
    Info: Parameter "lpm_direction" = "UP"
    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
    Info: Parameter "lpm_type" = "LPM_COUNTER"
    Info: Parameter "lpm_width" = "16"
Info: Found 1 design units, including 1 entities, in source file db/cntr_2si.tdf
    Info: Found entity 1: cntr_2si
Info: Elaborating entity "cntr_2si" for hierarchy "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated"
Info: Elaborating entity "BO" for hierarchy "BO:inst8"
Warning (10492): VHDL Process Statement warning at BO.vhd(205): signal "ng" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at BO.vhd(228): signal "var4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at BO.vhd(242): signal "var3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at BO.vhd(256): signal "var2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at BO.vhd(270): signal "var1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at BO.vhd(195): inferring latch(es) for signal or variable "var4", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "var4[0]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[1]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[2]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[3]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[4]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[5]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[6]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[7]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[8]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[9]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[10]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[11]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[12]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[13]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[14]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[15]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[16]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[17]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[18]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[19]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[20]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[21]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[22]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[23]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[24]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[25]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[26]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[27]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[28]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[29]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[30]" at BO.vhd(195)
Info (10041): Inferred latch for "var4[31]" at BO.vhd(195)
Warning: Port "M[6]" does not exist in entity definition of "lcdm_data".  The port's range differs between the entity definition and its actual instantiation, "lcdm_data:inst7".
Info: Inferred 5 megafunctions from design logic
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "lcdm_data:inst7|Div1"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "lcdm_data:inst7|Mod0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "lcdm_data:inst7|Mod1"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "lcdm_data:inst7|Div0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "lcdm_data:inst7|Mod2"
Info: Elaborated megafunction instantiation "lcdm_data:inst7|lpm_divide:Div1"
Info: Instantiated megafunction "lcdm_data:inst7|lpm_divide:Div1" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "11"
    Info: Parameter "LPM_WIDTHD" = "8"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ohm.tdf
    Info: Found entity 1: lpm_divide_ohm
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_plh.tdf
    Info: Found entity 1: sign_div_unsign_plh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_t5f.tdf
    Info: Found entity 1: alt_u_div_t5f
Info: Found 1 design units, including 1 entities, in source file db/add_sub_unc.tdf
    Info: Found entity 1: add_sub_unc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_vnc.tdf
    Info: Found entity 1: add_sub_vnc
Info: Elaborated megafunction instantiation "lcdm_data:inst7|lpm_divide:Mod0"
Info: Instantiated megafunction "lcdm_data:inst7|lpm_divide:Mod0" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "11"
    Info: Parameter "LPM_WIDTHD" = "11"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_5bm.tdf
    Info: Found entity 1: lpm_divide_5bm
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_3nh.tdf
    Info: Found entity 1: sign_div_unsign_3nh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_h8f.tdf
    Info: Found entity 1: alt_u_div_h8f
Info: Elaborated megafunction instantiation "lcdm_data:inst7|lpm_divide:Mod1"
Info: Instantiated megafunction "lcdm_data:inst7|lpm_divide:Mod1" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "7"
    Info: Parameter "LPM_WIDTHD" = "7"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_f8m.tdf
    Info: Found entity 1: lpm_divide_f8m
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_dkh.tdf
    Info: Found entity 1: sign_div_unsign_dkh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_53f.tdf
    Info: Found entity 1: alt_u_div_53f
Info: Elaborated megafunction instantiation "lcdm_data:inst7|lpm_divide:Div0"
Info: Instantiated megafunction "lcdm_data:inst7|lpm_divide:Div0" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "11"
    Info: Parameter "LPM_WIDTHD" = "11"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_2jm.tdf
    Info: Found entity 1: lpm_divide_2jm
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "rw" is stuck at GND
    Warning (13410): Pin "LCD_N" is stuck at GND
    Warning (13410): Pin "LCD_P" is stuck at VCC
    Warning (13410): Pin "sel[3]" is stuck at GND
    Warning (13410): Pin "sel[2]" is stuck at GND
    Warning (13410): Pin "sel[1]" is stuck at GND
    Warning (13410): Pin "sel[0]" is stuck at GND
Info: Timing-Driven Synthesis is running
Info: 10 registers lost all their fanouts during netlist optimizations. The first 10 are displayed below.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[15]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[14]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[13]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[12]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[11]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[10]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[9]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[8]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[7]" lost all its fanouts during netlist optimizations.
    Info: Register "cont:inst1|lpm_counter:lpm_counter_component|cntr_2si:auto_generated|counter_reg_bit[6]" lost all its fanouts during netlist optimizations.
Info: Found the following redundant logic cells in design
    Info (17048): Logic cell "lcdm_data:inst7|lpm_divide:Mod0|lpm_divide_5bm:auto_generated|sign_div_unsign_3nh:divider|alt_u_div_h8f:divider|add_sub_10_result_int[0]~22"
    Info (17048): Logic cell "CLK_DIV:inst|U9"
Info: Generating hard_block partition "hard_block:auto_generated_inst"
Info: Implemented 827 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 26 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 798 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings
    Info: Peak virtual memory: 289 megabytes
    Info: Processing ended: Wed Jun 20 11:04:06 2012
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:05


