Xilinx Design Summary

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	79	7,168	1%
Number used as Flip Flops	67
Number used as Latches	12
Number of 4 input LUTs	187	7,168	2%
Logic Distribution
Number of occupied Slices	142	3,584	3%
Number of Slices containing only related logic	142	142	100%
Number of Slices containing unrelated logic	0	142	0%
Total Number 4 input LUTs	235	7,168	3%
Number used as logic	187
Number used as a route-thru	16
Number used for Dual Port RAMs	32
Number of bonded IOBs	16	141	11%
IOB Flip Flops	11
Number of GCLKs	3	8	37%
Total equivalent gate count for design	4,049
Additional JTAG gate count for IOBs	768

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met