TimeQuest Timing Analyzer report for NOS031
Sat Feb 06 01:11:18 2016
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'CLK_REF'
 14. Slow 1200mV 85C Model Setup: 'CLK_BRD'
 15. Slow 1200mV 85C Model Setup: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 16. Slow 1200mV 85C Model Setup: 'JTAG_NEXUS_TCK'
 17. Slow 1200mV 85C Model Hold: 'CLK_REF'
 18. Slow 1200mV 85C Model Hold: 'CLK_BRD'
 19. Slow 1200mV 85C Model Hold: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 20. Slow 1200mV 85C Model Hold: 'JTAG_NEXUS_TCK'
 21. Slow 1200mV 85C Model Recovery: 'JTAG_NEXUS_TCK'
 22. Slow 1200mV 85C Model Recovery: 'CLK_REF'
 23. Slow 1200mV 85C Model Removal: 'JTAG_NEXUS_TCK'
 24. Slow 1200mV 85C Model Removal: 'CLK_REF'
 25. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_REF'
 26. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_BRD'
 27. Slow 1200mV 85C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
 28. Slow 1200mV 85C Model Minimum Pulse Width: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 29. Setup Times
 30. Hold Times
 31. Clock to Output Times
 32. Minimum Clock to Output Times
 33. Output Enable Times
 34. Minimum Output Enable Times
 35. Output Disable Times
 36. Minimum Output Disable Times
 37. Slow 1200mV 85C Model Metastability Report
 38. Slow 1200mV 0C Model Fmax Summary
 39. Slow 1200mV 0C Model Setup Summary
 40. Slow 1200mV 0C Model Hold Summary
 41. Slow 1200mV 0C Model Recovery Summary
 42. Slow 1200mV 0C Model Removal Summary
 43. Slow 1200mV 0C Model Minimum Pulse Width Summary
 44. Slow 1200mV 0C Model Setup: 'CLK_REF'
 45. Slow 1200mV 0C Model Setup: 'CLK_BRD'
 46. Slow 1200mV 0C Model Setup: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 47. Slow 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'
 48. Slow 1200mV 0C Model Hold: 'CLK_REF'
 49. Slow 1200mV 0C Model Hold: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 50. Slow 1200mV 0C Model Hold: 'CLK_BRD'
 51. Slow 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'
 52. Slow 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'
 53. Slow 1200mV 0C Model Recovery: 'CLK_REF'
 54. Slow 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'
 55. Slow 1200mV 0C Model Removal: 'CLK_REF'
 56. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_REF'
 57. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'
 58. Slow 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
 59. Slow 1200mV 0C Model Minimum Pulse Width: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 60. Setup Times
 61. Hold Times
 62. Clock to Output Times
 63. Minimum Clock to Output Times
 64. Output Enable Times
 65. Minimum Output Enable Times
 66. Output Disable Times
 67. Minimum Output Disable Times
 68. Slow 1200mV 0C Model Metastability Report
 69. Fast 1200mV 0C Model Setup Summary
 70. Fast 1200mV 0C Model Hold Summary
 71. Fast 1200mV 0C Model Recovery Summary
 72. Fast 1200mV 0C Model Removal Summary
 73. Fast 1200mV 0C Model Minimum Pulse Width Summary
 74. Fast 1200mV 0C Model Setup: 'CLK_REF'
 75. Fast 1200mV 0C Model Setup: 'CLK_BRD'
 76. Fast 1200mV 0C Model Setup: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 77. Fast 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'
 78. Fast 1200mV 0C Model Hold: 'CLK_REF'
 79. Fast 1200mV 0C Model Hold: 'CLK_BRD'
 80. Fast 1200mV 0C Model Hold: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 81. Fast 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'
 82. Fast 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'
 83. Fast 1200mV 0C Model Recovery: 'CLK_REF'
 84. Fast 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'
 85. Fast 1200mV 0C Model Removal: 'CLK_REF'
 86. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_REF'
 87. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'
 88. Fast 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
 89. Fast 1200mV 0C Model Minimum Pulse Width: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'
 90. Setup Times
 91. Hold Times
 92. Clock to Output Times
 93. Minimum Clock to Output Times
 94. Output Enable Times
 95. Minimum Output Enable Times
 96. Output Disable Times
 97. Minimum Output Disable Times
 98. Fast 1200mV 0C Model Metastability Report
 99. Multicorner Timing Analysis Summary
100. Setup Times
101. Hold Times
102. Clock to Output Times
103. Minimum Clock to Output Times
104. Board Trace Model Assignments
105. Input Transition Times
106. Slow Corner Signal Integrity Metrics
107. Fast Corner Signal Integrity Metrics
108. Setup Transfers
109. Hold Transfers
110. Recovery Transfers
111. Removal Transfers
112. Report TCCS
113. Report RSKM
114. Unconstrained Paths
115. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; NOS031                                                            ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C40F780C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+----------------------------------------------------+
; SDC File List                                      ;
+----------------+--------+--------------------------+
; SDC File Path  ; Status ; Read at                  ;
+----------------+--------+--------------------------+
; NOS031_sta.sdc ; OK     ; Sat Feb 06 01:10:55 2016 ;
+----------------+--------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------------------------------------------------------------------------+
; Clock Name                                                                                                 ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                                                                                        ;
+------------------------------------------------------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------------------------------------------------------------------------+
; CLK_BRD                                                                                                    ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK_BRD }                                                                                                    ;
; CLK_REF                                                                                                    ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK_REF }                                                                                                    ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] } ;
; JTAG_NEXUS_TCK                                                                                             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { JTAG_NEXUS_TCK }                                                                                             ;
+------------------------------------------------------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                              ;
+-----------+-----------------+------------------------------------------------------------------------------------------------------------+------+
; Fmax      ; Restricted Fmax ; Clock Name                                                                                                 ; Note ;
+-----------+-----------------+------------------------------------------------------------------------------------------------------------+------+
; 31.53 MHz ; 31.53 MHz       ; CLK_REF                                                                                                    ;      ;
; 45.54 MHz ; 45.54 MHz       ; CLK_BRD                                                                                                    ;      ;
; 80.35 MHz ; 80.35 MHz       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;      ;
; 98.74 MHz ; 98.74 MHz       ; JTAG_NEXUS_TCK                                                                                             ;      ;
+-----------+-----------------+------------------------------------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                                                  ;
+------------------------------------------------------------------------------------------------------------+---------+---------------+
; Clock                                                                                                      ; Slack   ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+---------+---------------+
; CLK_REF                                                                                                    ; -20.091 ; -2027.864     ;
; CLK_BRD                                                                                                    ; -17.494 ; -19184.186    ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; -11.445 ; -249.110      ;
; JTAG_NEXUS_TCK                                                                                             ; -6.938  ; -4774.992     ;
+------------------------------------------------------------------------------------------------------------+---------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                                                  ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; CLK_REF                                                                                                    ; -1.575 ; -30.425       ;
; CLK_BRD                                                                                                    ; 0.147  ; 0.000         ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.178  ; 0.000         ;
; JTAG_NEXUS_TCK                                                                                             ; 0.352  ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------+
; Slow 1200mV 85C Model Recovery Summary  ;
+----------------+--------+---------------+
; Clock          ; Slack  ; End Point TNS ;
+----------------+--------+---------------+
; JTAG_NEXUS_TCK ; -3.170 ; -135.590      ;
; CLK_REF        ; -2.643 ; -84.479       ;
+----------------+--------+---------------+


+----------------------------------------+
; Slow 1200mV 85C Model Removal Summary  ;
+----------------+-------+---------------+
; Clock          ; Slack ; End Point TNS ;
+----------------+-------+---------------+
; JTAG_NEXUS_TCK ; 1.387 ; 0.000         ;
; CLK_REF        ; 1.805 ; 0.000         ;
+----------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                                                   ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; CLK_REF                                                                                                    ; -7.360 ; -2165.557     ;
; CLK_BRD                                                                                                    ; -4.000 ; -3066.467     ;
; JTAG_NEXUS_TCK                                                                                             ; -3.000 ; -1708.589     ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; -1.487 ; -83.272       ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLK_REF'                                                                                                                                                                                                                                                                                      ;
+---------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                        ; To Node                                                                                                ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -20.091 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.894    ; 5.198      ;
; -20.091 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.894    ; 5.198      ;
; -19.493 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.107    ; 5.387      ;
; -19.493 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.107    ; 5.387      ;
; -18.612 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.859     ; 16.754     ;
; -18.612 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.859     ; 16.754     ;
; -18.603 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -13.340    ; 6.264      ;
; -18.603 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -13.340    ; 6.264      ;
; -18.483 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.463     ; 11.021     ;
; -18.483 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.463     ; 11.021     ;
; -18.428 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -13.340    ; 6.089      ;
; -18.428 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -13.340    ; 6.089      ;
; -18.371 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.859     ; 16.513     ;
; -18.371 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.859     ; 16.513     ;
; -17.884 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.284     ; 13.601     ;
; -17.884 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.284     ; 13.601     ;
; -17.807 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.780     ; 18.008     ;
; -17.807 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.780     ; 18.008     ;
; -17.680 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.901    ; 2.780      ;
; -17.668 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.284     ; 13.385     ;
; -17.668 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.284     ; 13.385     ;
; -17.577 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.259      ; 18.837     ;
; -17.577 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.259      ; 18.837     ;
; -17.471 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.660     ; 14.812     ;
; -17.471 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.660     ; 14.812     ;
; -17.468 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.438     ; 12.031     ;
; -17.468 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.438     ; 12.031     ;
; -17.458 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.999     ; 9.460      ;
; -17.458 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.999     ; 9.460      ;
; -17.449 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.898    ; 6.552      ;
; -17.449 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.898    ; 6.552      ;
; -17.431 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.259      ; 18.691     ;
; -17.431 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.259      ; 18.691     ;
; -17.401 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.635    ; 7.767      ;
; -17.401 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.635    ; 7.767      ;
; -17.382 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.133     ; 17.250     ;
; -17.382 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.133     ; 17.250     ;
; -17.363 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.302     ; 10.062     ;
; -17.363 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.302     ; 10.062     ;
; -17.289 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.898    ; 6.392      ;
; -17.289 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.898    ; 6.392      ;
; -17.269 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.635    ; 7.635      ;
; -17.269 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.635    ; 7.635      ;
; -17.240 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.133     ; 17.108     ;
; -17.240 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.133     ; 17.108     ;
; -17.171 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.999     ; 9.173      ;
; -17.171 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.660     ; 14.512     ;
; -17.171 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.999     ; 9.173      ;
; -17.171 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.660     ; 14.512     ;
; -17.170 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.438     ; 11.733     ;
; -17.170 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.438     ; 11.733     ;
; -17.082 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.114    ; 2.969      ;
; -17.042 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|un1_g3[0]                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.574     ; 10.469     ;
; -17.042 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|un1_g3[0]                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.574     ; 10.469     ;
; -16.516 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|un1_sig_B_x[0]                                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.786     ; 9.731      ;
; -16.516 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|un1_sig_B_x[0]                                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.786     ; 9.731      ;
; -16.201 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.866     ; 14.336     ;
; -16.192 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -13.347    ; 3.846      ;
; -16.072 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.470     ; 8.603      ;
; -16.026 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.780     ; 16.227     ;
; -16.026 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.780     ; 16.227     ;
; -16.017 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -13.347    ; 3.671      ;
; -15.960 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.866     ; 14.095     ;
; -15.796 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 3.010      ; 19.807     ;
; -15.796 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 3.010      ; 19.807     ;
; -15.473 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.291     ; 11.183     ;
; -15.396 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.787     ; 15.590     ;
; -15.358 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 0.500        ; 3.010      ; 18.869     ;
; -15.358 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 0.500        ; 3.010      ; 18.869     ;
; -15.257 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.291     ; 10.967     ;
; -15.166 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.252      ; 16.419     ;
; -15.139 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.780     ; 15.340     ;
; -15.139 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.780     ; 15.340     ;
; -15.060 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.667     ; 12.394     ;
; -15.057 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.445     ; 9.613      ;
; -15.047 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -9.006     ; 7.042      ;
; -15.038 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.905    ; 4.134      ;
; -15.020 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.252      ; 16.273     ;
; -14.990 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.642    ; 5.349      ;
; -14.971 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.140     ; 14.832     ;
; -14.962 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.088     ; 15.855     ;
; -14.952 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.309     ; 7.644      ;
; -14.878 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.905    ; 3.974      ;
; -14.858 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.642    ; 5.217      ;
; -14.829 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.140     ; 14.690     ;
; -14.760 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -9.006     ; 6.755      ;
; -14.760 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.667     ; 12.094     ;
; -14.759 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.445     ; 9.315      ;
; -14.631 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|un1_g3[0]                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.581     ; 8.051      ;
; -14.105 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|un1_sig_B_x[0]                                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.793     ; 7.313      ;
; -13.719 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.107     ; 14.613     ;
; -13.719 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.107     ; 14.613     ;
; -13.615 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.787     ; 13.809     ;
; -13.436 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_18__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.088     ; 14.349     ;
; -13.436 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_18__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.088     ; 14.349     ;
; -13.408 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_15__Z                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.081     ; 14.328     ;
; -13.388 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_4__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.107     ; 14.282     ;
; -13.388 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_4__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.107     ; 14.282     ;
; -13.385 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; 3.003      ; 17.389     ;
; -13.375 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_1__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.106     ; 14.270     ;
+---------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                             ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                                                                ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -17.494 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.061      ; 18.556     ;
; -17.478 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.060      ; 18.539     ;
; -17.470 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.063      ; 18.534     ;
; -17.305 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.043      ; 18.349     ;
; -17.296 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.055      ; 18.352     ;
; -17.271 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.373     ; 17.899     ;
; -17.264 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.027      ; 18.292     ;
; -17.255 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.039      ; 18.295     ;
; -17.246 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.385     ; 17.862     ;
; -17.228 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.848     ;
; -17.226 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.375     ; 17.852     ;
; -17.201 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.379     ; 17.823     ;
; -17.194 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.374     ; 17.821     ;
; -17.188 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.050      ; 18.239     ;
; -17.187 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.397     ; 17.791     ;
; -17.175 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.062      ; 18.238     ;
; -17.147 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.053      ; 18.201     ;
; -17.142 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.374     ; 17.769     ;
; -17.110 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.374     ; 17.737     ;
; -17.106 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.037      ; 18.144     ;
; -17.060 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.059      ; 18.120     ;
; -17.052 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.056      ; 18.109     ;
; -17.040 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.072      ; 18.113     ;
; -17.036 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.659     ;
; -17.032 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.075      ; 18.108     ;
; -17.028 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.648     ;
; -17.010 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.030      ; 18.041     ;
; -17.003 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.385     ; 17.619     ;
; -17.001 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.042      ; 18.044     ;
; -16.987 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.397     ; 17.591     ;
; -16.968 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.058      ; 18.027     ;
; -16.962 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.562     ;
; -16.961 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.050      ; 18.012     ;
; -16.944 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.565     ;
; -16.933 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.394     ; 17.540     ;
; -16.931 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.373     ; 17.559     ;
; -16.922 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.543     ;
; -16.922 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.409     ; 17.514     ;
; -16.916 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.060      ; 17.977     ;
; -16.912 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.533     ;
; -16.903 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.508     ;
; -16.882 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.505     ;
; -16.881 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.486     ;
; -16.871 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.476     ;
; -16.852 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.040      ; 17.893     ;
; -16.852 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_30   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.409     ; 17.444     ;
; -16.839 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.049      ; 17.889     ;
; -16.833 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.361     ; 17.473     ;
; -16.829 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.449     ;
; -16.828 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.436     ;
; -16.805 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.373     ; 17.433     ;
; -16.805 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.044      ; 17.850     ;
; -16.797 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.041      ; 17.839     ;
; -16.797 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.047      ; 17.845     ;
; -16.794 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.375     ; 17.420     ;
; -16.788 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.053      ; 17.842     ;
; -16.786 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.059      ; 17.846     ;
; -16.782 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.056      ; 17.839     ;
; -16.782 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.377     ; 17.406     ;
; -16.775 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.043      ; 17.819     ;
; -16.775 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_30   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.385     ; 17.391     ;
; -16.772 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.056      ; 17.829     ;
; -16.769 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.052      ; 17.822     ;
; -16.766 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.379     ; 17.388     ;
; -16.764 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.398     ; 17.367     ;
; -16.763 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.412     ; 17.352     ;
; -16.761 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.374     ; 17.388     ;
; -16.760 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.062      ; 17.823     ;
; -16.756 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.362     ; 17.395     ;
; -16.755 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_19   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.387     ; 17.369     ;
; -16.750 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.062      ; 17.813     ;
; -16.748 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.046      ; 17.795     ;
; -16.740 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.059      ; 17.800     ;
; -16.737 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.074      ; 17.812     ;
; -16.734 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.027      ; 17.762     ;
; -16.733 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.394     ; 17.340     ;
; -16.731 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.040      ; 17.772     ;
; -16.728 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.036      ; 17.765     ;
; -16.722 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.428     ; 17.295     ;
; -16.720 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.383     ; 17.338     ;
; -16.717 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_29   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.384     ; 17.334     ;
; -16.714 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_19   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.403     ; 17.312     ;
; -16.711 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_1 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.391     ; 17.321     ;
; -16.709 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.399     ; 17.311     ;
; -16.708 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.398     ; 17.311     ;
; -16.705 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.328     ;
; -16.700 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.067      ; 17.768     ;
; -16.693 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.388     ; 17.306     ;
; -16.691 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.055      ; 17.747     ;
; -16.675 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.382     ; 17.294     ;
; -16.672 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.362     ; 17.311     ;
; -16.668 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.053      ; 17.722     ;
; -16.652 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.249     ;
; -16.649 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.257     ;
; -16.639 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.051      ; 17.691     ;
; -16.630 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.386     ; 17.245     ;
; -16.627 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.235     ;
; -16.627 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.037      ; 17.665     ;
; -16.622 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.071      ; 17.694     ;
; -16.617 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.225     ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                            ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                               ; To Node                                                                       ; Launch Clock                                                                                               ; Latch Clock                                                                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; -11.445 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.834     ;
; -11.445 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.834     ;
; -11.445 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.834     ;
; -11.445 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.834     ;
; -11.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 12.320     ;
; -11.389 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 12.307     ;
; -11.128 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.516     ;
; -11.128 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.516     ;
; -11.128 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.516     ;
; -11.128 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.516     ;
; -11.085 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 12.002     ;
; -11.072 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.989     ;
; -10.900 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.288     ;
; -10.900 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.288     ;
; -10.900 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.288     ;
; -10.900 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.288     ;
; -10.883 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.272     ;
; -10.883 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.272     ;
; -10.883 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.272     ;
; -10.883 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.272     ;
; -10.864 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.252     ;
; -10.864 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.252     ;
; -10.864 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.252     ;
; -10.864 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.252     ;
; -10.857 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.774     ;
; -10.844 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.761     ;
; -10.840 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.758     ;
; -10.827 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.215     ;
; -10.827 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.215     ;
; -10.827 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.215     ;
; -10.827 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.215     ;
; -10.827 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.745     ;
; -10.825 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.213     ;
; -10.825 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.213     ;
; -10.825 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.213     ;
; -10.825 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.213     ;
; -10.821 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.738     ;
; -10.812 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.200     ;
; -10.812 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.200     ;
; -10.812 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.200     ;
; -10.812 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.200     ;
; -10.808 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.725     ;
; -10.784 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.701     ;
; -10.782 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.699     ;
; -10.771 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.688     ;
; -10.769 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.686     ;
; -10.769 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.686     ;
; -10.756 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.673     ;
; -10.751 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.140     ;
; -10.751 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.140     ;
; -10.751 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.140     ;
; -10.751 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.140     ;
; -10.725 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.386      ; 12.112     ;
; -10.725 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.386      ; 12.112     ;
; -10.725 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.386      ; 12.112     ;
; -10.725 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.386      ; 12.112     ;
; -10.716 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.104     ;
; -10.716 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.104     ;
; -10.716 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.104     ;
; -10.716 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.104     ;
; -10.708 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.626     ;
; -10.695 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.613     ;
; -10.682 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.085     ; 11.598     ;
; -10.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.066     ;
; -10.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.066     ;
; -10.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.066     ;
; -10.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.066     ;
; -10.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.066     ;
; -10.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.066     ;
; -10.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.066     ;
; -10.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.066     ;
; -10.673 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.590     ;
; -10.669 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.085     ; 11.585     ;
; -10.665 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.054     ;
; -10.665 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.054     ;
; -10.665 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.054     ;
; -10.665 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.054     ;
; -10.660 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.577     ;
; -10.643 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.031     ;
; -10.643 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.031     ;
; -10.643 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.031     ;
; -10.643 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 12.031     ;
; -10.634 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.552     ;
; -10.634 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.552     ;
; -10.631 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.020     ;
; -10.631 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.020     ;
; -10.631 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.020     ;
; -10.631 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.388      ; 12.020     ;
; -10.622 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.540     ;
; -10.621 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.539     ;
; -10.621 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.539     ;
; -10.609 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.527     ;
; -10.600 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.517     ;
; -10.592 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 11.980     ;
; -10.592 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 11.980     ;
; -10.592 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 11.980     ;
; -10.592 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.387      ; 11.980     ;
; -10.588 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.506     ;
; -10.587 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.084     ; 11.504     ;
; -10.575 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.083     ; 11.493     ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                      ; To Node                                                                                                                                                                        ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -6.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.087     ; 7.852      ;
; -6.929 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.087     ; 7.843      ;
; -6.921 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.127     ; 7.795      ;
; -6.912 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.131     ; 7.782      ;
; -6.906 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.811      ;
; -6.897 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.802      ;
; -6.856 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 7.764      ;
; -6.847 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 7.755      ;
; -6.841 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.763      ;
; -6.813 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 7.728      ;
; -6.804 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 7.719      ;
; -6.799 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.127     ; 7.673      ;
; -6.799 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.709      ;
; -6.797 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 7.705      ;
; -6.790 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.131     ; 7.660      ;
; -6.790 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.700      ;
; -6.778 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 7.684      ;
; -6.772 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.677      ;
; -6.736 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.087     ; 7.650      ;
; -6.728 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.650      ;
; -6.717 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.087     ; 7.631      ;
; -6.691 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.127     ; 7.565      ;
; -6.685 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.590      ;
; -6.684 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 7.592      ;
; -6.682 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.131     ; 7.552      ;
; -6.665 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 7.571      ;
; -6.663 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 7.599      ;
; -6.659 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.564      ;
; -6.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.571      ;
; -6.640 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.087     ; 7.554      ;
; -6.635 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 7.543      ;
; -6.623 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.087     ; 7.537      ;
; -6.619 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.541      ;
; -6.608 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.513      ;
; -6.605 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 7.513      ;
; -6.600 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 7.520      ;
; -6.594 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.513      ;
; -6.592 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 7.507      ;
; -6.586 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 7.492      ;
; -6.580 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.485      ;
; -6.578 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.488      ;
; -6.558 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 7.466      ;
; -6.558 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 7.486      ;
; -6.544 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.087     ; 7.458      ;
; -6.543 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.453      ;
; -6.543 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.453      ;
; -6.539 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.449      ;
; -6.527 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.127     ; 7.401      ;
; -6.518 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.131     ; 7.388      ;
; -6.515 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 7.430      ;
; -6.501 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.411      ;
; -6.479 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.401      ;
; -6.463 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.373      ;
; -6.457 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.362      ;
; -6.435 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 7.343      ;
; -6.430 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.340      ;
; -6.430 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.340      ;
; -6.417 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.327      ;
; -6.416 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 7.322      ;
; -6.410 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.315      ;
; -6.374 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.087     ; 7.288      ;
; -6.365 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.289      ;
; -6.365 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.289      ;
; -6.356 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.261      ;
; -6.351 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.261      ;
; -6.351 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.261      ;
; -6.344 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.249      ;
; -6.341 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.251      ;
; -6.309 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.219      ;
; -6.279 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.198      ;
; -6.265 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.170      ;
; -6.243 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.148      ;
; -6.233 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.143      ;
; -6.181 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.091      ;
; -6.181 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.091      ;
; -6.178 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.097      ;
; -6.164 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.069      ;
; -6.145 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.055      ;
; -6.125 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_3__Z                   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 7.035      ;
; -6.125 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.125     ; 7.001      ;
; -6.116 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.129     ; 6.988      ;
; -6.095 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.000      ;
; -6.069 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 6.979      ;
; -6.016 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]    ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.581     ; 6.436      ;
; -6.013 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 6.941      ;
; -6.003 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_3__Z                   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 6.913      ;
; -5.994 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 6.899      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_31__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_30__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_29__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_28__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_27__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_26__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_25__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_24__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_23__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_22__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_21__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_20__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
; -5.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_19__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 6.876      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLK_REF'                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                                                                                               ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.575 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.355     ; 16.032     ;
; -1.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.356     ; 16.141     ;
; -1.408 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.355     ; 16.199     ;
; -1.376 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.229     ;
; -1.287 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_20                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.355     ; 16.320     ;
; -1.269 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.336     ;
; -1.214 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_28                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.348     ; 16.386     ;
; -1.133 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.472     ;
; -1.123 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.348     ; 16.477     ;
; -1.075 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.348     ; 16.525     ;
; -1.071 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.355     ; 16.536     ;
; -1.015 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.348     ; 16.585     ;
; -0.986 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.352     ; 16.618     ;
; -0.924 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.352     ; 16.680     ;
; -0.871 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.734     ;
; -0.870 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.352     ; 16.734     ;
; -0.849 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.756     ;
; -0.823 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.348     ; 16.777     ;
; -0.792 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.348     ; 16.808     ;
; -0.784 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.355     ; 16.823     ;
; -0.770 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_6                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.835     ;
; -0.742 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.352     ; 16.862     ;
; -0.741 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_7                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.864     ;
; -0.718 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.356     ; 16.890     ;
; -0.710 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_4                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.895     ;
; -0.662 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.355     ; 16.945     ;
; -0.641 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 16.964     ;
; -0.637 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.356     ; 16.971     ;
; -0.612 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.356     ; 16.996     ;
; -0.599 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.348     ; 17.001     ;
; -0.582 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.353     ; 17.023     ;
; -0.503 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 17.356     ; 17.105     ;
; -0.479 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 2.668      ; 2.401      ;
; -0.117 ; JTAG_NEXUS_TCK                                                                                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|tck1_Z                                                                                         ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 3.131      ; 3.266      ;
; 0.004  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_16__Z                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; 0.000        ; 3.126      ; 3.633      ;
; 0.005  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_16__Z                                                ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; 0.000        ; 3.126      ; 3.634      ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.263  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.918     ; 17.433     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.324  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.914     ; 17.490     ;
; 0.390  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_16__Z                                                ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; -0.500       ; 3.126      ; 3.519      ;
; 0.391  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_16__Z                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; -0.500       ; 3.126      ; 3.520      ;
; 0.423  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.934      ; 1.569      ;
; 0.443  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z                                                               ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.103      ; 0.758      ;
; 0.452  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.082      ; 0.746      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.497  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.758      ;
; 0.498  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_16__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_16__Z                                                 ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.083      ; 0.793      ;
; 0.499  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_20__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_20__Z                                                 ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.083      ; 0.794      ;
; 0.510  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 10.527     ; 11.289     ;
; 0.519  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_C                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.055      ; 0.786      ;
; 0.523  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_6__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_6__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.083      ; 0.818      ;
; 0.534  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_C ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.056      ; 0.802      ;
; 0.541  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z                                                              ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a12~porta_datain_reg0                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.527      ; 1.322      ;
; 0.559  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.055      ; 0.826      ;
; 0.580  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z                                                              ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a12~porta_datain_reg0                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.527      ; 1.361      ;
; 0.601  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z                                                              ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a12~porta_datain_reg0                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.527      ; 1.382      ;
; 0.602  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_C                                                    ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 10.527     ; 11.381     ;
; 0.636  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|rst_Z                                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z                                                                 ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.530      ; 1.378      ;
; 0.654  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_DUMP:U_DUMP|startcap_s_Z                                                             ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_DUMP:U_DUMP|dstate_0__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.083      ; 0.949      ;
; 0.655  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z                                                               ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a8~porta_datain_reg0                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.481      ; 1.390      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                     ; To Node                                                                                                                                                                                                        ; Launch Clock                                                                                               ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.147 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                                                                     ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_BRD     ; 0.000        ; 3.128      ; 3.778      ;
; 0.416 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                                                                     ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_BRD     ; -0.500       ; 3.128      ; 3.547      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.431 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.103      ; 0.746      ;
; 0.450 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.084      ; 0.746      ;
; 0.450 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.084      ; 0.746      ;
; 0.450 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.084      ; 0.746      ;
; 0.450 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.084      ; 0.746      ;
; 0.450 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.084      ; 0.746      ;
; 0.450 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.084      ; 0.746      ;
; 0.450 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.084      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                          ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                              ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                   ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                                                                    ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                             ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                               ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]                                                   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]                                                                                                    ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                    ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.452 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.453 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.081      ; 0.746      ;
; 0.465 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.081      ; 0.758      ;
; 0.492 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|Reg_DoDivide_Z                                                                              ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_6__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.786      ;
; 0.505 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                      ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.084      ; 0.801      ;
; 0.508 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|Reg_DoDivide_Z                                                                              ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_3__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.802      ;
; 0.508 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF0                                                                                      ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF1                                                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.803      ;
; 0.509 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.804      ;
; 0.510 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_11                                                     ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.398      ; 1.162      ;
; 0.515 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.810      ;
; 0.519 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.081      ; 0.812      ;
; 0.520 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.081      ; 0.813      ;
; 0.521 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_2                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.398      ; 1.173      ;
; 0.522 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.817      ;
; 0.523 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_16__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_15__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.818      ;
; 0.524 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_1                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_1                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.819      ;
; 0.524 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_5                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_5                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.819      ;
; 0.524 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.819      ;
; 0.524 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_27__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.818      ;
; 0.524 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                         ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                                                                          ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.819      ;
; 0.525 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                              ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[2]                                                                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.820      ;
; 0.525 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.820      ;
; 0.525 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.819      ;
; 0.525 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_23__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.819      ;
; 0.525 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_23__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.819      ;
; 0.526 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_21__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.820      ;
; 0.526 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_15__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_14__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.821      ;
; 0.527 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.822      ;
; 0.527 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_29__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.082      ; 0.821      ;
; 0.536 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_7                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.398      ; 1.188      ;
; 0.542 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.402      ; 1.198      ;
; 0.542 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.398      ; 1.194      ;
; 0.543 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_1                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|RxSetFF0                                                                                                                                               ; JTAG_NEXUS_TCK                                                                                             ; CLK_BRD     ; 0.000        ; 0.023      ; 0.818      ;
; 0.548 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead                                                         ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select1_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.843      ;
; 0.549 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_DoRegWrite                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|DoRegWrite_WB                                                                                                        ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.844      ;
; 0.550 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead                                                         ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select0_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.845      ;
; 0.551 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_2                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_2                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.846      ;
; 0.554 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_6                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.398      ; 1.206      ;
; 0.569 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.402      ; 1.225      ;
; 0.573 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.397      ; 1.224      ;
; 0.576 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.394      ; 1.224      ;
; 0.580 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.402      ; 1.236      ;
; 0.583 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.397      ; 1.234      ;
; 0.590 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.398      ; 1.242      ;
; 0.599 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_8                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.398      ; 1.251      ;
; 0.625 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.397      ; 1.276      ;
; 0.625 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff2_Z           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_Z                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.920      ;
; 0.626 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.921      ;
; 0.637 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.394      ; 1.285      ;
; 0.649 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_13                                                     ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.398      ; 1.301      ;
; 0.667 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemWidth_0                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select0_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.962      ;
; 0.669 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemWidth_0                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select1_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.083      ; 0.964      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                                     ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                         ; To Node                                                                       ; Launch Clock                                                                                               ; Latch Clock                                                                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.178 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 1.610      ;
; 0.179 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 1.611      ;
; 0.264 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 1.695      ;
; 0.314 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 1.746      ;
; 0.426 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 1.858      ;
; 0.451 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]                                       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                      ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 0.746      ;
; 0.476 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.191      ; 1.909      ;
; 0.690 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.121      ;
; 0.692 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.123      ;
; 0.693 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.124      ;
; 0.694 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.125      ;
; 0.699 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 2.131      ;
; 0.741 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.055      ;
; 0.749 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.063      ;
; 0.764 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.078      ;
; 0.769 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.083      ;
; 0.819 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 2.251      ;
; 0.819 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.250      ;
; 0.835 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 1.795      ;
; 0.840 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 1.800      ;
; 0.841 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.272      ;
; 0.844 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.275      ;
; 0.847 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.278      ;
; 0.847 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.278      ;
; 0.848 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.279      ;
; 0.866 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.297      ;
; 0.871 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 1.831      ;
; 0.874 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 1.834      ;
; 0.879 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.310      ;
; 0.882 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.313      ;
; 0.885 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.316      ;
; 0.905 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.336      ;
; 0.952 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.383      ;
; 0.994 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.191      ; 2.427      ;
; 0.994 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.191      ; 2.427      ;
; 1.056 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.721      ; 2.019      ;
; 1.072 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 2.504      ;
; 1.072 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 2.504      ;
; 1.073 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 2.505      ;
; 1.074 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 2.506      ;
; 1.080 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.394      ;
; 1.082 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.719      ; 2.043      ;
; 1.092 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.406      ;
; 1.101 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.415      ;
; 1.106 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.720      ; 2.068      ;
; 1.108 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 2.540      ;
; 1.111 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.425      ;
; 1.118 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.432      ;
; 1.120 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.102      ; 1.434      ;
; 1.121 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.719      ; 2.082      ;
; 1.175 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.606      ;
; 1.207 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.638      ;
; 1.316 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.190      ; 2.748      ;
; 1.357 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.788      ;
; 1.374 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.721      ; 2.337      ;
; 1.376 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 2.807      ;
; 1.391 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.685      ;
; 1.408 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 2.368      ;
; 1.433 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 2.393      ;
; 1.435 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 2.395      ;
; 1.453 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 2.413      ;
; 1.483 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; -0.389     ; 1.306      ;
; 1.542 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.083      ; 1.837      ;
; 1.559 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.853      ;
; 1.563 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]                                       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.857      ;
; 1.565 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 2.525      ;
; 1.573 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]                                      ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.867      ;
; 1.582 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.189      ; 3.013      ;
; 1.653 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; -0.389     ; 1.476      ;
; 1.663 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.957      ;
; 1.675 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.969      ;
; 1.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.971      ;
; 1.678 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.972      ;
; 1.679 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.082      ; 1.973      ;
; 1.686 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 2.646      ;
; 1.764 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.718      ; 2.724      ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                         ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.352 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[2]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[2]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.793      ;
; 0.353 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[7]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.794      ;
; 0.353 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[5]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[5]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.794      ;
; 0.353 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[0]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg_0                                                                                                                                                                                   ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.794      ;
; 0.354 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[6]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[6]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.795      ;
; 0.354 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[4]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[4]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.795      ;
; 0.355 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[3]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[3]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.796      ;
; 0.356 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[1]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[1]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.797      ;
; 0.364 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[1]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.202      ; 0.818      ;
; 0.366 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[3]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.202      ; 0.820      ;
; 0.366 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                                                                                               ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.202      ; 0.820      ;
; 0.367 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z                                                                                                                                                                                                                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                                                                          ; CLK_REF        ; JTAG_NEXUS_TCK ; 0.000        ; 0.202      ; 0.821      ;
; 0.373 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.202      ; 0.827      ;
; 0.375 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[5]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.202      ; 0.829      ;
; 0.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.102      ; 0.746      ;
; 0.451 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.452 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.463 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.758      ;
; 0.464 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.758      ;
; 0.464 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.758      ;
; 0.464 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.758      ;
; 0.464 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.758      ;
; 0.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13                                                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.537      ; 1.216      ;
; 0.493 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0                                                                                                                                                                                                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                                                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.537      ; 1.242      ;
; 0.498 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[20]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[20]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[19]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[19]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[17]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[17]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_26__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_25__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_21__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_20__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_6__Z                                                                                                                                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_5__Z                                                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[28]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[28]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[27]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[27]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[22]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[22]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[12]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[12]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg_0                                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_23__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_22__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_14__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[29]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[28]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[11]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[10]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[10]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[9]                                                                                                                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_25|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_24|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.500 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[26]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[26]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[25]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[25]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[24]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[24]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[23]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[23]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[21]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[21]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[18]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[18]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[16]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[16]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[13]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[13]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[11]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[11]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[5]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[5]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[18]                                                                                                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[17]                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[4]                                                                                                                                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_30__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_29__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_24__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_23__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_12__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_1__Z                                                                                                                                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_0__Z                                                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_30|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_29|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_28|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_27|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_27|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_26|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_23|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_17|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.501 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[15]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[15]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.796      ;
; 0.501 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_28__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_27__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.796      ;
; 0.501 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[6]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[6]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.501 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[5]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[5]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.501 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[4]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[4]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.501 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[30]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.501 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[15]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[14]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.501 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[13]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[12]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.501 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg_0                                                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.501 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_19|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.501 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.796      ;
; 0.501 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_2|lpm_ff:ff1|dffs[0]                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.795      ;
; 0.502 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[4]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[4]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.797      ;
; 0.502 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[13]                                                                                                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[12]                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.796      ;
; 0.502 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[6]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.796      ;
; 0.502 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_19__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_18__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.797      ;
; 0.502 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[3]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.796      ;
; 0.502 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[2]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.796      ;
; 0.502 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_24|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_23|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.796      ;
; 0.507 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.802      ;
; 0.508 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_1__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.803      ;
; 0.508 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.803      ;
; 0.508 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|sh_reg_r_3__Z                                                                                                                                                                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|sh_reg_r_2__Z                                                                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.802      ;
; 0.508 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|sh_reg_r_6__Z                                                                                                                                                                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.802      ;
; 0.508 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_16|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.802      ;
; 0.509 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.804      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                        ; To Node                                                                                                                                                                 ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -3.170 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 4.143      ;
; -3.170 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 4.143      ;
; -3.132 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 4.104      ;
; -3.049 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.959      ;
; -3.049 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.959      ;
; -2.993 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.966      ;
; -2.993 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.966      ;
; -2.966 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.938      ;
; -2.963 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.936      ;
; -2.963 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.936      ;
; -2.960 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.870      ;
; -2.960 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.870      ;
; -2.950 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.923      ;
; -2.950 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.923      ;
; -2.929 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.839      ;
; -2.929 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.839      ;
; -2.925 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.897      ;
; -2.912 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.884      ;
; -2.897 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.856      ;
; -2.891 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.801      ;
; -2.891 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.801      ;
; -2.851 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.761      ;
; -2.851 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.761      ;
; -2.840 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.750      ;
; -2.840 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.750      ;
; -2.837 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.810      ;
; -2.837 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.810      ;
; -2.799 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.771      ;
; -2.771 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.681      ;
; -2.771 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.681      ;
; -2.750 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 3.683      ;
; -2.750 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 3.683      ;
; -2.747 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 3.680      ;
; -2.747 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 3.680      ;
; -2.738 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.711      ;
; -2.738 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.711      ;
; -2.731 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.641      ;
; -2.731 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 3.641      ;
; -2.723 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 3.655      ;
; -2.715 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.674      ;
; -2.711 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.683      ;
; -2.709 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 3.641      ;
; -2.690 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.649      ;
; -2.680 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.653      ;
; -2.680 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.008     ; 3.653      ;
; -2.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.636      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.615      ;
; -2.653 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.625      ;
; -2.653 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.625      ;
; -2.648 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.620      ;
; -2.626 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.010     ; 3.597      ;
; -2.614 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.427      ; 4.022      ;
; -2.570 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 3.503      ;
; -2.570 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 3.503      ;
; -2.564 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.523      ;
; -2.532 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 3.464      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.490 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.409      ;
; -2.474 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.393      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.474 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.433      ;
; -2.461 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.380      ;
; -2.449 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.408      ;
; -2.449 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.408      ;
; -2.449 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.408      ;
; -2.449 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.408      ;
; -2.449 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.408      ;
; -2.449 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.408      ;
; -2.449 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.408      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'CLK_REF'                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -2.643 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 3.423      ;
; -2.554 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 3.334      ;
; -2.500 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.206     ; 3.275      ;
; -2.485 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 3.265      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 3.225      ;
; -2.411 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.206     ; 3.186      ;
; -2.342 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.206     ; 3.117      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.303 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.578      ;
; -2.302 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.206     ; 3.077      ;
; -2.251 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.205     ; 3.027      ;
; -2.251 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.205     ; 3.027      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.489      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.202 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.979      ;
; -2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.205     ; 2.950      ;
; -2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.205     ; 2.950      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.170 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.948      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.145 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.420      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.918      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.112 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.890      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.105 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.294      ; 3.380      ;
; -2.093 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.205     ; 2.869      ;
; -2.093 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.205     ; 2.869      ;
; -2.053 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.205     ; 2.829      ;
; -2.053 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.205     ; 2.829      ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                                                     ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 1.387 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_8|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.682      ;
; 1.387 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_10|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.682      ;
; 1.387 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_9|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.682      ;
; 1.387 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_3|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.682      ;
; 1.387 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_2|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.682      ;
; 1.387 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_1|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.682      ;
; 1.404 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.697      ;
; 1.404 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.697      ;
; 1.404 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.697      ;
; 1.404 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.697      ;
; 1.648 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.072      ; 1.452      ;
; 1.648 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.072      ; 1.452      ;
; 1.648 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.072      ; 1.452      ;
; 1.648 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.072      ; 1.452      ;
; 1.657 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.955      ;
; 1.657 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_14|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.955      ;
; 1.657 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_15|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.955      ;
; 1.657 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_7|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.955      ;
; 1.657 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_6|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.955      ;
; 1.710 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_13|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.011      ;
; 1.710 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_12|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.011      ;
; 1.710 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_5|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.011      ;
; 1.710 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_4|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.089      ; 2.011      ;
; 1.713 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.091      ; 2.016      ;
; 1.713 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.091      ; 2.016      ;
; 1.713 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_17|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.091      ; 2.016      ;
; 1.713 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_0|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.091      ; 2.016      ;
; 1.856 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.072      ; 1.660      ;
; 1.856 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.072      ; 1.660      ;
; 1.856 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.072      ; 1.660      ;
; 1.856 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.072      ; 1.660      ;
; 1.891 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.071      ; 1.694      ;
; 1.891 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.071      ; 1.694      ;
; 1.891 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.071      ; 1.694      ;
; 1.891 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.071      ; 1.694      ;
; 2.217 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.551      ; 2.980      ;
; 2.308 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.551      ; 3.071      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.337 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.632      ;
; 2.377 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.667      ; 3.296      ;
; 2.399 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.668      ; 3.319      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.421 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 2.872      ;
; 2.427 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.718      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.432 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.727      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.443 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.895      ;
; 2.459 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.551      ; 3.222      ;
; 2.459 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.668      ; 3.379      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.200      ; 2.955      ;
; 2.509 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.551      ; 3.272      ;
; 2.512 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.668      ; 3.432      ;
; 2.526 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.079      ; 2.817      ;
; 2.553 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.848      ;
; 2.553 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.848      ;
; 2.553 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.848      ;
; 2.553 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.848      ;
; 2.553 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 2.848      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'CLK_REF'                                                                                                                                                                                                                            ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 1.805 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.464      ; 2.521      ;
; 1.831 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.506      ; 2.589      ;
; 1.904 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.464      ; 2.620      ;
; 1.930 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.506      ; 2.688      ;
; 2.005 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.464      ; 2.721      ;
; 2.031 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.506      ; 2.789      ;
; 2.062 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.464      ; 2.778      ;
; 2.063 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.506      ; 2.821      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.463      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.199 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 2.987      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.490      ;
; 2.253 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.016      ; 2.521      ;
; 2.253 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.016      ; 2.521      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.291 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.562      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.086      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.319 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.589      ;
; 2.352 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.016      ; 2.620      ;
; 2.352 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.016      ; 2.620      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.019      ; 2.663      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.536      ; 3.187      ;
; 2.420 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.690      ;
; 2.420 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.690      ;
; 2.420 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.690      ;
; 2.420 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.690      ;
; 2.420 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.690      ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_REF'                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ;
; -7.360 ; -7.140       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ;
; -7.359 ; -7.139       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ;
; -7.310 ; -7.090       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ;
; -7.304 ; -7.084       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_0_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_10_|clk                                                                               ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_11_|clk                                                                               ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_12_|clk                                                                               ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_13_|clk                                                                               ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_14_|clk                                                                               ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_15_|clk                                                                               ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_1_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_2_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_3_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_4_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_5_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_6_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_7_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_8_|clk                                                                                ;
; -7.091 ; -7.091       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_9_|clk                                                                                ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_16_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_17_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_18_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_19_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_20_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_21_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_22_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_23_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_24_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_25_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_26_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_27_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_28_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_29_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_30_|clk                                                                               ;
; -7.090 ; -7.090       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_31_|clk                                                                               ;
; -7.082 ; -7.082       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|inclk[0]                                                                      ;
; -7.082 ; -7.082       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|outclk                                                                        ;
; -7.041 ; -7.041       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|outstate_Z|clk                                                                              ;
; -7.036 ; -7.036       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_2_0_component_c11|clko_s_Z|clk                                                                                 ;
; -6.929 ; -6.929       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|combout                                                                            ;
; -6.918 ; -6.918       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -6.899 ; -6.899       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|dataa                                                                         ;
; -6.233 ; -6.013       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ;
; -6.233 ; -6.013       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ;
; -6.233 ; -6.013       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ;
; -5.972 ; -5.972       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|datad                                                                              ;
; -5.964 ; -5.964       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_A_Z|clk                                                                               ;
; -5.964 ; -5.964       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_B_Z|clk                                                                               ;
; -5.964 ; -5.964       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_C_Z|clk                                                                               ;
; -5.910 ; -5.690       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ;
; -5.910 ; -5.690       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ;
; -5.910 ; -5.690       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_C ;
; -5.897 ; -5.897       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout                                                                              ;
; -5.879 ; -5.879       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|combout                                                                         ;
; -5.860 ; -5.860       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|datad                                                                                ;
; -5.846 ; -5.658       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ;
; -5.830 ; -5.642       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ;
; -5.830 ; -5.830       ; 0.000          ; Low Pulse Width  ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -5.829 ; -5.829       ; 0.000          ; Low Pulse Width  ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|dataa                                                                         ;
; -5.798 ; -5.798       ; 0.000          ; Low Pulse Width  ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|combout                                                                            ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ;
; -5.784 ; -5.596       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock   ; Clock Edge ; Target                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT0  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT1  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT2  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT3  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT0 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT1 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT2 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT3 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a2~porta_datain_reg0              ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                           ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[10]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[11]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[12]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[1]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[2]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[3]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[4]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[5]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[6]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[7]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[8]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[9]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0 ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_1    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_10   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_11   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_12   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_15   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_5    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_6    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_7    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_8    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_9    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[10]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[11]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[12]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[13]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[15]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[16]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[17]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[18]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[19]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[1]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[20]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[21]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[22]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[23]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[24]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[25]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[26]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[27]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[28]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[29]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[2]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[30]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[3]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[4]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[5]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[6]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[7]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[8]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[9]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_20   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_28   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_4    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_6    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_7    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[1]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]  ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                      ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ;
; 0.131  ; 0.351        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ;
; 0.131  ; 0.351        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ;
; 0.131  ; 0.351        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ;
; 0.131  ; 0.351        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]  ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]  ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]  ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]  ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ;
; 0.140  ; 0.360        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]   ;
; 0.141  ; 0.361        ; 0.220          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------+
; Setup Times                                                                      ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; 5.084  ; 5.086  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 4.252  ; 4.261  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 4.165  ; 4.239  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 4.498  ; 4.641  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 4.099  ; 4.148  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.607  ; 4.588  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 4.430  ; 4.420  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 5.084  ; 5.086  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 4.546  ; 4.489  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 4.193  ; 4.261  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 4.813  ; 4.720  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.525  ; 4.561  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 4.380  ; 4.369  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 4.710  ; 4.737  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 4.298  ; 4.274  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 4.442  ; 4.514  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 4.450  ; 4.535  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 4.828  ; 4.957  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.791  ; 3.931  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 4.642  ; 4.705  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 4.548  ; 4.729  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 4.423  ; 4.515  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 4.240  ; 4.338  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.630  ; 4.607  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 4.513  ; 4.562  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 3.487  ; 3.680  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 4.244  ; 4.266  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 4.291  ; 4.452  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 4.631  ; 4.655  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 4.142  ; 4.125  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 4.092  ; 4.134  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 4.373  ; 4.506  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.418  ; 4.510  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 4.828  ; 4.957  ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; 5.275  ; 5.361  ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; 16.776 ; 15.838 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.339  ; 0.646  ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; 4.328  ; 4.536  ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; 3.775  ; 4.069  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Hold Times                                                                       ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; -1.601 ; -1.803 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; -1.601 ; -1.858 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; -1.786 ; -2.020 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; -2.480 ; -2.739 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; -2.204 ; -2.472 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; -2.288 ; -2.475 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; -1.830 ; -2.077 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; -2.345 ; -2.561 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; -2.142 ; -2.293 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; -1.854 ; -2.069 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; -2.112 ; -2.237 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; -2.137 ; -2.310 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; -1.918 ; -2.103 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; -2.301 ; -2.517 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; -1.614 ; -1.803 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; -2.060 ; -2.298 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; -2.047 ; -2.299 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; -1.567 ; -1.772 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; -2.653 ; -2.813 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; -3.397 ; -3.561 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; -2.216 ; -2.518 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; -2.021 ; -2.272 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; -3.425 ; -3.563 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; -3.416 ; -3.481 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; -2.195 ; -2.439 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; -2.841 ; -2.993 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; -1.921 ; -2.130 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; -1.948 ; -2.164 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; -1.855 ; -2.089 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; -1.567 ; -1.772 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; -1.692 ; -1.924 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; -2.073 ; -2.367 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; -2.077 ; -2.364 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; -2.074 ; -2.331 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; -1.903 ; -2.223 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; -6.944 ; -6.897 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.077  ; -0.210 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; -2.209 ; -2.437 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; -1.937 ; -2.246 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                   ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                                                 ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                            ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; SRAM0_A[*]     ; CLK_BRD                                                                                                    ; 20.358 ; 19.933 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[0]    ; CLK_BRD                                                                                                    ; 17.182 ; 16.744 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[1]    ; CLK_BRD                                                                                                    ; 17.448 ; 17.177 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[2]    ; CLK_BRD                                                                                                    ; 16.424 ; 16.142 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[3]    ; CLK_BRD                                                                                                    ; 17.589 ; 17.266 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[4]    ; CLK_BRD                                                                                                    ; 16.750 ; 16.406 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[5]    ; CLK_BRD                                                                                                    ; 16.971 ; 16.726 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[6]    ; CLK_BRD                                                                                                    ; 18.196 ; 18.049 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[7]    ; CLK_BRD                                                                                                    ; 20.358 ; 19.933 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[8]    ; CLK_BRD                                                                                                    ; 18.540 ; 18.372 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[9]    ; CLK_BRD                                                                                                    ; 19.282 ; 19.082 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[10]   ; CLK_BRD                                                                                                    ; 17.971 ; 17.759 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[11]   ; CLK_BRD                                                                                                    ; 17.503 ; 17.069 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[12]   ; CLK_BRD                                                                                                    ; 16.964 ; 16.754 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[13]   ; CLK_BRD                                                                                                    ; 18.481 ; 18.194 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[14]   ; CLK_BRD                                                                                                    ; 19.682 ; 19.402 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[15]   ; CLK_BRD                                                                                                    ; 17.202 ; 16.966 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[16]   ; CLK_BRD                                                                                                    ; 16.588 ; 16.300 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[17]   ; CLK_BRD                                                                                                    ; 18.765 ; 18.386 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_D[*]     ; CLK_BRD                                                                                                    ; 10.080 ; 9.729  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[0]    ; CLK_BRD                                                                                                    ; 8.801  ; 8.465  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[1]    ; CLK_BRD                                                                                                    ; 8.432  ; 8.173  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[2]    ; CLK_BRD                                                                                                    ; 8.838  ; 8.528  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[3]    ; CLK_BRD                                                                                                    ; 8.602  ; 8.287  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[4]    ; CLK_BRD                                                                                                    ; 8.006  ; 7.930  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[5]    ; CLK_BRD                                                                                                    ; 9.642  ; 9.245  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[6]    ; CLK_BRD                                                                                                    ; 7.746  ; 7.632  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[7]    ; CLK_BRD                                                                                                    ; 9.720  ; 9.632  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[8]    ; CLK_BRD                                                                                                    ; 9.205  ; 8.832  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[9]    ; CLK_BRD                                                                                                    ; 8.844  ; 8.659  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[10]   ; CLK_BRD                                                                                                    ; 9.714  ; 9.338  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[11]   ; CLK_BRD                                                                                                    ; 10.080 ; 9.729  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[12]   ; CLK_BRD                                                                                                    ; 9.873  ; 9.664  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[13]   ; CLK_BRD                                                                                                    ; 7.939  ; 7.781  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[14]   ; CLK_BRD                                                                                                    ; 9.548  ; 9.176  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[15]   ; CLK_BRD                                                                                                    ; 8.061  ; 7.815  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_E        ; CLK_BRD                                                                                                    ; 21.918 ; 21.686 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_LB       ; CLK_BRD                                                                                                    ; 21.223 ; 21.074 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_OE       ; CLK_BRD                                                                                                    ; 19.435 ; 19.444 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_UB       ; CLK_BRD                                                                                                    ; 20.921 ; 20.788 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_W        ; CLK_BRD                                                                                                    ; 8.001  ; 8.065  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_A[*]     ; CLK_BRD                                                                                                    ; 19.916 ; 19.893 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[0]    ; CLK_BRD                                                                                                    ; 15.707 ; 15.495 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[1]    ; CLK_BRD                                                                                                    ; 18.224 ; 18.106 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[2]    ; CLK_BRD                                                                                                    ; 16.879 ; 16.602 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[3]    ; CLK_BRD                                                                                                    ; 17.319 ; 17.034 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[4]    ; CLK_BRD                                                                                                    ; 16.333 ; 16.062 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[5]    ; CLK_BRD                                                                                                    ; 16.564 ; 16.347 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[6]    ; CLK_BRD                                                                                                    ; 19.916 ; 19.893 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[7]    ; CLK_BRD                                                                                                    ; 17.052 ; 16.860 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[8]    ; CLK_BRD                                                                                                    ; 19.185 ; 18.929 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[9]    ; CLK_BRD                                                                                                    ; 19.258 ; 19.017 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[10]   ; CLK_BRD                                                                                                    ; 17.990 ; 17.715 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[11]   ; CLK_BRD                                                                                                    ; 17.889 ; 17.430 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[12]   ; CLK_BRD                                                                                                    ; 17.714 ; 17.477 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[13]   ; CLK_BRD                                                                                                    ; 19.095 ; 18.958 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[14]   ; CLK_BRD                                                                                                    ; 17.110 ; 16.834 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[15]   ; CLK_BRD                                                                                                    ; 17.207 ; 16.964 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[16]   ; CLK_BRD                                                                                                    ; 15.970 ; 15.768 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[17]   ; CLK_BRD                                                                                                    ; 17.776 ; 17.486 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_D[*]     ; CLK_BRD                                                                                                    ; 9.828  ; 9.505  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[0]    ; CLK_BRD                                                                                                    ; 7.072  ; 6.975  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[1]    ; CLK_BRD                                                                                                    ; 9.055  ; 8.684  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[2]    ; CLK_BRD                                                                                                    ; 9.131  ; 8.728  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[3]    ; CLK_BRD                                                                                                    ; 9.235  ; 8.948  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[4]    ; CLK_BRD                                                                                                    ; 8.580  ; 8.475  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[5]    ; CLK_BRD                                                                                                    ; 8.996  ; 8.758  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[6]    ; CLK_BRD                                                                                                    ; 8.573  ; 8.477  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[7]    ; CLK_BRD                                                                                                    ; 9.828  ; 9.505  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[8]    ; CLK_BRD                                                                                                    ; 8.479  ; 8.332  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[9]    ; CLK_BRD                                                                                                    ; 8.324  ; 8.185  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[10]   ; CLK_BRD                                                                                                    ; 9.215  ; 8.874  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[11]   ; CLK_BRD                                                                                                    ; 8.357  ; 8.159  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[12]   ; CLK_BRD                                                                                                    ; 8.051  ; 7.819  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[13]   ; CLK_BRD                                                                                                    ; 8.702  ; 8.370  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[14]   ; CLK_BRD                                                                                                    ; 8.740  ; 8.435  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[15]   ; CLK_BRD                                                                                                    ; 8.083  ; 7.863  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_E        ; CLK_BRD                                                                                                    ; 22.407 ; 22.206 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_LB       ; CLK_BRD                                                                                                    ; 21.634 ; 21.472 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_OE       ; CLK_BRD                                                                                                    ; 20.866 ; 20.784 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_UB       ; CLK_BRD                                                                                                    ; 21.561 ; 21.368 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_W        ; CLK_BRD                                                                                                    ; 9.058  ; 9.006  ; Rise       ; CLK_BRD                                                                                                    ;
; DAC_CLK        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 9.077  ; 8.855  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_CS         ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 10.474 ; 10.269 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_DOUT       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 10.372 ; 10.122 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                                             ; 15.553 ; 14.782 ; Rise       ; JTAG_NEXUS_TCK                                                                                             ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                           ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                                                 ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                            ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; SRAM0_A[*]     ; CLK_BRD                                                                                                    ; 8.729  ; 8.378  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[0]    ; CLK_BRD                                                                                                    ; 10.057 ; 9.559  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[1]    ; CLK_BRD                                                                                                    ; 9.227  ; 8.916  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[2]    ; CLK_BRD                                                                                                    ; 8.751  ; 8.452  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[3]    ; CLK_BRD                                                                                                    ; 9.064  ; 8.658  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[4]    ; CLK_BRD                                                                                                    ; 9.449  ; 9.066  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[5]    ; CLK_BRD                                                                                                    ; 9.269  ; 9.011  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[6]    ; CLK_BRD                                                                                                    ; 10.365 ; 10.179 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[7]    ; CLK_BRD                                                                                                    ; 12.931 ; 12.480 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[8]    ; CLK_BRD                                                                                                    ; 9.572  ; 9.289  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[9]    ; CLK_BRD                                                                                                    ; 11.305 ; 10.966 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[10]   ; CLK_BRD                                                                                                    ; 10.483 ; 10.148 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[11]   ; CLK_BRD                                                                                                    ; 9.933  ; 9.511  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[12]   ; CLK_BRD                                                                                                    ; 9.153  ; 8.866  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[13]   ; CLK_BRD                                                                                                    ; 9.975  ; 9.608  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[14]   ; CLK_BRD                                                                                                    ; 12.589 ; 12.272 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[15]   ; CLK_BRD                                                                                                    ; 9.257  ; 9.068  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[16]   ; CLK_BRD                                                                                                    ; 8.729  ; 8.378  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[17]   ; CLK_BRD                                                                                                    ; 10.468 ; 9.950  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_D[*]     ; CLK_BRD                                                                                                    ; 7.568  ; 7.457  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[0]    ; CLK_BRD                                                                                                    ; 8.572  ; 8.247  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[1]    ; CLK_BRD                                                                                                    ; 8.218  ; 7.966  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[2]    ; CLK_BRD                                                                                                    ; 8.608  ; 8.307  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[3]    ; CLK_BRD                                                                                                    ; 8.380  ; 8.075  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[4]    ; CLK_BRD                                                                                                    ; 7.817  ; 7.742  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[5]    ; CLK_BRD                                                                                                    ; 9.386  ; 9.004  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[6]    ; CLK_BRD                                                                                                    ; 7.568  ; 7.457  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[7]    ; CLK_BRD                                                                                                    ; 9.462  ; 9.375  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[8]    ; CLK_BRD                                                                                                    ; 8.968  ; 8.608  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[9]    ; CLK_BRD                                                                                                    ; 8.622  ; 8.443  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[10]   ; CLK_BRD                                                                                                    ; 9.458  ; 9.095  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[11]   ; CLK_BRD                                                                                                    ; 9.809  ; 9.471  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[12]   ; CLK_BRD                                                                                                    ; 9.601  ; 9.397  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[13]   ; CLK_BRD                                                                                                    ; 7.747  ; 7.592  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[14]   ; CLK_BRD                                                                                                    ; 9.291  ; 8.931  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[15]   ; CLK_BRD                                                                                                    ; 7.862  ; 7.622  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_E        ; CLK_BRD                                                                                                    ; 10.328 ; 9.884  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_LB       ; CLK_BRD                                                                                                    ; 9.657  ; 9.395  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_OE       ; CLK_BRD                                                                                                    ; 7.945  ; 7.832  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_UB       ; CLK_BRD                                                                                                    ; 9.321  ; 9.016  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_W        ; CLK_BRD                                                                                                    ; 7.810  ; 7.874  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_A[*]     ; CLK_BRD                                                                                                    ; 8.136  ; 7.867  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[0]    ; CLK_BRD                                                                                                    ; 8.642  ; 8.361  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[1]    ; CLK_BRD                                                                                                    ; 10.030 ; 9.871  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[2]    ; CLK_BRD                                                                                                    ; 9.189  ; 8.895  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[3]    ; CLK_BRD                                                                                                    ; 8.805  ; 8.435  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[4]    ; CLK_BRD                                                                                                    ; 9.047  ; 8.733  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[5]    ; CLK_BRD                                                                                                    ; 8.878  ; 8.648  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[6]    ; CLK_BRD                                                                                                    ; 12.070 ; 12.009 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[7]    ; CLK_BRD                                                                                                    ; 9.701  ; 9.471  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[8]    ; CLK_BRD                                                                                                    ; 10.191 ; 9.824  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[9]    ; CLK_BRD                                                                                                    ; 11.285 ; 10.906 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[10]   ; CLK_BRD                                                                                                    ; 10.502 ; 10.107 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[11]   ; CLK_BRD                                                                                                    ; 10.303 ; 9.857  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[12]   ; CLK_BRD                                                                                                    ; 9.874  ; 9.559  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[13]   ; CLK_BRD                                                                                                    ; 10.618 ; 10.399 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[14]   ; CLK_BRD                                                                                                    ; 10.066 ; 9.748  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[15]   ; CLK_BRD                                                                                                    ; 9.261  ; 9.067  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[16]   ; CLK_BRD                                                                                                    ; 8.136  ; 7.867  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[17]   ; CLK_BRD                                                                                                    ; 9.519  ; 9.087  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_D[*]     ; CLK_BRD                                                                                                    ; 6.912  ; 6.816  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[0]    ; CLK_BRD                                                                                                    ; 6.912  ; 6.816  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[1]    ; CLK_BRD                                                                                                    ; 8.816  ; 8.456  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[2]    ; CLK_BRD                                                                                                    ; 8.891  ; 8.501  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[3]    ; CLK_BRD                                                                                                    ; 8.988  ; 8.709  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[4]    ; CLK_BRD                                                                                                    ; 8.359  ; 8.255  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[5]    ; CLK_BRD                                                                                                    ; 8.767  ; 8.537  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[6]    ; CLK_BRD                                                                                                    ; 8.362  ; 8.269  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[7]    ; CLK_BRD                                                                                                    ; 9.567  ; 9.256  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[8]    ; CLK_BRD                                                                                                    ; 8.271  ; 8.129  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[9]    ; CLK_BRD                                                                                                    ; 8.119  ; 7.983  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[10]   ; CLK_BRD                                                                                                    ; 8.979  ; 8.650  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[11]   ; CLK_BRD                                                                                                    ; 8.155  ; 7.964  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[12]   ; CLK_BRD                                                                                                    ; 7.853  ; 7.628  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[13]   ; CLK_BRD                                                                                                    ; 8.479  ; 8.158  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[14]   ; CLK_BRD                                                                                                    ; 8.515  ; 8.219  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[15]   ; CLK_BRD                                                                                                    ; 7.884  ; 7.669  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_E        ; CLK_BRD                                                                                                    ; 10.753 ; 10.454 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_LB       ; CLK_BRD                                                                                                    ; 10.057 ; 9.682  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_OE       ; CLK_BRD                                                                                                    ; 9.320  ; 9.119  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_UB       ; CLK_BRD                                                                                                    ; 9.944  ; 9.580  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_W        ; CLK_BRD                                                                                                    ; 8.883  ; 8.830  ; Rise       ; CLK_BRD                                                                                                    ;
; DAC_CLK        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 8.799  ; 8.583  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_CS         ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 10.150 ; 9.952  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_DOUT       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 10.051 ; 9.810  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                                             ; 9.562  ; 9.168  ; Rise       ; JTAG_NEXUS_TCK                                                                                             ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------+
; Output Enable Times                                                        ;
+--------------+------------+--------+--------+------------+-----------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+--------------+------------+--------+--------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 19.979 ; 19.979 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 20.258 ; 20.258 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 21.505 ; 21.505 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 20.937 ; 20.937 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 20.219 ; 20.219 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 21.763 ; 21.763 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 21.158 ; 21.158 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 21.981 ; 21.981 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 21.094 ; 21.094 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 21.126 ; 21.126 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 21.184 ; 21.184 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 21.763 ; 21.763 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 21.231 ; 21.231 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 21.005 ; 21.005 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 19.979 ; 19.979 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 20.611 ; 20.611 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 20.591 ; 20.591 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 19.605 ; 19.605 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 19.605 ; 19.605 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 21.485 ; 21.485 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 21.247 ; 21.247 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 21.197 ; 21.197 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 21.485 ; 21.485 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 21.770 ; 21.770 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 21.188 ; 21.188 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 21.622 ; 21.622 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 21.174 ; 21.174 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 21.188 ; 21.188 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 21.221 ; 21.221 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 21.184 ; 21.184 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 19.969 ; 19.969 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 21.218 ; 21.218 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 21.228 ; 21.228 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 20.872 ; 20.872 ; Rise       ; CLK_BRD         ;
+--------------+------------+--------+--------+------------+-----------------+


+--------------------------------------------------------------------------+
; Minimum Output Enable Times                                              ;
+--------------+------------+-------+-------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+-------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 7.917 ; 7.983 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 8.183 ; 8.249 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 9.381 ; 9.447 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 8.836 ; 8.902 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 8.146 ; 8.212 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 9.639 ; 9.699 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 9.058 ; 9.118 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 9.849 ; 9.909 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 8.996 ; 9.056 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 9.027 ; 9.087 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 9.084 ; 9.144 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 9.639 ; 9.699 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 9.129 ; 9.189 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 8.900 ; 8.966 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 7.917 ; 7.983 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 8.524 ; 8.590 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 8.504 ; 8.570 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 7.555 ; 7.621 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 7.555 ; 7.621 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 9.361 ; 9.427 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 9.134 ; 9.200 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 9.084 ; 9.150 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 9.361 ; 9.427 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 9.646 ; 9.706 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 9.088 ; 9.148 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 9.505 ; 9.565 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 9.074 ; 9.134 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 9.088 ; 9.148 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 9.119 ; 9.179 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 9.085 ; 9.145 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 7.907 ; 7.973 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 9.107 ; 9.173 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 9.117 ; 9.183 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 8.773 ; 8.839 ; Rise       ; CLK_BRD         ;
+--------------+------------+-------+-------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Output Disable Times                                                             ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 19.914    ; 20.051    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 20.123    ; 20.260    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 21.225    ; 21.362    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 20.739    ; 20.876    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 20.093    ; 20.230    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 21.435    ; 21.566    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 20.924    ; 21.055    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 21.655    ; 21.786    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 20.855    ; 20.986    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 20.885    ; 21.016    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 20.955    ; 21.086    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 21.435    ; 21.566    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 20.994    ; 21.125    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 20.821    ; 20.958    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 19.914    ; 20.051    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 20.440    ; 20.577    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 20.420    ; 20.557    ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 19.582    ; 19.719    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 19.582    ; 19.719    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 21.205    ; 21.342    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 20.983    ; 21.120    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 20.933    ; 21.070    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 21.205    ; 21.342    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 21.441    ; 21.572    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 20.954    ; 21.085    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 21.353    ; 21.484    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 20.945    ; 21.076    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 20.954    ; 21.085    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 20.984    ; 21.115    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 20.947    ; 21.078    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 19.904    ; 20.041    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 20.979    ; 21.116    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 20.989    ; 21.126    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 20.680    ; 20.817    ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                     ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 7.868     ; 7.868     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 8.068     ; 8.068     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 9.125     ; 9.125     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 8.659     ; 8.659     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 8.038     ; 8.038     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 9.332     ; 9.332     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 8.840     ; 8.840     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 9.543     ; 9.543     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 8.774     ; 8.774     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 8.804     ; 8.804     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 8.872     ; 8.872     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 9.332     ; 9.332     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 8.909     ; 8.909     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 8.737     ; 8.737     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 7.868     ; 7.868     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 8.372     ; 8.372     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 8.352     ; 8.352     ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 7.546     ; 7.546     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 7.546     ; 7.546     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 9.105     ; 9.105     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 8.893     ; 8.893     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 8.843     ; 8.843     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 9.105     ; 9.105     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 9.337     ; 9.337     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 8.870     ; 8.870     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 9.254     ; 9.254     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 8.862     ; 8.862     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 8.870     ; 8.870     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 8.899     ; 8.899     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 8.865     ; 8.865     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 7.858     ; 7.858     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 8.889     ; 8.889     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 8.899     ; 8.899     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 8.601     ; 8.601     ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                               ;
+-----------+-----------------+------------------------------------------------------------------------------------------------------------+------+
; Fmax      ; Restricted Fmax ; Clock Name                                                                                                 ; Note ;
+-----------+-----------------+------------------------------------------------------------------------------------------------------------+------+
; 34.62 MHz ; 34.62 MHz       ; CLK_REF                                                                                                    ;      ;
; 48.34 MHz ; 48.34 MHz       ; CLK_BRD                                                                                                    ;      ;
; 84.98 MHz ; 84.98 MHz       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;      ;
; 104.6 MHz ; 104.6 MHz       ; JTAG_NEXUS_TCK                                                                                             ;      ;
+-----------+-----------------+------------------------------------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                                                   ;
+------------------------------------------------------------------------------------------------------------+---------+---------------+
; Clock                                                                                                      ; Slack   ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+---------+---------------+
; CLK_REF                                                                                                    ; -19.229 ; -1906.571     ;
; CLK_BRD                                                                                                    ; -16.553 ; -17879.923    ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; -10.768 ; -233.203      ;
; JTAG_NEXUS_TCK                                                                                             ; -6.535  ; -4466.301     ;
+------------------------------------------------------------------------------------------------------------+---------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                                                   ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; CLK_REF                                                                                                    ; -2.497 ; -55.955       ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.089  ; 0.000         ;
; CLK_BRD                                                                                                    ; 0.263  ; 0.000         ;
; JTAG_NEXUS_TCK                                                                                             ; 0.320  ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------+
; Slow 1200mV 0C Model Recovery Summary   ;
+----------------+--------+---------------+
; Clock          ; Slack  ; End Point TNS ;
+----------------+--------+---------------+
; JTAG_NEXUS_TCK ; -2.846 ; -120.033      ;
; CLK_REF        ; -2.387 ; -75.739       ;
+----------------+--------+---------------+


+----------------------------------------+
; Slow 1200mV 0C Model Removal Summary   ;
+----------------+-------+---------------+
; Clock          ; Slack ; End Point TNS ;
+----------------+-------+---------------+
; JTAG_NEXUS_TCK ; 1.262 ; 0.000         ;
; CLK_REF        ; 1.633 ; 0.000         ;
+----------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                                                    ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; CLK_REF                                                                                                    ; -7.458 ; -2057.786     ;
; CLK_BRD                                                                                                    ; -4.000 ; -3066.467     ;
; JTAG_NEXUS_TCK                                                                                             ; -3.000 ; -1708.589     ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; -1.487 ; -83.416       ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLK_REF'                                                                                                                                                                                                                                                                                       ;
+---------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                        ; To Node                                                                                                ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -19.229 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.298    ; 4.933      ;
; -19.229 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.298    ; 4.933      ;
; -18.665 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -14.555    ; 5.112      ;
; -18.665 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -14.555    ; 5.112      ;
; -17.774 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -12.845    ; 5.931      ;
; -17.774 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -12.845    ; 5.931      ;
; -17.706 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.767     ; 15.941     ;
; -17.706 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.767     ; 15.941     ;
; -17.675 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.181     ; 10.496     ;
; -17.675 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.181     ; 10.496     ;
; -17.557 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.767     ; 15.792     ;
; -17.557 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.767     ; 15.792     ;
; -17.550 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -12.845    ; 5.707      ;
; -17.550 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -12.845    ; 5.707      ;
; -17.089 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.101     ; 12.990     ;
; -17.089 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.101     ; 12.990     ;
; -16.959 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -15.307    ; 2.654      ;
; -16.915 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.724     ; 17.173     ;
; -16.915 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.724     ; 17.173     ;
; -16.840 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.101     ; 12.741     ;
; -16.840 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.101     ; 12.741     ;
; -16.716 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.206      ; 17.924     ;
; -16.716 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.206      ; 17.924     ;
; -16.682 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.206      ; 17.890     ;
; -16.682 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.206      ; 17.890     ;
; -16.625 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.519     ; 14.108     ;
; -16.625 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.519     ; 14.108     ;
; -16.622 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.211     ; 11.413     ;
; -16.622 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.211     ; 11.413     ;
; -16.615 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.469    ; 6.148      ;
; -16.615 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.469    ; 6.148      ;
; -16.614 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.670     ; 8.946      ;
; -16.614 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.670     ; 8.946      ;
; -16.603 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.265    ; 7.340      ;
; -16.603 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.265    ; 7.340      ;
; -16.578 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.098     ; 16.482     ;
; -16.578 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.098     ; 16.482     ;
; -16.564 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.000     ; 9.566      ;
; -16.564 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.000     ; 9.566      ;
; -16.481 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.469    ; 6.014      ;
; -16.481 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.469    ; 6.014      ;
; -16.463 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.265    ; 7.200      ;
; -16.463 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.265    ; 7.200      ;
; -16.429 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.098     ; 16.333     ;
; -16.429 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.098     ; 16.333     ;
; -16.395 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -14.564    ; 2.833      ;
; -16.384 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.519     ; 13.867     ;
; -16.384 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.519     ; 13.867     ;
; -16.381 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.670     ; 8.713      ;
; -16.381 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.211     ; 11.172     ;
; -16.381 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.670     ; 8.713      ;
; -16.381 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.211     ; 11.172     ;
; -16.322 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|un1_g3[0]                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.348     ; 9.976      ;
; -16.322 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|un1_g3[0]                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.348     ; 9.976      ;
; -15.793 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|un1_sig_B_x[0]                                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.530     ; 9.265      ;
; -15.793 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|un1_sig_B_x[0]                                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.530     ; 9.265      ;
; -15.504 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -12.854    ; 3.652      ;
; -15.436 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.776     ; 13.662     ;
; -15.405 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.190     ; 8.217      ;
; -15.287 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.776     ; 13.513     ;
; -15.280 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -12.854    ; 3.428      ;
; -15.233 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.724     ; 15.491     ;
; -15.233 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.724     ; 15.491     ;
; -15.119 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 2.782      ; 18.903     ;
; -15.119 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 2.782      ; 18.903     ;
; -14.819 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.110     ; 10.711     ;
; -14.645 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.733     ; 14.894     ;
; -14.570 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.110     ; 10.462     ;
; -14.446 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.197      ; 15.645     ;
; -14.412 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.197      ; 15.611     ;
; -14.394 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.724     ; 14.652     ;
; -14.394 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.724     ; 14.652     ;
; -14.355 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.528     ; 11.829     ;
; -14.352 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.220     ; 9.134      ;
; -14.345 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.478    ; 3.869      ;
; -14.344 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.679     ; 6.667      ;
; -14.335 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.042     ; 15.275     ;
; -14.333 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.274    ; 5.061      ;
; -14.308 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.107     ; 14.203     ;
; -14.294 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.009     ; 7.287      ;
; -14.211 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -11.478    ; 3.735      ;
; -14.193 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -10.274    ; 4.921      ;
; -14.159 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.107     ; 14.054     ;
; -14.114 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.528     ; 11.588     ;
; -14.111 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -8.679     ; 6.434      ;
; -14.111 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.220     ; 8.893      ;
; -14.052 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|un1_g3[0]                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.357     ; 7.697      ;
; -13.943 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 0.500        ; 2.782      ; 17.227     ;
; -13.943 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 0.500        ; 2.782      ; 17.227     ;
; -13.523 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|un1_sig_B_x[0]                                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -7.539     ; 6.986      ;
; -12.963 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.733     ; 13.212     ;
; -12.849 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; 2.773      ; 16.624     ;
; -12.847 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.095     ; 13.754     ;
; -12.847 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.095     ; 13.754     ;
; -12.659 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_18__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.078     ; 13.583     ;
; -12.659 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_18__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.078     ; 13.583     ;
; -12.574 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_15__Z                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.072     ; 13.504     ;
; -12.536 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_5                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.724     ; 12.794     ;
; -12.536 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_5                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.724     ; 12.794     ;
; -12.520 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_4__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.095     ; 13.427     ;
+---------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                            ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                                                                ; To Node                                                                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -16.553 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.077      ; 17.632     ;
; -16.511 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.078      ; 17.591     ;
; -16.467 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.080      ; 17.549     ;
; -16.286 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.075      ; 17.363     ;
; -16.275 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.058      ; 17.335     ;
; -16.221 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.080      ; 17.303     ;
; -16.199 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.325     ; 16.876     ;
; -16.176 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.333     ; 16.845     ;
; -16.175 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.333     ; 16.844     ;
; -16.174 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.329     ; 16.847     ;
; -16.147 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.062      ; 17.211     ;
; -16.136 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.045      ; 17.183     ;
; -16.134 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.326     ; 16.810     ;
; -16.123 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.067      ; 17.192     ;
; -16.117 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.328     ; 16.791     ;
; -16.115 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.331     ; 16.786     ;
; -16.112 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.076      ; 17.190     ;
; -16.104 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.073      ; 17.179     ;
; -16.104 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.758     ;
; -16.093 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.056      ; 17.151     ;
; -16.085 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.326     ; 16.761     ;
; -16.066 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.089      ; 17.157     ;
; -16.032 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.074      ; 17.108     ;
; -16.022 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.091      ; 17.115     ;
; -16.019 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.061      ; 17.082     ;
; -15.983 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.076      ; 17.061     ;
; -15.980 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.330     ; 16.652     ;
; -15.939 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.078      ; 17.019     ;
; -15.916 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.067      ; 16.985     ;
; -15.908 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.575     ;
; -15.907 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.331     ; 16.578     ;
; -15.900 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.325     ; 16.577     ;
; -15.897 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.352     ; 16.547     ;
; -15.896 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.550     ;
; -15.880 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.048      ; 16.930     ;
; -15.874 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.061      ; 16.937     ;
; -15.850 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.330     ; 16.522     ;
; -15.848 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.345     ; 16.505     ;
; -15.843 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.330     ; 16.515     ;
; -15.839 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.347     ; 16.494     ;
; -15.837 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.059      ; 16.898     ;
; -15.836 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.077      ; 16.915     ;
; -15.830 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.063      ; 16.895     ;
; -15.829 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.329     ; 16.502     ;
; -15.819 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.069      ; 16.890     ;
; -15.818 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.073      ; 16.893     ;
; -15.804 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.452     ;
; -15.801 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.330     ; 16.473     ;
; -15.798 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.064      ; 16.864     ;
; -15.797 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.349     ; 16.450     ;
; -15.796 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_30 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.333     ; 16.465     ;
; -15.794 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.076      ; 16.872     ;
; -15.790 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.347     ; 16.445     ;
; -15.782 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.330     ; 16.454     ;
; -15.780 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.071      ; 16.853     ;
; -15.777 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_30 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.425     ;
; -15.776 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.091      ; 16.869     ;
; -15.771 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.347     ; 16.426     ;
; -15.769 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.054      ; 16.825     ;
; -15.758 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.325     ; 16.435     ;
; -15.755 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.075      ; 16.832     ;
; -15.754 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.314     ; 16.442     ;
; -15.748 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.339     ; 16.411     ;
; -15.745 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.328     ; 16.419     ;
; -15.718 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.075      ; 16.795     ;
; -15.707 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.058      ; 16.767     ;
; -15.704 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.079      ; 16.785     ;
; -15.699 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.072      ; 16.773     ;
; -15.692 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.333     ; 16.361     ;
; -15.690 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.073      ; 16.765     ;
; -15.689 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.315     ; 16.376     ;
; -15.687 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.062      ; 16.751     ;
; -15.686 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_19 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.337     ; 16.351     ;
; -15.680 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.056      ; 16.738     ;
; -15.679 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.056      ; 16.737     ;
; -15.678 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.078      ; 16.758     ;
; -15.676 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.045      ; 16.723     ;
; -15.675 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_19 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.323     ;
; -15.672 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.329     ; 16.345     ;
; -15.667 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.087      ; 16.756     ;
; -15.663 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.338     ; 16.327     ;
; -15.655 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.063      ; 16.720     ;
; -15.653 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.352     ; 16.303     ;
; -15.652 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.355     ; 16.299     ;
; -15.652 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.331     ; 16.323     ;
; -15.648 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.337     ; 16.313     ;
; -15.641 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.349     ; 16.294     ;
; -15.640 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.315     ; 16.327     ;
; -15.640 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.345     ; 16.297     ;
; -15.637 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.067      ; 16.706     ;
; -15.636 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.355     ; 16.283     ;
; -15.625 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.372     ; 16.255     ;
; -15.616 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_8  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.326     ; 16.292     ;
; -15.612 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.059      ; 16.673     ;
; -15.607 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.073      ; 16.682     ;
; -15.606 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_29 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.333     ; 16.275     ;
; -15.605 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.334     ; 16.273     ;
; -15.598 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.336     ; 16.264     ;
; -15.587 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.353     ; 16.236     ;
; -15.584 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.063      ; 16.649     ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                             ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                               ; To Node                                                                       ; Launch Clock                                                                                               ; Latch Clock                                                                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; -10.768 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 11.696     ;
; -10.760 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 12.134     ;
; -10.760 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 12.134     ;
; -10.760 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 12.134     ;
; -10.760 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 12.134     ;
; -10.692 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 11.621     ;
; -10.478 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 11.405     ;
; -10.470 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.843     ;
; -10.470 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.843     ;
; -10.470 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.843     ;
; -10.470 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.843     ;
; -10.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 11.330     ;
; -10.253 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 11.180     ;
; -10.245 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.618     ;
; -10.245 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.618     ;
; -10.245 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.618     ;
; -10.245 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.618     ;
; -10.240 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 11.168     ;
; -10.232 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.606     ;
; -10.232 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.606     ;
; -10.232 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.606     ;
; -10.232 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.606     ;
; -10.218 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.076     ; 11.144     ;
; -10.210 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.582     ;
; -10.210 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.582     ;
; -10.210 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.582     ;
; -10.210 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.582     ;
; -10.177 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 11.105     ;
; -10.169 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 11.096     ;
; -10.167 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 11.094     ;
; -10.164 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 11.093     ;
; -10.161 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.534     ;
; -10.161 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.534     ;
; -10.161 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.534     ;
; -10.161 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.534     ;
; -10.159 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.532     ;
; -10.159 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.532     ;
; -10.159 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.532     ;
; -10.159 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.532     ;
; -10.142 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 11.069     ;
; -10.093 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 11.021     ;
; -10.091 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 11.019     ;
; -10.089 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.076     ; 11.015     ;
; -10.081 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.453     ;
; -10.081 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.453     ;
; -10.081 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.453     ;
; -10.081 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.453     ;
; -10.080 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 11.007     ;
; -10.072 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.445     ;
; -10.072 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.445     ;
; -10.072 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.445     ;
; -10.072 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.445     ;
; -10.048 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 10.976     ;
; -10.040 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.414     ;
; -10.040 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.414     ;
; -10.040 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.414     ;
; -10.040 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.414     ;
; -10.028 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 10.956     ;
; -10.027 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 10.955     ;
; -10.020 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.394     ;
; -10.020 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.394     ;
; -10.020 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.394     ;
; -10.020 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.394     ;
; -10.019 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.393     ;
; -10.019 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.393     ;
; -10.019 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.393     ;
; -10.019 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.393     ;
; -10.013 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 10.940     ;
; -10.009 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 10.937     ;
; -10.004 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 10.932     ;
; -10.001 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.375     ;
; -10.001 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.375     ;
; -10.001 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.375     ;
; -10.001 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.375     ;
; -9.996  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 10.923     ;
; -9.990  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.076     ; 10.916     ;
; -9.988  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.361     ;
; -9.988  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.361     ;
; -9.988  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.361     ;
; -9.988  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.361     ;
; -9.982  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.354     ;
; -9.982  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.354     ;
; -9.982  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.354     ;
; -9.982  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.370      ; 11.354     ;
; -9.972  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 10.901     ;
; -9.966  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 10.893     ;
; -9.958  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.331     ;
; -9.958  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.331     ;
; -9.958  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.331     ;
; -9.958  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.371      ; 11.331     ;
; -9.952  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 10.881     ;
; -9.951  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 10.880     ;
; -9.933  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.073     ; 10.862     ;
; -9.920  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 10.848     ;
; -9.918  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.074     ; 10.846     ;
; -9.914  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.075     ; 10.841     ;
; -9.910  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.284     ;
; -9.910  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.284     ;
; -9.910  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.284     ;
; -9.910  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.372      ; 11.284     ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                      ; To Node                                                                                                                                                                        ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -6.535 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.119     ; 7.418      ;
; -6.528 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 7.416      ;
; -6.457 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.119     ; 7.340      ;
; -6.451 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.375      ;
; -6.450 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 7.338      ;
; -6.442 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.372      ;
; -6.440 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.364      ;
; -6.418 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.088     ; 7.332      ;
; -6.407 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.088     ; 7.321      ;
; -6.399 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 7.318      ;
; -6.384 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 7.302      ;
; -6.383 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 7.299      ;
; -6.366 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.296      ;
; -6.365 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 7.282      ;
; -6.357 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 7.302      ;
; -6.354 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 7.271      ;
; -6.335 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.119     ; 7.218      ;
; -6.331 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.255      ;
; -6.328 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 7.216      ;
; -6.326 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.246      ;
; -6.323 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 7.242      ;
; -6.320 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.244      ;
; -6.315 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.235      ;
; -6.314 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.248      ;
; -6.310 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.076     ; 7.236      ;
; -6.308 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 7.226      ;
; -6.307 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 7.223      ;
; -6.299 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 7.232      ;
; -6.298 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 7.229      ;
; -6.283 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.207      ;
; -6.250 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.088     ; 7.164      ;
; -6.249 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.179      ;
; -6.234 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.076     ; 7.160      ;
; -6.225 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 7.166      ;
; -6.206 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 7.125      ;
; -6.202 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.119     ; 7.085      ;
; -6.197 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 7.114      ;
; -6.195 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.114     ; 7.083      ;
; -6.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 7.109      ;
; -6.190 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 7.106      ;
; -6.187 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.111      ;
; -6.164 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 7.085      ;
; -6.163 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.087      ;
; -6.163 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 7.084      ;
; -6.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.078      ;
; -6.154 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.088     ; 7.068      ;
; -6.151 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.071      ;
; -6.124 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.054      ;
; -6.117 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.076     ; 7.043      ;
; -6.101 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 7.018      ;
; -6.091 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 7.008      ;
; -6.088 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 7.009      ;
; -6.087 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 7.008      ;
; -6.081 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 7.000      ;
; -6.079 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.066     ; 7.015      ;
; -6.078 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.066     ; 7.014      ;
; -6.077 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.994      ;
; -6.073 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.993      ;
; -6.067 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 6.991      ;
; -6.066 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.084     ; 6.984      ;
; -6.065 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 6.981      ;
; -6.062 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.982      ;
; -6.013 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.930      ;
; -6.001 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.918      ;
; -5.992 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.076     ; 6.918      ;
; -5.992 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.070     ; 6.924      ;
; -5.988 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 6.904      ;
; -5.971 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 6.892      ;
; -5.970 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 6.891      ;
; -5.951 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.871      ;
; -5.912 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 6.828      ;
; -5.903 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]     ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 6.834      ;
; -5.891 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.808      ;
; -5.884 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.801      ;
; -5.846 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 6.767      ;
; -5.845 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 6.766      ;
; -5.818 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.738      ;
; -5.815 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.117     ; 6.700      ;
; -5.808 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.112     ; 6.698      ;
; -5.795 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.086     ; 6.711      ;
; -5.759 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_3__Z                   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.679      ;
; -5.759 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                           ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.676      ;
; -5.758 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.675      ;
; -5.699 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]    ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.545     ; 6.156      ;
; -5.692 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.066     ; 6.628      ;
; -5.681 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_3__Z                   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.601      ;
; -5.675 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_31__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.595      ;
; -5.675 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_30__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.595      ;
; -5.675 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_29__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.595      ;
; -5.675 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_28__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.595      ;
; -5.675 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_27__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.595      ;
; -5.675 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_26__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.595      ;
; -5.675 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_25__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.595      ;
; -5.675 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_24__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.595      ;
; -5.672 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_31__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.592      ;
; -5.672 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_30__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.592      ;
; -5.672 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_29__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.592      ;
; -5.672 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_28__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.592      ;
; -5.672 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_27__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.592      ;
; -5.672 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|up_reg_26__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.592      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLK_REF'                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                                                                                               ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -2.497 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 14.286     ;
; -2.293 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 14.490     ;
; -2.292 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 14.491     ;
; -2.177 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_20                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 14.606     ;
; -2.110 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 14.669     ;
; -2.091 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 14.688     ;
; -1.909 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.540     ; 14.866     ;
; -1.905 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_28                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.540     ; 14.870     ;
; -1.897 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 14.882     ;
; -1.852 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.540     ; 14.923     ;
; -1.821 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 14.962     ;
; -1.799 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 14.980     ;
; -1.771 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.540     ; 15.004     ;
; -1.747 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.032     ;
; -1.653 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.126     ;
; -1.647 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.132     ;
; -1.620 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.159     ;
; -1.618 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.540     ; 15.157     ;
; -1.616 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.163     ;
; -1.590 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 15.193     ;
; -1.579 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_7                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.200     ;
; -1.561 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.540     ; 15.214     ;
; -1.537 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 15.246     ;
; -1.530 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_6                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.249     ;
; -1.497 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_4                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.282     ;
; -1.497 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.282     ;
; -1.450 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.540     ; 15.325     ;
; -1.391 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 15.392     ;
; -1.367 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 15.416     ;
; -1.327 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 15.456     ;
; -1.324 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.544     ; 15.455     ;
; -1.278 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.548     ; 15.505     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.517 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.141     ; 15.859     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.462 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 16.137     ; 15.910     ;
; -0.443 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 2.398      ; 2.150      ;
; -0.211 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 14.811     ; 14.835     ;
; -0.058 ; JTAG_NEXUS_TCK                                                                                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|tck1_Z                                                                                         ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 2.886      ; 3.063      ;
; 0.018  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 10.014     ; 10.267     ;
; 0.129  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_C                                                    ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 10.014     ; 10.378     ;
; 0.133  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_16__Z                                                ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; 0.000        ; 2.884      ; 3.482      ;
; 0.133  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_16__Z                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; 0.000        ; 2.884      ; 3.482      ;
; 0.143  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 14.068     ; 14.446     ;
; 0.232  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 12.358     ; 12.825     ;
; 0.304  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 12.358     ; 12.897     ;
; 0.323  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.904      ; 1.422      ;
; 0.327  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_16__Z                                                ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; -0.500       ; 2.884      ; 3.176      ;
; 0.327  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_16__Z                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; -0.500       ; 2.884      ; 3.176      ;
; 0.357  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 10.982     ; 11.574     ;
; 0.365  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 12.358     ; 12.958     ;
; 0.395  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z                                                               ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.094      ; 0.684      ;
; 0.399  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 10.982     ; 11.616     ;
; 0.401  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.073      ; 0.669      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.445  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.044      ; 0.684      ;
; 0.468  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_20__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_20__Z                                                 ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.074      ; 0.737      ;
; 0.468  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_16__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_16__Z                                                 ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.074      ; 0.737      ;
; 0.479  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_C                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.050      ; 0.724      ;
; 0.488  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_6__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_6__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.074      ; 0.757      ;
; 0.502  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_C ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.049      ; 0.746      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                                      ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                         ; To Node                                                                       ; Launch Clock                                                                                               ; Latch Clock                                                                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.089 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.127      ; 1.441      ;
; 0.090 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.127      ; 1.442      ;
; 0.167 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 1.517      ;
; 0.206 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 1.557      ;
; 0.306 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.127      ; 1.658      ;
; 0.356 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.127      ; 1.708      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                      ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]                                       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.563 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 1.913      ;
; 0.566 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 1.916      ;
; 0.567 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 1.917      ;
; 0.567 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 1.917      ;
; 0.580 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 1.931      ;
; 0.666 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.016      ;
; 0.666 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 0.952      ;
; 0.680 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.030      ;
; 0.683 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.033      ;
; 0.685 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.035      ;
; 0.686 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.036      ;
; 0.686 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.036      ;
; 0.691 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 2.042      ;
; 0.701 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 0.987      ;
; 0.702 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.052      ;
; 0.711 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.061      ;
; 0.715 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.065      ;
; 0.717 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 1.003      ;
; 0.719 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.069      ;
; 0.722 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 1.008      ;
; 0.729 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 1.634      ;
; 0.734 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 1.639      ;
; 0.745 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 1.650      ;
; 0.760 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 1.665      ;
; 0.774 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.124      ;
; 0.778 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.128      ;
; 0.843 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.127      ; 2.195      ;
; 0.843 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.127      ; 2.195      ;
; 0.881 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 2.232      ;
; 0.882 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 2.233      ;
; 0.883 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 2.234      ;
; 0.884 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 2.235      ;
; 0.920 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.683      ; 1.828      ;
; 0.921 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.681      ; 1.827      ;
; 0.961 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.682      ; 1.868      ;
; 0.963 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.681      ; 1.869      ;
; 0.996 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 2.347      ;
; 1.001 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 1.287      ;
; 1.002 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 1.288      ;
; 1.016 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 1.302      ;
; 1.018 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 1.304      ;
; 1.025 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.375      ;
; 1.033 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 1.319      ;
; 1.034 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.384      ;
; 1.041 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.091      ; 1.327      ;
; 1.182 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.683      ; 2.090      ;
; 1.202 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.552      ;
; 1.207 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.126      ; 2.558      ;
; 1.216 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.566      ;
; 1.233 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 2.138      ;
; 1.240 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.508      ;
; 1.259 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 2.164      ;
; 1.264 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 2.169      ;
; 1.278 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 2.183      ;
; 1.348 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; -0.373     ; 1.170      ;
; 1.360 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 2.265      ;
; 1.371 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.075      ; 1.641      ;
; 1.384 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]                                      ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.651      ;
; 1.403 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.670      ;
; 1.403 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]                                       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.072      ; 1.670      ;
; 1.429 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 1.125      ; 2.779      ;
; 1.479 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.747      ;
; 1.483 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 2.388      ;
; 1.506 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; -0.373     ; 1.328      ;
; 1.517 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.785      ;
; 1.520 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.788      ;
; 1.521 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.789      ;
; 1.521 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.073      ; 1.789      ;
; 1.582 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.680      ; 2.487      ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                     ; To Node                                                                                                                                                                                                        ; Launch Clock                                                                                               ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.263 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                                                                     ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_BRD     ; 0.000        ; 2.887      ; 3.615      ;
; 0.367 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                                                                     ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_BRD     ; -0.500       ; 2.887      ; 3.219      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.381 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.093      ; 0.669      ;
; 0.399 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                          ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                              ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                   ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                                                                    ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                             ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                               ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]                                                   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]                                                                                                    ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                    ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.401 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.073      ; 0.669      ;
; 0.415 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.684      ;
; 0.454 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|Reg_DoDivide_Z                                                                              ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_6__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.073      ; 0.722      ;
; 0.466 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                      ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.736      ;
; 0.476 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|Reg_DoDivide_Z                                                                              ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_3__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.073      ; 0.744      ;
; 0.477 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF0                                                                                      ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF1                                                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.746      ;
; 0.478 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.747      ;
; 0.479 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.748      ;
; 0.479 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.748      ;
; 0.483 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                              ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[2]                                                                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.752      ;
; 0.483 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.752      ;
; 0.488 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.757      ;
; 0.489 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_1                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_1                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.759      ;
; 0.489 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_27__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.758      ;
; 0.489 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_16__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_15__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.758      ;
; 0.490 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_5                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_5                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.760      ;
; 0.490 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.759      ;
; 0.490 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_21__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.759      ;
; 0.491 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_23__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.760      ;
; 0.491 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_23__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.760      ;
; 0.491 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                         ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                                                                          ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.760      ;
; 0.492 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.761      ;
; 0.492 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_29__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.761      ;
; 0.492 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_15__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_14__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.761      ;
; 0.493 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.762      ;
; 0.493 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.762      ;
; 0.494 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_11                                                     ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.073      ;
; 0.503 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.353      ; 1.086      ;
; 0.511 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_DoRegWrite                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|DoRegWrite_WB                                                                                                        ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.781      ;
; 0.512 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead                                                         ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select1_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.782      ;
; 0.513 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_2                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.092      ;
; 0.513 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_2                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_2                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.783      ;
; 0.514 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_1                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|RxSetFF0                                                                                                                                               ; JTAG_NEXUS_TCK                                                                                             ; CLK_BRD     ; 0.000        ; 0.010      ; 0.759      ;
; 0.516 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead                                                         ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select0_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.786      ;
; 0.518 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.097      ;
; 0.521 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_7                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.100      ;
; 0.525 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.353      ; 1.108      ;
; 0.539 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.353      ; 1.122      ;
; 0.539 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.353      ; 1.122      ;
; 0.541 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.120      ;
; 0.542 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_6                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.121      ;
; 0.547 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.353      ; 1.130      ;
; 0.566 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.145      ;
; 0.574 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_8                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.153      ;
; 0.577 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff2_Z           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_Z                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.847      ;
; 0.579 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.849      ;
; 0.586 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.353      ; 1.169      ;
; 0.601 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.180      ;
; 0.616 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Rd_Index_5                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_5                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.074      ; 0.885      ;
; 0.621 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_13                                                     ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.349      ; 1.200      ;
; 0.622 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemWidth_0                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select0_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.075      ; 0.892      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                         ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.320 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[2]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[2]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.181      ; 0.736      ;
; 0.321 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[5]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[5]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.181      ; 0.737      ;
; 0.321 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[4]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[4]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.181      ; 0.737      ;
; 0.321 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[0]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg_0                                                                                                                                                                                   ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.181      ; 0.737      ;
; 0.322 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[7]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.181      ; 0.738      ;
; 0.322 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[6]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[6]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.181      ; 0.738      ;
; 0.322 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[3]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[3]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.181      ; 0.738      ;
; 0.324 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[1]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[1]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.181      ; 0.740      ;
; 0.335 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[3]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.759      ;
; 0.335 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[1]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.759      ;
; 0.336 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                                                                                               ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.760      ;
; 0.337 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z                                                                                                                                                                                                                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                                                                          ; CLK_REF        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.761      ;
; 0.341 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.765      ;
; 0.344 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[5]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.189      ; 0.768      ;
; 0.382 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.092      ; 0.669      ;
; 0.395 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13                                                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.497      ; 1.087      ;
; 0.399 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.669      ;
; 0.400 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.411 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0                                                                                                                                                                                                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                                                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.497      ; 1.103      ;
; 0.414 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.684      ;
; 0.415 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.415 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.415 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.415 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.436 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg[14]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.497      ; 1.128      ;
; 0.455 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.878      ;
; 0.456 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.879      ;
; 0.456 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.879      ;
; 0.457 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.880      ;
; 0.457 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.880      ;
; 0.457 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.880      ;
; 0.457 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.880      ;
; 0.463 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.886      ;
; 0.465 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_25|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_24|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.735      ;
; 0.466 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[28]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[28]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[27]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[27]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[20]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[20]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[25]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[25]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[22]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[22]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[19]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[19]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[12]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[12]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[18]                                                                                                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[17]                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[4]                                                                                                                                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_26__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_25__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_23__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_22__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_21__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_20__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[29]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[28]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[11]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[10]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[10]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[9]                                                                                                                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_30|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_29|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_27|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_26|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_17|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[26]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[26]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[24]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[24]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[23]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[23]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[21]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[21]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[17]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[17]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[13]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[13]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[11]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[11]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[5]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[5]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[13]                                                                                                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[12]                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg_0                                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_30__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_29__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_28__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_27__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_6__Z                                                                                                                                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_5__Z                                                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_1__Z                                                                                                                                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_0__Z                                                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_28|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_27|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_23|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_19|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.469 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_1__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_i_0_0__Z                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[18]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[18]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[16]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[16]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[15]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[15]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[4]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[4]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.739      ;
; 0.469 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[6]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.739      ;
; 0.469 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_24__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_23__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.739      ;
; 0.469 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_14__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_12__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[6]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[6]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[5]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[5]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[4]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[4]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[3]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[2]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[30]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[15]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[14]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[13]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[12]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
; 0.469 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg_0                                                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.738      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                        ; To Node                                                                                                                                                                 ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -2.846 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.832      ;
; -2.846 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.832      ;
; -2.817 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.802      ;
; -2.795 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.715      ;
; -2.795 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.715      ;
; -2.742 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.662      ;
; -2.742 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.662      ;
; -2.715 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.701      ;
; -2.715 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.701      ;
; -2.700 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.620      ;
; -2.700 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.620      ;
; -2.686 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.671      ;
; -2.658 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 3.580      ;
; -2.658 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 3.580      ;
; -2.630 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.616      ;
; -2.630 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.616      ;
; -2.628 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.548      ;
; -2.628 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.548      ;
; -2.625 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.611      ;
; -2.625 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.611      ;
; -2.605 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 3.527      ;
; -2.605 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 3.527      ;
; -2.601 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.586      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.581      ;
; -2.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 3.485      ;
; -2.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 3.485      ;
; -2.553 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.526      ;
; -2.530 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.516      ;
; -2.530 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.516      ;
; -2.501 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.486      ;
; -2.496 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.482      ;
; -2.496 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.482      ;
; -2.491 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 3.413      ;
; -2.491 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 3.413      ;
; -2.468 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 3.409      ;
; -2.468 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 3.409      ;
; -2.467 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.452      ;
; -2.443 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 3.384      ;
; -2.443 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 3.384      ;
; -2.439 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.062     ; 3.379      ;
; -2.422 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.408      ;
; -2.422 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 3.408      ;
; -2.422 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.395      ;
; -2.414 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.062     ; 3.354      ;
; -2.414 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.399      ;
; -2.414 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.399      ;
; -2.393 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.003      ; 3.378      ;
; -2.385 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.002      ; 3.369      ;
; -2.354 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.327      ;
; -2.342 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.315      ;
; -2.332 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.408      ; 3.722      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.325 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.298      ;
; -2.299 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 3.240      ;
; -2.299 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 3.240      ;
; -2.270 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.062     ; 3.210      ;
; -2.247 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.220      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.167      ;
; -2.203 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.009     ; 3.176      ;
; -2.195 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 3.136      ;
; -2.195 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 3.136      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.114      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'CLK_REF'                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -2.387 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.188     ; 3.181      ;
; -2.334 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.188     ; 3.128      ;
; -2.292 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.188     ; 3.086      ;
; -2.251 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.193     ; 3.040      ;
; -2.220 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.188     ; 3.014      ;
; -2.198 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.193     ; 2.987      ;
; -2.156 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.193     ; 2.945      ;
; -2.084 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.193     ; 2.873      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.335      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.282      ;
; -2.000 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.192     ; 2.790      ;
; -2.000 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.192     ; 2.790      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.983 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.240      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.975 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.766      ;
; -1.947 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.192     ; 2.737      ;
; -1.947 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.192     ; 2.737      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.730      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.922 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.713      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.275      ; 3.168      ;
; -1.905 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.192     ; 2.695      ;
; -1.905 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.192     ; 2.695      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.885 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.190     ; 2.677      ;
; -1.880 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.671      ;
; -1.880 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.671      ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                                                     ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 1.262 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.070      ; 1.527      ;
; 1.262 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.070      ; 1.527      ;
; 1.262 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.070      ; 1.527      ;
; 1.262 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.070      ; 1.527      ;
; 1.282 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_8|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.552      ;
; 1.282 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_10|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.552      ;
; 1.282 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_9|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.552      ;
; 1.282 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_3|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.552      ;
; 1.282 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_2|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.552      ;
; 1.282 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_1|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 1.552      ;
; 1.486 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.078      ; 1.759      ;
; 1.486 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_14|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.078      ; 1.759      ;
; 1.486 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_15|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.078      ; 1.759      ;
; 1.486 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_7|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.078      ; 1.759      ;
; 1.486 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_6|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.078      ; 1.759      ;
; 1.545 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_13|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.823      ;
; 1.545 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_12|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.823      ;
; 1.545 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_5|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.823      ;
; 1.545 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_4|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 1.823      ;
; 1.550 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.826      ;
; 1.550 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.826      ;
; 1.550 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_17|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.826      ;
; 1.550 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_0|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.826      ;
; 1.556 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.064      ; 1.335      ;
; 1.556 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.064      ; 1.335      ;
; 1.556 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.064      ; 1.335      ;
; 1.556 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.064      ; 1.335      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.489      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.489      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.489      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.489      ;
; 1.746 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.524      ;
; 1.746 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.524      ;
; 1.746 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.524      ;
; 1.746 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.524      ;
; 1.971 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.509      ; 2.675      ;
; 2.072 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.509      ; 2.776      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.127 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.396      ;
; 2.157 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.621      ; 3.013      ;
; 2.165 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.622      ; 3.022      ;
; 2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.458      ;
; 2.210 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.509      ; 2.914      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.222 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.186      ; 2.643      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.228 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 2.497      ;
; 2.233 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.509      ; 2.937      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.236 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 2.658      ;
; 2.237 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.622      ; 3.094      ;
; 2.256 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.522      ;
; 2.270 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.622      ; 3.127      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
; 2.301 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 2.571      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'CLK_REF'                                                                                                                                                                                                                             ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 1.633 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.421      ; 2.289      ;
; 1.647 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.467      ; 2.349      ;
; 1.697 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.421      ; 2.353      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.467      ; 2.413      ;
; 1.827 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.421      ; 2.483      ;
; 1.841 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.467      ; 2.543      ;
; 1.861 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.421      ; 2.517      ;
; 1.875 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.467      ; 2.577      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.692      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.222      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.251      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.756      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.044 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.286      ;
; 2.049 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.005      ; 2.289      ;
; 2.049 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.005      ; 2.289      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.006      ; 2.315      ;
; 2.113 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.005      ; 2.353      ;
; 2.113 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.005      ; 2.353      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.886      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.174 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.416      ;
; 2.193 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.920      ;
; 2.193 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.920      ;
; 2.193 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.920      ;
; 2.193 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.920      ;
; 2.193 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.492      ; 2.920      ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_REF'                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; -7.458 ; -7.242       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ;
; -7.439 ; -7.223       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ;
; -7.427 ; -7.211       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ;
; -7.191 ; -7.191       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_2_0_component_c11|clko_s_Z|clk                                                                                 ;
; -7.169 ; -7.169       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|outstate_Z|clk                                                                              ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_0_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_10_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_11_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_12_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_13_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_14_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_15_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_16_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_17_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_18_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_19_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_1_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_20_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_21_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_22_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_23_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_24_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_25_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_26_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_27_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_28_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_29_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_2_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_30_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_31_|clk                                                                               ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_3_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_4_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_5_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_6_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_7_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_8_|clk                                                                                ;
; -7.157 ; -7.157       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_9_|clk                                                                                ;
; -7.152 ; -7.152       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|inclk[0]                                                                      ;
; -7.152 ; -7.152       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|outclk                                                                        ;
; -6.980 ; -6.980       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -6.969 ; -6.969       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|combout                                                                            ;
; -6.957 ; -6.957       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|dataa                                                                         ;
; -6.340 ; -6.124       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ;
; -6.340 ; -6.124       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ;
; -6.340 ; -6.124       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ;
; -6.102 ; -6.102       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|datad                                                                              ;
; -6.070 ; -6.070       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_A_Z|clk                                                                               ;
; -6.070 ; -6.070       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_B_Z|clk                                                                               ;
; -6.070 ; -6.070       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_C_Z|clk                                                                               ;
; -5.970 ; -5.970       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout                                                                              ;
; -5.958 ; -5.742       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ;
; -5.958 ; -5.742       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ;
; -5.958 ; -5.742       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_C ;
; -5.932 ; -5.932       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|combout                                                                         ;
; -5.924 ; -5.924       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|datad                                                                                ;
; -5.830 ; -5.830       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|datab                                                                              ;
; -5.734 ; -5.734       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|combout                                                                           ;
; -5.727 ; -5.727       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|datad                                                                           ;
; -5.704 ; -5.704       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_9_0_component_c8|clko_x_cZ|combout                                                                             ;
; -5.688 ; -5.688       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|datad                                                                             ;
; -5.688 ; -5.688       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|sig_A_Z|clk                                                                               ;
; -5.688 ; -5.688       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|sig_B_Z|clk                                                                               ;
; -5.688 ; -5.688       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|sig_C_Z|clk                                                                               ;
; -5.687 ; -5.687       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|dataa                                                                           ;
; -4.884 ; -4.884       ; 0.000          ; Low Pulse Width  ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|dataa                                                                         ;
; -4.873 ; -4.873       ; 0.000          ; Low Pulse Width  ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|combout                                                                            ;
; -4.873 ; -4.873       ; 0.000          ; Low Pulse Width  ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -4.825 ; -4.641       ; 0.184          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ;
; -4.825 ; -4.641       ; 0.184          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock   ; Clock Edge ; Target                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT0  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT1  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT2  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT3  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT0 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT1 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT2 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT3 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a2~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a2~porta_datain_reg0              ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[10]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[11]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[12]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[1]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[2]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[3]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[4]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[5]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[6]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[7]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[8]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[9]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0 ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_1    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_10   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_11   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_12   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_15   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_5    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_6    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_7    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_8    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_9    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[10]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[11]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[12]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[13]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[15]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[16]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[17]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[18]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[19]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[1]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[20]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[21]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[22]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[23]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[24]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[25]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[26]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[27]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[28]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[29]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[2]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[30]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[3]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[4]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[5]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[6]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[7]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[8]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[9]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_20   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_28   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_4    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_6    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_7    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[1]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]  ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                              ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                      ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ;
; -0.036 ; 0.180        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ;
; -0.036 ; 0.180        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ;
; -0.036 ; 0.180        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ;
; -0.036 ; 0.180        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ;
; 0.005  ; 0.221        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ;
; 0.005  ; 0.221        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ;
; 0.005  ; 0.221        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]   ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]  ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ;
; 0.006  ; 0.222        ; 0.216          ; High Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------+
; Setup Times                                                                      ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; 4.749  ; 4.450  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 4.000  ; 3.696  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 3.875  ; 3.682  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 4.183  ; 4.031  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 3.818  ; 3.613  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.303  ; 4.025  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 4.113  ; 3.862  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 4.749  ; 4.450  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 4.267  ; 3.885  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 3.918  ; 3.710  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 4.536  ; 4.105  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.208  ; 4.009  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 4.075  ; 3.819  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 4.390  ; 4.166  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 4.027  ; 3.712  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 4.129  ; 3.945  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 4.160  ; 3.943  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 4.512  ; 4.314  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.491  ; 3.407  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 4.331  ; 4.076  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 4.223  ; 4.145  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 4.119  ; 3.915  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 3.937  ; 3.786  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.309  ; 4.031  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 4.201  ; 3.979  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 3.204  ; 3.215  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 3.972  ; 3.718  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 3.954  ; 3.893  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 4.324  ; 4.084  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 3.870  ; 3.604  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 3.783  ; 3.616  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 4.075  ; 3.930  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.118  ; 3.924  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 4.512  ; 4.314  ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; 4.934  ; 4.793  ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; 16.099 ; 14.423 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.358  ; 0.766  ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; 4.017  ; 3.955  ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; 3.459  ; 3.548  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Hold Times                                                                       ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; -1.437 ; -1.491 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; -1.437 ; -1.548 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; -1.609 ; -1.679 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; -2.259 ; -2.333 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; -1.993 ; -2.102 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; -2.076 ; -2.122 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; -1.635 ; -1.757 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; -2.135 ; -2.177 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; -1.960 ; -1.929 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; -1.657 ; -1.739 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; -1.927 ; -1.895 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; -1.933 ; -1.991 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; -1.727 ; -1.779 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; -2.102 ; -2.145 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; -1.454 ; -1.491 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; -1.874 ; -1.937 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; -1.854 ; -1.928 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; -1.395 ; -1.485 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; -2.456 ; -2.406 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; -3.145 ; -3.067 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; -2.006 ; -2.155 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; -1.829 ; -1.904 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; -3.161 ; -3.087 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; -3.159 ; -3.018 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; -1.983 ; -2.076 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; -2.619 ; -2.596 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; -1.726 ; -1.803 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; -1.751 ; -1.835 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; -1.661 ; -1.773 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; -1.395 ; -1.485 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; -1.494 ; -1.622 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; -1.872 ; -2.006 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; -1.880 ; -2.010 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; -1.874 ; -1.986 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; -1.723 ; -1.877 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; -6.579 ; -6.276 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.018  ; -0.367 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; -2.029 ; -2.054 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; -1.734 ; -1.904 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                   ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                                                 ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                            ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; SRAM0_A[*]     ; CLK_BRD                                                                                                    ; 19.484 ; 18.711 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[0]    ; CLK_BRD                                                                                                    ; 16.301 ; 15.661 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[1]    ; CLK_BRD                                                                                                    ; 16.524 ; 16.086 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[2]    ; CLK_BRD                                                                                                    ; 15.488 ; 15.161 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[3]    ; CLK_BRD                                                                                                    ; 16.650 ; 16.197 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[4]    ; CLK_BRD                                                                                                    ; 15.843 ; 15.404 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[5]    ; CLK_BRD                                                                                                    ; 16.047 ; 15.717 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[6]    ; CLK_BRD                                                                                                    ; 17.216 ; 16.959 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[7]    ; CLK_BRD                                                                                                    ; 19.484 ; 18.711 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[8]    ; CLK_BRD                                                                                                    ; 17.561 ; 17.281 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[9]    ; CLK_BRD                                                                                                    ; 18.296 ; 17.796 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[10]   ; CLK_BRD                                                                                                    ; 17.025 ; 16.671 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[11]   ; CLK_BRD                                                                                                    ; 16.622 ; 15.991 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[12]   ; CLK_BRD                                                                                                    ; 16.044 ; 15.730 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[13]   ; CLK_BRD                                                                                                    ; 17.494 ; 17.040 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[14]   ; CLK_BRD                                                                                                    ; 18.740 ; 18.310 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[15]   ; CLK_BRD                                                                                                    ; 16.261 ; 15.876 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[16]   ; CLK_BRD                                                                                                    ; 15.720 ; 15.290 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[17]   ; CLK_BRD                                                                                                    ; 17.786 ; 17.173 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_D[*]     ; CLK_BRD                                                                                                    ; 9.678  ; 9.119  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[0]    ; CLK_BRD                                                                                                    ; 8.413  ; 7.965  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[1]    ; CLK_BRD                                                                                                    ; 8.093  ; 7.665  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[2]    ; CLK_BRD                                                                                                    ; 8.461  ; 7.989  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[3]    ; CLK_BRD                                                                                                    ; 8.208  ; 7.819  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[4]    ; CLK_BRD                                                                                                    ; 7.676  ; 7.460  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[5]    ; CLK_BRD                                                                                                    ; 9.241  ; 8.653  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[6]    ; CLK_BRD                                                                                                    ; 7.406  ; 7.188  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[7]    ; CLK_BRD                                                                                                    ; 9.328  ; 8.988  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[8]    ; CLK_BRD                                                                                                    ; 8.834  ; 8.275  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[9]    ; CLK_BRD                                                                                                    ; 8.470  ; 8.121  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[10]   ; CLK_BRD                                                                                                    ; 9.302  ; 8.766  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[11]   ; CLK_BRD                                                                                                    ; 9.678  ; 9.119  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[12]   ; CLK_BRD                                                                                                    ; 9.455  ; 9.018  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[13]   ; CLK_BRD                                                                                                    ; 7.568  ; 7.349  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[14]   ; CLK_BRD                                                                                                    ; 9.127  ; 8.625  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[15]   ; CLK_BRD                                                                                                    ; 7.735  ; 7.331  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_E        ; CLK_BRD                                                                                                    ; 20.631 ; 20.346 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_LB       ; CLK_BRD                                                                                                    ; 19.946 ; 19.805 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_OE       ; CLK_BRD                                                                                                    ; 18.218 ; 18.349 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_UB       ; CLK_BRD                                                                                                    ; 19.655 ; 19.526 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_W        ; CLK_BRD                                                                                                    ; 7.532  ; 7.731  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_A[*]     ; CLK_BRD                                                                                                    ; 18.929 ; 18.754 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[0]    ; CLK_BRD                                                                                                    ; 14.830 ; 14.572 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[1]    ; CLK_BRD                                                                                                    ; 17.317 ; 17.091 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[2]    ; CLK_BRD                                                                                                    ; 15.925 ; 15.568 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[3]    ; CLK_BRD                                                                                                    ; 16.367 ; 16.010 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[4]    ; CLK_BRD                                                                                                    ; 15.461 ; 15.051 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[5]    ; CLK_BRD                                                                                                    ; 15.668 ; 15.354 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[6]    ; CLK_BRD                                                                                                    ; 18.929 ; 18.754 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[7]    ; CLK_BRD                                                                                                    ; 16.150 ; 15.797 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[8]    ; CLK_BRD                                                                                                    ; 18.188 ; 17.787 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[9]    ; CLK_BRD                                                                                                    ; 18.260 ; 17.775 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[10]   ; CLK_BRD                                                                                                    ; 17.031 ; 16.636 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[11]   ; CLK_BRD                                                                                                    ; 16.985 ; 16.323 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[12]   ; CLK_BRD                                                                                                    ; 16.781 ; 16.373 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[13]   ; CLK_BRD                                                                                                    ; 18.124 ; 17.881 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[14]   ; CLK_BRD                                                                                                    ; 16.228 ; 15.816 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[15]   ; CLK_BRD                                                                                                    ; 16.266 ; 15.875 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[16]   ; CLK_BRD                                                                                                    ; 15.111 ; 14.814 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[17]   ; CLK_BRD                                                                                                    ; 16.792 ; 16.400 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_D[*]     ; CLK_BRD                                                                                                    ; 9.459  ; 8.906  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[0]    ; CLK_BRD                                                                                                    ; 6.766  ; 6.584  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[1]    ; CLK_BRD                                                                                                    ; 8.679  ; 8.135  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[2]    ; CLK_BRD                                                                                                    ; 8.756  ; 8.176  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[3]    ; CLK_BRD                                                                                                    ; 8.858  ; 8.337  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[4]    ; CLK_BRD                                                                                                    ; 8.231  ; 7.903  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[5]    ; CLK_BRD                                                                                                    ; 8.613  ; 8.245  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[6]    ; CLK_BRD                                                                                                    ; 8.210  ; 7.974  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[7]    ; CLK_BRD                                                                                                    ; 9.459  ; 8.906  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[8]    ; CLK_BRD                                                                                                    ; 8.106  ; 7.853  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[9]    ; CLK_BRD                                                                                                    ; 7.971  ; 7.682  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[10]   ; CLK_BRD                                                                                                    ; 8.839  ; 8.326  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[11]   ; CLK_BRD                                                                                                    ; 8.006  ; 7.683  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[12]   ; CLK_BRD                                                                                                    ; 7.712  ; 7.357  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[13]   ; CLK_BRD                                                                                                    ; 8.361  ; 7.826  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[14]   ; CLK_BRD                                                                                                    ; 8.383  ; 7.888  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[15]   ; CLK_BRD                                                                                                    ; 7.728  ; 7.391  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_E        ; CLK_BRD                                                                                                    ; 21.128 ; 20.820 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_LB       ; CLK_BRD                                                                                                    ; 20.339 ; 20.160 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_OE       ; CLK_BRD                                                                                                    ; 19.563 ; 19.548 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_UB       ; CLK_BRD                                                                                                    ; 20.274 ; 20.067 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_W        ; CLK_BRD                                                                                                    ; 8.631  ; 8.674  ; Rise       ; CLK_BRD                                                                                                    ;
; DAC_CLK        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 8.704  ; 8.319  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_CS         ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 10.090 ; 9.604  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_DOUT       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 9.926  ; 9.548  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                                             ; 14.902 ; 13.611 ; Rise       ; JTAG_NEXUS_TCK                                                                                             ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                           ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                                                 ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                            ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; SRAM0_A[*]     ; CLK_BRD                                                                                                    ; 8.370  ; 7.855  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[0]    ; CLK_BRD                                                                                                    ; 9.634  ; 8.883  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[1]    ; CLK_BRD                                                                                                    ; 8.863  ; 8.316  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[2]    ; CLK_BRD                                                                                                    ; 8.370  ; 7.927  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[3]    ; CLK_BRD                                                                                                    ; 8.708  ; 8.076  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[4]    ; CLK_BRD                                                                                                    ; 9.052  ; 8.489  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[5]    ; CLK_BRD                                                                                                    ; 8.868  ; 8.438  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[6]    ; CLK_BRD                                                                                                    ; 9.928  ; 9.487  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[7]    ; CLK_BRD                                                                                                    ; 12.561 ; 11.690 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[8]    ; CLK_BRD                                                                                                    ; 9.179  ; 8.703  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[9]    ; CLK_BRD                                                                                                    ; 10.900 ; 10.152 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[10]   ; CLK_BRD                                                                                                    ; 10.059 ; 9.441  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[11]   ; CLK_BRD                                                                                                    ; 9.565  ; 8.873  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[12]   ; CLK_BRD                                                                                                    ; 8.780  ; 8.275  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[13]   ; CLK_BRD                                                                                                    ; 9.594  ; 8.967  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[14]   ; CLK_BRD                                                                                                    ; 12.040 ; 11.563 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[15]   ; CLK_BRD                                                                                                    ; 8.861  ; 8.435  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[16]   ; CLK_BRD                                                                                                    ; 8.380  ; 7.855  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[17]   ; CLK_BRD                                                                                                    ; 10.076 ; 9.216  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_D[*]     ; CLK_BRD                                                                                                    ; 7.244  ; 7.033  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[0]    ; CLK_BRD                                                                                                    ; 8.203  ; 7.769  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[1]    ; CLK_BRD                                                                                                    ; 7.894  ; 7.481  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[2]    ; CLK_BRD                                                                                                    ; 8.249  ; 7.793  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[3]    ; CLK_BRD                                                                                                    ; 8.005  ; 7.628  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[4]    ; CLK_BRD                                                                                                    ; 7.503  ; 7.293  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[5]    ; CLK_BRD                                                                                                    ; 9.004  ; 8.438  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[6]    ; CLK_BRD                                                                                                    ; 7.244  ; 7.033  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[7]    ; CLK_BRD                                                                                                    ; 9.088  ; 8.760  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[8]    ; CLK_BRD                                                                                                    ; 8.614  ; 8.076  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[9]    ; CLK_BRD                                                                                                    ; 8.266  ; 7.928  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[10]   ; CLK_BRD                                                                                                    ; 9.063  ; 8.548  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[11]   ; CLK_BRD                                                                                                    ; 9.426  ; 8.887  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[12]   ; CLK_BRD                                                                                                    ; 9.202  ; 8.779  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[13]   ; CLK_BRD                                                                                                    ; 7.392  ; 7.178  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[14]   ; CLK_BRD                                                                                                    ; 8.889  ; 8.404  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[15]   ; CLK_BRD                                                                                                    ; 7.552  ; 7.161  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_E        ; CLK_BRD                                                                                                    ; 9.887  ; 9.228  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_LB       ; CLK_BRD                                                                                                    ; 9.240  ; 8.772  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_OE       ; CLK_BRD                                                                                                    ; 7.583  ; 7.376  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_UB       ; CLK_BRD                                                                                                    ; 8.836  ; 8.434  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_W        ; CLK_BRD                                                                                                    ; 7.362  ; 7.556  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_A[*]     ; CLK_BRD                                                                                                    ; 7.796  ; 7.398  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[0]    ; CLK_BRD                                                                                                    ; 8.224  ; 7.838  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[1]    ; CLK_BRD                                                                                                    ; 9.683  ; 9.344  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[2]    ; CLK_BRD                                                                                                    ; 8.790  ; 8.320  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[3]    ; CLK_BRD                                                                                                    ; 8.437  ; 7.897  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[4]    ; CLK_BRD                                                                                                    ; 8.684  ; 8.148  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[5]    ; CLK_BRD                                                                                                    ; 8.504  ; 8.089  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[6]    ; CLK_BRD                                                                                                    ; 11.626 ; 11.269 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[7]    ; CLK_BRD                                                                                                    ; 9.305  ; 8.833  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[8]    ; CLK_BRD                                                                                                    ; 9.781  ; 9.188  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[9]    ; CLK_BRD                                                                                                    ; 10.868 ; 10.134 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[10]   ; CLK_BRD                                                                                                    ; 10.065 ; 9.409  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[11]   ; CLK_BRD                                                                                                    ; 9.914  ; 9.192  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[12]   ; CLK_BRD                                                                                                    ; 9.488  ; 8.893  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[13]   ; CLK_BRD                                                                                                    ; 10.252 ; 9.833  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[14]   ; CLK_BRD                                                                                                    ; 9.574  ; 9.110  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[15]   ; CLK_BRD                                                                                                    ; 8.865  ; 8.433  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[16]   ; CLK_BRD                                                                                                    ; 7.796  ; 7.398  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[17]   ; CLK_BRD                                                                                                    ; 9.122  ; 8.475  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_D[*]     ; CLK_BRD                                                                                                    ; 6.620  ; 6.442  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[0]    ; CLK_BRD                                                                                                    ; 6.620  ; 6.442  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[1]    ; CLK_BRD                                                                                                    ; 8.457  ; 7.932  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[2]    ; CLK_BRD                                                                                                    ; 8.532  ; 7.972  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[3]    ; CLK_BRD                                                                                                    ; 8.628  ; 8.125  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[4]    ; CLK_BRD                                                                                                    ; 8.026  ; 7.709  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[5]    ; CLK_BRD                                                                                                    ; 8.402  ; 8.047  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[6]    ; CLK_BRD                                                                                                    ; 8.015  ; 7.787  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[7]    ; CLK_BRD                                                                                                    ; 9.215  ; 8.683  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[8]    ; CLK_BRD                                                                                                    ; 7.916  ; 7.671  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[9]    ; CLK_BRD                                                                                                    ; 7.782  ; 7.503  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[10]   ; CLK_BRD                                                                                                    ; 8.619  ; 8.125  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[11]   ; CLK_BRD                                                                                                    ; 7.821  ; 7.509  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[12]   ; CLK_BRD                                                                                                    ; 7.530  ; 7.186  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[13]   ; CLK_BRD                                                                                                    ; 8.153  ; 7.637  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[14]   ; CLK_BRD                                                                                                    ; 8.175  ; 7.696  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[15]   ; CLK_BRD                                                                                                    ; 7.544  ; 7.218  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_E        ; CLK_BRD                                                                                                    ; 10.242 ; 9.749  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_LB       ; CLK_BRD                                                                                                    ; 9.622  ; 9.053  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_OE       ; CLK_BRD                                                                                                    ; 8.876  ; 8.529  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_UB       ; CLK_BRD                                                                                                    ; 9.439  ; 8.960  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_W        ; CLK_BRD                                                                                                    ; 8.475  ; 8.514  ; Rise       ; CLK_BRD                                                                                                    ;
; DAC_CLK        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 8.444  ; 8.072  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_CS         ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 9.783  ; 9.315  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_DOUT       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 9.624  ; 9.261  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                                             ; 9.208  ; 8.550  ; Rise       ; JTAG_NEXUS_TCK                                                                                             ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------+
; Output Enable Times                                                        ;
+--------------+------------+--------+--------+------------+-----------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+--------------+------------+--------+--------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 18.342 ; 18.342 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 18.619 ; 18.619 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 19.825 ; 19.825 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 19.273 ; 19.273 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 18.581 ; 18.581 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 20.085 ; 20.085 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 19.490 ; 19.490 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 20.279 ; 20.279 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 19.441 ; 19.441 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 19.469 ; 19.469 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 19.523 ; 19.523 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 20.085 ; 20.085 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 19.566 ; 19.566 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 19.415 ; 19.415 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 18.342 ; 18.342 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 18.959 ; 18.959 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 18.939 ; 18.939 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 17.980 ; 17.980 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 17.980 ; 17.980 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 19.805 ; 19.805 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 19.577 ; 19.577 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 19.527 ; 19.527 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 19.805 ; 19.805 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 20.100 ; 20.100 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 19.520 ; 19.520 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 20.040 ; 20.040 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 19.513 ; 19.513 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 19.520 ; 19.520 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 19.556 ; 19.556 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 19.519 ; 19.519 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 18.332 ; 18.332 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 19.552 ; 19.552 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 19.562 ; 19.562 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 19.206 ; 19.206 ; Rise       ; CLK_BRD         ;
+--------------+------------+--------+--------+------------+-----------------+


+--------------------------------------------------------------------------+
; Minimum Output Enable Times                                              ;
+--------------+------------+-------+-------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+-------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 7.473 ; 7.466 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 7.738 ; 7.731 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 8.896 ; 8.889 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 8.366 ; 8.359 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 7.700 ; 7.693 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 9.154 ; 9.150 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 8.582 ; 8.578 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 9.341 ; 9.337 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 8.535 ; 8.531 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 8.562 ; 8.558 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 8.615 ; 8.611 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 9.154 ; 9.150 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 8.656 ; 8.652 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 8.501 ; 8.494 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 7.473 ; 7.466 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 8.065 ; 8.058 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 8.045 ; 8.038 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 7.123 ; 7.116 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 7.123 ; 7.116 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 8.876 ; 8.869 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 8.659 ; 8.652 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 8.609 ; 8.602 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 8.876 ; 8.869 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 9.168 ; 9.164 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 8.612 ; 8.608 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 9.112 ; 9.108 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 8.605 ; 8.601 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 8.612 ; 8.608 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 8.646 ; 8.642 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 8.612 ; 8.608 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 7.463 ; 7.456 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 8.635 ; 8.628 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 8.645 ; 8.638 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 8.301 ; 8.294 ; Rise       ; CLK_BRD         ;
+--------------+------------+-------+-------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Output Disable Times                                                             ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 18.386    ; 18.519    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 18.574    ; 18.707    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 19.554    ; 19.687    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 19.128    ; 19.261    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 18.547    ; 18.680    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 19.743    ; 19.864    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 19.277    ; 19.398    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 19.965    ; 20.086    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 19.203    ; 19.324    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 19.233    ; 19.354    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 19.308    ; 19.429    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 19.743    ; 19.864    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 19.344    ; 19.465    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 19.184    ; 19.317    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 18.386    ; 18.519    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 18.850    ; 18.983    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 18.830    ; 18.963    ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 18.089    ; 18.222    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 18.089    ; 18.222    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 19.534    ; 19.667    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 19.350    ; 19.483    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 19.300    ; 19.433    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 19.534    ; 19.667    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 19.733    ; 19.854    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 19.307    ; 19.428    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 19.635    ; 19.756    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 19.298    ; 19.419    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 19.307    ; 19.428    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 19.334    ; 19.455    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 19.301    ; 19.422    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 18.376    ; 18.509    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 19.341    ; 19.474    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 19.351    ; 19.484    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 19.066    ; 19.199    ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                     ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 7.305     ; 7.305     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 7.485     ; 7.485     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 8.426     ; 8.426     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 8.018     ; 8.018     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 7.459     ; 7.459     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 8.609     ; 8.609     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 8.160     ; 8.160     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 8.822     ; 8.822     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 8.089     ; 8.089     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 8.117     ; 8.117     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 8.191     ; 8.191     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 8.609     ; 8.609     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 8.226     ; 8.226     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 8.070     ; 8.070     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 7.305     ; 7.305     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 7.752     ; 7.752     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 7.732     ; 7.732     ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 7.019     ; 7.019     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 7.019     ; 7.019     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 8.406     ; 8.406     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 8.232     ; 8.232     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 8.182     ; 8.182     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 8.406     ; 8.406     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 8.599     ; 8.599     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 8.190     ; 8.190     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 8.506     ; 8.506     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 8.181     ; 8.181     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 8.190     ; 8.190     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 8.216     ; 8.216     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 8.185     ; 8.185     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 7.295     ; 7.295     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 8.223     ; 8.223     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 8.233     ; 8.233     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 7.957     ; 7.957     ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                                                  ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; CLK_REF                                                                                                    ; -7.255 ; -700.454      ;
; CLK_BRD                                                                                                    ; -6.864 ; -7329.211     ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; -4.366 ; -79.869       ;
; JTAG_NEXUS_TCK                                                                                             ; -2.394 ; -1603.248     ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                                                   ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; CLK_REF                                                                                                    ; -0.338 ; -0.681        ;
; CLK_BRD                                                                                                    ; -0.136 ; -0.136        ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.063  ; 0.000         ;
; JTAG_NEXUS_TCK                                                                                             ; 0.083  ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------+
; Fast 1200mV 0C Model Recovery Summary   ;
+----------------+--------+---------------+
; Clock          ; Slack  ; End Point TNS ;
+----------------+--------+---------------+
; JTAG_NEXUS_TCK ; -0.832 ; -30.838       ;
; CLK_REF        ; -0.669 ; -17.989       ;
+----------------+--------+---------------+


+----------------------------------------+
; Fast 1200mV 0C Model Removal Summary   ;
+----------------+-------+---------------+
; Clock          ; Slack ; End Point TNS ;
+----------------+-------+---------------+
; JTAG_NEXUS_TCK ; 0.569 ; 0.000         ;
; CLK_REF        ; 0.808 ; 0.000         ;
+----------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                                                    ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; CLK_REF                                                                                                    ; -3.208 ; -954.905      ;
; CLK_BRD                                                                                                    ; -3.000 ; -1975.537     ;
; JTAG_NEXUS_TCK                                                                                             ; -3.000 ; -1213.921     ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; -1.000 ; -56.000       ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLK_REF'                                                                                                                                                                                                                                                                                      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                        ; To Node                                                                                                ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -7.255 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.055     ; 2.187      ;
; -7.255 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.055     ; 2.187      ;
; -7.041 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.111     ; 6.917      ;
; -7.041 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.111     ; 6.917      ;
; -7.031 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.751     ; 2.267      ;
; -7.031 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.751     ; 2.267      ;
; -6.995 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.111     ; 6.871      ;
; -6.995 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.111     ; 6.871      ;
; -6.855 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.427     ; 7.395      ;
; -6.855 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.427     ; 7.395      ;
; -6.820 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.209     ; 4.598      ;
; -6.820 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.209     ; 4.598      ;
; -6.743 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.064     ; 2.666      ;
; -6.743 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.064     ; 2.666      ;
; -6.730 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 0.500        ; 1.393      ; 8.610      ;
; -6.730 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 0.500        ; 1.393      ; 8.610      ;
; -6.675 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.099      ; 7.761      ;
; -6.675 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.099      ; 7.761      ;
; -6.667 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.009     ; 5.645      ;
; -6.667 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.009     ; 5.645      ;
; -6.665 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.073     ; 7.559      ;
; -6.638 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.099      ; 7.724      ;
; -6.638 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.099      ; 7.724      ;
; -6.623 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.446     ; 7.164      ;
; -6.623 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.446     ; 7.164      ;
; -6.611 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.064     ; 2.534      ;
; -6.611 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.064     ; 2.534      ;
; -6.533 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.009     ; 5.511      ;
; -6.533 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.009     ; 5.511      ;
; -6.510 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.404     ; 6.093      ;
; -6.510 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.404     ; 6.093      ;
; -6.490 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.446     ; 7.031      ;
; -6.490 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.446     ; 7.031      ;
; -6.456 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.404     ; 6.039      ;
; -6.456 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.404     ; 6.039      ;
; -6.423 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.462     ; 4.948      ;
; -6.423 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.462     ; 4.948      ;
; -6.393 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.168     ; 4.212      ;
; -6.393 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.168     ; 4.212      ;
; -6.368 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.462     ; 4.893      ;
; -6.368 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.462     ; 4.893      ;
; -6.340 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.429     ; 3.898      ;
; -6.340 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.429     ; 3.898      ;
; -6.329 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.028     ; 3.288      ;
; -6.329 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.028     ; 3.288      ;
; -6.294 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.429     ; 3.852      ;
; -6.294 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.429     ; 3.852      ;
; -6.292 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.509     ; 2.770      ;
; -6.292 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.509     ; 2.770      ;
; -6.250 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -6.063     ; 1.174      ;
; -6.201 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.028     ; 3.160      ;
; -6.201 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.028     ; 3.160      ;
; -6.195 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|un1_g3[0]                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.841     ; 4.341      ;
; -6.195 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|un1_g3[0]                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.841     ; 4.341      ;
; -6.181 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.427     ; 6.721      ;
; -6.181 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.427     ; 6.721      ;
; -6.159 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.509     ; 2.637      ;
; -6.159 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.509     ; 2.637      ;
; -6.036 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.119     ; 5.904      ;
; -6.026 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.759     ; 1.254      ;
; -6.003 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|un1_sig_B_x[0]                                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.938     ; 4.052      ;
; -6.003 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|un1_sig_B_x[0]                                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.938     ; 4.052      ;
; -5.990 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.119     ; 5.858      ;
; -5.850 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.435     ; 6.382      ;
; -5.815 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.217     ; 3.585      ;
; -5.809 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.427     ; 6.349      ;
; -5.809 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.427     ; 6.349      ;
; -5.738 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.072     ; 1.653      ;
; -5.725 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 0.500        ; 1.385      ; 7.597      ;
; -5.670 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.091      ; 6.748      ;
; -5.662 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.017     ; 4.632      ;
; -5.633 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; 0.091      ; 6.711      ;
; -5.618 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.454     ; 6.151      ;
; -5.606 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -5.072     ; 1.521      ;
; -5.528 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.017     ; 4.498      ;
; -5.505 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.412     ; 5.080      ;
; -5.485 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.454     ; 6.018      ;
; -5.483 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 1.393      ; 7.863      ;
; -5.483 ; CLK_REF                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; 1.393      ; 7.863      ;
; -5.451 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -1.412     ; 5.026      ;
; -5.440 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.053     ; 6.374      ;
; -5.440 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.053     ; 6.374      ;
; -5.418 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.470     ; 3.935      ;
; -5.388 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.176     ; 3.199      ;
; -5.363 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -2.470     ; 3.880      ;
; -5.355 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_18__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.043     ; 6.299      ;
; -5.355 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_18__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.043     ; 6.299      ;
; -5.352 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_15__Z                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.035     ; 6.304      ;
; -5.335 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.437     ; 2.885      ;
; -5.324 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.036     ; 2.275      ;
; -5.289 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -3.437     ; 2.839      ;
; -5.289 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_18__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_15__Z                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.047     ; 6.229      ;
; -5.287 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|clken_ff_Z                                                           ; CLK_REF        ; CLK_REF     ; 1.000        ; -4.517     ; 1.757      ;
; -5.286 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_4__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.053     ; 6.220      ;
; -5.286 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_4__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.053     ; 6.220      ;
; -5.282 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_16__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.054     ; 6.215      ;
; -5.282 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_16__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.054     ; 6.215      ;
; -5.269 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_20__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_1__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.054     ; 6.202      ;
; -5.269 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_20__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_nxt_0__Z                                   ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.054     ; 6.202      ;
; -5.267 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_0__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_6__Z                            ; CLK_REF        ; CLK_REF     ; 1.000        ; -0.037     ; 6.217      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -6.864 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.014      ; 7.865      ;
; -6.775 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.020      ; 7.782      ;
; -6.725 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.165     ; 7.547      ;
; -6.718 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.018      ; 7.723      ;
; -6.713 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.023      ; 7.723      ;
; -6.707 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.525      ;
; -6.706 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.008      ; 7.701      ;
; -6.680 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.001      ; 7.668      ;
; -6.678 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.161     ; 7.504      ;
; -6.677 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.156     ; 7.508      ;
; -6.672 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.025      ; 7.684      ;
; -6.668 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.009     ; 7.646      ;
; -6.663 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.164     ; 7.486      ;
; -6.663 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.012      ; 7.662      ;
; -6.649 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.010      ; 7.646      ;
; -6.643 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.016      ; 7.646      ;
; -6.640 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.178     ; 7.449      ;
; -6.639 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.162     ; 7.464      ;
; -6.636 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.022      ; 7.645      ;
; -6.623 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.162     ; 7.448      ;
; -6.621 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.451      ;
; -6.615 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.012      ; 7.614      ;
; -6.610 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.028      ; 7.625      ;
; -6.605 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.001     ; 7.591      ;
; -6.592 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.010      ; 7.589      ;
; -6.581 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.164     ; 7.404      ;
; -6.580 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.167     ; 7.400      ;
; -6.579 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.161     ; 7.405      ;
; -6.574 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.151     ; 7.410      ;
; -6.564 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.020      ; 7.571      ;
; -6.561 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.165     ; 7.383      ;
; -6.560 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.364      ;
; -6.560 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.390      ;
; -6.558 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.005      ; 7.550      ;
; -6.557 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.012      ; 7.556      ;
; -6.555 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.359      ;
; -6.546 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.005     ; 7.528      ;
; -6.544 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.018      ; 7.549      ;
; -6.543 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.014      ; 7.544      ;
; -6.541 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.178     ; 7.350      ;
; -6.538 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.020      ; 7.545      ;
; -6.537 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.160     ; 7.364      ;
; -6.537 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.004      ; 7.528      ;
; -6.536 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.366      ;
; -6.533 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.027      ; 7.547      ;
; -6.531 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.350      ;
; -6.531 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_30   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.335      ;
; -6.531 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_28   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.350      ;
; -6.527 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.012      ; 7.526      ;
; -6.523 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.182     ; 7.328      ;
; -6.518 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.152     ; 7.353      ;
; -6.518 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.174     ; 7.331      ;
; -6.517 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.160     ; 7.344      ;
; -6.512 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.160     ; 7.339      ;
; -6.512 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.017      ; 7.516      ;
; -6.508 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.166     ; 7.329      ;
; -6.507 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.175     ; 7.319      ;
; -6.506 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.171     ; 7.322      ;
; -6.506 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.172     ; 7.321      ;
; -6.505 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.003     ; 7.489      ;
; -6.502 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.015      ; 7.504      ;
; -6.502 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.186     ; 7.303      ;
; -6.499 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.177     ; 7.309      ;
; -6.498 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.165     ; 7.320      ;
; -6.495 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.019      ; 7.501      ;
; -6.494 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.156     ; 7.325      ;
; -6.493 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.185     ; 7.295      ;
; -6.492 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.164     ; 7.315      ;
; -6.491 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_19   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.167     ; 7.311      ;
; -6.483 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.003      ; 7.473      ;
; -6.482 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.008      ; 7.477      ;
; -6.481 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.003      ; 7.471      ;
; -6.480 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.008      ; 7.475      ;
; -6.479 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.177     ; 7.289      ;
; -6.479 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.161     ; 7.305      ;
; -6.479 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.297      ;
; -6.478 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.159     ; 7.306      ;
; -6.475 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.181     ; 7.281      ;
; -6.474 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_21   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.177     ; 7.284      ;
; -6.465 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.014      ; 7.466      ;
; -6.461 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.025      ; 7.473      ;
; -6.460 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_30   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.162     ; 7.285      ;
; -6.458 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a4~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.152     ; 7.293      ;
; -6.457 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.152     ; 7.292      ;
; -6.457 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.002      ; 7.446      ;
; -6.456 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0    ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.003      ; 7.446      ;
; -6.454 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.002      ; 7.443      ;
; -6.454 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.017      ; 7.458      ;
; -6.454 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_1 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.175     ; 7.266      ;
; -6.453 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.004      ; 7.444      ;
; -6.453 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; 0.013      ; 7.453      ;
; -6.453 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_19   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.184     ; 7.256      ;
; -6.452 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_24   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.167     ; 7.272      ;
; -6.449 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.177     ; 7.259      ;
; -6.448 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_26   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.166     ; 7.269      ;
; -6.448 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.172     ; 7.263      ;
; -6.448 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.174     ; 7.261      ;
; -6.446 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.156     ; 7.277      ;
; -6.444 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_mqc2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_27   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.170     ; 7.261      ;
; -6.442 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18   ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.009     ; 7.420      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                            ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                               ; To Node                                                                       ; Launch Clock                                                                                               ; Latch Clock                                                                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; -4.366 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 5.315      ;
; -4.366 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.505      ;
; -4.366 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.505      ;
; -4.366 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.505      ;
; -4.366 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.505      ;
; -4.325 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 5.273      ;
; -4.181 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 5.129      ;
; -4.181 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.319      ;
; -4.181 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.319      ;
; -4.181 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.319      ;
; -4.181 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.319      ;
; -4.140 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 5.087      ;
; -4.095 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 5.043      ;
; -4.095 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.233      ;
; -4.095 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.233      ;
; -4.095 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.233      ;
; -4.095 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.233      ;
; -4.063 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 5.011      ;
; -4.063 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.201      ;
; -4.063 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.201      ;
; -4.063 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.201      ;
; -4.063 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.201      ;
; -4.062 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 5.010      ;
; -4.062 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.200      ;
; -4.062 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.200      ;
; -4.062 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.200      ;
; -4.062 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.200      ;
; -4.057 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 5.005      ;
; -4.057 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.195      ;
; -4.057 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.195      ;
; -4.057 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.195      ;
; -4.057 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.195      ;
; -4.054 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 5.001      ;
; -4.050 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 4.999      ;
; -4.050 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.189      ;
; -4.050 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.189      ;
; -4.050 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.189      ;
; -4.050 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.189      ;
; -4.022 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.972      ;
; -4.022 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.153      ; 5.162      ;
; -4.022 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.153      ; 5.162      ;
; -4.022 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.153      ; 5.162      ;
; -4.022 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.153      ; 5.162      ;
; -4.022 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 4.969      ;
; -4.021 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 4.968      ;
; -4.016 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 4.964      ;
; -4.016 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.154      ;
; -4.016 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.154      ;
; -4.016 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.154      ;
; -4.016 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.154      ;
; -4.016 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 4.963      ;
; -4.011 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 4.959      ;
; -4.011 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.149      ;
; -4.011 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.149      ;
; -4.011 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.149      ;
; -4.011 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.149      ;
; -4.009 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 4.957      ;
; -3.992 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 4.940      ;
; -3.992 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.130      ;
; -3.992 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.130      ;
; -3.992 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.130      ;
; -3.992 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.130      ;
; -3.982 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 4.930      ;
; -3.982 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.120      ;
; -3.982 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.120      ;
; -3.982 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.120      ;
; -3.982 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.120      ;
; -3.981 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 4.930      ;
; -3.975 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 4.922      ;
; -3.975 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 4.924      ;
; -3.975 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.114      ;
; -3.975 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.114      ;
; -3.975 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.114      ;
; -3.975 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.114      ;
; -3.970 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 4.919      ;
; -3.970 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.109      ;
; -3.970 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.109      ;
; -3.970 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.109      ;
; -3.970 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.109      ;
; -3.970 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 4.917      ;
; -3.963 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 4.912      ;
; -3.963 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.102      ;
; -3.963 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.102      ;
; -3.963 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.102      ;
; -3.963 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.102      ;
; -3.954 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.039     ; 4.902      ;
; -3.954 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.092      ;
; -3.954 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.092      ;
; -3.954 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.092      ;
; -3.954 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.151      ; 5.092      ;
; -3.951 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 4.898      ;
; -3.943 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.038     ; 4.892      ;
; -3.943 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.082      ;
; -3.943 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.082      ;
; -3.943 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.082      ;
; -3.943 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.152      ; 5.082      ;
; -3.941 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.040     ; 4.888      ;
; -3.934 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; -0.037     ; 4.884      ;
; -3.934 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.153      ; 5.074      ;
; -3.934 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 1.000        ; 0.153      ; 5.074      ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                  ; To Node                                                                                                                                                                        ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -2.394 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.345      ;
; -2.381 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 3.330      ;
; -2.379 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.318      ;
; -2.368 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.319      ;
; -2.366 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.067     ; 3.286      ;
; -2.366 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.306      ;
; -2.360 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.075     ; 3.272      ;
; -2.358 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 3.300      ;
; -2.358 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.309      ;
; -2.355 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.067     ; 3.275      ;
; -2.355 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 3.304      ;
; -2.353 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.292      ;
; -2.349 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.075     ; 3.261      ;
; -2.346 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.020     ; 3.313      ;
; -2.345 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.291      ;
; -2.345 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 3.294      ;
; -2.343 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.282      ;
; -2.341 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.287      ;
; -2.340 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.280      ;
; -2.334 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.051     ; 3.270      ;
; -2.333 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.022     ; 3.298      ;
; -2.332 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 3.274      ;
; -2.331 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 3.286      ;
; -2.330 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.051     ; 3.266      ;
; -2.330 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.270      ;
; -2.322 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 3.264      ;
; -2.321 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.067     ; 3.241      ;
; -2.318 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.031     ; 3.274      ;
; -2.315 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.075     ; 3.227      ;
; -2.315 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.261      ;
; -2.311 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.257      ;
; -2.310 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.249      ;
; -2.310 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.029     ; 3.268      ;
; -2.309 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.255      ;
; -2.306 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.245      ;
; -2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.051     ; 3.234      ;
; -2.286 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.237      ;
; -2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.225      ;
; -2.274 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.213      ;
; -2.273 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 3.222      ;
; -2.271 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|byp_reg                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.217      ;
; -2.271 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.210      ;
; -2.268 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.043     ; 3.212      ;
; -2.267 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.043     ; 3.211      ;
; -2.266 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 3.207      ;
; -2.262 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 3.203      ;
; -2.260 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.051     ; 3.196      ;
; -2.258 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg[1]                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.198      ;
; -2.255 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.195      ;
; -2.250 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 3.192      ;
; -2.249 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.067     ; 3.169      ;
; -2.243 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.075     ; 3.155      ;
; -2.242 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.043     ; 3.186      ;
; -2.241 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.187      ;
; -2.241 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.043     ; 3.185      ;
; -2.236 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.175      ;
; -2.232 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.043     ; 3.176      ;
; -2.231 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.043     ; 3.175      ;
; -2.230 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 3.171      ;
; -2.229 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.169      ;
; -2.220 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.027     ; 3.180      ;
; -2.219 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.159      ;
; -2.219 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.027     ; 3.179      ;
; -2.207 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.031     ; 3.163      ;
; -2.206 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.145      ;
; -2.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 3.133      ;
; -2.180 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.119      ;
; -2.170 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.048     ; 3.109      ;
; -2.160 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.043     ; 3.104      ;
; -2.159 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[31]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.043     ; 3.103      ;
; -2.158 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[31]                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 3.113      ;
; -2.147 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|sh_ireg[3]                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.087      ;
; -2.146 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 3.088      ;
; -2.135 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 3.077      ;
; -2.134 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.044     ; 3.077      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_31__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_30__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_29__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_28__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_27__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_26__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_25__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_24__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_23__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_22__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_21__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_20__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_19__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_18__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_17__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.127 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_16__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.060      ;
; -2.123 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.044     ; 3.066      ;
; -2.123 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_31__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.056      ;
; -2.123 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_30__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.056      ;
; -2.123 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_29__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.056      ;
; -2.123 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_28__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.056      ;
; -2.123 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_27__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.056      ;
; -2.123 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_26__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.056      ;
; -2.123 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_25__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.056      ;
; -2.123 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_24__Z                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.054     ; 3.056      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLK_REF'                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                                                                                               ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.338 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 1.267      ; 1.013      ;
; -0.166 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_trig_16__Z                                                ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; 0.000        ; 1.451      ; 1.504      ;
; -0.165 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_16__Z                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF     ; 0.000        ; 1.451      ; 1.505      ;
; -0.012 ; JTAG_NEXUS_TCK                                                                                                                   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|tck1_Z                                                                                         ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 1.452      ; 1.564      ;
; 0.184  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z                                                               ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.046      ; 0.314      ;
; 0.186  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.188  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.347      ; 0.619      ;
; 0.192  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_20__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_20__Z                                                 ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.314      ;
; 0.192  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_16__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_16__Z                                                 ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.314      ;
; 0.194  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z                                                              ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a12~porta_datain_reg0                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.246      ; 0.544      ;
; 0.202  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_6__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_6__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.324      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_A                           ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_1_5:divisor_1_5_component_c7|sig_A                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.208  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.314      ;
; 0.210  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_C ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.318      ;
; 0.213  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z                                                              ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a12~porta_datain_reg0                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.246      ; 0.563      ;
; 0.215  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_C                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.323      ;
; 0.221  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z                                                              ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a12~porta_datain_reg0                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.246      ; 0.571      ;
; 0.233  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_B                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_2:divisor_5_0_component_c4|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.341      ;
; 0.248  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z                                                               ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a8~porta_datain_reg0                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.221      ; 0.573      ;
; 0.251  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z                                                               ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a0~porta_datain_reg0                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.222      ; 0.577      ;
; 0.257  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_11__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.379      ;
; 0.259  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z                                                               ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a8~porta_datain_reg0                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.221      ; 0.584      ;
; 0.260  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z                                                              ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a8~porta_datain_reg0                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.221      ; 0.585      ;
; 0.262  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_nxt_0__Z                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_0__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.384      ;
; 0.263  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_nxt_3__Z                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_3__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.385      ;
; 0.263  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_0__Z                                                              ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_nxt_0__Z                                                          ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.384      ;
; 0.264  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_nxt_6__Z                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_6__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.386      ;
; 0.265  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_1__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z                                                               ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.387      ;
; 0.265  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_5__Z                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_5__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.387      ;
; 0.265  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_0__Z                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_0__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.387      ;
; 0.266  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_16__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.388      ;
; 0.266  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_8__Z                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_8__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.388      ;
; 0.266  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_DUMP:U_DUMP|startcap_s_Z                                                             ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_DUMP:U_DUMP|dstate_0__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.388      ;
; 0.267  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_14__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_14__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.389      ;
; 0.267  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_13__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_13__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.389      ;
; 0.267  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z                                                              ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a8~porta_datain_reg0                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.221      ; 0.592      ;
; 0.267  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_8__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z                                                               ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.389      ;
; 0.267  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_15__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_15__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.388      ;
; 0.267  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_3__Z                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_3__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.389      ;
; 0.268  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_9__Z                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_9__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.390      ;
; 0.269  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_nxt_5__Z                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_5__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.391      ;
; 0.272  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|rst_Z                                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z                                                                 ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.220      ; 0.576      ;
; 0.277  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_11__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_11__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.398      ;
; 0.277  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_7__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_7__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.398      ;
; 0.277  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_2__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_2__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.398      ;
; 0.277  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_15__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_15__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.398      ;
; 0.277  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_3__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_3__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.399      ;
; 0.277  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_C                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                                    ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.398      ;
; 0.278  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_14__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_14__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.400      ;
; 0.278  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_13__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_13__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.400      ;
; 0.278  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_4__Z                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_4__Z                                                      ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.399      ;
; 0.279  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.023      ; 0.386      ;
; 0.279  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|cursormask_4__Z                                                            ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z                                                               ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.401      ;
; 0.280  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_17__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_17__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.402      ;
; 0.280  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_16__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_16__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.037      ; 0.401      ;
; 0.282  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.025      ; 0.391      ;
; 0.282  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.390      ;
; 0.284  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.023      ; 0.391      ;
; 0.285  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.391      ;
; 0.286  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.023      ; 0.393      ;
; 0.286  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.394      ;
; 0.287  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_C ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.395      ;
; 0.287  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_B                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_2:divisor_3_0_component_c5|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.023      ; 0.394      ;
; 0.290  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_C                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.023      ; 0.397      ;
; 0.291  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_B                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1_1:divisor_3_0_component_c3|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.022      ; 0.397      ;
; 0.292  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_B                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_3_0_divisor_3_0_component_c1:divisor_3_0_component_c1|sig_A                           ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.023      ; 0.399      ;
; 0.295  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_B                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0_1:divisor_5_0_component_c2|sig_A                         ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.023      ; 0.402      ;
; 0.304  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.036      ; 0.424      ;
; 0.305  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ; JTAG_NEXUS_TCK                                                                                             ; CLK_REF     ; 0.000        ; 6.805      ; 7.234      ;
; 0.305  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.036      ; 0.425      ;
; 0.305  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.036      ; 0.425      ;
; 0.305  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.036      ; 0.425      ;
; 0.305  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_B                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_5_0_divisor_5_0_component_c0:divisor_5_0_component_c0|sig_C                           ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.190      ; 0.579      ;
; 0.316  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.036      ; 0.436      ;
; 0.319  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_nxt_1__Z                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_1__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.441      ;
; 0.322  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_B   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_3:U1|sig_A   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.023      ; 0.429      ;
; 0.322  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_nxt_2__Z                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_2__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.444      ;
; 0.322  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.025      ; 0.431      ;
; 0.323  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_nxt_7__Z                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|curevcnt_7__Z                                                              ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.445      ;
; 0.331  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.439      ;
; 0.331  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_18__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_18__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.453      ;
; 0.333  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_11__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_11__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.455      ;
; 0.334  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow0_cap_3__Z                                                  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_3__Z                                                  ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.456      ;
; 0.336  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow1_cap_17__Z                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_17__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.458      ;
; 0.339  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_DUMP:U_DUMP|memrdaddr_9__Z                                                           ; memory_u2:U2_U2|altsyncram:altsyncram_component|altsyncram_o781:auto_generated|ram_block1a20~porta_address_reg0                  ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.220      ; 0.663      ;
; 0.339  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow2_12__Z                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|channels_shadow3_12__Z                                                     ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.038      ; 0.461      ;
; 0.341  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.449      ;
; 0.343  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.451      ;
; 0.343  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_C ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ; CLK_REF                                                                                                    ; CLK_REF     ; 0.000        ; 0.024      ; 0.451      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                     ; To Node                                                                                                                                                                                                        ; Launch Clock                                                                                               ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.136 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                                                                     ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_BRD     ; 0.000        ; 1.452      ; 1.535      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                              ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.178  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                             ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.045      ; 0.307      ;
; 0.184  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.039      ; 0.307      ;
; 0.184  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.039      ; 0.307      ;
; 0.184  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.039      ; 0.307      ;
; 0.184  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.039      ; 0.307      ;
; 0.185  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                             ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                               ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]                                                   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]                                                                                                    ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                    ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.186  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                          ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                                                                           ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                                                                            ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                              ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                                                               ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                   ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                                                                    ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                                                                  ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.187  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.036      ; 0.307      ;
; 0.193  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_11                                                     ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.179      ; 0.476      ;
; 0.194  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.036      ; 0.314      ;
; 0.196  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|Reg_DoDivide_Z                                                                              ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_3__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.317      ;
; 0.196  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF0                                                                                      ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF1                                                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.318      ;
; 0.198  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.179      ; 0.481      ;
; 0.200  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.183      ; 0.487      ;
; 0.200  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.321      ;
; 0.200  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.321      ;
; 0.201  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|Reg_DoDivide_Z                                                                              ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_6__Z                                                                                                                                   ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.322      ;
; 0.203  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                      ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.325      ;
; 0.203  ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.325      ;
; 0.203  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.324      ;
; 0.203  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_16__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_15__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.324      ;
; 0.204  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_1                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_1                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.204  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_27__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.204  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.204  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_23__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.204  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_21__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.205  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_1                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|RxSetFF0                                                                                                                                               ; JTAG_NEXUS_TCK                                                                                             ; CLK_BRD     ; 0.000        ; -0.004     ; 0.325      ;
; 0.205  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_2                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.179      ; 0.488      ;
; 0.205  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_7                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.179      ; 0.488      ;
; 0.205  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_5                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_5                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.326      ;
; 0.205  ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.327      ;
; 0.205  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_23__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.326      ;
; 0.205  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                         ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                                                                          ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.326      ;
; 0.207  ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                            ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.329      ;
; 0.207  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_29__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.328      ;
; 0.207  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_15__Z                                                                        ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_14__Z                                                                                                                         ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.328      ;
; 0.209  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_6                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.179      ; 0.492      ;
; 0.213  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.183      ; 0.500      ;
; 0.213  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.184      ; 0.501      ;
; 0.213  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.036      ; 0.333      ;
; 0.213  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                             ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.036      ; 0.333      ;
; 0.215  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_5                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.183      ; 0.502      ;
; 0.216  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead                                                         ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select1_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.338      ;
; 0.216  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                              ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[2]                                                                                                                                                 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.337      ;
; 0.217  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_DoRegWrite                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|DoRegWrite_WB                                                                                                        ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.338      ;
; 0.219  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_IsMemRead                                                         ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Select0_Half                                                                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.341      ;
; 0.219  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_2                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_2                                                                                                     ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.037      ; 0.340      ;
; 0.220  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.179      ; 0.503      ;
; 0.220  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.181      ; 0.505      ;
; 0.222  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.184      ; 0.510      ;
; 0.225  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_8                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.179      ; 0.508      ;
; 0.233  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_lqc2:auto_generated|ram_block1a0~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.184      ; 0.521      ;
; 0.238  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_3                                                      ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.181      ; 0.523      ;
; 0.251  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_13                                                     ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~portb_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.179      ; 0.534      ;
; 0.251  ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.373      ;
; 0.252  ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff2_Z           ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_Z                                                                ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.038      ; 0.374      ;
; 0.255  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                                                         ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Result_23                                                                                                          ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.222      ; 0.561      ;
; 0.261  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a4~porta_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.225      ; 0.590      ;
; 0.263  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a3~porta_address_reg0 ; CLK_BRD                                                                                                    ; CLK_BRD     ; 0.000        ; 0.223      ; 0.590      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                                                                                                                                                                                                                                                      ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                         ; To Node                                                                       ; Launch Clock                                                                                               ; Latch Clock                                                                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.063 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 0.646      ;
; 0.064 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 0.647      ;
; 0.097 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 0.678      ;
; 0.131 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 0.714      ;
; 0.166 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 0.749      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                      ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]                                       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.196 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 0.779      ;
; 0.283 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.412      ;
; 0.294 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 0.875      ;
; 0.299 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 0.880      ;
; 0.299 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 0.880      ;
; 0.299 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.428      ;
; 0.300 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 0.881      ;
; 0.307 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 0.890      ;
; 0.308 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.437      ;
; 0.311 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.440      ;
; 0.341 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 0.733      ;
; 0.343 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 0.735      ;
; 0.344 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 0.736      ;
; 0.351 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 0.743      ;
; 0.356 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 0.939      ;
; 0.361 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.943      ;
; 0.362 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.944      ;
; 0.364 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.946      ;
; 0.364 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.946      ;
; 0.365 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.947      ;
; 0.371 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 0.952      ;
; 0.375 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.957      ;
; 0.375 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.957      ;
; 0.377 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.959      ;
; 0.380 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.962      ;
; 0.396 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.978      ;
; 0.396 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 0.978      ;
; 0.430 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.559      ;
; 0.434 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 1.017      ;
; 0.434 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 1.017      ;
; 0.443 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.279      ; 0.836      ;
; 0.449 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.280      ; 0.843      ;
; 0.450 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 0.842      ;
; 0.452 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.581      ;
; 0.455 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.584      ;
; 0.457 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 1.040      ;
; 0.460 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.589      ;
; 0.460 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.589      ;
; 0.463 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.045      ; 0.592      ;
; 0.466 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.280      ; 0.860      ;
; 0.470 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 1.053      ;
; 0.470 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 1.053      ;
; 0.472 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 1.055      ;
; 0.472 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 1.055      ;
; 0.473 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 1.054      ;
; 0.520 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 1.101      ;
; 0.542 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.469      ; 1.125      ;
; 0.555 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.676      ;
; 0.560 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.280      ; 0.954      ;
; 0.561 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 1.142      ;
; 0.583 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; -0.154     ; 0.513      ;
; 0.593 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 0.985      ;
; 0.599 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 0.991      ;
; 0.607 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.729      ;
; 0.610 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.468      ; 1.192      ;
; 0.611 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 1.003      ;
; 0.635 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]                                       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.756      ;
; 0.638 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.039      ; 0.761      ;
; 0.646 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]                                      ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.767      ;
; 0.659 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]  ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 1.051      ;
; 0.663 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]   ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.278      ; 1.055      ;
; 0.666 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.788      ;
; 0.672 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                          ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; -0.154     ; 0.602      ;
; 0.689 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.811      ;
; 0.695 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.816      ;
; 0.700 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.821      ;
; 0.700 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.821      ;
; 0.701 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.037      ; 0.822      ;
; 0.713 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.038      ; 0.835      ;
; 0.722 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 0.000        ; 0.467      ; 1.303      ;
+-------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                         ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.083 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[2]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[2]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.106      ; 0.313      ;
; 0.083 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[0]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg_0                                                                                                                                                                                   ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.106      ; 0.313      ;
; 0.084 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[7]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.106      ; 0.314      ;
; 0.084 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[5]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[5]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.106      ; 0.314      ;
; 0.084 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[4]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[4]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.106      ; 0.314      ;
; 0.085 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[6]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[6]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.106      ; 0.315      ;
; 0.085 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[3]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[3]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.106      ; 0.315      ;
; 0.086 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[1]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[1]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.106      ; 0.316      ;
; 0.089 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[1]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.325      ;
; 0.090 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[3]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.326      ;
; 0.091 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                                                                                               ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.327      ;
; 0.092 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z                                                                                                                                                                                                                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                                                                          ; CLK_REF        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.327      ;
; 0.092 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.328      ;
; 0.094 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[5]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.330      ;
; 0.143 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.378      ;
; 0.144 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.379      ;
; 0.145 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.380      ;
; 0.146 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.381      ;
; 0.146 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.381      ;
; 0.146 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.381      ;
; 0.147 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.382      ;
; 0.149 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.384      ;
; 0.178 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.413      ;
; 0.179 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_2|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.414      ;
; 0.180 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_13|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.415      ;
; 0.180 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.415      ;
; 0.180 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.415      ;
; 0.181 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13                                                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.223      ; 0.488      ;
; 0.181 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.416      ;
; 0.181 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.416      ;
; 0.182 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.111      ; 0.417      ;
; 0.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.190 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0                                                                                                                                                                                                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                                                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.223      ; 0.497      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[28]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[28]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[27]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[27]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[20]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[20]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[19]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[19]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[12]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[12]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_25|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_24|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_19|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[22]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[22]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[21]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[21]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[17]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[17]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[16]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[16]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[11]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[11]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[5]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[5]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[6]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[6]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[4]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[4]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[3]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[2]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[29]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[28]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[11]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[10]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[10]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[9]                                                                                                                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_30|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_29|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_28|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_27|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_27|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_26|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_17|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.193 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[26]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[26]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[25]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[25]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[24]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[24]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[23]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[23]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[18]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[18]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[15]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[15]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[13]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[13]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[18]                                                                                                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[17]                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[4]                                                                                                                                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg_0                                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_30__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_29__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_26__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_25__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_23__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_22__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_21__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_20__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_12__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_6__Z                                                                                                                                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_5__Z                                                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[5]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[5]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.193 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg_0                                                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_23|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.315      ;
; 0.194 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[4]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[4]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.316      ;
; 0.194 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[13]                                                                                                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[12]                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_24__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_23__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_14__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_1__Z                                                                                                                                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_0__Z                                                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.315      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                              ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -0.832 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.812      ;
; -0.832 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.812      ;
; -0.806 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.783      ;
; -0.801 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 1.743      ;
; -0.801 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 1.743      ;
; -0.796 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 1.742      ;
; -0.796 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 1.742      ;
; -0.761 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.741      ;
; -0.761 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.741      ;
; -0.750 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.425     ; 0.812      ;
; -0.750 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.425     ; 0.812      ;
; -0.750 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.425     ; 0.812      ;
; -0.750 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.425     ; 0.812      ;
; -0.744 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 1.686      ;
; -0.744 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 1.686      ;
; -0.740 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.720      ;
; -0.740 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.720      ;
; -0.739 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 1.685      ;
; -0.739 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 1.685      ;
; -0.739 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.719      ;
; -0.739 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.719      ;
; -0.735 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.712      ;
; -0.733 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 1.675      ;
; -0.733 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 1.675      ;
; -0.733 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.794      ;
; -0.733 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.794      ;
; -0.733 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.794      ;
; -0.733 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.794      ;
; -0.728 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 1.674      ;
; -0.728 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 1.674      ;
; -0.714 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.691      ;
; -0.713 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.690      ;
; -0.692 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 1.663      ;
; -0.676 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.656      ;
; -0.676 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.656      ;
; -0.664 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 1.606      ;
; -0.664 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 1.606      ;
; -0.659 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 1.605      ;
; -0.659 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 1.605      ;
; -0.657 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.029     ; 1.615      ;
; -0.657 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.029     ; 1.615      ;
; -0.650 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.425     ; 0.712      ;
; -0.650 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.425     ; 0.712      ;
; -0.650 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.425     ; 0.712      ;
; -0.650 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.425     ; 0.712      ;
; -0.650 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.630      ;
; -0.650 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.630      ;
; -0.650 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.627      ;
; -0.631 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 1.586      ;
; -0.624 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.601      ;
; -0.621 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 1.592      ;
; -0.617 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.597      ;
; -0.617 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.013      ; 1.597      ;
; -0.600 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 1.571      ;
; -0.599 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 1.570      ;
; -0.598 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.029     ; 1.556      ;
; -0.598 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.029     ; 1.556      ;
; -0.591 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 1.546      ;
; -0.591 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.568      ;
; -0.586 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.012      ; 1.565      ;
; -0.586 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.012      ; 1.565      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.575 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.005      ; 1.547      ;
; -0.563 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.029     ; 1.521      ;
; -0.563 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.029     ; 1.521      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.563 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.514      ;
; -0.560 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.536      ;
; -0.543 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.191      ; 1.701      ;
; -0.537 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 1.492      ;
; -0.536 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 1.507      ;
; -0.517 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 1.466      ;
; -0.510 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.004      ; 1.481      ;
; -0.506 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.457      ;
; -0.506 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.457      ;
; -0.506 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.457      ;
; -0.506 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.457      ;
; -0.506 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 1.457      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'CLK_REF'                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -0.669 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.526      ;
; -0.612 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.469      ;
; -0.601 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.458      ;
; -0.591 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.443      ;
; -0.534 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.386      ;
; -0.532 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.389      ;
; -0.523 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.375      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.502 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.561      ;
; -0.497 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.349      ;
; -0.497 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.349      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.316      ;
; -0.454 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.306      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.504      ;
; -0.440 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.292      ;
; -0.440 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.292      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.434 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.092      ; 1.493      ;
; -0.429 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.281      ;
; -0.429 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.281      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.405 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.259      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.113     ; 1.248      ;
; -0.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.248      ;
; -0.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.248      ;
; -0.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.248      ;
; -0.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.248      ;
; -0.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.248      ;
; -0.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.248      ;
; -0.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.248      ;
; -0.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.248      ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                          ; To Node                                                                                                                                                                                                                                                     ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.569 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.692      ;
; 0.569 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.692      ;
; 0.569 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.692      ;
; 0.569 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.692      ;
; 0.579 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_8|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.700      ;
; 0.579 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_10|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.700      ;
; 0.579 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_9|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.700      ;
; 0.579 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_3|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.700      ;
; 0.579 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_2|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.700      ;
; 0.579 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_1|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.700      ;
; 0.697 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 0.822      ;
; 0.697 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_14|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 0.822      ;
; 0.697 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_15|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 0.822      ;
; 0.697 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_7|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 0.822      ;
; 0.697 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_6|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 0.822      ;
; 0.709 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.042      ; 0.835      ;
; 0.709 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.042      ; 0.835      ;
; 0.709 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_17|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.042      ; 0.835      ;
; 0.709 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_0|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.042      ; 0.835      ;
; 0.720 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_13|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.045      ; 0.849      ;
; 0.720 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_12|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.045      ; 0.849      ;
; 0.720 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_5|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.045      ; 0.849      ;
; 0.720 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_4|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.045      ; 0.849      ;
; 0.921 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.232      ; 1.237      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.960 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.192      ;
; 0.965 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.302      ; 1.391      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.977 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.099      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.983 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.217      ;
; 0.994 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.304      ; 1.422      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.000 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.234      ;
; 1.007 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.232      ; 1.323      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.026 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 1.148      ;
; 1.027 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.304      ; 1.455      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.028 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.262      ;
; 1.041 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.232      ; 1.357      ;
; 1.050 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.304      ; 1.478      ;
; 1.052 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 1.284      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
; 1.070 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 1.304      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'CLK_REF'                                                                                                                                                                                                                             ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 0.808 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.172      ; 1.104      ;
; 0.813 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.186      ; 1.123      ;
; 0.817 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.172      ; 1.113      ;
; 0.822 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.186      ; 1.132      ;
; 0.854 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.172      ; 1.150      ;
; 0.859 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.186      ; 1.169      ;
; 0.910 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.172      ; 1.206      ;
; 0.915 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.186      ; 1.225      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.061      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.953 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.070      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.073      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.965 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.294      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.966 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.082      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.974 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.303      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.010     ; 1.104      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.010     ; 1.104      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.107      ;
; 0.999 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.010     ; 1.113      ;
; 0.999 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.010     ; 1.113      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.008     ; 1.119      ;
; 1.011 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.340      ;
; 1.011 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.205      ; 1.340      ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_REF'                                                                                                                                                                ;
+--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock   ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; -3.208 ; -3.024       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ;
; -3.191 ; -3.007       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ;
; -3.159 ; -2.975       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ;
; -3.028 ; -3.028       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_2_0_component_c11|clko_s_Z|clk                                                                                 ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_0_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_10_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_11_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_12_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_13_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_14_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_15_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_16_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_17_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_18_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_19_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_1_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_20_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_21_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_22_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_23_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_24_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_25_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_26_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_27_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_28_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_29_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_2_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_30_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_31_|clk                                                                               ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_3_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_4_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_5_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_6_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_7_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_8_|clk                                                                                ;
; -3.011 ; -3.011       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_9_|clk                                                                                ;
; -3.002 ; -3.002       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|inclk[0]                                                                      ;
; -3.002 ; -3.002       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|outclk                                                                        ;
; -3.000 ; 1.000        ; 4.000          ; Port Rate       ; CLK_REF ; Rise       ; CLK_REF                                                                                                                          ;
; -2.979 ; -2.979       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|outstate_Z|clk                                                                              ;
; -2.963 ; -2.963       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -2.955 ; -2.955       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|dataa                                                                         ;
; -2.925 ; -2.925       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|combout                                                                            ;
; -2.710 ; -2.526       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ;
; -2.710 ; -2.526       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ;
; -2.710 ; -2.526       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ;
; -2.604 ; -2.420       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_A ;
; -2.604 ; -2.420       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_B ;
; -2.604 ; -2.420       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_3:U1|sig_C ;
; -2.551 ; -2.551       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|datad                                                                              ;
; -2.530 ; -2.530       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_A_Z|clk                                                                               ;
; -2.530 ; -2.530       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_B_Z|clk                                                                               ;
; -2.530 ; -2.530       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_C_Z|clk                                                                               ;
; -2.507 ; -2.507       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|datad                                                                                ;
; -2.503 ; -2.503       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout                                                                              ;
; -2.490 ; -2.490       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|combout                                                                         ;
; -2.449 ; -2.449       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|datab                                                                              ;
; -2.427 ; -2.427       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|datad                                                                           ;
; -2.426 ; -2.426       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|dataa                                                                           ;
; -2.424 ; -2.424       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|sig_A_Z|clk                                                                               ;
; -2.424 ; -2.424       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|sig_B_Z|clk                                                                               ;
; -2.424 ; -2.424       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|sig_C_Z|clk                                                                               ;
; -2.415 ; -2.415       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|datad                                                                             ;
; -2.411 ; -2.411       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|combout                                                                           ;
; -2.394 ; -2.394       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_9_0_component_c8|clko_x_cZ|combout                                                                             ;
; -2.043 ; -1.859       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_A   ;
; -2.043 ; -1.859       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_9_0:divisor_9_0_component_c8|CLKGEN_divisor_3_0_divisor_3_0_component_c1_4:U2|sig_B   ;
; -1.877 ; -1.877       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_9_0_component_c8|clko_x_cZ|datac                                                                               ;
; -1.863 ; -1.863       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_9_0_component_c8|U2|sig_A_Z|clk                                                                                ;
+--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                                                                                                                                         ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock   ; Clock Edge ; Target                                                                                                                                                                                                         ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; CLK_BRD ; Rise       ; CLK_BRD                                                                                                                                                                                                        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]                                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]                                                                                                    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                                                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0]                                                                                         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsync:UseBadDecode|lpm_ff:ff1|dffs[0]                                                                                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_0|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_1|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_2|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_3|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_4|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_5|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_6|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_7|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0]                                                                                         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsync:UseBadDecode|lpm_ff:ff1|dffs[0]                                                                                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_0|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_1|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_2|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_3|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_4|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_5|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_6|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_7|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a0~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a1~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a2~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a3~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a4~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a5~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a6~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_jqc2:auto_generated|ram_block1a7~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_kqc2:auto_generated|ram_block1a0~porta_address_reg0 ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[10]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[11]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[12]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[1]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[2]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[3]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[4]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[5]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[6]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[7]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[8]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[9]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg[14]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_1    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_10   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_11   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_12   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_15   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_5    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_6    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_7    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_8    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_9    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[10]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[11]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[12]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[13]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[14]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[15]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[16]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[17]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[18]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[19]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[1]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[20]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[21]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[22]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[23]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[24]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[25]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[26]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[27]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[28]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[29]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[2]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[30]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[3]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[4]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[5]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[6]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[7]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[8]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[9]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg_0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_20   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_28   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_4    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_6    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_7    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]  ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]'                                                                                                             ;
+--------+--------------+----------------+-----------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                                                      ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+-----------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ;
; 0.175  ; 0.359        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ;
; 0.175  ; 0.359        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ;
; 0.175  ; 0.359        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ;
; 0.175  ; 0.359        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]  ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]    ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]        ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]        ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]        ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]       ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]        ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]        ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]        ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]        ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]  ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]  ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]   ;
; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]   ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]       ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]        ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]        ;
; 0.203  ; 0.387        ; 0.184          ; Low Pulse Width ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]        ;
+--------+--------------+----------------+-----------------+------------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------+
; Setup Times                                                                    ;
+----------------+----------------+-------+-------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+----------------+----------------+-------+-------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; 2.178 ; 2.976 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 1.786 ; 2.532 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 1.792 ; 2.498 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 1.926 ; 2.668 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 1.742 ; 2.474 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 1.973 ; 2.706 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 1.864 ; 2.583 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 2.178 ; 2.976 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 1.898 ; 2.634 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 1.790 ; 2.539 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 2.033 ; 2.769 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 1.934 ; 2.649 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 1.877 ; 2.589 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 2.014 ; 2.783 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 1.805 ; 2.525 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 1.940 ; 2.687 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 1.910 ; 2.678 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 2.052 ; 2.846 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 1.615 ; 2.296 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 1.958 ; 2.742 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 2.001 ; 2.753 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 1.893 ; 2.646 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 1.828 ; 2.551 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 1.984 ; 2.705 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 1.942 ; 2.666 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 1.541 ; 2.196 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 1.822 ; 2.563 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 1.899 ; 2.649 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 1.948 ; 2.667 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 1.794 ; 2.509 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 1.768 ; 2.489 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 1.896 ; 2.663 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 1.929 ; 2.690 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 2.052 ; 2.846 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; 2.313 ; 3.119 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; 6.463 ; 7.210 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.209 ; 0.510 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; 1.866 ; 2.613 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; 1.689 ; 2.417 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+-------+-------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Hold Times                                                                       ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; -0.732 ; -1.327 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; -0.751 ; -1.358 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; -0.835 ; -1.466 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; -1.113 ; -1.776 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; -0.970 ; -1.607 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; -1.041 ; -1.661 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; -0.832 ; -1.440 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; -1.068 ; -1.717 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; -0.938 ; -1.550 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; -0.844 ; -1.453 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; -0.958 ; -1.562 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; -0.984 ; -1.610 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; -0.889 ; -1.488 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; -1.040 ; -1.696 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; -0.732 ; -1.327 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; -0.961 ; -1.594 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; -0.933 ; -1.577 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; -0.760 ; -1.349 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; -1.148 ; -1.809 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; -1.445 ; -2.136 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; -1.059 ; -1.720 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; -0.912 ; -1.558 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; -1.456 ; -2.115 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; -1.458 ; -2.115 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; -1.004 ; -1.631 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; -1.263 ; -1.921 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; -0.894 ; -1.503 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; -0.895 ; -1.504 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; -0.862 ; -1.461 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; -0.760 ; -1.349 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; -0.806 ; -1.397 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; -0.967 ; -1.624 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; -0.993 ; -1.638 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; -0.945 ; -1.585 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; -0.914 ; -1.579 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; -2.709 ; -3.277 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; -0.028 ; -0.325 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; -0.982 ; -1.660 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; -0.906 ; -1.553 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                   ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                                                 ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                            ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; SRAM0_A[*]     ; CLK_BRD                                                                                                    ; 9.313  ; 9.632  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[0]    ; CLK_BRD                                                                                                    ; 7.664  ; 7.770  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[1]    ; CLK_BRD                                                                                                    ; 7.871  ; 7.958  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[2]    ; CLK_BRD                                                                                                    ; 7.406  ; 7.436  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[3]    ; CLK_BRD                                                                                                    ; 7.906  ; 7.976  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[4]    ; CLK_BRD                                                                                                    ; 7.532  ; 7.611  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[5]    ; CLK_BRD                                                                                                    ; 7.733  ; 7.824  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[6]    ; CLK_BRD                                                                                                    ; 8.324  ; 8.407  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[7]    ; CLK_BRD                                                                                                    ; 9.313  ; 9.632  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[8]    ; CLK_BRD                                                                                                    ; 8.484  ; 8.513  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[9]    ; CLK_BRD                                                                                                    ; 8.734  ; 8.994  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[10]   ; CLK_BRD                                                                                                    ; 8.192  ; 8.247  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[11]   ; CLK_BRD                                                                                                    ; 7.876  ; 7.960  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[12]   ; CLK_BRD                                                                                                    ; 7.748  ; 7.791  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[13]   ; CLK_BRD                                                                                                    ; 8.404  ; 8.510  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[14]   ; CLK_BRD                                                                                                    ; 9.101  ; 9.383  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[15]   ; CLK_BRD                                                                                                    ; 7.754  ; 7.908  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[16]   ; CLK_BRD                                                                                                    ; 7.432  ; 7.505  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[17]   ; CLK_BRD                                                                                                    ; 8.397  ; 8.564  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_D[*]     ; CLK_BRD                                                                                                    ; 4.685  ; 4.851  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[0]    ; CLK_BRD                                                                                                    ; 4.093  ; 4.235  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[1]    ; CLK_BRD                                                                                                    ; 3.907  ; 4.053  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[2]    ; CLK_BRD                                                                                                    ; 4.091  ; 4.253  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[3]    ; CLK_BRD                                                                                                    ; 4.003  ; 4.144  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[4]    ; CLK_BRD                                                                                                    ; 3.852  ; 3.967  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[5]    ; CLK_BRD                                                                                                    ; 4.491  ; 4.667  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[6]    ; CLK_BRD                                                                                                    ; 3.728  ; 3.820  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[7]    ; CLK_BRD                                                                                                    ; 4.608  ; 4.851  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[8]    ; CLK_BRD                                                                                                    ; 4.282  ; 4.423  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[9]    ; CLK_BRD                                                                                                    ; 4.214  ; 4.362  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[10]   ; CLK_BRD                                                                                                    ; 4.539  ; 4.692  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[11]   ; CLK_BRD                                                                                                    ; 4.685  ; 4.828  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[12]   ; CLK_BRD                                                                                                    ; 4.557  ; 4.823  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[13]   ; CLK_BRD                                                                                                    ; 3.780  ; 3.882  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[14]   ; CLK_BRD                                                                                                    ; 4.388  ; 4.534  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[15]   ; CLK_BRD                                                                                                    ; 3.751  ; 3.865  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_E        ; CLK_BRD                                                                                                    ; 9.787  ; 9.816  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_LB       ; CLK_BRD                                                                                                    ; 9.510  ; 9.511  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_OE       ; CLK_BRD                                                                                                    ; 8.813  ; 8.737  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_UB       ; CLK_BRD                                                                                                    ; 9.393  ; 9.392  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_W        ; CLK_BRD                                                                                                    ; 3.986  ; 3.860  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_A[*]     ; CLK_BRD                                                                                                    ; 9.291  ; 9.547  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[0]    ; CLK_BRD                                                                                                    ; 7.099  ; 7.141  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[1]    ; CLK_BRD                                                                                                    ; 8.513  ; 8.656  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[2]    ; CLK_BRD                                                                                                    ; 7.612  ; 7.682  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[3]    ; CLK_BRD                                                                                                    ; 7.814  ; 7.887  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[4]    ; CLK_BRD                                                                                                    ; 7.314  ; 7.382  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[5]    ; CLK_BRD                                                                                                    ; 7.540  ; 7.619  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[6]    ; CLK_BRD                                                                                                    ; 9.291  ; 9.547  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[7]    ; CLK_BRD                                                                                                    ; 7.729  ; 7.836  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[8]    ; CLK_BRD                                                                                                    ; 8.747  ; 8.797  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[9]    ; CLK_BRD                                                                                                    ; 8.737  ; 8.930  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[10]   ; CLK_BRD                                                                                                    ; 8.189  ; 8.235  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[11]   ; CLK_BRD                                                                                                    ; 8.053  ; 8.150  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[12]   ; CLK_BRD                                                                                                    ; 8.063  ; 8.151  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[13]   ; CLK_BRD                                                                                                    ; 8.891  ; 9.087  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[14]   ; CLK_BRD                                                                                                    ; 7.766  ; 7.849  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[15]   ; CLK_BRD                                                                                                    ; 7.757  ; 7.910  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[16]   ; CLK_BRD                                                                                                    ; 7.191  ; 7.228  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[17]   ; CLK_BRD                                                                                                    ; 8.025  ; 8.129  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_D[*]     ; CLK_BRD                                                                                                    ; 4.638  ; 4.829  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[0]    ; CLK_BRD                                                                                                    ; 3.345  ; 3.423  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[1]    ; CLK_BRD                                                                                                    ; 4.168  ; 4.331  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[2]    ; CLK_BRD                                                                                                    ; 4.218  ; 4.379  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[3]    ; CLK_BRD                                                                                                    ; 4.251  ; 4.459  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[4]    ; CLK_BRD                                                                                                    ; 3.987  ; 4.166  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[5]    ; CLK_BRD                                                                                                    ; 4.261  ; 4.394  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[6]    ; CLK_BRD                                                                                                    ; 4.077  ; 4.191  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[7]    ; CLK_BRD                                                                                                    ; 4.638  ; 4.829  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[8]    ; CLK_BRD                                                                                                    ; 4.064  ; 4.195  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[9]    ; CLK_BRD                                                                                                    ; 3.909  ; 4.094  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[10]   ; CLK_BRD                                                                                                    ; 4.334  ; 4.478  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[11]   ; CLK_BRD                                                                                                    ; 3.976  ; 4.087  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[12]   ; CLK_BRD                                                                                                    ; 3.772  ; 3.881  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[13]   ; CLK_BRD                                                                                                    ; 4.012  ; 4.162  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[14]   ; CLK_BRD                                                                                                    ; 4.067  ; 4.228  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[15]   ; CLK_BRD                                                                                                    ; 3.777  ; 3.891  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_E        ; CLK_BRD                                                                                                    ; 10.016 ; 10.110 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_LB       ; CLK_BRD                                                                                                    ; 9.707  ; 9.726  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_OE       ; CLK_BRD                                                                                                    ; 9.468  ; 9.482  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_UB       ; CLK_BRD                                                                                                    ; 9.668  ; 9.672  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_W        ; CLK_BRD                                                                                                    ; 4.730  ; 4.491  ; Rise       ; CLK_BRD                                                                                                    ;
; DAC_CLK        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.140  ; 4.239  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_CS         ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.825  ; 5.027  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_DOUT       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.800  ; 4.984  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                                             ; 6.818  ; 7.362  ; Rise       ; JTAG_NEXUS_TCK                                                                                             ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                         ;
+----------------+------------------------------------------------------------------------------------------------------------+-------+-------+------------+------------------------------------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                                                 ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                                            ;
+----------------+------------------------------------------------------------------------------------------------------------+-------+-------+------------+------------------------------------------------------------------------------------------------------------+
; SRAM0_A[*]     ; CLK_BRD                                                                                                    ; 3.975 ; 4.108 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[0]    ; CLK_BRD                                                                                                    ; 4.503 ; 4.726 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[1]    ; CLK_BRD                                                                                                    ; 4.184 ; 4.356 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[2]    ; CLK_BRD                                                                                                    ; 4.007 ; 4.134 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[3]    ; CLK_BRD                                                                                                    ; 4.098 ; 4.242 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[4]    ; CLK_BRD                                                                                                    ; 4.308 ; 4.473 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[5]    ; CLK_BRD                                                                                                    ; 4.334 ; 4.493 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[6]    ; CLK_BRD                                                                                                    ; 4.822 ; 5.063 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[7]    ; CLK_BRD                                                                                                    ; 6.042 ; 6.443 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[8]    ; CLK_BRD                                                                                                    ; 4.456 ; 4.655 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[9]    ; CLK_BRD                                                                                                    ; 5.134 ; 5.483 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[10]   ; CLK_BRD                                                                                                    ; 4.817 ; 5.051 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[11]   ; CLK_BRD                                                                                                    ; 4.555 ; 4.699 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[12]   ; CLK_BRD                                                                                                    ; 4.219 ; 4.370 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[13]   ; CLK_BRD                                                                                                    ; 4.597 ; 4.799 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[14]   ; CLK_BRD                                                                                                    ; 5.996 ; 6.340 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[15]   ; CLK_BRD                                                                                                    ; 4.253 ; 4.460 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[16]   ; CLK_BRD                                                                                                    ; 3.975 ; 4.108 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[17]   ; CLK_BRD                                                                                                    ; 4.675 ; 4.909 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_D[*]     ; CLK_BRD                                                                                                    ; 3.648 ; 3.736 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[0]    ; CLK_BRD                                                                                                    ; 3.992 ; 4.127 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[1]    ; CLK_BRD                                                                                                    ; 3.813 ; 3.953 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[2]    ; CLK_BRD                                                                                                    ; 3.990 ; 4.145 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[3]    ; CLK_BRD                                                                                                    ; 3.905 ; 4.040 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[4]    ; CLK_BRD                                                                                                    ; 3.768 ; 3.877 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[5]    ; CLK_BRD                                                                                                    ; 4.380 ; 4.547 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[6]    ; CLK_BRD                                                                                                    ; 3.648 ; 3.736 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[7]    ; CLK_BRD                                                                                                    ; 4.492 ; 4.724 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[8]    ; CLK_BRD                                                                                                    ; 4.180 ; 4.314 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[9]    ; CLK_BRD                                                                                                    ; 4.115 ; 4.256 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[10]   ; CLK_BRD                                                                                                    ; 4.427 ; 4.573 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[11]   ; CLK_BRD                                                                                                    ; 4.567 ; 4.704 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[12]   ; CLK_BRD                                                                                                    ; 4.437 ; 4.692 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[13]   ; CLK_BRD                                                                                                    ; 3.692 ; 3.789 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[14]   ; CLK_BRD                                                                                                    ; 4.276 ; 4.416 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[15]   ; CLK_BRD                                                                                                    ; 3.663 ; 3.773 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_E        ; CLK_BRD                                                                                                    ; 4.636 ; 4.815 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_LB       ; CLK_BRD                                                                                                    ; 4.370 ; 4.559 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_OE       ; CLK_BRD                                                                                                    ; 3.701 ; 3.824 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_UB       ; CLK_BRD                                                                                                    ; 4.255 ; 4.330 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_W        ; CLK_BRD                                                                                                    ; 3.894 ; 3.773 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_A[*]     ; CLK_BRD                                                                                                    ; 3.744 ; 3.843 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[0]    ; CLK_BRD                                                                                                    ; 3.962 ; 4.123 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[1]    ; CLK_BRD                                                                                                    ; 4.836 ; 5.067 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[2]    ; CLK_BRD                                                                                                    ; 4.206 ; 4.372 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[3]    ; CLK_BRD                                                                                                    ; 4.011 ; 4.157 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[4]    ; CLK_BRD                                                                                                    ; 4.096 ; 4.251 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[5]    ; CLK_BRD                                                                                                    ; 4.149 ; 4.296 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[6]    ; CLK_BRD                                                                                                    ; 5.782 ; 6.195 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[7]    ; CLK_BRD                                                                                                    ; 4.488 ; 4.679 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[8]    ; CLK_BRD                                                                                                    ; 4.709 ; 4.929 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[9]    ; CLK_BRD                                                                                                    ; 5.139 ; 5.422 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[10]   ; CLK_BRD                                                                                                    ; 4.815 ; 5.040 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[11]   ; CLK_BRD                                                                                                    ; 4.724 ; 4.881 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[12]   ; CLK_BRD                                                                                                    ; 4.522 ; 4.717 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[13]   ; CLK_BRD                                                                                                    ; 5.096 ; 5.390 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[14]   ; CLK_BRD                                                                                                    ; 4.681 ; 4.830 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[15]   ; CLK_BRD                                                                                                    ; 4.255 ; 4.461 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[16]   ; CLK_BRD                                                                                                    ; 3.744 ; 3.843 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[17]   ; CLK_BRD                                                                                                    ; 4.318 ; 4.492 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_D[*]     ; CLK_BRD                                                                                                    ; 3.273 ; 3.347 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[0]    ; CLK_BRD                                                                                                    ; 3.273 ; 3.347 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[1]    ; CLK_BRD                                                                                                    ; 4.063 ; 4.219 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[2]    ; CLK_BRD                                                                                                    ; 4.113 ; 4.267 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[3]    ; CLK_BRD                                                                                                    ; 4.143 ; 4.342 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[4]    ; CLK_BRD                                                                                                    ; 3.889 ; 4.060 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[5]    ; CLK_BRD                                                                                                    ; 4.160 ; 4.286 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[6]    ; CLK_BRD                                                                                                    ; 3.983 ; 4.092 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[7]    ; CLK_BRD                                                                                                    ; 4.523 ; 4.706 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[8]    ; CLK_BRD                                                                                                    ; 3.970 ; 4.096 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[9]    ; CLK_BRD                                                                                                    ; 3.818 ; 3.997 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[10]   ; CLK_BRD                                                                                                    ; 4.230 ; 4.367 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[11]   ; CLK_BRD                                                                                                    ; 3.887 ; 3.993 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[12]   ; CLK_BRD                                                                                                    ; 3.684 ; 3.788 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[13]   ; CLK_BRD                                                                                                    ; 3.915 ; 4.058 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[14]   ; CLK_BRD                                                                                                    ; 3.968 ; 4.122 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[15]   ; CLK_BRD                                                                                                    ; 3.688 ; 3.798 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_E        ; CLK_BRD                                                                                                    ; 4.856 ; 5.026 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_LB       ; CLK_BRD                                                                                                    ; 4.561 ; 4.731 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_OE       ; CLK_BRD                                                                                                    ; 4.331 ; 4.540 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_UB       ; CLK_BRD                                                                                                    ; 4.523 ; 4.609 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_W        ; CLK_BRD                                                                                                    ; 4.645 ; 4.411 ; Rise       ; CLK_BRD                                                                                                    ;
; DAC_CLK        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.021 ; 4.115 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_CS         ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.686 ; 4.879 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_DOUT       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.661 ; 4.837 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                                             ; 4.334 ; 4.522 ; Rise       ; JTAG_NEXUS_TCK                                                                                             ;
+----------------+------------------------------------------------------------------------------------------------------------+-------+-------+------------+------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------+
; Output Enable Times                                                        ;
+--------------+------------+--------+--------+------------+-----------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+--------------+------------+--------+--------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 9.835  ; 9.832  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 9.930  ; 9.927  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 10.439 ; 10.436 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 10.229 ; 10.226 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 9.900  ; 9.897  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 10.552 ; 10.548 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 10.296 ; 10.292 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 10.661 ; 10.657 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 10.253 ; 10.249 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 10.272 ; 10.268 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 10.326 ; 10.322 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 10.552 ; 10.548 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 10.347 ; 10.343 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 10.229 ; 10.226 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 9.835  ; 9.832  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 10.086 ; 10.083 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 10.066 ; 10.063 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 9.665  ; 9.662  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 9.665  ; 9.662  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 10.419 ; 10.416 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 10.347 ; 10.344 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 10.297 ; 10.294 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 10.419 ; 10.416 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 10.540 ; 10.536 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 10.326 ; 10.322 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 10.490 ; 10.486 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 10.316 ; 10.312 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 10.326 ; 10.322 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 10.337 ; 10.333 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 10.333 ; 10.329 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 9.825  ; 9.822  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 10.346 ; 10.343 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 10.356 ; 10.353 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 10.177 ; 10.174 ; Rise       ; CLK_BRD         ;
+--------------+------------+--------+--------+------------+-----------------+


+--------------------------------------------------------------------------+
; Minimum Output Enable Times                                              ;
+--------------+------------+-------+-------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+-------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 3.876 ; 3.876 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 3.967 ; 3.967 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 4.454 ; 4.454 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 4.254 ; 4.254 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 3.937 ; 3.937 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 4.561 ; 4.561 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 4.314 ; 4.314 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 4.667 ; 4.667 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 4.273 ; 4.273 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 4.292 ; 4.292 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 4.345 ; 4.345 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 4.561 ; 4.561 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 4.365 ; 4.365 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 4.253 ; 4.253 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 3.876 ; 3.876 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 4.117 ; 4.117 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 4.097 ; 4.097 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 3.711 ; 3.711 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 3.711 ; 3.711 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 4.434 ; 4.434 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 4.367 ; 4.367 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 4.317 ; 4.317 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 4.434 ; 4.434 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 4.549 ; 4.549 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 4.344 ; 4.344 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 4.503 ; 4.503 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 4.335 ; 4.335 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 4.344 ; 4.344 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 4.355 ; 4.355 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 4.351 ; 4.351 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 3.866 ; 3.866 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 4.367 ; 4.367 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 4.377 ; 4.377 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 4.203 ; 4.203 ; Rise       ; CLK_BRD         ;
+--------------+------------+-------+-------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Output Disable Times                                                             ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 9.784     ; 9.784     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 9.889     ; 9.889     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 10.468    ; 10.468    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 10.230    ; 10.230    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 9.860     ; 9.860     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 10.589    ; 10.589    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 10.307    ; 10.307    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 10.717    ; 10.717    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 10.267    ; 10.267    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 10.287    ; 10.287    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 10.339    ; 10.339    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 10.589    ; 10.589    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 10.363    ; 10.363    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 10.248    ; 10.248    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 9.784     ; 9.784     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 10.080    ; 10.080    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 10.060    ; 10.060    ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 9.599     ; 9.599     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 9.599     ; 9.599     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 10.448    ; 10.448    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 10.356    ; 10.356    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 10.306    ; 10.306    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 10.448    ; 10.448    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 10.580    ; 10.580    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 10.337    ; 10.337    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 10.535    ; 10.535    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 10.329    ; 10.329    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 10.337    ; 10.337    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 10.353    ; 10.353    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 10.342    ; 10.342    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 9.774     ; 9.774     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 10.359    ; 10.359    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 10.369    ; 10.369    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 10.172    ; 10.172    ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                     ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 4.023     ; 4.089     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 4.122     ; 4.188     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 4.678     ; 4.744     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 4.450     ; 4.516     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 4.094     ; 4.160     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 4.792     ; 4.850     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 4.520     ; 4.578     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 4.916     ; 4.974     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 4.482     ; 4.540     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 4.501     ; 4.559     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 4.553     ; 4.611     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 4.792     ; 4.850     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 4.576     ; 4.634     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 4.467     ; 4.533     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 4.023     ; 4.089     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 4.307     ; 4.373     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 4.287     ; 4.353     ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 3.843     ; 3.909     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 3.843     ; 3.909     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 4.658     ; 4.724     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 4.572     ; 4.638     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 4.522     ; 4.588     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 4.658     ; 4.724     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 4.784     ; 4.842     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 4.550     ; 4.608     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 4.742     ; 4.800     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 4.543     ; 4.601     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 4.550     ; 4.608     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 4.566     ; 4.624     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 4.556     ; 4.614     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 4.013     ; 4.079     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 4.575     ; 4.641     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 4.585     ; 4.651     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 4.394     ; 4.460     ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                                           ;
+-------------------------------------------------------------------------------------------------------------+------------+---------+----------+---------+---------------------+
; Clock                                                                                                       ; Setup      ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------------------------------------------------------------------------+------------+---------+----------+---------+---------------------+
; Worst-case Slack                                                                                            ; -20.091    ; -2.497  ; -3.170   ; 0.569   ; -7.458              ;
;  CLK_BRD                                                                                                    ; -17.494    ; -0.136  ; N/A      ; N/A     ; -4.000              ;
;  CLK_REF                                                                                                    ; -20.091    ; -2.497  ; -2.643   ; 0.808   ; -7.458              ;
;  Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; -11.445    ; 0.063   ; N/A      ; N/A     ; -1.487              ;
;  JTAG_NEXUS_TCK                                                                                             ; -6.938     ; 0.083   ; -3.170   ; 0.569   ; -3.000              ;
; Design-wide TNS                                                                                             ; -26236.152 ; -55.955 ; -220.069 ; 0.0     ; -7023.885           ;
;  CLK_BRD                                                                                                    ; -19184.186 ; -0.136  ; N/A      ; N/A     ; -3066.467           ;
;  CLK_REF                                                                                                    ; -2027.864  ; -55.955 ; -84.479  ; 0.000   ; -2165.557           ;
;  Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; -249.110   ; 0.000   ; N/A      ; N/A     ; -83.416             ;
;  JTAG_NEXUS_TCK                                                                                             ; -4774.992  ; 0.000   ; -135.590 ; 0.000   ; -1708.589           ;
+-------------------------------------------------------------------------------------------------------------+------------+---------+----------+---------+---------------------+


+----------------------------------------------------------------------------------+
; Setup Times                                                                      ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; 5.084  ; 5.086  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 4.252  ; 4.261  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 4.165  ; 4.239  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 4.498  ; 4.641  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 4.099  ; 4.148  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.607  ; 4.588  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 4.430  ; 4.420  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 5.084  ; 5.086  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 4.546  ; 4.489  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 4.193  ; 4.261  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 4.813  ; 4.720  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.525  ; 4.561  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 4.380  ; 4.369  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 4.710  ; 4.737  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 4.298  ; 4.274  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 4.442  ; 4.514  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 4.450  ; 4.535  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 4.828  ; 4.957  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.791  ; 3.931  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 4.642  ; 4.705  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 4.548  ; 4.729  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 4.423  ; 4.515  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 4.240  ; 4.338  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.630  ; 4.607  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 4.513  ; 4.562  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 3.487  ; 3.680  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 4.244  ; 4.266  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 4.291  ; 4.452  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 4.631  ; 4.655  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 4.142  ; 4.125  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 4.092  ; 4.134  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 4.373  ; 4.506  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.418  ; 4.510  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 4.828  ; 4.957  ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; 5.275  ; 5.361  ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; 16.776 ; 15.838 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.358  ; 0.766  ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; 4.328  ; 4.536  ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; 3.775  ; 4.069  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Hold Times                                                                       ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; -0.732 ; -1.327 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; -0.751 ; -1.358 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; -0.835 ; -1.466 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; -1.113 ; -1.776 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; -0.970 ; -1.607 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; -1.041 ; -1.661 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; -0.832 ; -1.440 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; -1.068 ; -1.717 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; -0.938 ; -1.550 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; -0.844 ; -1.453 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; -0.958 ; -1.562 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; -0.984 ; -1.610 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; -0.889 ; -1.488 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; -1.040 ; -1.696 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; -0.732 ; -1.327 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; -0.961 ; -1.594 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; -0.933 ; -1.577 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; -0.760 ; -1.349 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; -1.148 ; -1.809 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; -1.445 ; -2.136 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; -1.059 ; -1.720 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; -0.912 ; -1.558 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; -1.456 ; -2.115 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; -1.458 ; -2.115 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; -1.004 ; -1.631 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; -1.263 ; -1.921 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; -0.894 ; -1.503 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; -0.895 ; -1.504 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; -0.862 ; -1.461 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; -0.760 ; -1.349 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; -0.806 ; -1.397 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; -0.967 ; -1.624 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; -0.993 ; -1.638 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; -0.945 ; -1.585 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; -0.914 ; -1.579 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; -2.709 ; -3.277 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.077  ; -0.210 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; -0.982 ; -1.660 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; -0.906 ; -1.553 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                   ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                                                 ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                            ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+
; SRAM0_A[*]     ; CLK_BRD                                                                                                    ; 20.358 ; 19.933 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[0]    ; CLK_BRD                                                                                                    ; 17.182 ; 16.744 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[1]    ; CLK_BRD                                                                                                    ; 17.448 ; 17.177 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[2]    ; CLK_BRD                                                                                                    ; 16.424 ; 16.142 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[3]    ; CLK_BRD                                                                                                    ; 17.589 ; 17.266 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[4]    ; CLK_BRD                                                                                                    ; 16.750 ; 16.406 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[5]    ; CLK_BRD                                                                                                    ; 16.971 ; 16.726 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[6]    ; CLK_BRD                                                                                                    ; 18.196 ; 18.049 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[7]    ; CLK_BRD                                                                                                    ; 20.358 ; 19.933 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[8]    ; CLK_BRD                                                                                                    ; 18.540 ; 18.372 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[9]    ; CLK_BRD                                                                                                    ; 19.282 ; 19.082 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[10]   ; CLK_BRD                                                                                                    ; 17.971 ; 17.759 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[11]   ; CLK_BRD                                                                                                    ; 17.503 ; 17.069 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[12]   ; CLK_BRD                                                                                                    ; 16.964 ; 16.754 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[13]   ; CLK_BRD                                                                                                    ; 18.481 ; 18.194 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[14]   ; CLK_BRD                                                                                                    ; 19.682 ; 19.402 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[15]   ; CLK_BRD                                                                                                    ; 17.202 ; 16.966 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[16]   ; CLK_BRD                                                                                                    ; 16.588 ; 16.300 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[17]   ; CLK_BRD                                                                                                    ; 18.765 ; 18.386 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_D[*]     ; CLK_BRD                                                                                                    ; 10.080 ; 9.729  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[0]    ; CLK_BRD                                                                                                    ; 8.801  ; 8.465  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[1]    ; CLK_BRD                                                                                                    ; 8.432  ; 8.173  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[2]    ; CLK_BRD                                                                                                    ; 8.838  ; 8.528  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[3]    ; CLK_BRD                                                                                                    ; 8.602  ; 8.287  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[4]    ; CLK_BRD                                                                                                    ; 8.006  ; 7.930  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[5]    ; CLK_BRD                                                                                                    ; 9.642  ; 9.245  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[6]    ; CLK_BRD                                                                                                    ; 7.746  ; 7.632  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[7]    ; CLK_BRD                                                                                                    ; 9.720  ; 9.632  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[8]    ; CLK_BRD                                                                                                    ; 9.205  ; 8.832  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[9]    ; CLK_BRD                                                                                                    ; 8.844  ; 8.659  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[10]   ; CLK_BRD                                                                                                    ; 9.714  ; 9.338  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[11]   ; CLK_BRD                                                                                                    ; 10.080 ; 9.729  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[12]   ; CLK_BRD                                                                                                    ; 9.873  ; 9.664  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[13]   ; CLK_BRD                                                                                                    ; 7.939  ; 7.781  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[14]   ; CLK_BRD                                                                                                    ; 9.548  ; 9.176  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[15]   ; CLK_BRD                                                                                                    ; 8.061  ; 7.815  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_E        ; CLK_BRD                                                                                                    ; 21.918 ; 21.686 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_LB       ; CLK_BRD                                                                                                    ; 21.223 ; 21.074 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_OE       ; CLK_BRD                                                                                                    ; 19.435 ; 19.444 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_UB       ; CLK_BRD                                                                                                    ; 20.921 ; 20.788 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_W        ; CLK_BRD                                                                                                    ; 8.001  ; 8.065  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_A[*]     ; CLK_BRD                                                                                                    ; 19.916 ; 19.893 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[0]    ; CLK_BRD                                                                                                    ; 15.707 ; 15.495 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[1]    ; CLK_BRD                                                                                                    ; 18.224 ; 18.106 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[2]    ; CLK_BRD                                                                                                    ; 16.879 ; 16.602 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[3]    ; CLK_BRD                                                                                                    ; 17.319 ; 17.034 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[4]    ; CLK_BRD                                                                                                    ; 16.333 ; 16.062 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[5]    ; CLK_BRD                                                                                                    ; 16.564 ; 16.347 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[6]    ; CLK_BRD                                                                                                    ; 19.916 ; 19.893 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[7]    ; CLK_BRD                                                                                                    ; 17.052 ; 16.860 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[8]    ; CLK_BRD                                                                                                    ; 19.185 ; 18.929 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[9]    ; CLK_BRD                                                                                                    ; 19.258 ; 19.017 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[10]   ; CLK_BRD                                                                                                    ; 17.990 ; 17.715 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[11]   ; CLK_BRD                                                                                                    ; 17.889 ; 17.430 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[12]   ; CLK_BRD                                                                                                    ; 17.714 ; 17.477 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[13]   ; CLK_BRD                                                                                                    ; 19.095 ; 18.958 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[14]   ; CLK_BRD                                                                                                    ; 17.110 ; 16.834 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[15]   ; CLK_BRD                                                                                                    ; 17.207 ; 16.964 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[16]   ; CLK_BRD                                                                                                    ; 15.970 ; 15.768 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[17]   ; CLK_BRD                                                                                                    ; 17.776 ; 17.486 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_D[*]     ; CLK_BRD                                                                                                    ; 9.828  ; 9.505  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[0]    ; CLK_BRD                                                                                                    ; 7.072  ; 6.975  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[1]    ; CLK_BRD                                                                                                    ; 9.055  ; 8.684  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[2]    ; CLK_BRD                                                                                                    ; 9.131  ; 8.728  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[3]    ; CLK_BRD                                                                                                    ; 9.235  ; 8.948  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[4]    ; CLK_BRD                                                                                                    ; 8.580  ; 8.475  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[5]    ; CLK_BRD                                                                                                    ; 8.996  ; 8.758  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[6]    ; CLK_BRD                                                                                                    ; 8.573  ; 8.477  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[7]    ; CLK_BRD                                                                                                    ; 9.828  ; 9.505  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[8]    ; CLK_BRD                                                                                                    ; 8.479  ; 8.332  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[9]    ; CLK_BRD                                                                                                    ; 8.324  ; 8.185  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[10]   ; CLK_BRD                                                                                                    ; 9.215  ; 8.874  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[11]   ; CLK_BRD                                                                                                    ; 8.357  ; 8.159  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[12]   ; CLK_BRD                                                                                                    ; 8.051  ; 7.819  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[13]   ; CLK_BRD                                                                                                    ; 8.702  ; 8.370  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[14]   ; CLK_BRD                                                                                                    ; 8.740  ; 8.435  ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[15]   ; CLK_BRD                                                                                                    ; 8.083  ; 7.863  ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_E        ; CLK_BRD                                                                                                    ; 22.407 ; 22.206 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_LB       ; CLK_BRD                                                                                                    ; 21.634 ; 21.472 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_OE       ; CLK_BRD                                                                                                    ; 20.866 ; 20.784 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_UB       ; CLK_BRD                                                                                                    ; 21.561 ; 21.368 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_W        ; CLK_BRD                                                                                                    ; 9.058  ; 9.006  ; Rise       ; CLK_BRD                                                                                                    ;
; DAC_CLK        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 9.077  ; 8.855  ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_CS         ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 10.474 ; 10.269 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_DOUT       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 10.372 ; 10.122 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                                             ; 15.553 ; 14.782 ; Rise       ; JTAG_NEXUS_TCK                                                                                             ;
+----------------+------------------------------------------------------------------------------------------------------------+--------+--------+------------+------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                         ;
+----------------+------------------------------------------------------------------------------------------------------------+-------+-------+------------+------------------------------------------------------------------------------------------------------------+
; Data Port      ; Clock Port                                                                                                 ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                                            ;
+----------------+------------------------------------------------------------------------------------------------------------+-------+-------+------------+------------------------------------------------------------------------------------------------------------+
; SRAM0_A[*]     ; CLK_BRD                                                                                                    ; 3.975 ; 4.108 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[0]    ; CLK_BRD                                                                                                    ; 4.503 ; 4.726 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[1]    ; CLK_BRD                                                                                                    ; 4.184 ; 4.356 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[2]    ; CLK_BRD                                                                                                    ; 4.007 ; 4.134 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[3]    ; CLK_BRD                                                                                                    ; 4.098 ; 4.242 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[4]    ; CLK_BRD                                                                                                    ; 4.308 ; 4.473 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[5]    ; CLK_BRD                                                                                                    ; 4.334 ; 4.493 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[6]    ; CLK_BRD                                                                                                    ; 4.822 ; 5.063 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[7]    ; CLK_BRD                                                                                                    ; 6.042 ; 6.443 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[8]    ; CLK_BRD                                                                                                    ; 4.456 ; 4.655 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[9]    ; CLK_BRD                                                                                                    ; 5.134 ; 5.483 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[10]   ; CLK_BRD                                                                                                    ; 4.817 ; 5.051 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[11]   ; CLK_BRD                                                                                                    ; 4.555 ; 4.699 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[12]   ; CLK_BRD                                                                                                    ; 4.219 ; 4.370 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[13]   ; CLK_BRD                                                                                                    ; 4.597 ; 4.799 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[14]   ; CLK_BRD                                                                                                    ; 5.996 ; 6.340 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[15]   ; CLK_BRD                                                                                                    ; 4.253 ; 4.460 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[16]   ; CLK_BRD                                                                                                    ; 3.975 ; 4.108 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_A[17]   ; CLK_BRD                                                                                                    ; 4.675 ; 4.909 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_D[*]     ; CLK_BRD                                                                                                    ; 3.648 ; 3.736 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[0]    ; CLK_BRD                                                                                                    ; 3.992 ; 4.127 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[1]    ; CLK_BRD                                                                                                    ; 3.813 ; 3.953 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[2]    ; CLK_BRD                                                                                                    ; 3.990 ; 4.145 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[3]    ; CLK_BRD                                                                                                    ; 3.905 ; 4.040 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[4]    ; CLK_BRD                                                                                                    ; 3.768 ; 3.877 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[5]    ; CLK_BRD                                                                                                    ; 4.380 ; 4.547 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[6]    ; CLK_BRD                                                                                                    ; 3.648 ; 3.736 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[7]    ; CLK_BRD                                                                                                    ; 4.492 ; 4.724 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[8]    ; CLK_BRD                                                                                                    ; 4.180 ; 4.314 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[9]    ; CLK_BRD                                                                                                    ; 4.115 ; 4.256 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[10]   ; CLK_BRD                                                                                                    ; 4.427 ; 4.573 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[11]   ; CLK_BRD                                                                                                    ; 4.567 ; 4.704 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[12]   ; CLK_BRD                                                                                                    ; 4.437 ; 4.692 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[13]   ; CLK_BRD                                                                                                    ; 3.692 ; 3.789 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[14]   ; CLK_BRD                                                                                                    ; 4.276 ; 4.416 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM0_D[15]   ; CLK_BRD                                                                                                    ; 3.663 ; 3.773 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_E        ; CLK_BRD                                                                                                    ; 4.636 ; 4.815 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_LB       ; CLK_BRD                                                                                                    ; 4.370 ; 4.559 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_OE       ; CLK_BRD                                                                                                    ; 3.701 ; 3.824 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_UB       ; CLK_BRD                                                                                                    ; 4.255 ; 4.330 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM0_W        ; CLK_BRD                                                                                                    ; 3.894 ; 3.773 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_A[*]     ; CLK_BRD                                                                                                    ; 3.744 ; 3.843 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[0]    ; CLK_BRD                                                                                                    ; 3.962 ; 4.123 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[1]    ; CLK_BRD                                                                                                    ; 4.836 ; 5.067 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[2]    ; CLK_BRD                                                                                                    ; 4.206 ; 4.372 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[3]    ; CLK_BRD                                                                                                    ; 4.011 ; 4.157 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[4]    ; CLK_BRD                                                                                                    ; 4.096 ; 4.251 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[5]    ; CLK_BRD                                                                                                    ; 4.149 ; 4.296 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[6]    ; CLK_BRD                                                                                                    ; 5.782 ; 6.195 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[7]    ; CLK_BRD                                                                                                    ; 4.488 ; 4.679 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[8]    ; CLK_BRD                                                                                                    ; 4.709 ; 4.929 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[9]    ; CLK_BRD                                                                                                    ; 5.139 ; 5.422 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[10]   ; CLK_BRD                                                                                                    ; 4.815 ; 5.040 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[11]   ; CLK_BRD                                                                                                    ; 4.724 ; 4.881 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[12]   ; CLK_BRD                                                                                                    ; 4.522 ; 4.717 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[13]   ; CLK_BRD                                                                                                    ; 5.096 ; 5.390 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[14]   ; CLK_BRD                                                                                                    ; 4.681 ; 4.830 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[15]   ; CLK_BRD                                                                                                    ; 4.255 ; 4.461 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[16]   ; CLK_BRD                                                                                                    ; 3.744 ; 3.843 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_A[17]   ; CLK_BRD                                                                                                    ; 4.318 ; 4.492 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_D[*]     ; CLK_BRD                                                                                                    ; 3.273 ; 3.347 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[0]    ; CLK_BRD                                                                                                    ; 3.273 ; 3.347 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[1]    ; CLK_BRD                                                                                                    ; 4.063 ; 4.219 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[2]    ; CLK_BRD                                                                                                    ; 4.113 ; 4.267 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[3]    ; CLK_BRD                                                                                                    ; 4.143 ; 4.342 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[4]    ; CLK_BRD                                                                                                    ; 3.889 ; 4.060 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[5]    ; CLK_BRD                                                                                                    ; 4.160 ; 4.286 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[6]    ; CLK_BRD                                                                                                    ; 3.983 ; 4.092 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[7]    ; CLK_BRD                                                                                                    ; 4.523 ; 4.706 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[8]    ; CLK_BRD                                                                                                    ; 3.970 ; 4.096 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[9]    ; CLK_BRD                                                                                                    ; 3.818 ; 3.997 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[10]   ; CLK_BRD                                                                                                    ; 4.230 ; 4.367 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[11]   ; CLK_BRD                                                                                                    ; 3.887 ; 3.993 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[12]   ; CLK_BRD                                                                                                    ; 3.684 ; 3.788 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[13]   ; CLK_BRD                                                                                                    ; 3.915 ; 4.058 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[14]   ; CLK_BRD                                                                                                    ; 3.968 ; 4.122 ; Rise       ; CLK_BRD                                                                                                    ;
;  SRAM1_D[15]   ; CLK_BRD                                                                                                    ; 3.688 ; 3.798 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_E        ; CLK_BRD                                                                                                    ; 4.856 ; 5.026 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_LB       ; CLK_BRD                                                                                                    ; 4.561 ; 4.731 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_OE       ; CLK_BRD                                                                                                    ; 4.331 ; 4.540 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_UB       ; CLK_BRD                                                                                                    ; 4.523 ; 4.609 ; Rise       ; CLK_BRD                                                                                                    ;
; SRAM1_W        ; CLK_BRD                                                                                                    ; 4.645 ; 4.411 ; Rise       ; CLK_BRD                                                                                                    ;
; DAC_CLK        ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.021 ; 4.115 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_CS         ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.686 ; 4.879 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; DAC_DOUT       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 4.661 ; 4.837 ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK                                                                                             ; 4.334 ; 4.522 ; Rise       ; JTAG_NEXUS_TCK                                                                                             ;
+----------------+------------------------------------------------------------------------------------------------------------+-------+-------+------------+------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; DAC_CLK        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DAC_CS         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DAC_DOUT       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[16]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[17]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_E        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_LB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_OE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_UB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_W        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[16]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[17]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_E        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_LB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_OE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_UB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_W        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; SRAM0_D[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TCK          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TMS          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK_BRD                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; TEST_BUTTON             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TDI          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK_REF                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DCLK~           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DAC_CLK        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; DAC_CS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DOUT       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00616 V          ; 0.065 V                              ; 0.016 V                              ; 6.89e-10 s                  ; 6.77e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00616 V         ; 0.065 V                             ; 0.016 V                             ; 6.89e-10 s                 ; 6.77e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.33 V              ; -0.00201 V          ; 0.092 V                              ; 0.05 V                               ; 3.78e-09 s                  ; 3.59e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.33 V             ; -0.00201 V         ; 0.092 V                             ; 0.05 V                              ; 3.78e-09 s                 ; 3.59e-09 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00616 V          ; 0.065 V                              ; 0.016 V                              ; 6.89e-10 s                  ; 6.77e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00616 V         ; 0.065 V                             ; 0.016 V                             ; 6.89e-10 s                 ; 6.77e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DAC_CLK        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; DAC_CS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; DAC_DOUT       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM0_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM0_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.64 V              ; -0.011 V            ; 0.212 V                              ; 0.198 V                              ; 2.38e-09 s                  ; 2.29e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.64 V             ; -0.011 V           ; 0.212 V                             ; 0.198 V                             ; 2.38e-09 s                 ; 2.29e-09 s                 ; No                        ; Yes                       ;
; SRAM1_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM1_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM1_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM0_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                                                                     ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                                                 ; To Clock                                                                                                   ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+----------+----------+----------+----------+
; CLK_BRD                                                                                                    ; CLK_BRD                                                                                                    ; 1917218  ; 504      ; 5186     ; 0        ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_BRD                                                                                                    ; 3        ; 1        ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                                             ; CLK_BRD                                                                                                    ; 25682    ; 1        ; 482      ; 0        ;
; CLK_BRD                                                                                                    ; CLK_REF                                                                                                    ; 36       ; 0        ; 0        ; 0        ;
; CLK_REF                                                                                                    ; CLK_REF                                                                                                    ; 160270   ; 1728     ; 96       ; 0        ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF                                                                                                    ; 10       ; 2        ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                                             ; CLK_REF                                                                                                    ; 211540   ; 1        ; 256      ; 0        ;
; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 72840    ; 0        ; 0        ; 0        ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 223056   ; 0        ; 0        ; 0        ;
; CLK_BRD                                                                                                    ; JTAG_NEXUS_TCK                                                                                             ; 95       ; 0        ; 0        ; 0        ;
; CLK_REF                                                                                                    ; JTAG_NEXUS_TCK                                                                                             ; 1        ; 32       ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                                             ; JTAG_NEXUS_TCK                                                                                             ; 15622    ; 1344     ; 68       ; 0        ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                                                                      ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                                                 ; To Clock                                                                                                   ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+----------+----------+----------+----------+
; CLK_BRD                                                                                                    ; CLK_BRD                                                                                                    ; 1917218  ; 504      ; 5186     ; 0        ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_BRD                                                                                                    ; 3        ; 1        ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                                             ; CLK_BRD                                                                                                    ; 25682    ; 1        ; 482      ; 0        ;
; CLK_BRD                                                                                                    ; CLK_REF                                                                                                    ; 36       ; 0        ; 0        ; 0        ;
; CLK_REF                                                                                                    ; CLK_REF                                                                                                    ; 160270   ; 1728     ; 96       ; 0        ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; CLK_REF                                                                                                    ; 10       ; 2        ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                                             ; CLK_REF                                                                                                    ; 211540   ; 1        ; 256      ; 0        ;
; CLK_BRD                                                                                                    ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 72840    ; 0        ; 0        ; 0        ;
; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] ; 223056   ; 0        ; 0        ; 0        ;
; CLK_BRD                                                                                                    ; JTAG_NEXUS_TCK                                                                                             ; 95       ; 0        ; 0        ; 0        ;
; CLK_REF                                                                                                    ; JTAG_NEXUS_TCK                                                                                             ; 1        ; 32       ; 0        ; 0        ;
; JTAG_NEXUS_TCK                                                                                             ; JTAG_NEXUS_TCK                                                                                             ; 15622    ; 1344     ; 68       ; 0        ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------+
; Recovery Transfers                                                          ;
+----------------+----------------+----------+----------+----------+----------+
; From Clock     ; To Clock       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------+----------------+----------+----------+----------+----------+
; JTAG_NEXUS_TCK ; CLK_REF        ; 152      ; 0        ; 0        ; 0        ;
; CLK_BRD        ; JTAG_NEXUS_TCK ; 120      ; 0        ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 163      ; 12       ; 0        ; 4        ;
+----------------+----------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------+
; Removal Transfers                                                           ;
+----------------+----------------+----------+----------+----------+----------+
; From Clock     ; To Clock       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------+----------------+----------+----------+----------+----------+
; JTAG_NEXUS_TCK ; CLK_REF        ; 152      ; 0        ; 0        ; 0        ;
; CLK_BRD        ; JTAG_NEXUS_TCK ; 120      ; 0        ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 163      ; 12       ; 0        ; 4        ;
+----------------+----------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 35    ; 35   ;
; Unconstrained Input Port Paths  ; 257   ; 257  ;
; Unconstrained Output Ports      ; 82    ; 82   ;
; Unconstrained Output Port Paths ; 3192  ; 3192 ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Sat Feb 06 01:10:46 2016
Info: Command: quartus_sta NOS031 --sdc=NOS031_sta.sdc
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Warning (335093): TimeQuest Timing Analyzer is analyzing 2 combinational loops as latches.
Info (332104): Reading SDC File: 'NOS031_sta.sdc'
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name JTAG_NEXUS_TCK JTAG_NEXUS_TCK
    Info (332105): create_clock -period 1.000 -name CLK_REF CLK_REF
    Info (332105): create_clock -period 1.000 -name CLK_BRD CLK_BRD
    Info (332105): create_clock -period 1.000 -name Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0]
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_9_0_component_c8|U2|clkd|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_9_0_component_c8|U2|clkd|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_9_0_component_c8|U1|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_9_0_component_c8|U1|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c5|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c5|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c4|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c4|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c3|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c3|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c2|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c2|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c1|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c1|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c0|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c0|clkd_cZ|dataa"
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -20.091
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -20.091     -2027.864 CLK_REF 
    Info (332119):   -17.494    -19184.186 CLK_BRD 
    Info (332119):   -11.445      -249.110 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
    Info (332119):    -6.938     -4774.992 JTAG_NEXUS_TCK 
Info (332146): Worst-case hold slack is -1.575
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.575       -30.425 CLK_REF 
    Info (332119):     0.147         0.000 CLK_BRD 
    Info (332119):     0.178         0.000 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.352         0.000 JTAG_NEXUS_TCK 
Info (332146): Worst-case recovery slack is -3.170
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.170      -135.590 JTAG_NEXUS_TCK 
    Info (332119):    -2.643       -84.479 CLK_REF 
Info (332146): Worst-case removal slack is 1.387
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.387         0.000 JTAG_NEXUS_TCK 
    Info (332119):     1.805         0.000 CLK_REF 
Info (332146): Worst-case minimum pulse width slack is -7.360
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.360     -2165.557 CLK_REF 
    Info (332119):    -4.000     -3066.467 CLK_BRD 
    Info (332119):    -3.000     -1708.589 JTAG_NEXUS_TCK 
    Info (332119):    -1.487       -83.272 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -19.229
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -19.229     -1906.571 CLK_REF 
    Info (332119):   -16.553    -17879.923 CLK_BRD 
    Info (332119):   -10.768      -233.203 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
    Info (332119):    -6.535     -4466.301 JTAG_NEXUS_TCK 
Info (332146): Worst-case hold slack is -2.497
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.497       -55.955 CLK_REF 
    Info (332119):     0.089         0.000 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.263         0.000 CLK_BRD 
    Info (332119):     0.320         0.000 JTAG_NEXUS_TCK 
Info (332146): Worst-case recovery slack is -2.846
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.846      -120.033 JTAG_NEXUS_TCK 
    Info (332119):    -2.387       -75.739 CLK_REF 
Info (332146): Worst-case removal slack is 1.262
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.262         0.000 JTAG_NEXUS_TCK 
    Info (332119):     1.633         0.000 CLK_REF 
Info (332146): Worst-case minimum pulse width slack is -7.458
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.458     -2057.786 CLK_REF 
    Info (332119):    -4.000     -3066.467 CLK_BRD 
    Info (332119):    -3.000     -1708.589 JTAG_NEXUS_TCK 
    Info (332119):    -1.487       -83.416 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -7.255
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.255      -700.454 CLK_REF 
    Info (332119):    -6.864     -7329.211 CLK_BRD 
    Info (332119):    -4.366       -79.869 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
    Info (332119):    -2.394     -1603.248 JTAG_NEXUS_TCK 
Info (332146): Worst-case hold slack is -0.338
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.338        -0.681 CLK_REF 
    Info (332119):    -0.136        -0.136 CLK_BRD 
    Info (332119):     0.063         0.000 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
    Info (332119):     0.083         0.000 JTAG_NEXUS_TCK 
Info (332146): Worst-case recovery slack is -0.832
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.832       -30.838 JTAG_NEXUS_TCK 
    Info (332119):    -0.669       -17.989 CLK_REF 
Info (332146): Worst-case removal slack is 0.569
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.569         0.000 JTAG_NEXUS_TCK 
    Info (332119):     0.808         0.000 CLK_REF 
Info (332146): Worst-case minimum pulse width slack is -3.208
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.208      -954.905 CLK_REF 
    Info (332119):    -3.000     -1975.537 CLK_BRD 
    Info (332119):    -3.000     -1213.921 JTAG_NEXUS_TCK 
    Info (332119):    -1.000       -56.000 Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:clk0|lpm_ff:ff1|dffs[0] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 35 warnings
    Info: Peak virtual memory: 450 megabytes
    Info: Processing ended: Sat Feb 06 01:11:18 2016
    Info: Elapsed time: 00:00:32
    Info: Total CPU time (on all processors): 00:00:18


