TimeQuest Timing Analyzer report for NOS031
Fri Feb 05 21:35:26 2016
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'CLK_REF'
 14. Slow 1200mV 85C Model Setup: 'CLK_BRD'
 15. Slow 1200mV 85C Model Setup: 'JTAG_NEXUS_TCK'
 16. Slow 1200mV 85C Model Hold: 'CLK_REF'
 17. Slow 1200mV 85C Model Hold: 'JTAG_NEXUS_TCK'
 18. Slow 1200mV 85C Model Hold: 'CLK_BRD'
 19. Slow 1200mV 85C Model Recovery: 'JTAG_NEXUS_TCK'
 20. Slow 1200mV 85C Model Recovery: 'CLK_REF'
 21. Slow 1200mV 85C Model Removal: 'JTAG_NEXUS_TCK'
 22. Slow 1200mV 85C Model Removal: 'CLK_REF'
 23. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_REF'
 24. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_BRD'
 25. Slow 1200mV 85C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
 26. Setup Times
 27. Hold Times
 28. Clock to Output Times
 29. Minimum Clock to Output Times
 30. Output Enable Times
 31. Minimum Output Enable Times
 32. Output Disable Times
 33. Minimum Output Disable Times
 34. Slow 1200mV 85C Model Metastability Report
 35. Slow 1200mV 0C Model Fmax Summary
 36. Slow 1200mV 0C Model Setup Summary
 37. Slow 1200mV 0C Model Hold Summary
 38. Slow 1200mV 0C Model Recovery Summary
 39. Slow 1200mV 0C Model Removal Summary
 40. Slow 1200mV 0C Model Minimum Pulse Width Summary
 41. Slow 1200mV 0C Model Setup: 'CLK_REF'
 42. Slow 1200mV 0C Model Setup: 'CLK_BRD'
 43. Slow 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'
 44. Slow 1200mV 0C Model Hold: 'CLK_REF'
 45. Slow 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'
 46. Slow 1200mV 0C Model Hold: 'CLK_BRD'
 47. Slow 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'
 48. Slow 1200mV 0C Model Recovery: 'CLK_REF'
 49. Slow 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'
 50. Slow 1200mV 0C Model Removal: 'CLK_REF'
 51. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_REF'
 52. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'
 53. Slow 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
 54. Setup Times
 55. Hold Times
 56. Clock to Output Times
 57. Minimum Clock to Output Times
 58. Output Enable Times
 59. Minimum Output Enable Times
 60. Output Disable Times
 61. Minimum Output Disable Times
 62. Slow 1200mV 0C Model Metastability Report
 63. Fast 1200mV 0C Model Setup Summary
 64. Fast 1200mV 0C Model Hold Summary
 65. Fast 1200mV 0C Model Recovery Summary
 66. Fast 1200mV 0C Model Removal Summary
 67. Fast 1200mV 0C Model Minimum Pulse Width Summary
 68. Fast 1200mV 0C Model Setup: 'CLK_REF'
 69. Fast 1200mV 0C Model Setup: 'CLK_BRD'
 70. Fast 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'
 71. Fast 1200mV 0C Model Hold: 'CLK_REF'
 72. Fast 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'
 73. Fast 1200mV 0C Model Hold: 'CLK_BRD'
 74. Fast 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'
 75. Fast 1200mV 0C Model Recovery: 'CLK_REF'
 76. Fast 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'
 77. Fast 1200mV 0C Model Removal: 'CLK_REF'
 78. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_REF'
 79. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'
 80. Fast 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'
 81. Setup Times
 82. Hold Times
 83. Clock to Output Times
 84. Minimum Clock to Output Times
 85. Output Enable Times
 86. Minimum Output Enable Times
 87. Output Disable Times
 88. Minimum Output Disable Times
 89. Fast 1200mV 0C Model Metastability Report
 90. Multicorner Timing Analysis Summary
 91. Setup Times
 92. Hold Times
 93. Clock to Output Times
 94. Minimum Clock to Output Times
 95. Board Trace Model Assignments
 96. Input Transition Times
 97. Slow Corner Signal Integrity Metrics
 98. Fast Corner Signal Integrity Metrics
 99. Setup Transfers
100. Hold Transfers
101. Recovery Transfers
102. Removal Transfers
103. Report TCCS
104. Report RSKM
105. Unconstrained Paths
106. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; NOS031                                                            ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C40F780C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+----------------------------------------------------+
; SDC File List                                      ;
+----------------+--------+--------------------------+
; SDC File Path  ; Status ; Read at                  ;
+----------------+--------+--------------------------+
; NOS031_sta.sdc ; OK     ; Fri Feb 05 21:35:04 2016 ;
+----------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                         ;
+----------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------------+
; Clock Name     ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets            ;
+----------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------------+
; CLK_BRD        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK_BRD }        ;
; CLK_REF        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK_REF }        ;
; JTAG_NEXUS_TCK ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { JTAG_NEXUS_TCK } ;
+----------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------------+


+------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                   ;
+------------+-----------------+----------------+------+
; Fmax       ; Restricted Fmax ; Clock Name     ; Note ;
+------------+-----------------+----------------+------+
; 28.74 MHz  ; 28.74 MHz       ; CLK_REF        ;      ;
; 46.55 MHz  ; 46.55 MHz       ; CLK_BRD        ;      ;
; 101.46 MHz ; 101.46 MHz      ; JTAG_NEXUS_TCK ;      ;
+------------+-----------------+----------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+------------------------------------------+
; Slow 1200mV 85C Model Setup Summary      ;
+----------------+---------+---------------+
; Clock          ; Slack   ; End Point TNS ;
+----------------+---------+---------------+
; CLK_REF        ; -24.053 ; -3253.348     ;
; CLK_BRD        ; -19.081 ; -19572.457    ;
; JTAG_NEXUS_TCK ; -7.149  ; -5088.325     ;
+----------------+---------+---------------+


+------------------------------------------+
; Slow 1200mV 85C Model Hold Summary       ;
+----------------+---------+---------------+
; Clock          ; Slack   ; End Point TNS ;
+----------------+---------+---------------+
; CLK_REF        ; -14.232 ; -558.200      ;
; JTAG_NEXUS_TCK ; 0.343   ; 0.000         ;
; CLK_BRD        ; 0.448   ; 0.000         ;
+----------------+---------+---------------+


+-----------------------------------------+
; Slow 1200mV 85C Model Recovery Summary  ;
+----------------+--------+---------------+
; Clock          ; Slack  ; End Point TNS ;
+----------------+--------+---------------+
; JTAG_NEXUS_TCK ; -3.723 ; -141.589      ;
; CLK_REF        ; -2.530 ; -83.786       ;
+----------------+--------+---------------+


+----------------------------------------+
; Slow 1200mV 85C Model Removal Summary  ;
+----------------+-------+---------------+
; Clock          ; Slack ; End Point TNS ;
+----------------+-------+---------------+
; JTAG_NEXUS_TCK ; 1.158 ; 0.000         ;
; CLK_REF        ; 1.711 ; 0.000         ;
+----------------+-------+---------------+


+---------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+----------------+--------+-------------------------+
; Clock          ; Slack  ; End Point TNS           ;
+----------------+--------+-------------------------+
; CLK_REF        ; -7.914 ; -5190.791               ;
; CLK_BRD        ; -4.000 ; -3064.980               ;
; JTAG_NEXUS_TCK ; -3.000 ; -1946.509               ;
+----------------+--------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLK_REF'                                                                                                                                                                                                  ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                               ; To Node                                                                       ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -24.053 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 18.640     ;
; -24.046 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 18.621     ;
; -23.930 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.425     ; 18.506     ;
; -23.810 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 18.385     ;
; -23.806 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 18.381     ;
; -23.615 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 18.190     ;
; -23.577 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.423     ; 18.155     ;
; -23.570 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.435     ; 18.136     ;
; -23.550 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 18.137     ;
; -23.550 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 18.137     ;
; -23.550 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 18.137     ;
; -23.550 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 18.137     ;
; -23.543 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 18.118     ;
; -23.543 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 18.118     ;
; -23.543 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 18.118     ;
; -23.543 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 18.118     ;
; -23.493 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 18.083     ;
; -23.491 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 18.081     ;
; -23.460 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 18.047     ;
; -23.454 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.434     ; 18.021     ;
; -23.441 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 18.031     ;
; -23.427 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.425     ; 18.003     ;
; -23.427 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.425     ; 18.003     ;
; -23.427 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.425     ; 18.003     ;
; -23.427 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.425     ; 18.003     ;
; -23.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.991     ;
; -23.391 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.966     ;
; -23.339 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.926     ;
; -23.334 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.435     ; 17.900     ;
; -23.330 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.435     ; 17.896     ;
; -23.307 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.882     ;
; -23.307 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.882     ;
; -23.307 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.882     ;
; -23.307 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.882     ;
; -23.303 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.878     ;
; -23.303 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.878     ;
; -23.303 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.878     ;
; -23.303 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.878     ;
; -23.303 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.412     ; 17.892     ;
; -23.297 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.412     ; 17.886     ;
; -23.286 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.412     ; 17.875     ;
; -23.272 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.847     ;
; -23.252 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.827     ;
; -23.230 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.415     ; 17.816     ;
; -23.192 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.782     ;
; -23.173 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.748     ;
; -23.154 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.729     ;
; -23.139 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.435     ; 17.705     ;
; -23.112 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.687     ;
; -23.112 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.687     ;
; -23.112 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.687     ;
; -23.112 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.687     ;
; -23.089 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.679     ;
; -23.079 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.666     ;
; -23.033 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.412     ; 17.622     ;
; -23.017 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.420     ; 17.598     ;
; -23.015 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.420     ; 17.596     ;
; -22.990 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.580     ;
; -22.990 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.580     ;
; -22.990 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.580     ;
; -22.990 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.580     ;
; -22.990 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.565     ;
; -22.988 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.578     ;
; -22.988 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.578     ;
; -22.988 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.578     ;
; -22.988 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.578     ;
; -22.984 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.423     ; 17.562     ;
; -22.967 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.557     ;
; -22.965 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.420     ; 17.546     ;
; -22.957 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.544     ;
; -22.957 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.544     ;
; -22.957 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.544     ;
; -22.957 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.544     ;
; -22.954 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.529     ;
; -22.938 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.528     ;
; -22.938 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.528     ;
; -22.938 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.528     ;
; -22.938 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.528     ;
; -22.934 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.521     ;
; -22.925 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.420     ; 17.506     ;
; -22.915 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.435     ; 17.481     ;
; -22.898 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.488     ;
; -22.898 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.488     ;
; -22.898 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.488     ;
; -22.898 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.411     ; 17.488     ;
; -22.888 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.463     ;
; -22.888 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.463     ;
; -22.888 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.463     ;
; -22.888 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.426     ; 17.463     ;
; -22.863 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.423     ; 17.441     ;
; -22.851 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.412     ; 17.440     ;
; -22.836 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.423     ;
; -22.836 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.423     ;
; -22.836 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.423     ;
; -22.836 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.414     ; 17.423     ;
; -22.827 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.421     ; 17.407     ;
; -22.821 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.421     ; 17.401     ;
; -22.810 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.421     ; 17.390     ;
; -22.800 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.412     ; 17.389     ;
; -22.800 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.412     ; 17.389     ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                           ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                                                                ; To Node                                                                                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -19.081 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                                                                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[0]  ; CLK_REF      ; CLK_BRD     ; 1.000        ; -16.342    ; 3.720      ;
; -18.986 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                                                                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[16] ; CLK_REF      ; CLK_BRD     ; 1.000        ; -16.342    ; 3.625      ;
; -17.512 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 18.109     ;
; -17.296 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.916     ;
; -17.215 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.823     ;
; -17.141 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.412     ; 17.730     ;
; -17.132 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.737     ;
; -17.125 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.730     ;
; -17.090 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.713     ;
; -17.082 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.415     ; 17.668     ;
; -17.078 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.400     ; 17.679     ;
; -17.070 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.399     ; 17.672     ;
; -17.028 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.406     ; 17.623     ;
; -17.017 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.617     ;
; -17.007 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.627     ;
; -17.000 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.620     ;
; -16.971 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.579     ;
; -16.967 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.567     ;
; -16.953 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.403     ; 17.551     ;
; -16.943 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.414     ; 17.530     ;
; -16.934 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.531     ;
; -16.927 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.524     ;
; -16.925 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.389     ; 17.537     ;
; -16.915 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.520     ;
; -16.914 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.519     ;
; -16.912 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.517     ;
; -16.911 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.516     ;
; -16.893 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.501     ;
; -16.874 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.405     ; 17.470     ;
; -16.871 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_4                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.415     ; 17.457     ;
; -16.846 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.469     ;
; -16.844 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.444     ;
; -16.841 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.438     ;
; -16.813 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.411     ; 17.403     ;
; -16.808 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.400     ; 17.409     ;
; -16.802 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.383     ; 17.420     ;
; -16.790 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.410     ;
; -16.789 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.409     ;
; -16.787 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.407     ;
; -16.786 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.406     ;
; -16.785 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.405     ; 17.381     ;
; -16.775 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.399     ; 17.377     ;
; -16.773 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.373     ;
; -16.767 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.407     ; 17.361     ;
; -16.763 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.371     ;
; -16.762 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.370     ;
; -16.761 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.358     ;
; -16.760 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.368     ;
; -16.758 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.366     ;
; -16.754 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.393     ; 17.362     ;
; -16.754 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.351     ;
; -16.750 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.371     ;
; -16.749 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.370     ;
; -16.749 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.415     ; 17.335     ;
; -16.748 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.369     ;
; -16.748 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_20                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.369     ;
; -16.744 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.365     ;
; -16.742 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.380     ; 17.363     ;
; -16.717 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.314     ;
; -16.716 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.313     ;
; -16.714 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.311     ;
; -16.713 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.404     ; 17.310     ;
; -16.711 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.423     ; 17.289     ;
; -16.707 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.408     ; 17.300     ;
; -16.699 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.407     ; 17.293     ;
; -16.694 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.294     ;
; -16.684 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.395     ; 17.290     ;
; -16.683 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.410     ; 17.274     ;
; -16.681 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.382     ; 17.300     ;
; -16.674 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.428     ; 17.247     ;
; -16.648 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.381     ; 17.268     ;
; -16.638 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.261     ;
; -16.637 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.260     ;
; -16.635 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.258     ;
; -16.633 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.396     ; 17.238     ;
; -16.633 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.256     ;
; -16.629 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 17.252     ;
; -16.625 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.365     ; 17.261     ;
; -16.624 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.365     ; 17.260     ;
; -16.623 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.365     ; 17.259     ;
; -16.623 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_20                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.365     ; 17.259     ;
; -16.619 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.365     ; 17.255     ;
; -16.617 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.365     ; 17.253     ;
; -16.613 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.405     ; 17.209     ;
; -16.606 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.402     ; 17.205     ;
; -16.605 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.416     ; 17.190     ;
; -16.604 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.388     ; 17.217     ;
; -16.600 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.400     ; 17.201     ;
; -16.600 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.200     ;
; -16.590 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.385     ; 17.206     ;
; -16.588 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.417     ; 17.172     ;
; -16.582 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.411     ; 17.172     ;
; -16.572 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.422     ; 17.151     ;
; -16.565 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.165     ;
; -16.564 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.164     ;
; -16.562 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.162     ;
; -16.560 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.408     ; 17.153     ;
; -16.560 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.160     ;
; -16.556 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.401     ; 17.156     ;
; -16.556 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.392     ; 17.165     ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                  ; To Node                                                                                                                                                                        ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -7.149 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.076     ; 8.074      ;
; -7.133 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 8.052      ;
; -7.027 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.076     ; 7.952      ;
; -7.011 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.930      ;
; -6.984 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.076     ; 7.909      ;
; -6.983 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 7.874      ;
; -6.968 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.887      ;
; -6.882 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 7.773      ;
; -6.855 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 7.782      ;
; -6.839 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.760      ;
; -6.825 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.746      ;
; -6.801 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.723      ;
; -6.774 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.076     ; 7.699      ;
; -6.769 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 7.696      ;
; -6.758 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 7.649      ;
; -6.758 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 7.677      ;
; -6.757 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.679      ;
; -6.753 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.674      ;
; -6.747 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.096     ; 7.652      ;
; -6.703 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.624      ;
; -6.679 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.601      ;
; -6.660 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.581      ;
; -6.637 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.110     ; 7.528      ;
; -6.636 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.558      ;
; -6.635 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.557      ;
; -6.592 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 7.519      ;
; -6.592 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.514      ;
; -6.576 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.497      ;
; -6.531 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.454      ;
; -6.507 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.431      ;
; -6.480 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.564     ; 6.917      ;
; -6.479 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 7.411      ;
; -6.464 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.570     ; 6.895      ;
; -6.464 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.388      ;
; -6.463 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.075     ; 7.389      ;
; -6.463 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.387      ;
; -6.450 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.371      ;
; -6.448 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.083     ; 7.366      ;
; -6.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.368      ;
; -6.426 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.348      ;
; -6.421 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.345      ;
; -6.393 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 7.320      ;
; -6.382 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 7.304      ;
; -6.377 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.298      ;
; -6.377 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.301      ;
; -6.332 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.380      ; 7.713      ;
; -6.268 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 7.191      ;
; -6.244 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.168      ;
; -6.231 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.380      ; 7.612      ;
; -6.200 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 7.124      ;
; -6.181 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 7.088      ;
; -6.156 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.568     ; 6.589      ;
; -6.155 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 7.083      ;
; -6.140 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.081     ; 7.060      ;
; -6.132 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.567     ; 6.566      ;
; -6.131 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.060      ;
; -6.118 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 7.045      ;
; -6.116 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.037      ;
; -6.111 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 7.043      ;
; -6.107 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.380      ; 7.488      ;
; -6.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 7.023      ;
; -6.096 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.394      ; 7.491      ;
; -6.095 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.075     ; 7.021      ;
; -6.088 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.567     ; 6.522      ;
; -6.087 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.016      ;
; -6.080 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 6.987      ;
; -6.072 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 6.993      ;
; -6.069 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 6.992      ;
; -6.062 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 6.995      ;
; -6.046 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 6.968      ;
; -6.046 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 6.973      ;
; -6.045 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 6.969      ;
; -6.017 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 6.941      ;
; -6.014 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 6.938      ;
; -6.012 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg_0                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.104     ; 6.909      ;
; -6.007 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 6.929      ;
; -6.001 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 6.925      ;
; -6.000 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.919      ;
; -5.986 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.380      ; 7.367      ;
; -5.984 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ0:U_MAGNITREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 6.913      ;
; -5.978 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 6.902      ;
; -5.975 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.077     ; 6.899      ;
; -5.968 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ0:U_MAGNITREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.078     ; 6.891      ;
; -5.961 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.880      ;
; -5.956 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.094     ; 6.863      ;
; -5.945 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 6.866      ;
; -5.942 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 6.871      ;
; -5.922 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.103     ; 6.820      ;
; -5.913 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.070     ; 6.844      ;
; -5.910 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.070     ; 6.841      ;
; -5.900 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3_2:U_TRMASKREG|sh_reg_0__Z                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.046     ; 6.855      ;
; -5.896 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.075     ; 6.822      ;
; -5.896 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|sh_reg_r_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 6.823      ;
; -5.884 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3_2:U_TRMASKREG|sh_reg_0__Z                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.052     ; 6.833      ;
; -5.881 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.091     ; 6.791      ;
; -5.880 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|sh_reg_r_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 6.801      ;
; -5.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 6.803      ;
; -5.860 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.080     ; 6.781      ;
; -5.854 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_0__Z                                                                                                          ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.786      ;
; -5.853 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.079     ; 6.775      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLK_REF'                                                                                                                                                                                                                                                 ;
+---------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                         ; To Node                                                                         ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -14.232 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]      ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 2.790      ;
; -14.184 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 2.852      ;
; -13.831 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 3.191      ;
; -13.784 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 3.252      ;
; -13.776 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 3.260      ;
; -13.736 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 3.286      ;
; -13.602 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 3.434      ;
; -13.585 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 3.451      ;
; -13.542 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 3.493      ;
; -13.536 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 3.500      ;
; -13.461 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 3.575      ;
; -13.041 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 3.995      ;
; -12.953 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.769     ; 4.068      ;
; -12.903 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 4.133      ;
; -12.777 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 4.245      ;
; -12.653 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 4.383      ;
; -12.633 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.769     ; 4.388      ;
; -12.618 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.784     ; 4.418      ;
; -12.614 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.769     ; 4.407      ;
; -11.882 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.769     ; 5.139      ;
; -11.659 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.772     ; 5.365      ;
; -11.479 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.772     ; 5.545      ;
; -11.037 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 5.985      ;
; -10.640 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.772     ; 6.384      ;
; -8.170  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.782     ; 8.864      ;
; -7.684  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0]   ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.773     ; 9.341      ;
; -7.333  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.773     ; 9.692      ;
; -7.285  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.769     ; 9.736      ;
; -7.263  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.772     ; 9.761      ;
; -7.177  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 9.845      ;
; -7.144  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.769     ; 9.877      ;
; -7.140  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.769     ; 9.881      ;
; -7.093  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 9.942      ;
; -7.068  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 9.967      ;
; -7.055  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 9.980      ;
; -7.055  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 9.980      ;
; -7.055  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 9.980      ;
; -7.055  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 9.980      ;
; -7.011  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 10.011     ;
; -6.990  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.045     ;
; -6.985  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.050     ;
; -6.979  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.772     ; 10.045     ;
; -6.955  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.080     ;
; -6.924  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.111     ;
; -6.911  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.124     ;
; -6.890  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.145     ;
; -6.860  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.175     ;
; -6.847  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.188     ;
; -6.845  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.803     ; 10.210     ;
; -6.811  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.224     ;
; -6.802  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 10.220     ;
; -6.779  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.256     ;
; -6.731  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.304     ;
; -6.705  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.330     ;
; -6.691  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.751     ; 10.312     ;
; -6.679  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.770     ; 10.343     ;
; -6.658  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.783     ; 10.377     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -6.385  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 16.802     ; 10.669     ;
; -2.064  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 16.431     ;
; -1.652  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.242     ; 16.842     ;
; -1.451  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.044     ;
; -1.198  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.297     ;
; -0.997  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.498     ;
; -0.979  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.242     ; 17.515     ;
; -0.973  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.522     ;
; -0.963  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.242     ; 17.531     ;
; -0.901  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.266     ; 17.617     ;
; -0.864  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.631     ;
; -0.779  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.266     ; 17.739     ;
; -0.765  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.266     ; 17.753     ;
; -0.659  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.836     ;
; -0.639  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.856     ;
; -0.621  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.242     ; 17.873     ;
; -0.612  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.266     ; 17.906     ;
; -0.553  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.942     ;
; -0.535  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 17.960     ;
; -0.469  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.266     ; 18.049     ;
; -0.451  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.242     ; 18.043     ;
; -0.444  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.266     ; 18.074     ;
; -0.421  ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 15.286     ; 15.117     ;
; -0.419  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 18.076     ;
; -0.404  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.243     ; 18.091     ;
; -0.356  ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26                                   ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 15.253     ; 15.149     ;
; -0.354  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.266     ; 18.164     ;
; -0.345  ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12                                   ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 15.286     ; 15.193     ;
; -0.335  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 18.242     ; 18.159     ;
+---------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                         ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.343 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[2]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[2]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.793      ;
; 0.344 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[3]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[3]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.794      ;
; 0.344 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[0]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg_0                                                                                                                                                                                   ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.794      ;
; 0.345 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[7]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.795      ;
; 0.345 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[4]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[4]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.795      ;
; 0.345 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[1]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[1]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.795      ;
; 0.346 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[6]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[6]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.796      ;
; 0.347 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[5]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[5]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.797      ;
; 0.367 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[3]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.817      ;
; 0.368 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[1]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.818      ;
; 0.369 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                                                                                               ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.198      ; 0.819      ;
; 0.378 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[5]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.197      ; 0.827      ;
; 0.379 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z                                                                                                                                                                                                                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                                                                          ; CLK_REF        ; JTAG_NEXUS_TCK ; 0.000        ; 0.190      ; 0.821      ;
; 0.380 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.197      ; 0.829      ;
; 0.451 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.746      ;
; 0.452 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.746      ;
; 0.463 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.758      ;
; 0.463 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.758      ;
; 0.464 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.758      ;
; 0.464 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.758      ;
; 0.464 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.758      ;
; 0.484 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.199      ; 0.935      ;
; 0.491 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_2__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_1__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 0.803      ;
; 0.493 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_3__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_2__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.100      ; 0.805      ;
; 0.493 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13                                                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.575      ; 1.280      ;
; 0.497 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[3]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.793      ;
; 0.498 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_2|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[24]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[24]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[21]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[21]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[12]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[12]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_26__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_25__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[2]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.794      ;
; 0.498 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_6__Z                                                                                                                                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_5__Z                                                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.498 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[2]                                                                                                                                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.793      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_30|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_29|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_17|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_13|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_13|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[29]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[29]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[26]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[26]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[22]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[22]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[19]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[19]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[18]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[18]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[15]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[15]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[11]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[11]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[6]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[6]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[4]                                                                                                                                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_22__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_21__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_21__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_20__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_19__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_18__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_18__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_17__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_14__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_13__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_13|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.793      ;
; 0.499 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[6]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[6]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[5]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[5]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[4]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[4]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[2]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[5]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[5]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.795      ;
; 0.499 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[4]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[4]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.084      ; 0.795      ;
; 0.499 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_12__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[18]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[17]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.499 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[18]                                                                                                                                                                                                                     ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[17]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.794      ;
; 0.500 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_20|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_19|lpm_ff:ff1|dffs[0]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.083      ; 0.795      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_20|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_19|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_18|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
; 0.500 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 0.794      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                              ; To Node                                                                                                                                                                                                        ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 0.448 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                         ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a3~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.479      ; 1.181      ;
; 0.450 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.084      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                                                                    ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                           ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                         ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                     ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                        ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                     ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.451 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.746      ;
; 0.452 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                           ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                     ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                      ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                          ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                          ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                           ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                      ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                      ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                         ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                       ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                           ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                          ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                     ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                                   ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.746      ;
; 0.464 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                      ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.758      ;
; 0.473 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_5                                                                          ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.479      ; 1.206      ;
; 0.490 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|clkval[9]                                                                                                        ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|clkval[9]                                                                                                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.784      ;
; 0.491 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                               ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.785      ;
; 0.495 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_11                                                                         ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.479      ; 1.228      ;
; 0.509 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff1_Z          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.803      ;
; 0.509 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff1_Z          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.803      ;
; 0.518 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_1                                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_1                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.813      ;
; 0.522 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                               ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.402      ; 1.178      ;
; 0.522 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|RegA_Abs_26__Z                                                                                       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|RegA_Abs_30__Z                                                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.817      ;
; 0.522 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_10                                                                         ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.479      ; 1.255      ;
; 0.523 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_21__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.818      ;
; 0.524 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.819      ;
; 0.524 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_20__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.819      ;
; 0.524 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.819      ;
; 0.524 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_14__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_13__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.819      ;
; 0.524 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_3                                                                 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_3                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.084      ; 0.820      ;
; 0.525 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_9__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.820      ;
; 0.525 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOnlineFF0                                                                                                    ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOnlineFF1                                                                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.819      ;
; 0.526 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_2                                                               ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.402      ; 1.182      ;
; 0.535 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_1                                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_0                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.830      ;
; 0.541 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_6__Z                                                                                           ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.835      ;
; 0.543 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z      ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff1_Z                                                            ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; 0.023      ; 0.818      ;
; 0.545 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_1                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|RxSetFF0                                                                                                                                               ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; 0.023      ; 0.820      ;
; 0.546 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_0                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF0                                                                                                                                       ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; 0.023      ; 0.821      ;
; 0.547 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_30__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_29__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.842      ;
; 0.547 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_17__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_16__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.842      ;
; 0.548 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_3__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_2__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.843      ;
; 0.549 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_2__Z                                                                                           ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_1__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.843      ;
; 0.549 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_27__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.844      ;
; 0.549 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_26__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.844      ;
; 0.549 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_17__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.844      ;
; 0.549 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_6__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.844      ;
; 0.549 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_6__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_5__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.844      ;
; 0.550 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_1__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_0__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.845      ;
; 0.551 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_13__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_12__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.846      ;
; 0.552 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_i_8__Z                                                                                         ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_7__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.847      ;
; 0.566 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_14                                                              ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.402      ; 1.222      ;
; 0.568 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_6                                                               ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.402      ; 1.224      ;
; 0.629 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.923      ;
; 0.672 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_0                                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_1                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.967      ;
; 0.675 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_0                                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_0                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.970      ;
; 0.697 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugReset_ff_Z                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugReset_Z                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.991      ;
; 0.698 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugEnable_ff_Z                   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugEnable_Z                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.992      ;
; 0.698 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff1_Z                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_Z                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.993      ;
; 0.702 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|DIN_REG1_13                                                                  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rs_Data_13                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.997      ;
; 0.703 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.083      ; 0.998      ;
; 0.705 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|SubstituteReg_Update_ff1_Z         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|SubstituteReg_Update_ff2_Z                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.999      ;
; 0.705 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOfflineFF0                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOfflineFF1                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.082      ; 0.999      ;
; 0.708 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemDataOut_12                                                              ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~portb_datain_reg0  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.399      ; 1.361      ;
; 0.710 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                                                                          ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.478      ; 1.442      ;
; 0.716 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|SubstituteReg_Update_Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|SubstituteReg_Update_ff1_Z                                                 ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; 0.023      ; 0.991      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                        ; To Node                                                                                                                                                                 ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -3.723 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.015     ; 4.689      ;
; -3.508 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.473      ;
; -3.508 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.473      ;
; -3.403 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.015     ; 4.369      ;
; -3.390 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.015     ; 4.356      ;
; -3.375 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.015     ; 4.341      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.239 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.204      ;
; -3.224 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.017     ; 4.188      ;
; -3.188 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.153      ;
; -3.188 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.153      ;
; -3.175 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.140      ;
; -3.175 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.140      ;
; -3.167 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.015     ; 4.133      ;
; -3.160 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.125      ;
; -3.160 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 4.125      ;
; -3.139 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.505     ; 3.615      ;
; -3.080 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.015     ; 4.046      ;
; -3.021 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.015     ; 3.987      ;
; -2.947 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.912      ;
; -2.947 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.912      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.919 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.884      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.906 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.871      ;
; -2.904 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.017     ; 3.868      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.017     ; 3.855      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.891 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.856      ;
; -2.876 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.017     ; 3.840      ;
; -2.871 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.506     ; 3.346      ;
; -2.871 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.506     ; 3.346      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.830      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.830      ;
; -2.780 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.745      ;
; -2.780 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.745      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.678 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.643      ;
; -2.663 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.017     ; 3.627      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.596 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.016     ; 3.561      ;
; -2.591 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 3.510      ;
; -2.591 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.506     ; 3.066      ;
; -2.591 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.506     ; 3.066      ;
; -2.591 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.506     ; 3.066      ;
; -2.591 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.506     ; 3.066      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'CLK_REF'                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.530 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.315      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.230      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.368 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 3.153      ;
; -2.366 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 3.144      ;
; -2.300 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 3.078      ;
; -2.297 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 3.074      ;
; -2.212 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.989      ;
; -2.204 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.982      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.966      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.966      ;
; -2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.966      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.957      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.153 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.938      ;
; -2.135 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.912      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.102 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.887      ;
; -2.101 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.881      ;
; -2.101 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.881      ;
; -2.101 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.881      ;
; -2.024 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.804      ;
; -2.024 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.804      ;
; -2.024 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.201     ; 2.804      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -2.010 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.196     ; 2.795      ;
; -1.989 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.203     ; 2.767      ;
; -1.920 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.204     ; 2.697      ;
; -1.875 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.268      ; 3.124      ;
; -1.875 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.268      ; 3.124      ;
; -1.875 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.268      ; 3.124      ;
; -1.875 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.268      ; 3.124      ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                                                     ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 1.158 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.452      ;
; 1.158 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.452      ;
; 1.158 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.452      ;
; 1.158 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 1.452      ;
; 1.354 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_10|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.114      ; 1.680      ;
; 1.354 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_9|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.114      ; 1.680      ;
; 1.354 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_2|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.114      ; 1.680      ;
; 1.354 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_1|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.114      ; 1.680      ;
; 1.399 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.692      ;
; 1.399 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.692      ;
; 1.399 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.692      ;
; 1.399 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.081      ; 1.692      ;
; 1.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.071      ; 1.452      ;
; 1.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.071      ; 1.452      ;
; 1.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.071      ; 1.452      ;
; 1.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.071      ; 1.452      ;
; 1.651 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.069      ; 1.452      ;
; 1.651 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.069      ; 1.452      ;
; 1.651 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.069      ; 1.452      ;
; 1.651 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.069      ; 1.452      ;
; 1.686 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_12|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.984      ;
; 1.686 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.984      ;
; 1.686 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_3|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.984      ;
; 1.686 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_4|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 1.984      ;
; 1.714 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_6|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.008      ;
; 1.714 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_14|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.008      ;
; 1.714 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_13|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.008      ;
; 1.714 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_5|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.008      ;
; 1.847 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.065      ; 1.644      ;
; 1.847 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.065      ; 1.644      ;
; 1.847 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.065      ; 1.644      ;
; 1.847 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.065      ; 1.644      ;
; 1.918 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_7|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.076      ; 2.206      ;
; 1.918 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_15|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.076      ; 2.206      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.185 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.479      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.501      ;
; 2.225 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.069      ; 2.506      ;
; 2.225 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.069      ; 2.506      ;
; 2.227 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.069      ; 2.508      ;
; 2.277 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_8|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 2.575      ;
; 2.277 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 2.575      ;
; 2.277 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 2.575      ;
; 2.277 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_17|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 2.575      ;
; 2.277 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_0|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.086      ; 2.575      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.279 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.080      ; 2.571      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.285 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.082      ; 2.579      ;
; 2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.069      ; 2.576      ;
; 2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.069      ; 2.576      ;
; 2.297 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.069      ; 2.578      ;
; 2.409 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.571      ; 3.192      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'CLK_REF'                                                                                                                                                                                                                            ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.472      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.472      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.472      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.472      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.472      ;
; 1.711 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.472      ;
; 1.781 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.542      ;
; 1.781 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.542      ;
; 1.781 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.542      ;
; 1.781 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.542      ;
; 1.781 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.542      ;
; 1.781 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.542      ;
; 1.803 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.565      ;
; 1.803 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.565      ;
; 1.803 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.565      ;
; 1.803 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.565      ;
; 1.803 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.565      ;
; 1.873 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.635      ;
; 1.873 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.635      ;
; 1.873 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.635      ;
; 1.873 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.635      ;
; 1.873 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.635      ;
; 1.946 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.707      ;
; 1.946 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.707      ;
; 1.946 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.707      ;
; 1.946 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.707      ;
; 1.946 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.707      ;
; 1.946 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.707      ;
; 2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.786      ;
; 2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.786      ;
; 2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.786      ;
; 2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.786      ;
; 2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.786      ;
; 2.025 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.509      ; 2.786      ;
; 2.038 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.800      ;
; 2.038 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.800      ;
; 2.038 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.800      ;
; 2.038 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.800      ;
; 2.038 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.800      ;
; 2.113 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.875      ;
; 2.113 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.875      ;
; 2.113 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.875      ;
; 2.113 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.875      ;
; 2.113 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.510      ; 2.875      ;
; 2.118 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.392      ;
; 2.118 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.392      ;
; 2.118 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.392      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.139 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.417      ;
; 2.188 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.462      ;
; 2.188 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.462      ;
; 2.188 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.462      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.487      ;
; 2.238 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.508      ;
; 2.308 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.018      ; 2.578      ;
; 2.329 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.020      ; 2.601      ;
; 2.353 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.627      ;
; 2.353 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.627      ;
; 2.353 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.627      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.374 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.026      ; 2.652      ;
; 2.399 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.020      ; 2.671      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.027      ; 2.695      ;
; 2.432 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.706      ;
; 2.432 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.706      ;
; 2.432 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.022      ; 2.706      ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_REF'                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ;
; -7.914 ; -7.694       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ;
; -7.913 ; -7.693       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ;
; -7.853 ; -7.633       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ;
; -7.852 ; -7.632       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_0_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_10_|clk                                                                               ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_11_|clk                                                                               ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_12_|clk                                                                               ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_13_|clk                                                                               ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_14_|clk                                                                               ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_15_|clk                                                                               ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_1_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_2_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_3_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_4_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_5_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_6_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_7_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_8_|clk                                                                                ;
; -7.645 ; -7.645       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_9_|clk                                                                                ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_16_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_17_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_18_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_19_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_20_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_21_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_22_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_23_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_24_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_25_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_26_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_27_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_28_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_29_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_30_|clk                                                                               ;
; -7.644 ; -7.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_31_|clk                                                                               ;
; -7.635 ; -7.635       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|inclk[0]                                                                      ;
; -7.635 ; -7.635       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|outclk                                                                        ;
; -7.585 ; -7.585       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_2_0_component_c11|clko_s_Z|clk                                                                                 ;
; -7.583 ; -7.583       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|outstate_Z|clk                                                                              ;
; -7.522 ; -7.522       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|combout                                                                            ;
; -7.521 ; -7.521       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -7.497 ; -7.497       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|datab                                                                         ;
; -6.889 ; -6.669       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ;
; -6.889 ; -6.669       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ;
; -6.889 ; -6.669       ; 0.220          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ;
; -6.702 ; -6.514       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ;
; -6.687 ; -6.499       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ;
; -6.671 ; -6.671       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout                                                                              ;
; -6.643 ; -6.643       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|datab                                                                              ;
; -6.633 ; -6.633       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|datad                                                                                ;
; -6.630 ; -6.630       ; 0.000          ; Low Pulse Width  ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -6.630 ; -6.630       ; 0.000          ; Low Pulse Width  ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|datab                                                                         ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ;
; -6.628 ; -6.440       ; 0.188          ; Low Pulse Width  ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock   ; Clock Edge ; Target                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT0  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT1  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT2  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT3  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT0 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT1 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT2 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT3 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a2~porta_datain_reg0              ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                           ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[10]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[11]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[12]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[1]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[2]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[3]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[4]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[5]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[6]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[7]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[8]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[9]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0 ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_1    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_10   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_11   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_12   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_15   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_5    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_6    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_7    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_8    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_9    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[10]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[11]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[12]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[13]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[15]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[16]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[17]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[18]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[19]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[1]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[20]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[21]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[22]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[23]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[24]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[25]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[26]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[27]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[28]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[29]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[2]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[30]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[3]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[4]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[5]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[6]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[7]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[8]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[9]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_20   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_28   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_4    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_6    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_7    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[1]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]  ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------+
; Setup Times                                                                      ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; 5.157  ; 5.173  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 3.766  ; 3.956  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 4.780  ; 4.846  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 3.769  ; 3.981  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 4.061  ; 4.225  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.578  ; 4.710  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 5.157  ; 5.173  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 4.897  ; 4.983  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 3.688  ; 3.873  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 3.934  ; 4.096  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 4.877  ; 5.086  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.669  ; 4.880  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 4.570  ; 4.674  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 3.968  ; 4.170  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 4.303  ; 4.425  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 4.373  ; 4.551  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 4.086  ; 4.292  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 5.079  ; 5.054  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.427  ; 3.513  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 4.376  ; 4.572  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 3.678  ; 3.890  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 4.115  ; 4.291  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 4.876  ; 4.966  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.952  ; 4.997  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 4.750  ; 4.806  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 3.731  ; 3.890  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 3.925  ; 4.046  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 4.346  ; 4.427  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 4.181  ; 4.320  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 4.230  ; 4.443  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 5.079  ; 5.054  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 4.244  ; 4.415  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.647  ; 4.765  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 3.848  ; 4.052  ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; 5.049  ; 5.357  ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; 18.429 ; 17.379 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.261  ; 0.527  ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; 3.937  ; 4.177  ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; 4.717  ; 4.950  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Hold Times                                                                       ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; -1.936 ; -2.236 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; -1.975 ; -2.249 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; -2.691 ; -2.914 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; -2.037 ; -2.320 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; -2.385 ; -2.630 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; -2.502 ; -2.733 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; -2.489 ; -2.660 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; -2.477 ; -2.716 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; -2.032 ; -2.267 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; -2.237 ; -2.425 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; -2.886 ; -3.122 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; -2.885 ; -3.175 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; -2.473 ; -2.676 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; -1.936 ; -2.236 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; -1.982 ; -2.259 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; -2.325 ; -2.585 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; -2.141 ; -2.419 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; -1.800 ; -2.029 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; -1.800 ; -2.029 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; -2.160 ; -2.421 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; -1.965 ; -2.246 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; -2.088 ; -2.360 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; -2.478 ; -2.719 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; -2.440 ; -2.641 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; -2.384 ; -2.582 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; -2.076 ; -2.285 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; -2.563 ; -2.761 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; -2.324 ; -2.492 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; -2.428 ; -2.630 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; -2.228 ; -2.480 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; -2.016 ; -2.208 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; -2.204 ; -2.449 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; -2.578 ; -2.807 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; -2.081 ; -2.317 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; -2.157 ; -2.466 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; -6.893 ; -6.910 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.231  ; 0.008  ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; -1.985 ; -2.290 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; -2.199 ; -2.456 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Clock to Output Times                                                            ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_A[*]     ; CLK_BRD        ; 20.873 ; 20.793 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[0]    ; CLK_BRD        ; 16.175 ; 15.854 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[1]    ; CLK_BRD        ; 18.432 ; 18.220 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[2]    ; CLK_BRD        ; 16.298 ; 16.096 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[3]    ; CLK_BRD        ; 17.286 ; 17.197 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[4]    ; CLK_BRD        ; 18.766 ; 18.428 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[5]    ; CLK_BRD        ; 19.319 ; 19.005 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[6]    ; CLK_BRD        ; 18.915 ; 18.624 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[7]    ; CLK_BRD        ; 20.873 ; 20.793 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[8]    ; CLK_BRD        ; 18.533 ; 18.238 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[9]    ; CLK_BRD        ; 20.179 ; 19.969 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[10]   ; CLK_BRD        ; 19.332 ; 19.020 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[11]   ; CLK_BRD        ; 18.322 ; 18.116 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[12]   ; CLK_BRD        ; 18.503 ; 18.255 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[13]   ; CLK_BRD        ; 19.699 ; 19.322 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[14]   ; CLK_BRD        ; 19.724 ; 19.491 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[15]   ; CLK_BRD        ; 17.718 ; 17.372 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[16]   ; CLK_BRD        ; 17.023 ; 16.767 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[17]   ; CLK_BRD        ; 17.748 ; 17.476 ; Rise       ; CLK_BRD         ;
; SRAM0_D[*]     ; CLK_BRD        ; 9.914  ; 9.467  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 7.765  ; 7.580  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 9.914  ; 9.467  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 8.308  ; 8.219  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 7.105  ; 6.989  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 9.006  ; 8.744  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 9.587  ; 9.244  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 7.982  ; 7.845  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 7.700  ; 7.626  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 8.565  ; 8.293  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 8.239  ; 8.039  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 8.707  ; 8.498  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 8.315  ; 8.119  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 8.362  ; 8.247  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 7.709  ; 7.473  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 8.403  ; 8.101  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 8.140  ; 7.883  ; Rise       ; CLK_BRD         ;
; SRAM0_E        ; CLK_BRD        ; 22.512 ; 22.153 ; Rise       ; CLK_BRD         ;
; SRAM0_LB       ; CLK_BRD        ; 21.697 ; 21.473 ; Rise       ; CLK_BRD         ;
; SRAM0_OE       ; CLK_BRD        ; 19.665 ; 19.650 ; Rise       ; CLK_BRD         ;
; SRAM0_UB       ; CLK_BRD        ; 21.388 ; 21.288 ; Rise       ; CLK_BRD         ;
; SRAM0_W        ; CLK_BRD        ; 7.919  ; 8.032  ; Rise       ; CLK_BRD         ;
; SRAM1_A[*]     ; CLK_BRD        ; 20.268 ; 20.081 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[0]    ; CLK_BRD        ; 16.249 ; 15.912 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[1]    ; CLK_BRD        ; 19.227 ; 19.169 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[2]    ; CLK_BRD        ; 16.981 ; 16.681 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[3]    ; CLK_BRD        ; 17.249 ; 17.168 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[4]    ; CLK_BRD        ; 18.410 ; 18.113 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[5]    ; CLK_BRD        ; 18.505 ; 18.232 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[6]    ; CLK_BRD        ; 19.652 ; 19.558 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[7]    ; CLK_BRD        ; 18.936 ; 18.715 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[8]    ; CLK_BRD        ; 18.150 ; 17.916 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[9]    ; CLK_BRD        ; 18.978 ; 18.806 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[10]   ; CLK_BRD        ; 18.986 ; 18.654 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[11]   ; CLK_BRD        ; 18.379 ; 18.193 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[12]   ; CLK_BRD        ; 18.582 ; 18.388 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[13]   ; CLK_BRD        ; 20.268 ; 20.081 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[14]   ; CLK_BRD        ; 19.657 ; 19.174 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[15]   ; CLK_BRD        ; 18.475 ; 18.064 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[16]   ; CLK_BRD        ; 16.675 ; 16.445 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[17]   ; CLK_BRD        ; 17.701 ; 17.440 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 9.266  ; 8.843  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 8.153  ; 7.955  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 8.341  ; 8.044  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 8.447  ; 8.143  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 8.895  ; 8.579  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 9.266  ; 8.780  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 8.862  ; 8.641  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 8.361  ; 8.226  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 8.948  ; 8.843  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 8.580  ; 8.322  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 8.747  ; 8.451  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 8.832  ; 8.739  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 8.345  ; 8.167  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 7.737  ; 7.557  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 7.894  ; 7.756  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 9.135  ; 8.777  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 7.728  ; 7.573  ; Rise       ; CLK_BRD         ;
; SRAM1_E        ; CLK_BRD        ; 21.855 ; 21.711 ; Rise       ; CLK_BRD         ;
; SRAM1_LB       ; CLK_BRD        ; 22.511 ; 22.285 ; Rise       ; CLK_BRD         ;
; SRAM1_OE       ; CLK_BRD        ; 20.988 ; 20.802 ; Rise       ; CLK_BRD         ;
; SRAM1_UB       ; CLK_BRD        ; 22.026 ; 21.852 ; Rise       ; CLK_BRD         ;
; SRAM1_W        ; CLK_BRD        ; 10.080 ; 10.159 ; Rise       ; CLK_BRD         ;
; DAC_CLK        ; CLK_REF        ; 25.761 ; 25.617 ; Rise       ; CLK_REF         ;
; DAC_CS         ; CLK_REF        ; 27.160 ; 26.803 ; Rise       ; CLK_REF         ;
; DAC_DOUT       ; CLK_REF        ; 28.411 ; 27.845 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ; 12.132 ; 11.954 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                    ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_A[*]     ; CLK_BRD        ; 8.439  ; 8.188  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[0]    ; CLK_BRD        ; 9.419  ; 9.057  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[1]    ; CLK_BRD        ; 11.428 ; 10.904 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[2]    ; CLK_BRD        ; 8.439  ; 8.188  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[3]    ; CLK_BRD        ; 10.020 ; 9.749  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[4]    ; CLK_BRD        ; 10.885 ; 10.442 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[5]    ; CLK_BRD        ; 12.231 ; 11.628 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[6]    ; CLK_BRD        ; 12.214 ; 11.658 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[7]    ; CLK_BRD        ; 14.587 ; 14.291 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[8]    ; CLK_BRD        ; 10.626 ; 10.201 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[9]    ; CLK_BRD        ; 13.290 ; 12.761 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[10]   ; CLK_BRD        ; 10.209 ; 9.889  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[11]   ; CLK_BRD        ; 10.542 ; 10.238 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[12]   ; CLK_BRD        ; 10.783 ; 10.486 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[13]   ; CLK_BRD        ; 10.576 ; 10.188 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[14]   ; CLK_BRD        ; 12.302 ; 11.944 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[15]   ; CLK_BRD        ; 10.021 ; 9.561  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[16]   ; CLK_BRD        ; 8.963  ; 8.641  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[17]   ; CLK_BRD        ; 9.973  ; 9.599  ; Rise       ; CLK_BRD         ;
; SRAM0_D[*]     ; CLK_BRD        ; 6.944  ; 6.830  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 7.579  ; 7.398  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 9.641  ; 9.209  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 8.100  ; 8.012  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 6.944  ; 6.830  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 8.778  ; 8.525  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 9.334  ; 9.004  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 7.795  ; 7.662  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 7.523  ; 7.450  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 8.353  ; 8.090  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 8.041  ; 7.847  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 8.490  ; 8.288  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 8.115  ; 7.924  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 8.151  ; 8.037  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 7.525  ; 7.295  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 8.192  ; 7.899  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 7.938  ; 7.689  ; Rise       ; CLK_BRD         ;
; SRAM0_E        ; CLK_BRD        ; 10.346 ; 9.871  ; Rise       ; CLK_BRD         ;
; SRAM0_LB       ; CLK_BRD        ; 9.564  ; 9.218  ; Rise       ; CLK_BRD         ;
; SRAM0_OE       ; CLK_BRD        ; 7.614  ; 7.469  ; Rise       ; CLK_BRD         ;
; SRAM0_UB       ; CLK_BRD        ; 9.060  ; 8.810  ; Rise       ; CLK_BRD         ;
; SRAM0_W        ; CLK_BRD        ; 7.731  ; 7.842  ; Rise       ; CLK_BRD         ;
; SRAM1_A[*]     ; CLK_BRD        ; 8.629  ; 8.332  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[0]    ; CLK_BRD        ; 9.491  ; 9.114  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[1]    ; CLK_BRD        ; 12.249 ; 11.878 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[2]    ; CLK_BRD        ; 9.095  ; 8.750  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[3]    ; CLK_BRD        ; 9.985  ; 9.722  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[4]    ; CLK_BRD        ; 10.541 ; 10.138 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[5]    ; CLK_BRD        ; 11.449 ; 10.886 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[6]    ; CLK_BRD        ; 12.976 ; 12.613 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[7]    ; CLK_BRD        ; 12.671 ; 12.236 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[8]    ; CLK_BRD        ; 10.259 ; 9.893  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[9]    ; CLK_BRD        ; 12.139 ; 11.646 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[10]   ; CLK_BRD        ; 9.877  ; 9.539  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[11]   ; CLK_BRD        ; 10.596 ; 10.312 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[12]   ; CLK_BRD        ; 10.859 ; 10.613 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[13]   ; CLK_BRD        ; 11.176 ; 10.974 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[14]   ; CLK_BRD        ; 12.183 ; 11.580 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[15]   ; CLK_BRD        ; 10.748 ; 10.225 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[16]   ; CLK_BRD        ; 8.629  ; 8.332  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[17]   ; CLK_BRD        ; 9.928  ; 9.565  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 7.542  ; 7.375  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 7.948  ; 7.756  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 8.130  ; 7.841  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 8.233  ; 7.938  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 8.662  ; 8.355  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 9.017  ; 8.547  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 8.638  ; 8.425  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 8.158  ; 8.027  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 8.723  ; 8.620  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 8.368  ; 8.119  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 8.525  ; 8.239  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 8.611  ; 8.520  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 8.143  ; 7.971  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 7.551  ; 7.375  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 7.702  ; 7.567  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 8.894  ; 8.548  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 7.542  ; 7.391  ; Rise       ; CLK_BRD         ;
; SRAM1_E        ; CLK_BRD        ; 9.717  ; 9.447  ; Rise       ; CLK_BRD         ;
; SRAM1_LB       ; CLK_BRD        ; 10.139 ; 9.791  ; Rise       ; CLK_BRD         ;
; SRAM1_OE       ; CLK_BRD        ; 8.885  ; 8.576  ; Rise       ; CLK_BRD         ;
; SRAM1_UB       ; CLK_BRD        ; 9.678  ; 9.362  ; Rise       ; CLK_BRD         ;
; SRAM1_W        ; CLK_BRD        ; 9.864  ; 9.938  ; Rise       ; CLK_BRD         ;
; DAC_CLK        ; CLK_REF        ; 19.035 ; 18.893 ; Rise       ; CLK_REF         ;
; DAC_CS         ; CLK_REF        ; 20.386 ; 20.042 ; Rise       ; CLK_REF         ;
; DAC_DOUT       ; CLK_REF        ; 21.586 ; 21.041 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ; 9.365  ; 9.209  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------+
; Output Enable Times                                                        ;
+--------------+------------+--------+--------+------------+-----------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+--------------+------------+--------+--------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 20.478 ; 20.478 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 21.089 ; 21.089 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 22.151 ; 22.151 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 21.842 ; 21.842 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 20.757 ; 20.757 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 21.204 ; 21.204 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 21.886 ; 21.886 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 22.243 ; 22.243 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 22.212 ; 22.212 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 22.279 ; 22.279 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 21.900 ; 21.900 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 21.204 ; 21.204 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 21.922 ; 21.922 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 21.740 ; 21.740 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 20.478 ; 20.478 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 21.411 ; 21.411 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 21.391 ; 21.391 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 20.429 ; 20.429 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 20.429 ; 20.429 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 22.131 ; 22.131 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 21.810 ; 21.810 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 21.760 ; 21.760 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 22.131 ; 22.131 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 21.847 ; 21.847 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 21.916 ; 21.916 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 21.735 ; 21.735 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 21.890 ; 21.890 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 21.916 ; 21.916 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 21.912 ; 21.912 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 22.683 ; 22.683 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 20.468 ; 20.468 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 21.796 ; 21.796 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 21.806 ; 21.806 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 21.360 ; 21.360 ; Rise       ; CLK_BRD         ;
+--------------+------------+--------+--------+------------+-----------------+


+---------------------------------------------------------------------------+
; Minimum Output Enable Times                                               ;
+--------------+------------+-------+--------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall   ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+--------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 7.844 ; 7.910  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 8.430 ; 8.496  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 9.449 ; 9.515  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 9.154 ; 9.220  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 8.110 ; 8.176  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 8.552 ; 8.612  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 9.205 ; 9.265  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 9.549 ; 9.609  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 9.518 ; 9.578  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 9.582 ; 9.642  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 9.220 ; 9.280  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 8.552 ; 8.612  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 9.241 ; 9.301  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 9.054 ; 9.120  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 7.844 ; 7.910  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 8.740 ; 8.806  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 8.720 ; 8.786  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 7.795 ; 7.861  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 7.795 ; 7.861  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 9.429 ; 9.495  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 9.124 ; 9.190  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 9.074 ; 9.140  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 9.429 ; 9.495  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 9.168 ; 9.228  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 9.235 ; 9.295  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 9.062 ; 9.122  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 9.210 ; 9.270  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 9.235 ; 9.295  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 9.231 ; 9.291  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 9.972 ; 10.032 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 7.834 ; 7.900  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 9.109 ; 9.175  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 9.119 ; 9.185  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 8.690 ; 8.756  ; Rise       ; CLK_BRD         ;
+--------------+------------+-------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Output Disable Times                                                             ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 20.303    ; 20.440    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 20.838    ; 20.975    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 21.818    ; 21.955    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 21.525    ; 21.662    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 20.524    ; 20.661    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 21.012    ; 21.143    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 21.594    ; 21.725    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 21.973    ; 22.104    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 21.901    ; 22.032    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 21.959    ; 22.090    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 21.621    ; 21.752    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 21.012    ; 21.143    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 21.636    ; 21.767    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 21.407    ; 21.544    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 20.303    ; 20.440    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 21.130    ; 21.267    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 21.110    ; 21.247    ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 20.255    ; 20.392    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 20.255    ; 20.392    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 21.798    ; 21.935    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 21.510    ; 21.647    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 21.460    ; 21.597    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 21.798    ; 21.935    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 21.562    ; 21.693    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 21.624    ; 21.755    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 21.440    ; 21.571    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 21.611    ; 21.742    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 21.624    ; 21.755    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 21.626    ; 21.757    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 22.319    ; 22.450    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 20.293    ; 20.430    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 21.471    ; 21.608    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 21.481    ; 21.618    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 21.083    ; 21.220    ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                     ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 7.680     ; 7.680     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 8.193     ; 8.193     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 9.133     ; 9.133     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 8.852     ; 8.852     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 7.891     ; 7.891     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 8.365     ; 8.365     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 8.923     ; 8.923     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 9.288     ; 9.288     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 9.218     ; 9.218     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 9.273     ; 9.273     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 8.950     ; 8.950     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 8.365     ; 8.365     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 8.965     ; 8.965     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 8.738     ; 8.738     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 7.680     ; 7.680     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 8.474     ; 8.474     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 8.454     ; 8.454     ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 7.633     ; 7.633     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 7.633     ; 7.633     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 9.113     ; 9.113     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 8.839     ; 8.839     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 8.789     ; 8.789     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 9.113     ; 9.113     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 8.893     ; 8.893     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 8.953     ; 8.953     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 8.778     ; 8.778     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 8.940     ; 8.940     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 8.953     ; 8.953     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 8.955     ; 8.955     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 9.621     ; 9.621     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 7.670     ; 7.670     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 8.801     ; 8.801     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 8.811     ; 8.811     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 8.428     ; 8.428     ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                    ;
+------------+-----------------+----------------+------+
; Fmax       ; Restricted Fmax ; Clock Name     ; Note ;
+------------+-----------------+----------------+------+
; 31.41 MHz  ; 31.41 MHz       ; CLK_REF        ;      ;
; 49.71 MHz  ; 49.71 MHz       ; CLK_BRD        ;      ;
; 108.62 MHz ; 108.62 MHz      ; JTAG_NEXUS_TCK ;      ;
+------------+-----------------+----------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------+
; Slow 1200mV 0C Model Setup Summary       ;
+----------------+---------+---------------+
; Clock          ; Slack   ; End Point TNS ;
+----------------+---------+---------------+
; CLK_REF        ; -22.936 ; -3074.914     ;
; CLK_BRD        ; -18.159 ; -18224.853    ;
; JTAG_NEXUS_TCK ; -6.681  ; -4729.865     ;
+----------------+---------+---------------+


+------------------------------------------+
; Slow 1200mV 0C Model Hold Summary        ;
+----------------+---------+---------------+
; Clock          ; Slack   ; End Point TNS ;
+----------------+---------+---------------+
; CLK_REF        ; -13.651 ; -598.797      ;
; JTAG_NEXUS_TCK ; 0.315   ; 0.000         ;
; CLK_BRD        ; 0.399   ; 0.000         ;
+----------------+---------+---------------+


+-----------------------------------------+
; Slow 1200mV 0C Model Recovery Summary   ;
+----------------+--------+---------------+
; Clock          ; Slack  ; End Point TNS ;
+----------------+--------+---------------+
; JTAG_NEXUS_TCK ; -3.327 ; -124.319      ;
; CLK_REF        ; -2.295 ; -75.306       ;
+----------------+--------+---------------+


+----------------------------------------+
; Slow 1200mV 0C Model Removal Summary   ;
+----------------+-------+---------------+
; Clock          ; Slack ; End Point TNS ;
+----------------+-------+---------------+
; JTAG_NEXUS_TCK ; 1.069 ; 0.000         ;
; CLK_REF        ; 1.510 ; 0.000         ;
+----------------+-------+---------------+


+--------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------+--------+------------------------+
; Clock          ; Slack  ; End Point TNS          ;
+----------------+--------+------------------------+
; CLK_REF        ; -7.940 ; -4881.689              ;
; CLK_BRD        ; -4.000 ; -3064.980              ;
; JTAG_NEXUS_TCK ; -3.000 ; -1946.509              ;
+----------------+--------+------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLK_REF'                                                                                                                                                                                                   ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                               ; To Node                                                                       ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -22.936 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 17.712     ;
; -22.926 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.218     ; 17.710     ;
; -22.819 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 17.596     ;
; -22.710 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 17.486     ;
; -22.690 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 17.466     ;
; -22.502 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 17.278     ;
; -22.398 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.231     ; 17.169     ;
; -22.388 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.223     ; 17.167     ;
; -22.378 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 17.155     ;
; -22.378 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 17.155     ;
; -22.378 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 17.155     ;
; -22.378 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 17.155     ;
; -22.373 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 17.160     ;
; -22.371 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 17.158     ;
; -22.368 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.218     ; 17.152     ;
; -22.368 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 17.153     ;
; -22.368 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 17.153     ;
; -22.368 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 17.153     ;
; -22.368 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 17.153     ;
; -22.332 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 17.119     ;
; -22.302 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 17.089     ;
; -22.289 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 17.065     ;
; -22.281 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.230     ; 17.053     ;
; -22.261 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.224     ; 17.039     ;
; -22.261 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.224     ; 17.039     ;
; -22.261 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.224     ; 17.039     ;
; -22.261 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.224     ; 17.039     ;
; -22.232 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.218     ; 17.016     ;
; -22.204 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 16.991     ;
; -22.185 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 16.972     ;
; -22.178 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 16.954     ;
; -22.172 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.231     ; 16.943     ;
; -22.169 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.216     ; 16.955     ;
; -22.152 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 16.928     ;
; -22.152 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.231     ; 16.923     ;
; -22.152 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.929     ;
; -22.152 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.929     ;
; -22.152 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.929     ;
; -22.152 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.929     ;
; -22.134 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.218     ; 16.918     ;
; -22.132 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.909     ;
; -22.132 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.909     ;
; -22.132 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.909     ;
; -22.132 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.909     ;
; -22.095 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 16.882     ;
; -22.073 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 16.849     ;
; -22.057 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 16.833     ;
; -21.997 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.218     ; 16.781     ;
; -21.991 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 16.778     ;
; -21.964 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.231     ; 16.735     ;
; -21.944 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.721     ;
; -21.944 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.721     ;
; -21.944 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.721     ;
; -21.944 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.721     ;
; -21.919 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.216     ; 16.705     ;
; -21.909 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 16.685     ;
; -21.884 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.215     ; 16.671     ;
; -21.873 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.226     ; 16.649     ;
; -21.853 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.218     ; 16.637     ;
; -21.835 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.220     ; 16.617     ;
; -21.833 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.220     ; 16.615     ;
; -21.830 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.223     ; 16.609     ;
; -21.815 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.603     ;
; -21.815 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.603     ;
; -21.815 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.603     ;
; -21.815 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.603     ;
; -21.813 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.601     ;
; -21.813 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.601     ;
; -21.813 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.601     ;
; -21.813 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.601     ;
; -21.810 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 16.595     ;
; -21.810 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 16.595     ;
; -21.810 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 16.595     ;
; -21.810 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 16.595     ;
; -21.794 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.220     ; 16.576     ;
; -21.774 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.562     ;
; -21.774 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.562     ;
; -21.774 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.562     ;
; -21.774 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.562     ;
; -21.764 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.220     ; 16.546     ;
; -21.751 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.231     ; 16.522     ;
; -21.746 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.216     ; 16.532     ;
; -21.744 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.532     ;
; -21.744 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.532     ;
; -21.744 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.532     ;
; -21.744 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.532     ;
; -21.731 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.508     ;
; -21.731 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.508     ;
; -21.731 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.508     ;
; -21.731 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.225     ; 16.508     ;
; -21.694 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.223     ; 16.473     ;
; -21.674 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 16.459     ;
; -21.674 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 16.459     ;
; -21.674 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 16.459     ;
; -21.674 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.217     ; 16.459     ;
; -21.666 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.220     ; 16.448     ;
; -21.647 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.220     ; 16.429     ;
; -21.646 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.434     ;
; -21.646 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.434     ;
; -21.646 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -6.214     ; 16.434     ;
+---------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                            ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                                                                ; To Node                                                                                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -18.159 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                                                                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[0]  ; CLK_REF      ; CLK_BRD     ; 1.000        ; -15.550    ; 3.591      ;
; -18.055 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                                                                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[16] ; CLK_REF      ; CLK_BRD     ; 1.000        ; -15.550    ; 3.487      ;
; -16.372 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 17.017     ;
; -16.195 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.862     ;
; -16.181 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.835     ;
; -16.090 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.332     ; 16.760     ;
; -16.077 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.351     ; 16.728     ;
; -16.072 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.720     ;
; -16.070 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.351     ; 16.721     ;
; -16.020 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.361     ; 16.661     ;
; -16.014 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.369     ; 16.647     ;
; -15.986 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.653     ;
; -15.979 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.646     ;
; -15.975 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.353     ; 16.624     ;
; -15.968 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.613     ;
; -15.961 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.606     ;
; -15.929 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.583     ;
; -15.908 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.359     ; 16.551     ;
; -15.860 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.351     ; 16.511     ;
; -15.858 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.351     ; 16.509     ;
; -15.858 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.351     ; 16.509     ;
; -15.858 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.351     ; 16.509     ;
; -15.857 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.351     ; 16.508     ;
; -15.851 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.356     ; 16.497     ;
; -15.843 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.339     ; 16.506     ;
; -15.838 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.332     ; 16.508     ;
; -15.836 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.356     ; 16.482     ;
; -15.830 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.475     ;
; -15.829 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.352     ; 16.479     ;
; -15.820 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.468     ;
; -15.814 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_4                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.369     ; 16.447     ;
; -15.794 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.368     ; 16.428     ;
; -15.772 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.353     ; 16.421     ;
; -15.767 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.434     ;
; -15.767 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.434     ;
; -15.767 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.434     ;
; -15.766 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.433     ;
; -15.751 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.367     ; 16.386     ;
; -15.749 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.394     ;
; -15.749 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.394     ;
; -15.749 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.394     ;
; -15.748 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.393     ;
; -15.741 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.337     ; 16.406     ;
; -15.725 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.355     ; 16.372     ;
; -15.723 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.358     ; 16.367     ;
; -15.718 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.372     ;
; -15.718 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.355     ; 16.365     ;
; -15.717 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.371     ;
; -15.716 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.370     ;
; -15.714 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.368     ;
; -15.713 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.348     ; 16.367     ;
; -15.710 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.377     ;
; -15.709 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.376     ;
; -15.709 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_20                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.376     ;
; -15.708 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.375     ;
; -15.707 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.374     ;
; -15.706 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.335     ; 16.373     ;
; -15.703 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.344     ; 16.361     ;
; -15.700 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.350     ; 16.352     ;
; -15.687 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.334     ; 16.355     ;
; -15.685 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.350     ; 16.337     ;
; -15.672 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.355     ; 16.319     ;
; -15.672 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.334     ; 16.340     ;
; -15.662 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.373     ; 16.291     ;
; -15.660 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.361     ; 16.301     ;
; -15.629 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.343     ; 16.288     ;
; -15.627 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.332     ; 16.297     ;
; -15.626 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.332     ; 16.296     ;
; -15.625 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.332     ; 16.295     ;
; -15.623 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.268     ;
; -15.623 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.332     ; 16.293     ;
; -15.622 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.332     ; 16.292     ;
; -15.619 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.319     ; 16.302     ;
; -15.618 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.319     ; 16.301     ;
; -15.618 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_20                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.319     ; 16.301     ;
; -15.617 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.319     ; 16.300     ;
; -15.616 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.319     ; 16.299     ;
; -15.615 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.378     ; 16.239     ;
; -15.615 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.319     ; 16.298     ;
; -15.609 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.257     ;
; -15.608 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.256     ;
; -15.607 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.255     ;
; -15.605 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.253     ;
; -15.604 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.354     ; 16.252     ;
; -15.601 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.341     ; 16.262     ;
; -15.600 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.341     ; 16.261     ;
; -15.600 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_20                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.341     ; 16.261     ;
; -15.600 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.361     ; 16.241     ;
; -15.599 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.341     ; 16.260     ;
; -15.598 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.353     ; 16.247     ;
; -15.598 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.341     ; 16.259     ;
; -15.597 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.341     ; 16.258     ;
; -15.587 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.345     ; 16.244     ;
; -15.577 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.352     ; 16.227     ;
; -15.576 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.355     ; 16.223     ;
; -15.562 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_0                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.337     ; 16.227     ;
; -15.560 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.371     ; 16.191     ;
; -15.556 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.355     ; 16.203     ;
; -15.545 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.357     ; 16.190     ;
; -15.525 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.346     ; 16.181     ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                  ; To Node                                                                                                                                                                        ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -6.681 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.615      ;
; -6.659 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.589      ;
; -6.608 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.542      ;
; -6.586 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.516      ;
; -6.585 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.100     ; 7.487      ;
; -6.547 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.481      ;
; -6.537 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 7.474      ;
; -6.527 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.100     ; 7.429      ;
; -6.525 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.455      ;
; -6.515 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 7.448      ;
; -6.416 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 7.353      ;
; -6.406 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.100     ; 7.308      ;
; -6.394 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 7.327      ;
; -6.389 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 7.306      ;
; -6.371 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.305      ;
; -6.359 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 7.288      ;
; -6.349 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 7.280      ;
; -6.349 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.279      ;
; -6.315 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 7.246      ;
; -6.296 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.100     ; 7.198      ;
; -6.286 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 7.215      ;
; -6.276 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 7.207      ;
; -6.267 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 7.204      ;
; -6.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 7.178      ;
; -6.242 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 7.173      ;
; -6.225 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 7.154      ;
; -6.215 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.070     ; 7.147      ;
; -6.215 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 7.146      ;
; -6.205 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.139      ;
; -6.181 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 7.112      ;
; -6.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.064     ; 7.110      ;
; -6.171 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.105      ;
; -6.163 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.097      ;
; -6.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.526     ; 6.635      ;
; -6.150 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.084      ;
; -6.141 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.072     ; 7.071      ;
; -6.137 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.530     ; 6.609      ;
; -6.103 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 7.040      ;
; -6.094 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.070     ; 7.026      ;
; -6.084 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 7.018      ;
; -6.081 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 7.014      ;
; -6.050 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 6.984      ;
; -6.049 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 6.978      ;
; -6.039 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 6.970      ;
; -6.005 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 6.936      ;
; -5.945 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.070     ; 6.877      ;
; -5.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 6.869      ;
; -5.931 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.363      ; 7.296      ;
; -5.901 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 6.835      ;
; -5.873 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.363      ; 7.238      ;
; -5.850 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.783      ;
; -5.841 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 6.770      ;
; -5.840 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.067     ; 6.775      ;
; -5.837 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.531     ; 6.308      ;
; -5.831 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 6.762      ;
; -5.827 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.529     ; 6.300      ;
; -5.810 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 6.747      ;
; -5.806 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.723      ;
; -5.806 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.067     ; 6.741      ;
; -5.797 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 6.728      ;
; -5.793 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.529     ; 6.266      ;
; -5.788 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.721      ;
; -5.781 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.070     ; 6.713      ;
; -5.771 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 6.705      ;
; -5.752 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.363      ; 7.117      ;
; -5.748 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.665      ;
; -5.744 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.060     ; 6.686      ;
; -5.737 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.068     ; 6.671      ;
; -5.737 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.058     ; 6.681      ;
; -5.735 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.378      ; 7.115      ;
; -5.722 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.064     ; 6.660      ;
; -5.715 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.062     ; 6.655      ;
; -5.694 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg_0                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.095     ; 6.601      ;
; -5.679 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 6.610      ;
; -5.677 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ0:U_MAGNITREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.062     ; 6.617      ;
; -5.671 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 6.602      ;
; -5.656 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.063     ; 6.595      ;
; -5.655 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ0:U_MAGNITREG|sh_reg_0__Z                                                                                                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.066     ; 6.591      ;
; -5.650 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.583      ;
; -5.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.582      ;
; -5.644 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.093     ; 6.553      ;
; -5.642 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 6.571      ;
; -5.642 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.363      ; 7.007      ;
; -5.642 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.575      ;
; -5.641 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.574      ;
; -5.634 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.073     ; 6.563      ;
; -5.627 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.544      ;
; -5.627 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 6.568      ;
; -5.626 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.061     ; 6.567      ;
; -5.626 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3_2:U_TRMASKREG|sh_reg_0__Z                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 6.587      ;
; -5.619 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 6.556      ;
; -5.612 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 6.549      ;
; -5.610 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                                       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.070     ; 6.542      ;
; -5.604 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3_2:U_TRMASKREG|sh_reg_0__Z                                                                                                                 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.045     ; 6.561      ;
; -5.595 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|sh_reg_r_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.065     ; 6.532      ;
; -5.590 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_4__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.523      ;
; -5.573 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|sh_reg_r_0__Z                                                                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.069     ; 6.506      ;
; -5.535 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.071     ; 6.466      ;
; -5.517 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.085     ; 6.434      ;
; -5.506 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|DataRegister:tsk3000_DebugDataRegister|NexusReg_Shift_31__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.082     ; 6.426      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLK_REF'                                                                                                                                                                                                                                                  ;
+---------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                         ; To Node                                                                         ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -13.651 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 2.545      ;
; -13.650 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]      ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.951     ; 2.536      ;
; -13.300 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.951     ; 2.886      ;
; -13.253 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 2.943      ;
; -13.251 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 2.945      ;
; -13.219 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.951     ; 2.967      ;
; -13.107 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 3.089      ;
; -13.103 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 3.093      ;
; -13.044 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.960     ; 3.151      ;
; -13.043 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 3.153      ;
; -12.973 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 3.223      ;
; -12.649 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 3.547      ;
; -12.487 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 3.698      ;
; -12.484 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 3.712      ;
; -12.386 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.951     ; 3.800      ;
; -12.270 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 3.926      ;
; -12.248 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 3.937      ;
; -12.246 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 3.939      ;
; -12.232 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 3.964      ;
; -11.583 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 4.602      ;
; -11.392 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.953     ; 4.796      ;
; -11.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.953     ; 5.003      ;
; -10.849 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.951     ; 5.337      ;
; -10.445 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.953     ; 5.743      ;
; -8.224  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.959     ; 7.970      ;
; -7.724  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0]   ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.953     ; 8.464      ;
; -7.507  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.953     ; 8.681      ;
; -7.353  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 8.832      ;
; -7.351  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.953     ; 8.837      ;
; -7.229  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 8.956      ;
; -7.219  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 8.966      ;
; -7.214  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 8.982      ;
; -7.210  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 8.975      ;
; -7.175  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.959     ; 9.019      ;
; -7.175  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.959     ; 9.019      ;
; -7.175  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.959     ; 9.019      ;
; -7.175  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.959     ; 9.019      ;
; -7.175  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.021      ;
; -7.132  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.064      ;
; -7.124  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.953     ; 9.064      ;
; -7.093  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 9.092      ;
; -7.084  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.112      ;
; -7.084  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.112      ;
; -7.045  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.151      ;
; -7.031  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.165      ;
; -7.018  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.178      ;
; -7.014  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.182      ;
; -6.997  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 9.188      ;
; -6.986  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.210      ;
; -6.980  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.216      ;
; -6.954  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.259      ;
; -6.893  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.303      ;
; -6.888  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.308      ;
; -6.852  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.344      ;
; -6.842  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.961     ; 9.354      ;
; -6.779  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.933     ; 9.389      ;
; -6.724  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.950     ; 9.461      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -6.482  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 15.978     ; 9.731      ;
; -2.821  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 14.795     ;
; -2.525  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.091     ;
; -2.266  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.350     ;
; -2.013  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.603     ;
; -1.972  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.644     ;
; -1.917  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.699     ;
; -1.879  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.737     ;
; -1.865  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.751     ;
; -1.858  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.399     ; 15.776     ;
; -1.855  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.761     ;
; -1.725  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.399     ; 15.909     ;
; -1.658  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 15.958     ;
; -1.645  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.399     ; 15.989     ;
; -1.508  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.108     ;
; -1.470  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.146     ;
; -1.467  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.149     ;
; -1.452  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.399     ; 16.182     ;
; -1.448  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.168     ;
; -1.399  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.217     ;
; -1.391  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.225     ;
; -1.381  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.399     ; 16.253     ;
; -1.370  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.399     ; 16.264     ;
; -1.334  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.282     ;
; -1.297  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.319     ;
; -1.284  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.399     ; 16.350     ;
; -1.209  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 17.381     ; 16.407     ;
; -1.172  ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 14.539     ; 13.602     ;
; -1.169  ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 14.538     ; 13.604     ;
+---------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                         ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.315 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[7]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.737      ;
; 0.315 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[3]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[3]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.737      ;
; 0.315 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[2]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[2]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.737      ;
; 0.315 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[0]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg_0                                                                                                                                                                                   ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.737      ;
; 0.316 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[4]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[4]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.738      ;
; 0.316 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[1]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[1]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.738      ;
; 0.317 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[6]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[6]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.739      ;
; 0.317 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[5]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[5]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.739      ;
; 0.337 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[3]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.185      ; 0.757      ;
; 0.338 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[1]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.185      ; 0.758      ;
; 0.339 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                                                                                               ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.185      ; 0.759      ;
; 0.342 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z                                                                                                                                                                                                                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                                                                          ; CLK_REF        ; JTAG_NEXUS_TCK ; 0.000        ; 0.182      ; 0.759      ;
; 0.346 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[5]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.184      ; 0.765      ;
; 0.349 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.184      ; 0.768      ;
; 0.400 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.669      ;
; 0.410 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13                                                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.539      ; 1.144      ;
; 0.415 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_0__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.415 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_1__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.415 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_0|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.415 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_0__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.415 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_1__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.684      ;
; 0.443 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg[14]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.539      ; 1.177      ;
; 0.444 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.866      ;
; 0.450 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0                                                                                                                                                                                                                                  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0                                                                                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.539      ; 1.184      ;
; 0.455 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.877      ;
; 0.456 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.878      ;
; 0.457 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.880      ;
; 0.458 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_2__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_1__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.091      ; 0.744      ;
; 0.458 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.881      ;
; 0.459 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_3__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_2__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.091      ; 0.745      ;
; 0.459 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.882      ;
; 0.460 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.188      ; 0.883      ;
; 0.460 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.882      ;
; 0.463 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.187      ; 0.885      ;
; 0.465 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[3]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.735      ;
; 0.466 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_17|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.735      ;
; 0.466 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[21]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[21]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[15]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[15]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[12]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[12]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[6]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[6]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_13|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.735      ;
; 0.466 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[4]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[4]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.466 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[2]                                                                                                                                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_2|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_30|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_29|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_20|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[29]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[29]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[26]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[26]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[24]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[24]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[22]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[22]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[18]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[18]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[11]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[11]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[4]                                                                                                                                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_26__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_25__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_21__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_20__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.736      ;
; 0.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[6]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[6]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[5]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[5]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[2]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[6]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[6]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[4]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[4]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[2]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_14__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_13__Z                                                                                                                                                                        ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_12__Z                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_6__Z                                                                                                                                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|LAX_CFG32_DRNOOUT:id_reg_unit|sh_reg_5__Z                                                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[18]                                                                                                                                                                                                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[17]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.467 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[18]                                                                                                                                                                                                                     ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[17]                                                                                                                                                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.737      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.075      ; 0.738      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_24|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_23|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_19|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_18|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
; 0.468 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.074      ; 0.737      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                         ; To Node                                                                                                                                                                                                        ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 0.399 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                      ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                    ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                   ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                               ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                  ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.399 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                        ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                       ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                                                                    ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                      ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                               ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                               ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                               ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                      ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.400 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                              ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.669      ;
; 0.401 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                     ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                     ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                    ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                  ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                      ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                     ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.073      ; 0.669      ;
; 0.415 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.684      ;
; 0.426 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                    ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a3~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.424      ; 1.080      ;
; 0.448 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_5                                                                     ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.423      ; 1.101      ;
; 0.452 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|clkval[9]                                                                                                   ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|clkval[9]                                                                                                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.721      ;
; 0.453 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                          ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.722      ;
; 0.464 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_11                                                                    ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.424      ; 1.118      ;
; 0.476 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff1_Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.745      ;
; 0.476 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff1_Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.745      ;
; 0.478 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_1                                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_1                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.747      ;
; 0.487 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_10                                                                    ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.424      ; 1.141      ;
; 0.489 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|RegA_Abs_26__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|RegA_Abs_30__Z                                                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.758      ;
; 0.489 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_21__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.758      ;
; 0.489 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_3                                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_3                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.759      ;
; 0.490 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                          ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.353      ; 1.073      ;
; 0.490 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_20__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.759      ;
; 0.490 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.759      ;
; 0.490 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_14__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_13__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.759      ;
; 0.490 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_9__Z                                                                             ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.759      ;
; 0.491 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.760      ;
; 0.493 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_2                                                          ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.353      ; 1.076      ;
; 0.493 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOnlineFF0                                                                                               ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOnlineFF1                                                                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.762      ;
; 0.498 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_1                                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_0                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.767      ;
; 0.504 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_6__Z                                                                                      ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.773      ;
; 0.510 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_30__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_29__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.779      ;
; 0.511 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_17__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_16__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.780      ;
; 0.512 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff1_Z                                                            ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; 0.011      ; 0.758      ;
; 0.512 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_1                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|RxSetFF0                                                                                                                                               ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; 0.012      ; 0.759      ;
; 0.512 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_i_8__Z                                                                                    ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_7__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.782      ;
; 0.512 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_27__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.781      ;
; 0.512 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_26__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.781      ;
; 0.512 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_17__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.781      ;
; 0.512 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_3__Z                                                                             ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_2__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.781      ;
; 0.513 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_0                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF0                                                                                                                                       ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; 0.012      ; 0.760      ;
; 0.513 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_1__Z                                                                             ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_0__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.782      ;
; 0.513 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                             ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_6__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.782      ;
; 0.513 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_6__Z                                                                             ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_5__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.782      ;
; 0.514 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_2__Z                                                                                      ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_1__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.783      ;
; 0.514 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_13__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_12__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.783      ;
; 0.531 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_6                                                          ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.353      ; 1.114      ;
; 0.531 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_14                                                         ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.353      ; 1.114      ;
; 0.582 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.851      ;
; 0.621 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff1_Z               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_Z                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.890      ;
; 0.623 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|DIN_REG1_13                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rs_Data_13                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.893      ;
; 0.626 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_0                                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_1                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.895      ;
; 0.627 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                             ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.896      ;
; 0.628 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_0                                                           ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_0                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.897      ;
; 0.639 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_11__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_10__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.908      ;
; 0.643 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_12__Z                                                                            ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_11__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.912      ;
; 0.643 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugReset_ff_Z               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugReset_Z                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.912      ;
; 0.646 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugEnable_ff_Z              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugEnable_Z                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.074      ; 0.915      ;
; 0.648 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|DIN_REG1_28                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rs_Data_28                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.918      ;
; 0.649 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|DIN_REG1_27                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rs_Data_27                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.075      ; 0.919      ;
; 0.652 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                                                                     ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.422      ; 1.304      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                        ; To Node                                                                                                                                                                 ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -3.327 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 4.306      ;
; -3.104 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 4.082      ;
; -3.104 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 4.082      ;
; -3.061 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 4.040      ;
; -2.997 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.976      ;
; -2.991 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.970      ;
; -2.877 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.856      ;
; -2.866 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.865 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.844      ;
; -2.817 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 3.336      ;
; -2.817 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.795      ;
; -2.817 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.795      ;
; -2.810 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.788      ;
; -2.810 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.788      ;
; -2.798 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.776      ;
; -2.798 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.776      ;
; -2.759 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.738      ;
; -2.711 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.690      ;
; -2.608 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.586      ;
; -2.608 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.586      ;
; -2.579 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.578 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.557      ;
; -2.572 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.550      ;
; -2.560 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.559 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.538      ;
; -2.548 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.464     ; 3.066      ;
; -2.548 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.464     ; 3.066      ;
; -2.533 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.511      ;
; -2.533 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.511      ;
; -2.452 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.430      ;
; -2.452 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.430      ;
; -2.360 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.359 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.338      ;
; -2.317 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.074     ; 3.245      ;
; -2.306 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.464     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.305 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.463     ; 2.824      ;
; -2.295 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.004     ; 3.273      ;
; -2.294 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.273      ;
; -2.294 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.003     ; 3.273      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'CLK_REF'                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.295 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.093      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 3.043      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.158 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.956      ;
; -2.128 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.919      ;
; -2.078 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.869      ;
; -2.048 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.193     ; 2.837      ;
; -1.998 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.193     ; 2.787      ;
; -1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.782      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.980 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.778      ;
; -1.963 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.756      ;
; -1.963 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.756      ;
; -1.963 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.756      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.957 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.755      ;
; -1.913 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.706      ;
; -1.913 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.706      ;
; -1.913 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.706      ;
; -1.911 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.193     ; 2.700      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.907 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.705      ;
; -1.826 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.619      ;
; -1.826 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.619      ;
; -1.826 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.189     ; 2.619      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.820 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.184     ; 2.618      ;
; -1.813 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.191     ; 2.604      ;
; -1.733 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.193     ; 2.522      ;
; -1.665 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.250      ; 2.897      ;
; -1.665 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.250      ; 2.897      ;
; -1.665 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.250      ; 2.897      ;
; -1.665 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.250      ; 2.897      ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                                                     ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 1.069 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 1.335      ;
; 1.069 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 1.335      ;
; 1.069 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 1.335      ;
; 1.069 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 1.335      ;
; 1.252 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_10|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 1.548      ;
; 1.252 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_9|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 1.548      ;
; 1.252 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_2|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 1.548      ;
; 1.252 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_1|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.101      ; 1.548      ;
; 1.256 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 1.522      ;
; 1.256 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 1.522      ;
; 1.256 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 1.522      ;
; 1.256 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 1.522      ;
; 1.520 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_12|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 1.792      ;
; 1.520 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 1.792      ;
; 1.520 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_3|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 1.792      ;
; 1.520 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_4|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 1.792      ;
; 1.553 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_6|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 1.821      ;
; 1.553 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_14|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 1.821      ;
; 1.553 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_13|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 1.821      ;
; 1.553 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_5|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 1.821      ;
; 1.557 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.335      ;
; 1.557 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.335      ;
; 1.557 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.335      ;
; 1.557 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                                          ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.335      ;
; 1.557 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.335      ;
; 1.557 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.335      ;
; 1.557 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0]                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.335      ;
; 1.557 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.063      ; 1.335      ;
; 1.701 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.059      ; 1.475      ;
; 1.701 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.059      ; 1.475      ;
; 1.701 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.059      ; 1.475      ;
; 1.701 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; -0.500       ; 0.059      ; 1.475      ;
; 1.717 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_7|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.068      ; 1.980      ;
; 1.717 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_15|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.068      ; 1.980      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.991 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.257      ;
; 1.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.064      ; 2.252      ;
; 1.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.064      ; 2.252      ;
; 2.003 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.064      ; 2.262      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.016 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.284      ;
; 2.048 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_8|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 2.320      ;
; 2.048 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 2.320      ;
; 2.048 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 2.320      ;
; 2.048 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_17|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 2.320      ;
; 2.048 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0]                                                               ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_0|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.077      ; 2.320      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.080 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.071      ; 2.346      ;
; 2.082 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.064      ; 2.341      ;
; 2.082 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.064      ; 2.341      ;
; 2.092 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                     ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.064      ; 2.351      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.094 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.073      ; 2.362      ;
; 2.142 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.533      ; 2.870      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'CLK_REF'                                                                                                                                                                                                                             ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 1.510 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.210      ;
; 1.510 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.210      ;
; 1.510 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.210      ;
; 1.510 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.210      ;
; 1.510 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.210      ;
; 1.510 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.210      ;
; 1.597 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.298      ;
; 1.597 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.298      ;
; 1.597 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.298      ;
; 1.597 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.298      ;
; 1.597 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.298      ;
; 1.599 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.299      ;
; 1.599 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.299      ;
; 1.599 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.299      ;
; 1.599 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.299      ;
; 1.599 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.299      ;
; 1.599 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.299      ;
; 1.686 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.387      ;
; 1.686 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.387      ;
; 1.686 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.387      ;
; 1.686 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.387      ;
; 1.686 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.387      ;
; 1.759 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.459      ;
; 1.759 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.459      ;
; 1.759 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.459      ;
; 1.759 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.459      ;
; 1.759 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.459      ;
; 1.759 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.459      ;
; 1.795 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.495      ;
; 1.795 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.495      ;
; 1.795 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.495      ;
; 1.795 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.495      ;
; 1.795 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.495      ;
; 1.795 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.465      ; 2.495      ;
; 1.846 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.547      ;
; 1.846 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.547      ;
; 1.846 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.547      ;
; 1.846 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.547      ;
; 1.846 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.547      ;
; 1.882 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.583      ;
; 1.882 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.583      ;
; 1.882 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.583      ;
; 1.882 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.583      ;
; 1.882 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.466      ; 2.583      ;
; 1.901 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.145      ;
; 1.901 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.145      ;
; 1.901 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.145      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.918 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.166      ;
; 1.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.234      ;
; 1.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.234      ;
; 1.990 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.234      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.007 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.255      ;
; 2.022 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.005      ; 2.262      ;
; 2.096 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.338      ;
; 2.111 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.005      ; 2.351      ;
; 2.150 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.394      ;
; 2.150 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.394      ;
; 2.150 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.394      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.159 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.014      ; 2.408      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.167 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.013      ; 2.415      ;
; 2.185 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.007      ; 2.427      ;
; 2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.430      ;
; 2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.430      ;
; 2.186 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.009      ; 2.430      ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_REF'                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ;
; -7.940 ; -7.724       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ;
; -7.939 ; -7.723       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ;
; -7.897 ; -7.681       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ;
; -7.878 ; -7.662       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_16_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_17_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_18_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_19_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_20_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_21_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_22_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_23_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_24_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_25_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_26_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_27_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_28_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_29_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_30_|clk                                                                               ;
; -7.670 ; -7.670       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_31_|clk                                                                               ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_0_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_10_|clk                                                                               ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_11_|clk                                                                               ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_12_|clk                                                                               ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_13_|clk                                                                               ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_14_|clk                                                                               ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_15_|clk                                                                               ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_1_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_2_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_3_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_4_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_5_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_6_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_7_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_8_|clk                                                                                ;
; -7.669 ; -7.669       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_9_|clk                                                                                ;
; -7.664 ; -7.664       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|inclk[0]                                                                      ;
; -7.664 ; -7.664       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|outclk                                                                        ;
; -7.630 ; -7.630       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_2_0_component_c11|clko_s_Z|clk                                                                                 ;
; -7.608 ; -7.608       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|outstate_Z|clk                                                                              ;
; -7.499 ; -7.499       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -7.477 ; -7.477       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|combout                                                                            ;
; -7.470 ; -7.470       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|datab                                                                         ;
; -6.914 ; -6.698       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ;
; -6.914 ; -6.698       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ;
; -6.914 ; -6.698       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ;
; -6.682 ; -6.682       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout                                                                              ;
; -6.673 ; -6.673       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|datab                                                                              ;
; -6.644 ; -6.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_A_Z|clk                                                                               ;
; -6.644 ; -6.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_B_Z|clk                                                                               ;
; -6.644 ; -6.644       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_C_Z|clk                                                                               ;
; -6.636 ; -6.636       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|datad                                                                                ;
; -6.518 ; -6.518       ; 0.000          ; High Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|combout                                                                         ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]                                                       ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]                                                           ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]                                                           ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]                                                          ;
; -6.452 ; -6.236       ; 0.216          ; High Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]                                                           ;
+--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock   ; Clock Edge ; Target                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT0  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT1  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT2  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_cnb1:left_mult|mac_mult2~OBSERVABLEDATAB_REGOUT3  ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT0 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT1 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT2 ;
; -4.000 ; 1.000        ; 5.000          ; Min Period ; CLK_BRD ; Rise       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|altmult_add:RegA_Abs_0_muladd_0_31_28__Z|mult_add_rhr3:auto_generated|ded_mult_a851:ded_mult1|ded_mult_gnb1:right_mult|mac_mult4~OBSERVABLEDATAB_REGOUT3 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a2~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a3~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a4~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a5~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a6~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a0~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~porta_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_datain_reg0              ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg                   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a2~porta_address_reg0             ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a2~porta_datain_reg0              ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[10]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[11]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[12]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[1]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[2]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[3]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[4]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[5]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[6]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[7]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[8]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[9]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0 ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_1    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_10   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_11   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_12   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_15   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_5    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_6    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_7    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_8    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_9    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[10]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[11]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[12]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[13]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[14]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[15]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[16]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[17]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[18]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[19]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[1]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[20]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[21]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[22]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[23]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[24]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[25]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[26]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[27]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[28]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[29]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[2]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[30]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[3]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[4]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[5]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[6]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[7]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[8]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[9]   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_20   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_28   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31   ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_4    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_6    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_7    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[1]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]  ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------+
; Setup Times                                                                      ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; 4.857  ; 4.513  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 3.473  ; 3.428  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 4.445  ; 4.256  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 3.470  ; 3.458  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 3.759  ; 3.676  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.278  ; 4.117  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 4.857  ; 4.513  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 4.605  ; 4.354  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 3.413  ; 3.370  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 3.647  ; 3.565  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 4.489  ; 4.474  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.327  ; 4.274  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 4.256  ; 4.100  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 3.670  ; 3.637  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 4.012  ; 3.845  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 4.071  ; 3.952  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 3.795  ; 3.730  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 4.769  ; 4.424  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.160  ; 3.017  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 4.059  ; 3.992  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 3.378  ; 3.383  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 3.808  ; 3.735  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 4.556  ; 4.352  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.639  ; 4.371  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 4.438  ; 4.206  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 3.457  ; 3.391  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 3.640  ; 3.516  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 4.041  ; 3.852  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 3.865  ; 3.774  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 3.909  ; 3.886  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 4.769  ; 4.424  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 3.929  ; 3.840  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.314  ; 4.167  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 3.567  ; 3.539  ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; 4.632  ; 4.776  ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; 17.683 ; 15.898 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.247  ; 0.652  ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; 3.630  ; 3.619  ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; 4.359  ; 4.362  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Hold Times                                                                       ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; -1.746 ; -1.893 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; -1.786 ; -1.905 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; -2.467 ; -2.510 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; -1.844 ; -1.971 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; -2.170 ; -2.238 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; -2.303 ; -2.333 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; -2.291 ; -2.263 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; -2.286 ; -2.328 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; -1.842 ; -1.926 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; -2.037 ; -2.068 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; -2.628 ; -2.695 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; -2.644 ; -2.744 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; -2.261 ; -2.314 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; -1.746 ; -1.893 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; -1.802 ; -1.908 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; -2.132 ; -2.191 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; -1.933 ; -2.055 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; -1.627 ; -1.706 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; -1.627 ; -1.706 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; -1.979 ; -2.057 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; -1.775 ; -1.910 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; -1.885 ; -2.007 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; -2.269 ; -2.336 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; -2.247 ; -2.263 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; -2.171 ; -2.219 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; -1.889 ; -1.951 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; -2.352 ; -2.371 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; -2.124 ; -2.121 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; -2.218 ; -2.261 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; -2.033 ; -2.113 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; -1.838 ; -1.868 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; -2.003 ; -2.081 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; -2.371 ; -2.421 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; -1.886 ; -1.984 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; -1.963 ; -2.094 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; -6.505 ; -6.265 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.202  ; -0.161 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; -1.777 ; -1.941 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; -2.006 ; -2.081 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Clock to Output Times                                                            ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_A[*]     ; CLK_BRD        ; 19.835 ; 19.547 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[0]    ; CLK_BRD        ; 15.347 ; 14.909 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[1]    ; CLK_BRD        ; 17.410 ; 17.065 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[2]    ; CLK_BRD        ; 15.379 ; 15.123 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[3]    ; CLK_BRD        ; 16.337 ; 16.117 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[4]    ; CLK_BRD        ; 17.722 ; 17.282 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[5]    ; CLK_BRD        ; 18.278 ; 17.785 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[6]    ; CLK_BRD        ; 17.875 ; 17.478 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[7]    ; CLK_BRD        ; 19.835 ; 19.547 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[8]    ; CLK_BRD        ; 17.520 ; 17.127 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[9]    ; CLK_BRD        ; 19.093 ; 18.656 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[10]   ; CLK_BRD        ; 18.306 ; 17.808 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[11]   ; CLK_BRD        ; 17.303 ; 17.008 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[12]   ; CLK_BRD        ; 17.492 ; 17.133 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[13]   ; CLK_BRD        ; 18.616 ; 18.121 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[14]   ; CLK_BRD        ; 18.782 ; 18.361 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[15]   ; CLK_BRD        ; 16.757 ; 16.297 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[16]   ; CLK_BRD        ; 16.084 ; 15.736 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[17]   ; CLK_BRD        ; 16.820 ; 16.364 ; Rise       ; CLK_BRD         ;
; SRAM0_D[*]     ; CLK_BRD        ; 9.492  ; 8.847  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 7.439  ; 7.129  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 9.492  ; 8.847  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 7.962  ; 7.694  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 6.799  ; 6.601  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 8.659  ; 8.194  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 9.204  ; 8.645  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 7.650  ; 7.397  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 7.364  ; 7.203  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 8.212  ; 7.791  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 7.890  ; 7.565  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 8.330  ; 7.980  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 7.959  ; 7.659  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 8.005  ; 7.731  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 7.378  ; 7.029  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 8.036  ; 7.631  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 7.781  ; 7.436  ; Rise       ; CLK_BRD         ;
; SRAM0_E        ; CLK_BRD        ; 21.190 ; 20.730 ; Rise       ; CLK_BRD         ;
; SRAM0_LB       ; CLK_BRD        ; 20.357 ; 20.164 ; Rise       ; CLK_BRD         ;
; SRAM0_OE       ; CLK_BRD        ; 18.392 ; 18.530 ; Rise       ; CLK_BRD         ;
; SRAM0_UB       ; CLK_BRD        ; 20.040 ; 20.003 ; Rise       ; CLK_BRD         ;
; SRAM0_W        ; CLK_BRD        ; 7.467  ; 7.691  ; Rise       ; CLK_BRD         ;
; SRAM1_A[*]     ; CLK_BRD        ; 19.224 ; 18.930 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[0]    ; CLK_BRD        ; 15.412 ; 14.952 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[1]    ; CLK_BRD        ; 18.222 ; 18.085 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[2]    ; CLK_BRD        ; 16.055 ; 15.627 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[3]    ; CLK_BRD        ; 16.303 ; 16.085 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[4]    ; CLK_BRD        ; 17.366 ; 17.000 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[5]    ; CLK_BRD        ; 17.491 ; 17.100 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[6]    ; CLK_BRD        ; 18.639 ; 18.439 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[7]    ; CLK_BRD        ; 17.906 ; 17.538 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[8]    ; CLK_BRD        ; 17.149 ; 16.820 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[9]    ; CLK_BRD        ; 17.929 ; 17.627 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[10]   ; CLK_BRD        ; 17.955 ; 17.496 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[11]   ; CLK_BRD        ; 17.352 ; 17.087 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[12]   ; CLK_BRD        ; 17.577 ; 17.235 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[13]   ; CLK_BRD        ; 19.224 ; 18.930 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[14]   ; CLK_BRD        ; 18.686 ; 17.920 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[15]   ; CLK_BRD        ; 17.503 ; 16.921 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[16]   ; CLK_BRD        ; 15.741 ; 15.445 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[17]   ; CLK_BRD        ; 16.782 ; 16.326 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 8.881  ; 8.278  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 7.793  ; 7.509  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 7.994  ; 7.532  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 8.101  ; 7.647  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 8.505  ; 8.035  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 8.881  ; 8.201  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 8.474  ; 8.149  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 8.019  ; 7.724  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 8.602  ; 8.278  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 8.222  ; 7.826  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 8.403  ; 7.899  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 8.474  ; 8.212  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 8.001  ; 7.682  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 7.423  ; 7.095  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 7.558  ; 7.287  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 8.740  ; 8.257  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 7.403  ; 7.114  ; Rise       ; CLK_BRD         ;
; SRAM1_E        ; CLK_BRD        ; 20.511 ; 20.372 ; Rise       ; CLK_BRD         ;
; SRAM1_LB       ; CLK_BRD        ; 21.123 ; 20.901 ; Rise       ; CLK_BRD         ;
; SRAM1_OE       ; CLK_BRD        ; 19.676 ; 19.564 ; Rise       ; CLK_BRD         ;
; SRAM1_UB       ; CLK_BRD        ; 20.684 ; 20.481 ; Rise       ; CLK_BRD         ;
; SRAM1_W        ; CLK_BRD        ; 9.580  ; 9.774  ; Rise       ; CLK_BRD         ;
; DAC_CLK        ; CLK_REF        ; 24.579 ; 24.229 ; Rise       ; CLK_REF         ;
; DAC_CS         ; CLK_REF        ; 25.980 ; 25.289 ; Rise       ; CLK_REF         ;
; DAC_DOUT       ; CLK_REF        ; 27.288 ; 26.225 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ; 11.643 ; 11.054 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                    ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_A[*]     ; CLK_BRD        ; 8.071  ; 7.687  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[0]    ; CLK_BRD        ; 9.028  ; 8.456  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[1]    ; CLK_BRD        ; 10.951 ; 10.110 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[2]    ; CLK_BRD        ; 8.071  ; 7.687  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[3]    ; CLK_BRD        ; 9.577  ; 9.075  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[4]    ; CLK_BRD        ; 10.438 ; 9.697  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[5]    ; CLK_BRD        ; 11.753 ; 10.772 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[6]    ; CLK_BRD        ; 11.734 ; 10.861 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[7]    ; CLK_BRD        ; 13.953 ; 13.336 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[8]    ; CLK_BRD        ; 10.210 ; 9.514  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[9]    ; CLK_BRD        ; 12.775 ; 11.813 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[10]   ; CLK_BRD        ; 9.826  ; 9.218  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[11]   ; CLK_BRD        ; 10.099 ; 9.547  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[12]   ; CLK_BRD        ; 10.360 ; 9.764  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[13]   ; CLK_BRD        ; 10.149 ; 9.512  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[14]   ; CLK_BRD        ; 11.880 ; 11.228 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[15]   ; CLK_BRD        ; 9.600  ; 8.929  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[16]   ; CLK_BRD        ; 8.586  ; 8.093  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[17]   ; CLK_BRD        ; 9.606  ; 8.925  ; Rise       ; CLK_BRD         ;
; SRAM0_D[*]     ; CLK_BRD        ; 6.651  ; 6.459  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 7.267  ; 6.967  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 9.237  ; 8.616  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 7.770  ; 7.509  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 6.651  ; 6.459  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 8.446  ; 7.998  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 8.968  ; 8.430  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 7.478  ; 7.234  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 7.202  ; 7.046  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 8.016  ; 7.611  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 7.709  ; 7.395  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 8.131  ; 7.793  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 7.775  ; 7.485  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 7.810  ; 7.544  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 7.210  ; 6.872  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 7.842  ; 7.450  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 7.596  ; 7.262  ; Rise       ; CLK_BRD         ;
; SRAM0_E        ; CLK_BRD        ; 9.967  ; 9.147  ; Rise       ; CLK_BRD         ;
; SRAM0_LB       ; CLK_BRD        ; 9.167  ; 8.602  ; Rise       ; CLK_BRD         ;
; SRAM0_OE       ; CLK_BRD        ; 7.280  ; 7.035  ; Rise       ; CLK_BRD         ;
; SRAM0_UB       ; CLK_BRD        ; 8.580  ; 8.254  ; Rise       ; CLK_BRD         ;
; SRAM0_W        ; CLK_BRD        ; 7.299  ; 7.516  ; Rise       ; CLK_BRD         ;
; SRAM1_A[*]     ; CLK_BRD        ; 8.257  ; 7.814  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[0]    ; CLK_BRD        ; 9.092  ; 8.498  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[1]    ; CLK_BRD        ; 11.788 ; 11.152 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[2]    ; CLK_BRD        ; 8.721  ; 8.172  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[3]    ; CLK_BRD        ; 9.544  ; 9.044  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[4]    ; CLK_BRD        ; 10.093 ; 9.425  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[5]    ; CLK_BRD        ; 10.997 ; 10.114 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[6]    ; CLK_BRD        ; 12.522 ; 11.842 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[7]    ; CLK_BRD        ; 12.046 ; 11.348 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[8]    ; CLK_BRD        ; 9.855  ; 9.220  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[9]    ; CLK_BRD        ; 11.659 ; 10.828 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[10]   ; CLK_BRD        ; 9.489  ; 8.918  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[11]   ; CLK_BRD        ; 10.146 ; 9.622  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[12]   ; CLK_BRD        ; 10.442 ; 9.862  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[13]   ; CLK_BRD        ; 10.786 ; 10.347 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[14]   ; CLK_BRD        ; 11.734 ; 10.745 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[15]   ; CLK_BRD        ; 10.315 ; 9.526  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[16]   ; CLK_BRD        ; 8.257  ; 7.814  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[17]   ; CLK_BRD        ; 9.570  ; 8.890  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 7.233  ; 6.934  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 7.605  ; 7.330  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 7.799  ; 7.352  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 7.903  ; 7.464  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 8.289  ; 7.835  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 8.650  ; 7.994  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 8.268  ; 7.955  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 7.831  ; 7.547  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 8.392  ; 8.080  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 8.027  ; 7.646  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 8.197  ; 7.711  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 8.269  ; 8.016  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 7.815  ; 7.508  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 7.252  ; 6.934  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 7.383  ; 7.120  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 8.517  ; 8.051  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 7.233  ; 6.952  ; Rise       ; CLK_BRD         ;
; SRAM1_E        ; CLK_BRD        ; 9.316  ; 8.802  ; Rise       ; CLK_BRD         ;
; SRAM1_LB       ; CLK_BRD        ; 9.621  ; 9.221  ; Rise       ; CLK_BRD         ;
; SRAM1_OE       ; CLK_BRD        ; 8.514  ; 8.028  ; Rise       ; CLK_BRD         ;
; SRAM1_UB       ; CLK_BRD        ; 9.204  ; 8.721  ; Rise       ; CLK_BRD         ;
; SRAM1_W        ; CLK_BRD        ; 9.386  ; 9.569  ; Rise       ; CLK_BRD         ;
; DAC_CLK        ; CLK_REF        ; 18.069 ; 17.731 ; Rise       ; CLK_REF         ;
; DAC_CS         ; CLK_REF        ; 19.423 ; 18.759 ; Rise       ; CLK_REF         ;
; DAC_DOUT       ; CLK_REF        ; 20.679 ; 19.657 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ; 8.951  ; 8.593  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------+
; Output Enable Times                                                        ;
+--------------+------------+--------+--------+------------+-----------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+--------------+------------+--------+--------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 18.795 ; 18.795 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 19.385 ; 19.385 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 20.417 ; 20.417 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 20.126 ; 20.126 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 19.065 ; 19.065 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 19.491 ; 19.491 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 20.155 ; 20.155 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 20.501 ; 20.501 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 20.456 ; 20.456 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 20.529 ; 20.529 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 20.162 ; 20.162 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 19.491 ; 19.491 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 20.197 ; 20.197 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 20.047 ; 20.047 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 18.795 ; 18.795 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 19.702 ; 19.702 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 19.682 ; 19.682 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 18.745 ; 18.745 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 18.745 ; 18.745 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 20.397 ; 20.397 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 20.095 ; 20.095 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 20.045 ; 20.045 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 20.397 ; 20.397 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 20.125 ; 20.125 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 20.185 ; 20.185 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 20.062 ; 20.062 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 20.152 ; 20.152 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 20.185 ; 20.185 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 20.187 ; 20.187 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 20.902 ; 20.902 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 18.785 ; 18.785 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 20.078 ; 20.078 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 20.088 ; 20.088 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 19.655 ; 19.655 ; Rise       ; CLK_BRD         ;
+--------------+------------+--------+--------+------------+-----------------+


+--------------------------------------------------------------------------+
; Minimum Output Enable Times                                              ;
+--------------+------------+-------+-------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+-------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 7.438 ; 7.431 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 8.003 ; 7.996 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 8.993 ; 8.986 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 8.715 ; 8.708 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 7.695 ; 7.688 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 8.114 ; 8.110 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 8.750 ; 8.746 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 9.084 ; 9.080 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 9.039 ; 9.035 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 9.109 ; 9.105 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 8.759 ; 8.755 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 8.114 ; 8.110 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 8.792 ; 8.788 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 8.637 ; 8.630 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 7.438 ; 7.431 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 8.308 ; 8.301 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 8.288 ; 8.281 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 7.387 ; 7.380 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 7.387 ; 7.380 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 8.973 ; 8.966 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 8.685 ; 8.678 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 8.635 ; 8.628 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 8.973 ; 8.966 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 8.722 ; 8.718 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 8.780 ; 8.776 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 8.663 ; 8.659 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 8.749 ; 8.745 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 8.780 ; 8.776 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 8.782 ; 8.778 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 9.469 ; 9.465 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 7.428 ; 7.421 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 8.669 ; 8.662 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 8.679 ; 8.672 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 8.262 ; 8.255 ; Rise       ; CLK_BRD         ;
+--------------+------------+-------+-------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Output Disable Times                                                             ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 18.738    ; 18.871    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 19.212    ; 19.345    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 20.084    ; 20.217    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 19.827    ; 19.960    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 18.931    ; 19.064    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 19.376    ; 19.497    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 19.898    ; 20.019    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 20.242    ; 20.363    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 20.192    ; 20.313    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 20.243    ; 20.364    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 19.932    ; 20.053    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 19.376    ; 19.497    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 19.940    ; 20.061    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 19.716    ; 19.849    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 18.738    ; 18.871    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 19.478    ; 19.611    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 19.458    ; 19.591    ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 18.689    ; 18.822    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 18.689    ; 18.822    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 20.064    ; 20.197    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 19.816    ; 19.949    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 19.766    ; 19.899    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 20.064    ; 20.197    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 19.863    ; 19.984    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 19.928    ; 20.049    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 19.733    ; 19.854    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 19.922    ; 20.043    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 19.928    ; 20.049    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 19.930    ; 20.051    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 20.561    ; 20.682    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 18.728    ; 18.861    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 19.781    ; 19.914    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 19.791    ; 19.924    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 19.433    ; 19.566    ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                     ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 7.128     ; 7.128     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 7.583     ; 7.583     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 8.419     ; 8.419     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 8.174     ; 8.174     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 7.313     ; 7.313     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 7.741     ; 7.741     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 8.241     ; 8.241     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 8.572     ; 8.572     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 8.523     ; 8.523     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 8.572     ; 8.572     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 8.274     ; 8.274     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 7.741     ; 7.741     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 8.283     ; 8.283     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 8.066     ; 8.066     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 7.128     ; 7.128     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 7.839     ; 7.839     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 7.819     ; 7.819     ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 7.079     ; 7.079     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 7.079     ; 7.079     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 8.399     ; 8.399     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 8.164     ; 8.164     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 8.114     ; 8.114     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 8.399     ; 8.399     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 8.207     ; 8.207     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 8.271     ; 8.271     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 8.084     ; 8.084     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 8.264     ; 8.264     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 8.271     ; 8.271     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 8.273     ; 8.273     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 8.879     ; 8.879     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 7.118     ; 7.118     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 8.130     ; 8.130     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 8.140     ; 8.140     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 7.794     ; 7.794     ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------+
; Fast 1200mV 0C Model Setup Summary      ;
+----------------+--------+---------------+
; Clock          ; Slack  ; End Point TNS ;
+----------------+--------+---------------+
; CLK_REF        ; -9.796 ; -1190.685     ;
; CLK_BRD        ; -7.114 ; -7371.741     ;
; JTAG_NEXUS_TCK ; -2.488 ; -1711.602     ;
+----------------+--------+---------------+


+-----------------------------------------+
; Fast 1200mV 0C Model Hold Summary       ;
+----------------+--------+---------------+
; Clock          ; Slack  ; End Point TNS ;
+----------------+--------+---------------+
; CLK_REF        ; -5.532 ; -191.720      ;
; JTAG_NEXUS_TCK ; 0.079  ; 0.000         ;
; CLK_BRD        ; 0.153  ; 0.000         ;
+----------------+--------+---------------+


+-----------------------------------------+
; Fast 1200mV 0C Model Recovery Summary   ;
+----------------+--------+---------------+
; Clock          ; Slack  ; End Point TNS ;
+----------------+--------+---------------+
; JTAG_NEXUS_TCK ; -1.067 ; -31.893       ;
; CLK_REF        ; -0.593 ; -17.677       ;
+----------------+--------+---------------+


+----------------------------------------+
; Fast 1200mV 0C Model Removal Summary   ;
+----------------+-------+---------------+
; Clock          ; Slack ; End Point TNS ;
+----------------+-------+---------------+
; JTAG_NEXUS_TCK ; 0.486 ; 0.000         ;
; CLK_REF        ; 0.716 ; 0.000         ;
+----------------+-------+---------------+


+--------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------+--------+------------------------+
; Clock          ; Slack  ; End Point TNS          ;
+----------------+--------+------------------------+
; CLK_REF        ; -3.601 ; -2113.356              ;
; CLK_BRD        ; -3.000 ; -1972.417              ;
; JTAG_NEXUS_TCK ; -3.000 ; -1382.907              ;
+----------------+--------+------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLK_REF'                                                                                                                                                                                                  ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                               ; To Node                                                                       ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -9.796 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.414      ;
; -9.795 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.363     ; 8.419      ;
; -9.739 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 8.358      ;
; -9.699 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.317      ;
; -9.677 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.295      ;
; -9.629 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.247      ;
; -9.622 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.358     ; 8.251      ;
; -9.594 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.358     ; 8.223      ;
; -9.570 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.358     ; 8.199      ;
; -9.540 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.363     ; 8.164      ;
; -9.535 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.153      ;
; -9.533 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.358     ; 8.162      ;
; -9.520 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.363     ; 8.144      ;
; -9.505 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.371     ; 8.121      ;
; -9.504 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.365     ; 8.126      ;
; -9.499 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 8.126      ;
; -9.493 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 8.120      ;
; -9.481 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 8.108      ;
; -9.473 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.091      ;
; -9.469 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.364     ; 8.092      ;
; -9.468 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.086      ;
; -9.464 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 8.083      ;
; -9.464 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 8.083      ;
; -9.464 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 8.083      ;
; -9.464 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 8.083      ;
; -9.463 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 8.088      ;
; -9.463 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 8.088      ;
; -9.463 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 8.088      ;
; -9.463 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 8.088      ;
; -9.454 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.358     ; 8.083      ;
; -9.448 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.370     ; 8.065      ;
; -9.441 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.059      ;
; -9.431 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 8.049      ;
; -9.408 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.371     ; 8.024      ;
; -9.407 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.367     ; 8.027      ;
; -9.407 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.367     ; 8.027      ;
; -9.407 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.367     ; 8.027      ;
; -9.407 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.367     ; 8.027      ;
; -9.401 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.358     ; 8.030      ;
; -9.397 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 8.024      ;
; -9.391 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.363     ; 8.015      ;
; -9.386 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.371     ; 8.002      ;
; -9.374 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.358     ; 8.003      ;
; -9.370 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 7.988      ;
; -9.367 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.986      ;
; -9.367 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.986      ;
; -9.367 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.986      ;
; -9.367 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.986      ;
; -9.351 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.369     ; 7.969      ;
; -9.347 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.363     ; 7.971      ;
; -9.345 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.964      ;
; -9.345 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.964      ;
; -9.345 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.964      ;
; -9.345 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.964      ;
; -9.338 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.371     ; 7.954      ;
; -9.331 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 7.958      ;
; -9.319 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 7.946      ;
; -9.303 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 7.930      ;
; -9.297 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.916      ;
; -9.297 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.916      ;
; -9.297 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.916      ;
; -9.297 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.916      ;
; -9.290 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.920      ;
; -9.290 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.920      ;
; -9.290 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.920      ;
; -9.290 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.920      ;
; -9.279 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 7.906      ;
; -9.262 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.892      ;
; -9.262 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.892      ;
; -9.262 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.892      ;
; -9.262 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.892      ;
; -9.249 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.365     ; 7.871      ;
; -9.244 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.371     ; 7.860      ;
; -9.242 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 7.869      ;
; -9.238 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.868      ;
; -9.238 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.868      ;
; -9.238 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.868      ;
; -9.238 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.868      ;
; -9.229 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.365     ; 7.851      ;
; -9.208 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.833      ;
; -9.208 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.833      ;
; -9.208 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.833      ;
; -9.208 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.833      ;
; -9.208 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.833      ;
; -9.203 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.822      ;
; -9.203 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.822      ;
; -9.203 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.822      ;
; -9.203 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.368     ; 7.822      ;
; -9.202 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.827      ;
; -9.201 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]   ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.360     ; 7.828      ;
; -9.201 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.831      ;
; -9.201 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.831      ;
; -9.201 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.831      ;
; -9.201 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.357     ; 7.831      ;
; -9.190 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.815      ;
; -9.188 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.813      ;
; -9.188 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.813      ;
; -9.188 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.813      ;
; -9.188 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]      ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.362     ; 7.813      ;
; -9.182 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0] ; CLK_REF      ; CLK_REF     ; 1.000        ; -2.371     ; 7.798      ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                           ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                ; To Node                                                                                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -7.114 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                                                                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[0]  ; CLK_REF      ; CLK_BRD     ; 1.000        ; -6.405     ; 1.676      ;
; -7.100 ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                                                                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|CaptureRegister_DMain[16] ; CLK_REF      ; CLK_BRD     ; 1.000        ; -6.405     ; 1.662      ;
; -6.721 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.525      ;
; -6.675 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.167     ; 7.495      ;
; -6.650 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.443      ;
; -6.628 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.172     ; 7.443      ;
; -6.627 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.431      ;
; -6.625 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.172     ; 7.440      ;
; -6.624 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.428      ;
; -6.622 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.440      ;
; -6.621 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.180     ; 7.428      ;
; -6.592 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.191     ; 7.388      ;
; -6.588 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.185     ; 7.390      ;
; -6.576 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.189     ; 7.374      ;
; -6.551 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.172     ; 7.366      ;
; -6.550 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.354      ;
; -6.548 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.172     ; 7.363      ;
; -6.547 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.173     ; 7.361      ;
; -6.547 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.351      ;
; -6.545 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.172     ; 7.360      ;
; -6.544 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.348      ;
; -6.541 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.172     ; 7.356      ;
; -6.540 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.344      ;
; -6.535 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.178     ; 7.344      ;
; -6.535 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.185     ; 7.337      ;
; -6.533 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.351      ;
; -6.532 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.180     ; 7.339      ;
; -6.522 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.200     ; 7.309      ;
; -6.512 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.305      ;
; -6.511 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.304      ;
; -6.510 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.187     ; 7.310      ;
; -6.508 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.301      ;
; -6.505 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.191     ; 7.301      ;
; -6.503 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_4                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.296      ;
; -6.490 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.188     ; 7.289      ;
; -6.489 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.307      ;
; -6.480 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.284      ;
; -6.477 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_20                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.183     ; 7.281      ;
; -6.466 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.181     ; 7.272      ;
; -6.464 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.196     ; 7.255      ;
; -6.462 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.280      ;
; -6.461 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.279      ;
; -6.461 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_20                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.291      ;
; -6.461 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_4                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.203     ; 7.245      ;
; -6.461 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_26                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.180     ; 7.268      ;
; -6.460 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.290      ;
; -6.460 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.178     ; 7.269      ;
; -6.460 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_30                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.180     ; 7.267      ;
; -6.460 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_20                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.279      ;
; -6.459 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.289      ;
; -6.459 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_16                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.278      ;
; -6.458 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.288      ;
; -6.458 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.277      ;
; -6.457 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_17                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.276      ;
; -6.456 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.286      ;
; -6.456 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.157     ; 7.286      ;
; -6.455 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.273      ;
; -6.455 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_13                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.274      ;
; -6.455 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_15                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.274      ;
; -6.454 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_18                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.180     ; 7.261      ;
; -6.453 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.271      ;
; -6.452 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.169     ; 7.270      ;
; -6.452 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_31                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.180     ; 7.259      ;
; -6.451 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_28                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.180     ; 7.258      ;
; -6.450 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.165     ; 7.272      ;
; -6.447 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.186     ; 7.248      ;
; -6.441 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_1                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.184     ; 7.244      ;
; -6.441 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.185     ; 7.243      ;
; -6.438 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.185     ; 7.240      ;
; -6.438 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_23                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.200     ; 7.225      ;
; -6.435 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.182     ; 7.240      ;
; -6.434 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.227      ;
; -6.431 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.184     ; 7.234      ;
; -6.431 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.224      ;
; -6.430 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_18                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.184     ; 7.233      ;
; -6.428 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.221      ;
; -6.425 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.192     ; 7.220      ;
; -6.424 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_23                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.217      ;
; -6.421 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_22                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.214      ;
; -6.416 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_24                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.191     ; 7.212      ;
; -6.415 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.188     ; 7.214      ;
; -6.407 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.184     ; 7.210      ;
; -6.405 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_14                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.194     ; 7.198      ;
; -6.402 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_25                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.187     ; 7.202      ;
; -6.402 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.168     ; 7.221      ;
; -6.401 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_17                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.186     ; 7.202      ;
; -6.389 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_31                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.174     ; 7.202      ;
; -6.386 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_0                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.167     ; 7.206      ;
; -6.385 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_16                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.170     ; 7.202      ;
; -6.380 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_2                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.192     ; 7.175      ;
; -6.377 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.192     ; 7.172      ;
; -6.377 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.195     ; 7.169      ;
; -6.375 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3:Memory_TSK3000A_1_u3_component|altsyncram:altsyncram_component|altsyncram_9bd2:auto_generated|ram_block1a1~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_4                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.200     ; 7.162      ;
; -6.374 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_19                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.189     ; 7.172      ;
; -6.371 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_31                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.165     ; 7.193      ;
; -6.368 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_3                  ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.193     ; 7.162      ;
; -6.364 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_25                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.185     ; 7.166      ;
; -6.361 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_3                         ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.185     ; 7.163      ;
; -6.360 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a0~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_Result_12                 ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.197     ; 7.150      ;
; -6.358 ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_we_reg ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_27                        ; CLK_BRD      ; CLK_BRD     ; 1.000        ; -0.185     ; 7.160      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                            ; To Node                                                                                                                                                                        ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -2.488 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 3.441      ;
; -2.483 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.429      ;
; -2.462 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 3.415      ;
; -2.457 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.403      ;
; -2.447 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.063     ; 3.371      ;
; -2.420 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.063     ; 3.344      ;
; -2.408 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.047     ; 3.348      ;
; -2.403 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 3.356      ;
; -2.400 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.063     ; 3.324      ;
; -2.398 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.344      ;
; -2.349 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 3.302      ;
; -2.344 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.041     ; 3.290      ;
; -2.339 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.063     ; 3.263      ;
; -2.336 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.028     ; 3.295      ;
; -2.331 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.035     ; 3.283      ;
; -2.330 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.281      ;
; -2.324 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.275      ;
; -2.308 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 3.257      ;
; -2.304 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.255      ;
; -2.298 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.249      ;
; -2.282 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 3.231      ;
; -2.254 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.028     ; 3.213      ;
; -2.249 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.035     ; 3.201      ;
; -2.245 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.196      ;
; -2.239 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.190      ;
; -2.223 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 3.172      ;
; -2.219 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 3.176      ;
; -2.214 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 3.164      ;
; -2.212 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 3.167      ;
; -2.209 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.226     ; 2.970      ;
; -2.207 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.039     ; 3.155      ;
; -2.204 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.233     ; 2.958      ;
; -2.191 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.142      ;
; -2.185 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 3.136      ;
; -2.181 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.028     ; 3.140      ;
; -2.178 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 3.135      ;
; -2.176 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.035     ; 3.128      ;
; -2.172 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 3.129      ;
; -2.169 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                           ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 3.118      ;
; -2.160 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.028     ; 3.119      ;
; -2.156 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_2__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 3.111      ;
; -2.155 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.035     ; 3.107      ;
; -2.105 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.142      ; 3.234      ;
; -2.100 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.056     ; 3.031      ;
; -2.096 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 3.053      ;
; -2.090 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 3.047      ;
; -2.084 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.028     ; 3.043      ;
; -2.079 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_1__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.035     ; 3.031      ;
; -2.078 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.142      ; 3.207      ;
; -2.074 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_5__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 3.029      ;
; -2.072 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg_0                                                                                                              ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|SubstituteRegister:tsk3000_SubstituteRegister|NexusReg_Shift_31__Z ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.057     ; 3.002      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[12]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[11]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[9]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[8]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[7]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[6]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[5]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[4]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.071 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[3]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.439     ; 2.119      ;
; -2.066 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.158      ; 3.211      ;
; -2.061 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 3.016      ;
; -2.059 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.026     ; 3.020      ;
; -2.058 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.142      ; 3.187      ;
; -2.055 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 3.010      ;
; -2.054 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 3.007      ;
; -2.054 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_3__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.033     ; 3.008      ;
; -2.051 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.228     ; 2.810      ;
; -2.048 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 3.001      ;
; -2.045 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.228     ; 2.804      ;
; -2.043 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.050     ; 2.980      ;
; -2.040 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.023     ; 3.004      ;
; -2.039 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ2:U_CURSORREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 2.992      ;
; -2.038 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.438     ; 2.087      ;
; -2.038 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[14]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.438     ; 2.087      ;
; -2.038 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[13]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.438     ; 2.087      ;
; -2.038 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[12]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.438     ; 2.087      ;
; -2.038 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[11]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.438     ; 2.087      ;
; -2.038 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[10]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.438     ; 2.087      ;
; -2.038 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[9]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.438     ; 2.087      ;
; -2.038 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                    ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[8]                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.438     ; 2.087      ;
; -2.035 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ3:U_TRWORDREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 2.992      ;
; -2.032 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ1:U_ECNTREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.036     ; 2.983      ;
; -2.029 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.230     ; 2.786      ;
; -2.027 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ0:U_MAGNITREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[31]                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.028     ; 2.986      ;
; -2.023 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 2.980      ;
; -2.022 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXREGZ0:U_MAGNITREG|sh_reg_0__Z                                                                                             ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.035     ; 2.974      ;
; -2.017 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 2.974      ;
; -2.016 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.050     ; 2.953      ;
; -2.014 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 2.969      ;
; -2.013 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 2.968      ;
; -2.005 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|byp_reg                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 2.958      ;
; -2.004 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|sh_reg_0                                                                                                                 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.034     ; 2.957      ;
; -2.002 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_7__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|sh_ireg[3]                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.030     ; 2.959      ;
; -2.001 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.038     ; 2.950      ;
; -2.001 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_2:RegisterWriteFromInstrument|sh_reg[7]                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 2.956      ;
; -2.001 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|up_reg_r_6__Z                                                                                                                         ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 2.956      ;
; -2.000 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0] ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8:control_register|sh_reg[7]                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.032     ; 2.955      ;
; -1.997 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|byp_reg_Z                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.142      ; 3.126      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLK_REF'                                                                                                                                                                                                                                                 ;
+--------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                         ; To Node                                                                         ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -5.532 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.176      ;
; -5.503 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_cs|lpm_ff:ff1|dffs[0]      ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 1.196      ;
; -5.366 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.342      ;
; -5.361 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.347      ;
; -5.297 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 1.402      ;
; -5.282 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 1.417      ;
; -5.271 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.437      ;
; -5.269 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.439      ;
; -5.250 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.458      ;
; -5.243 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.583      ; 1.464      ;
; -5.228 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.480      ;
; -5.010 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.698      ;
; -4.987 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.721      ;
; -4.953 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.573      ; 1.744      ;
; -4.920 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 1.779      ;
; -4.844 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.864      ;
; -4.843 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.584      ; 1.865      ;
; -4.830 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.573      ; 1.867      ;
; -4.803 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.573      ; 1.894      ;
; -4.511 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_29|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.573      ; 2.186      ;
; -4.373 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.578      ; 2.329      ;
; -4.288 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_28|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.578      ; 2.414      ;
; -4.077 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_31|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 2.622      ;
; -3.978 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_27|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.578      ; 2.724      ;
; -3.035 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.581      ; 3.670      ;
; -2.717 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:INST_sdi|lpm_ff:ff1|dffs[0]   ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.579      ; 3.986      ;
; -2.549 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.581      ; 4.156      ;
; -2.549 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.581      ; 4.156      ;
; -2.549 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.581      ; 4.156      ;
; -2.549 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]        ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.581      ; 4.156      ;
; -2.501 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_30|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.579      ; 4.202      ;
; -2.419 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_20|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.578      ; 4.283      ;
; -2.384 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_26|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.573      ; 4.313      ;
; -2.325 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_6|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.573      ; 4.372      ;
; -2.323 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_2|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 4.376      ;
; -2.311 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_5|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.573      ; 4.386      ;
; -2.300 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_22|lpm_ff:ff1|dffs[0]         ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.578      ; 4.402      ;
; -2.260 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_4|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 4.439      ;
; -2.249 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_3|lpm_ff:ff1|dffs[0]          ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 4.450      ;
; -2.232 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.474      ;
; -2.198 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.508      ;
; -2.144 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.562      ;
; -2.141 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.565      ;
; -2.137 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.569      ;
; -2.122 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.584      ;
; -2.098 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.608      ;
; -2.083 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.594      ; 4.635      ;
; -2.082 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.624      ;
; -2.076 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.630      ;
; -2.073 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.633      ;
; -2.063 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.643      ;
; -2.037 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.669      ;
; -2.020 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.686      ;
; -2.011 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0] ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.695      ;
; -1.995 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.564      ; 4.693      ;
; -1.949 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_4|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.575      ; 4.750      ;
; -1.934 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.582      ; 4.772      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_12|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_0|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_8|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_1|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_9|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_13|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_5|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_3|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_7|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_15|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_11|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_14|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_10|lpm_ff:ff1|dffs[0]    ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_2|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -1.860 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:data_6|lpm_ff:ff1|dffs[0]     ; CLK_BRD        ; CLK_REF     ; 0.000        ; 6.593      ; 4.857      ;
; -0.127 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                     ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B   ; CLK_REF        ; CLK_REF     ; 0.000        ; 1.086      ; 1.043      ;
; -0.108 ; JTAG_NEXUS_TCK                                                                                                    ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|tck1_Z                                        ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 1.457      ; 1.473      ;
; 0.015  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8                                    ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 7.268      ; 7.407      ;
; 0.089  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_A                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B   ; CLK_REF        ; CLK_REF     ; 0.000        ; 1.235      ; 1.408      ;
; 0.181  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25                                   ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25] ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 7.266      ; 7.571      ;
; 0.184  ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z                                                ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z              ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.046      ; 0.314      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]          ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_8|lpm_ff:ff1|dffs[0]          ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_9|lpm_ff:ff1|dffs[0]          ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                      ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]    ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]                                       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]     ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.038      ; 0.307      ;
; 0.186  ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B                                     ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divisor_2_5:divisor_2_5_component_c6|sig_B   ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_0|lpm_ff:ff1|dffs[0]          ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]                                            ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_1|lpm_ff:ff1|dffs[0]          ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_17|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_21|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_23|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_24|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]                                           ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_25|lpm_ff:ff1|dffs[0]         ; CLK_REF        ; CLK_REF     ; 0.000        ; 0.037      ; 0.307      ;
+--------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                         ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.079 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[3]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[3]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.313      ;
; 0.080 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[7]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[7]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.314      ;
; 0.080 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[4]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[4]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.314      ;
; 0.080 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[2]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[2]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.314      ;
; 0.080 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[0]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg_0                                                                                                                                                                                   ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.314      ;
; 0.081 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[1]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[1]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.315      ;
; 0.082 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[6]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[6]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.316      ;
; 0.082 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_TXBUFFER[5]                                                                                                                                                                                                                                          ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_1:RegisterReadFromInstrument|sh_reg[5]                                                                                                                                                                                  ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.316      ;
; 0.090 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[3]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.324      ;
; 0.091 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[1]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.325      ;
; 0.092 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg_0                                                                                                                                                                                               ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.326      ;
; 0.097 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[5]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 0.329      ;
; 0.099 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z                                                                                                                                                                                                                                                      ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                                                                          ; CLK_REF        ; JTAG_NEXUS_TCK ; 0.000        ; 0.105      ; 0.328      ;
; 0.099 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                                                                                                                            ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_8_3:RegisterStatus|sh_reg[7]                                                                                                                                                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.108      ; 0.331      ;
; 0.139 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.373      ;
; 0.144 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.380      ;
; 0.145 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.379      ;
; 0.146 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.382      ;
; 0.146 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.382      ;
; 0.146 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.380      ;
; 0.146 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.380      ;
; 0.148 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.384      ;
; 0.150 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.384      ;
; 0.178 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.414      ;
; 0.179 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.415      ;
; 0.179 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_13|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.415      ;
; 0.180 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.414      ;
; 0.182 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                      ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.112      ; 0.418      ;
; 0.183 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                                                                                                                   ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                       ; CLK_BRD        ; JTAG_NEXUS_TCK ; 0.000        ; 0.110      ; 0.417      ;
; 0.185 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_2__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|tapstate_r_i_3__Z                                                                                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_NXCTRLFSM:U_NEXUS_CTRL_FSM|nxcfsm_r_1__Z                                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_2__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|tapstate_r_i_0_3__Z                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_0|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_2|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:tapstate_r_3|lpm_ff:ff1|dffs[0]                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_2|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_1|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:StartUpCounter_3|lpm_ff:ff1|dffs[0]                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.307      ;
; 0.188 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_2__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_1__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.045      ; 0.317      ;
; 0.190 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_17|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.312      ;
; 0.190 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[3]                                                                                                                                                                                                                                ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.312      ;
; 0.190 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[2]                                                                                                                                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[1]                                                                                                                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_10|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_30|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_29|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_20|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[29]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[29]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[21]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[21]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[15]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[15]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[12]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[12]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[6]                                                                                                                                                                                        ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[6]                                                                                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                              ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|TERMINALCORE_DRNOOUT:id_reg_unit|sh_reg[4]                                                                                                                                                                              ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_3__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_ireg_2__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.045      ; 0.320      ;
; 0.191 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_14__Z                                                                                                                                                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|sh_reg_13__Z                                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|up_reg[4]                                                                                                                                                                                                                                ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[4]                                                                                                                                                                                                                                ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.313      ;
; 0.191 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[7]                                                                                                                                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[6]                                                                                                                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.314      ;
; 0.191 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[6]                                                                                                                                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|CLKGEN_DRNOOUT:id_reg_unit|sh_reg[5]                                                                                                                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.314      ;
; 0.192 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[7]                                                                                                                                                                                                                                 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_7                                                                                                                                                                                                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.345      ; 0.621      ;
; 0.192 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                                                                         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_19|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_18|lpm_ff:ff1|dffs[0]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_16|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_2|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterExtConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_2|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                      ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_27|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_26|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_24|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_23|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_23|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_22|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_21|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_19|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_18|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_18|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_17|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_15|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_14|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0]                                                    ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0]                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_7|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_6|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_5|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_2|lpm_ff:ff1|dffs[0]                                                     ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_:RegisterConfiguration|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_12|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 0.313      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_9|lpm_ff:ff1|dffs[0]  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_8|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_4|lpm_ff:ff1|dffs[0]  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_3|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_1|lpm_ff:ff1|dffs[0]  ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DRNOOUT_32_:id_reg_unit|NOS031__AltSyn_AltiumAlteraDffAsyncEn:sh_reg_0|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[26]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[26]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[24]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[24]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[22]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[22]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
; 0.192 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|up_reg[20]                                                                                                                                                                                       ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_32:RegisterConfiguration|sh_reg[20]                                                                                                                                                                                       ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.314      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLK_BRD'                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                              ; To Node                                                                                                                                                                                                        ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 0.153 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_14                                                                         ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4:Memory_TSK3000A_1_u4_component|altsyncram:altsyncram_component|altsyncram_abd2:auto_generated|ram_block1a3~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.224      ; 0.481      ;
; 0.165 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_5                                                                          ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.223      ; 0.492      ;
; 0.173 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_11                                                                         ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.223      ; 0.500      ;
; 0.181 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_10                                                                         ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.223      ; 0.508      ;
; 0.185 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                         ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                     ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                        ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                     ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_2                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                      ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsOffline                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                             ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|IsInstrumentOnline                                                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[1]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[0]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[3]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                     ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_0                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_SP:U_Registers_SP|CompareRegister_Interrupt                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                      ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                             ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem_2                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                            ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|StateMainMem[3]                                                                                                    ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                           ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                           ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_0__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[8]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[1]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                                    ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState[4]                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                     ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_3                                                                                             ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|WB_STATUS[7]                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                          ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[5]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                          ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[4]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                           ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_1                                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                      ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[1]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                      ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[2]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                         ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state[1]                                                                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                       ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|state_i[5]                                                                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                           ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl_2                                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                          ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|ctrl[3]                                                                                                                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                                   ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|DebugState_i_0                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.307      ;
; 0.193 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                      ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|bitcount[0]                                                                                                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.314      ;
; 0.196 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_4                                                               ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.183      ; 0.483      ;
; 0.196 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff1_Z          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z                                                  ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|clkval[9]                                                                                                        ; WB_SPI32:U_NOS031_OB_SPI_DAC_SubPart_Port|spi32:U_spi|clkval[9]                                                                                                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                               ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|PipeLineController:U_PipeLineController|FlushCycleCount[3]                                                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.317      ;
; 0.197 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff1_Z          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.318      ;
; 0.200 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_2                                                               ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.183      ; 0.487      ;
; 0.203 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_14__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_13__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.325      ;
; 0.204 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_1                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|RxSetFF0                                                                                                                                               ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; -0.003     ; 0.325      ;
; 0.204 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_24__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|RegA_Abs_26__Z                                                                                       ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|RegA_Abs_30__Z                                                                                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_22__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_21__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_9__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.326      ;
; 0.205 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z      ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff1_Z                                                            ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; -0.004     ; 0.325      ;
; 0.205 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_20__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_19__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.326      ;
; 0.205 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_MEM_WB:U_Regs_MEM_WB|Reg_Rd_Index_3                                                                 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Destination_WB_3                                                                                                     ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.327      ;
; 0.205 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOnlineFF0                                                                                                    ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOnlineFF1                                                                                                                                            ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.327      ;
; 0.206 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_DATAREG_INOUT_WR_2:RegisterAcknowledge|up_reg_0                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TxAcknowledgeFF0                                                                                                                                       ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; -0.003     ; 0.327      ;
; 0.210 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_1                                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_0                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.332      ;
; 0.212 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_6__Z                                                                                           ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_5__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.333      ;
; 0.213 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_6                                                               ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.183      ; 0.500      ;
; 0.214 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemAddress_14                                                              ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a7~portb_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.183      ; 0.501      ;
; 0.214 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_1                                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_1                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.336      ;
; 0.215 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_30__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_29__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.336      ;
; 0.215 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_17__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_16__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.336      ;
; 0.215 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_6__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.337      ;
; 0.215 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_6__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_5__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.337      ;
; 0.215 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_3__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_2__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.337      ;
; 0.216 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_2__Z                                                                                           ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_1__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.337      ;
; 0.216 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_28__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_27__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.337      ;
; 0.216 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_26__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_25__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.337      ;
; 0.216 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_18__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_17__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.337      ;
; 0.217 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_1__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_0__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.339      ;
; 0.218 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_13__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_12__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.340      ;
; 0.234 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_i_8__Z                                                                                         ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|State_7__Z                                                                                                                                   ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.355      ;
; 0.254 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Update_ff2_Z          ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugDataReg_Write_Z                                                       ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.375      ;
; 0.265 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_ff1_Z                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugStep_Z                                                                ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.386      ;
; 0.266 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_8__Z                                                                                  ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_7__Z                                                                                                                          ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.388      ;
; 0.266 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugReset_ff_Z                    ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugReset_Z                                                               ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.387      ;
; 0.267 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|SubstituteReg_Update_Z ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|SubstituteReg_Update_ff1_Z                                                 ; JTAG_NEXUS_TCK ; CLK_BRD     ; 0.000        ; -0.004     ; 0.387      ;
; 0.267 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Registers_GP:U_Registers_GP|DIN_REG1_13                                                                  ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|RegisterFile:U_RegisterFile|Rs_Data_13                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.389      ;
; 0.267 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_0                                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_0                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.389      ;
; 0.267 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_EX_MEM:U_Regs_EX_MEM|Reg_MemSelect_0                                                                ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|MemoryManager:U_MemoryManager|DMem_Segment_Reg_1                                                                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.389      ;
; 0.267 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugEnable_ff_Z                   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|DebugEnable_Z                                                              ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.388      ;
; 0.268 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_12__Z                                                                                 ; TSK3000A_MDU:U_NOS031_OB_TSK3000A_1_SubPart_MDU|MultDiv:U_MultDiv|WorkingReg_0_0_11__Z                                                                                                                         ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.390      ;
; 0.270 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|SubstituteReg_Update_ff1_Z         ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugSignalController:TSK3000_DebugSignalController|SubstituteReg_Update_ff2_Z                                                 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.037      ; 0.391      ;
; 0.270 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOfflineFF0                                                                                                   ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|GoOfflineFF1                                                                                                                                           ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.038      ; 0.392      ;
; 0.271 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|MCU_Top:U_MCU|Regs_PC:ProgramCounter|Reg_PC_6                                                                          ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_address_reg0 ; CLK_BRD        ; CLK_BRD     ; 0.000        ; 0.222      ; 0.597      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                              ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; -1.067 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 2.044      ;
; -0.958 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.934      ;
; -0.958 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.934      ;
; -0.925 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.902      ;
; -0.915 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.892      ;
; -0.912 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.889      ;
; -0.833 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.810      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.829 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.805      ;
; -0.816 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.792      ;
; -0.816 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.792      ;
; -0.806 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.782      ;
; -0.806 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.782      ;
; -0.803 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.779      ;
; -0.803 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.779      ;
; -0.794 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[4]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.770      ;
; -0.778 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.755      ;
; -0.765 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.188     ; 1.544      ;
; -0.744 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.010      ; 1.721      ;
; -0.727 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.429     ; 0.785      ;
; -0.727 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                                                                                         ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.429     ; 0.785      ;
; -0.727 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.429     ; 0.785      ;
; -0.727 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|reset_r_Z                                                                                                                          ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.429     ; 0.785      ;
; -0.724 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.700      ;
; -0.724 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.700      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.687 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.663      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.677 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.653      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.674 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.650      ;
; -0.669 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.645      ;
; -0.669 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[2]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.645      ;
; -0.664 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[5]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.640      ;
; -0.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.189     ; 1.434      ;
; -0.656 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.189     ; 1.434      ;
; -0.650 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg[2]                                                                                                                                   ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.711      ;
; -0.650 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_i[0]                                                                                                                                 ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.711      ;
; -0.650 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_0                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.711      ;
; -0.650 ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|reset_r                                                                                                                                  ; TERMINAL:U_NOS031_OB_TERMINAL_1|TERMINALCORE:U_terminal|TERMINALCORE_TAPCONTROLLER:TAP1|up_ireg_2                                                                                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.711      ;
; -0.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_3|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.710      ;
; -0.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_1|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.710      ;
; -0.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_0|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.710      ;
; -0.649 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsync:reset_r|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_TAPCONTROLLER:TAP1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_ireg_2|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.500        ; -0.426     ; 0.710      ;
; -0.642 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter[3]                                                                                                                            ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.618      ;
; -0.639 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_6                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.615      ;
; -0.635 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_7__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.611      ;
; -0.635 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_7                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_1__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.611      ;
; -0.598 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_1__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.147      ; 1.732      ;
; -0.598 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z                                                                                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_0__Z                                                                                               ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; 0.147      ; 1.732      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                              ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.595 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.571      ;
; -0.582 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_0                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; -0.189     ; 1.360      ;
; -0.571 ; TSK3000A_MCU:U_NOS031_OB_TSK3000A_1_SubPart_MCU|InputSynchronizer:U_InputSynchronizer|ResetCounter_1                                                                                                                             ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                    ; CLK_BRD        ; JTAG_NEXUS_TCK ; 1.000        ; 0.009      ; 1.547      ;
; -0.564 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z                                                                     ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_5__Z                                                                    ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 1.000        ; -0.037     ; 1.514      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'CLK_REF'                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.593 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.453      ;
; -0.551 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.406      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.529 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.389      ;
; -0.508 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.360      ;
; -0.487 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.342      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.465 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.325      ;
; -0.457 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.309      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.456 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.314      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.445 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.107     ; 1.305      ;
; -0.429 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.286      ;
; -0.429 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.286      ;
; -0.429 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.286      ;
; -0.423 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.278      ;
; -0.403 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.112     ; 1.258      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.392 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.250      ;
; -0.382 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.239      ;
; -0.382 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.239      ;
; -0.382 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.110     ; 1.239      ;
; -0.380 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.232      ;
; -0.360 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.115     ; 1.212      ;
; -0.346 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.078      ; 1.391      ;
; -0.346 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.078      ; 1.391      ;
; -0.346 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.078      ; 1.391      ;
; -0.346 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.078      ; 1.391      ;
; -0.346 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; 0.078      ; 1.391      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.328 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.186      ;
; -0.308 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.166      ;
; -0.308 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 1.000        ; -0.109     ; 1.166      ;
+--------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'JTAG_NEXUS_TCK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                          ; To Node                                                                                                                                                                                                                                                     ; Launch Clock   ; Latch Clock    ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+
; 0.486 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.609      ;
; 0.486 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.609      ;
; 0.486 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.609      ;
; 0.486 ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.039      ; 0.609      ;
; 0.568 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_1                                                                                                                                                                                             ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.690      ;
; 0.568 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[3]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.690      ;
; 0.568 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg_i_0                                                                                                                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.690      ;
; 0.568 ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|reset_r                                                                                                      ; CLKGEN:U4|clkgen_top:U_FREQ|CLKGEN_TAPCONTROLLER:tap1|up_ireg[1]                                                                                                                                                                                            ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.038      ; 0.690      ;
; 0.577 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_10|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.054      ; 0.715      ;
; 0.577 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_9|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.054      ; 0.715      ;
; 0.577 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_2|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.054      ; 0.715      ;
; 0.577 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_1|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.054      ; 0.715      ;
; 0.714 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_12|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.040      ; 0.838      ;
; 0.714 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_11|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.040      ; 0.838      ;
; 0.714 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_3|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.040      ; 0.838      ;
; 0.714 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_4|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.040      ; 0.838      ;
; 0.726 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_6|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.036      ; 0.846      ;
; 0.726 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_14|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.036      ; 0.846      ;
; 0.726 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_13|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.036      ; 0.846      ;
; 0.726 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_5|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.036      ; 0.846      ;
; 0.819 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_7|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.032      ; 0.935      ;
; 0.819 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_15|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.032      ; 0.935      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.917 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.038      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.935 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.053      ;
; 0.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_0__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.028      ; 1.050      ;
; 0.938 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|up_reg_1__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.028      ; 1.050      ;
; 0.944 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z                                                         ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CTRLREG:U_CTRLREG|sh_reg_2__Z                                                                                                                      ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.028      ; 1.056      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.969 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_3__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.090      ;
; 0.974 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_8|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.099      ;
; 0.974 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_16|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.099      ;
; 0.974 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_18|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.099      ;
; 0.974 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_17|lpm_ff:ff1|dffs[0] ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.099      ;
; 0.974 ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DefaultEnable|lpm_ff:ff1|dffs[0] ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|Configurable_CTLPANEL_internal:InternalComponent|Configurable_CTLPANEL_internalUNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_19_:RegisterOutput_Value|NOS031__AltSyn_AltiumAlteraDffAsyncEn:up_reg_0|lpm_ff:ff1|dffs[0]  ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.041      ; 1.099      ;
; 1.012 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_1__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_4__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.036      ; 1.132      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_2__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_4__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_3__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_2__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_1__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_0__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.023 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_i_0_0__Z   ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_0__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.144      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_7__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_6__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_5__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_4__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_3__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_2__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_1__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|sh_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.030 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z                                                       ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_NXMODULE:U_NX_MODULE|LAX_CFG32_CFGREG:U_CFGREG|up_reg_0__Z                                                                                                                        ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.034      ; 1.148      ;
; 1.032 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_7__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.153      ;
; 1.032 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|RegOut_1_6__Z                                                                                           ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.153      ;
; 1.032 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_6__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.153      ;
; 1.032 ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|TapController:tsk3000_TapController|up_ireg_2__Z       ; TSK3000A_OCDS:U_NOS031_OB_TSK3000A_1_SubPart_OCDS|JtagDebugUnit:U_JtagDebugUnit|DebugPort:TSK3000_DebugPort|ControlRegister:tsk3000_ControlRegister|NexusReg_Shift_5__Z                                                                                     ; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 0.000        ; 0.037      ; 1.153      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'CLK_REF'                                                                                                                                                                                                                             ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                    ; To Node                                                              ; Launch Clock   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+
; 0.716 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.030      ;
; 0.716 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.030      ;
; 0.716 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.030      ;
; 0.716 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.030      ;
; 0.716 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.030      ;
; 0.716 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.030      ;
; 0.742 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.058      ;
; 0.742 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.058      ;
; 0.742 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.058      ;
; 0.742 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.058      ;
; 0.742 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.058      ;
; 0.811 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.125      ;
; 0.811 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.125      ;
; 0.811 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.125      ;
; 0.811 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.125      ;
; 0.811 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.125      ;
; 0.811 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.125      ;
; 0.833 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.147      ;
; 0.833 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.147      ;
; 0.833 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.147      ;
; 0.833 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.147      ;
; 0.833 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.147      ;
; 0.833 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.147      ;
; 0.837 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.153      ;
; 0.837 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.153      ;
; 0.837 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.153      ;
; 0.837 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.153      ;
; 0.837 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.153      ;
; 0.859 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.175      ;
; 0.859 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.175      ;
; 0.859 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.175      ;
; 0.859 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.175      ;
; 0.859 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.175      ;
; 0.868 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 0.988      ;
; 0.868 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 0.988      ;
; 0.868 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 0.988      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.876 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 0.997      ;
; 0.891 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.205      ;
; 0.891 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.205      ;
; 0.891 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.205      ;
; 0.891 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.205      ;
; 0.891 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.205      ;
; 0.891 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.190      ; 1.205      ;
; 0.917 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.233      ;
; 0.917 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.233      ;
; 0.917 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.233      ;
; 0.917 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.233      ;
; 0.917 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memaddr_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; 0.192      ; 1.233      ;
; 0.941 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.009     ; 1.056      ;
; 0.955 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.072      ;
; 0.963 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.083      ;
; 0.963 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.083      ;
; 0.963 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.083      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.971 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.092      ;
; 0.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.105      ;
; 0.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.105      ;
; 0.985 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.105      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_21__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_20__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_16__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_14__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_6__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_5__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_3__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_1__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.993 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_2__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_0__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.003     ; 1.114      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_19__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_18__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_17__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_15__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_13__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_12__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_11__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_10__Z  ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_9__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_8__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_7__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_4__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 0.994 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_3__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memdata_2__Z   ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.001     ; 1.117      ;
; 1.032 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_1__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.152      ;
; 1.032 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|startcap_ff1_Z ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.152      ;
; 1.032 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_1__Z   ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|memrw_i_Z      ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.004     ; 1.152      ;
; 1.036 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|bf_Z           ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.009     ; 1.151      ;
; 1.050 ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_LA16PORT:U_LA16PORT|LAX_CFG32_TAPCONTROLLER:U_TAP|up_ireg_i_0__Z ; LAX_CFG32:U2_U1|LAX_CFG32_LA16:U1|LAX_CFG32_FSM:U_FSM|state_0__Z     ; JTAG_NEXUS_TCK ; CLK_REF     ; 0.000        ; -0.007     ; 1.167      ;
+-------+--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_REF'                                                                                                                                                                ;
+--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock   ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[16]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[17]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[18]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[19]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[20]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[21]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[22]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[23]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[24]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[25]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[26]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[27]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[28]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[29]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[30]                                                  ;
; -3.601 ; -3.417       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[31]                                                  ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[0]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[10]                                                  ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[11]                                                  ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[12]                                                  ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[13]                                                  ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[14]                                                  ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[15]                                                  ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[1]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[2]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[3]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[4]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[5]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[6]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[7]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[8]                                                   ;
; -3.600 ; -3.416       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|count[9]                                                   ;
; -3.583 ; -3.399       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_2_0:divisor_2_0_component_c11|clko_s                                                  ;
; -3.555 ; -3.371       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_divider:divisor_main_component_c10|outstate                                                   ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_16_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_17_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_18_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_19_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_20_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_21_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_22_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_23_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_24_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_25_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_26_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_27_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_28_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_29_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_30_|clk                                                                               ;
; -3.421 ; -3.421       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_31_|clk                                                                               ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_0_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_10_|clk                                                                               ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_11_|clk                                                                               ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_12_|clk                                                                               ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_13_|clk                                                                               ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_14_|clk                                                                               ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_15_|clk                                                                               ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_1_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_2_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_3_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_4_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_5_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_6_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_7_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_8_|clk                                                                                ;
; -3.420 ; -3.420       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|count_9_|clk                                                                                ;
; -3.413 ; -3.413       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|inclk[0]                                                                      ;
; -3.413 ; -3.413       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x~clkctrl|outclk                                                                        ;
; -3.403 ; -3.403       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_2_0_component_c11|clko_s_Z|clk                                                                                 ;
; -3.375 ; -3.375       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|outstate_Z|clk                                                                              ;
; -3.358 ; -3.358       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|combout                                                                       ;
; -3.347 ; -3.347       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_main_component_c10|clockout_x_cZ|datab                                                                         ;
; -3.317 ; -3.317       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|combout                                                                            ;
; -3.120 ; -2.936       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_A ;
; -3.120 ; -2.936       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_B ;
; -3.120 ; -2.936       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DIVISOR_25_0:divisor_25_0_component_c9|CLKGEN_divisor_5_0_divisor_5_0_component_c0_4:U2|sig_C ;
; -3.000 ; 1.000        ; 4.000          ; Port Rate       ; CLK_REF ; Rise       ; CLK_REF                                                                                                                          ;
; -2.957 ; -2.957       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|clko_x_cZ|datab                                                                              ;
; -2.940 ; -2.940       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_A_Z|clk                                                                               ;
; -2.940 ; -2.940       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_B_Z|clk                                                                               ;
; -2.940 ; -2.940       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|sig_C_Z|clk                                                                               ;
; -2.932 ; -2.932       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|datad                                                                                ;
; -2.927 ; -2.927       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout                                                                              ;
; -2.886 ; -2.886       ; 0.000          ; Low Pulse Width ; CLK_REF ; Rise       ; U3|U_FREQ|divisor_25_0_component_c9|U1|clko_x_cZ|combout                                                                         ;
; -2.860 ; -2.676       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_0|lpm_ff:ff1|dffs[0]                                                         ;
; -2.860 ; -2.676       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_1|lpm_ff:ff1|dffs[0]                                                         ;
; -2.860 ; -2.676       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_2|lpm_ff:ff1|dffs[0]                                                         ;
; -2.860 ; -2.676       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsyncEn:k_3|lpm_ff:ff1|dffs[0]                                                         ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_busy|lpm_ff:ff1|dffs[0]                                                     ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:INST_sck|lpm_ff:ff1|dffs[0]                                                      ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_10|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_11|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_12|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_13|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_14|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_15|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_16|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_18|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_19|lpm_ff:ff1|dffs[0]                                                          ;
; -2.859 ; -2.675       ; 0.184          ; Low Pulse Width ; CLK_REF ; Rise       ; spia:U_spia|NOS031__AltSyn_AltiumAlteraDffAsync:i_7|lpm_ff:ff1|dffs[0]                                                           ;
+--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_BRD'                                                                                                                                                                                                                                         ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock   ; Clock Edge ; Target                                                                                                                                                                                                         ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; CLK_BRD ; Rise       ; CLK_BRD                                                                                                                                                                                                        ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:XIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_0|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_1|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_2|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_3|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_4|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_5|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_6|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_CTLPANEL:U_NOS031_OB_CTLPANEL|NOS031__AltSyn_AltiumAlteraDffAsyncEn:YIN_Reg_7|lpm_ff:ff1|dffs[0]                                                                                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_0|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_10|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_11|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_12|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_13|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_14|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_15|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_1|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_2|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_3|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_4|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_5|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_6|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_7|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_8|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:dataout0_9|lpm_ff:ff1|dffs[0]                                                                                               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SPIDACTEST:U_NOS031_OB_SPIDACTEST|NOS031__AltSyn_AltiumAlteraDffAsync:load0|lpm_ff:ff1|dffs[0]                                                                                                    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_addresssetup|lpm_ff:ff1|dffs[0]                                                                                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_read_ack|lpm_ff:ff1|dffs[0]                                                                                                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_ack|lpm_ff:ff1|dffs[0]                                                                                                ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_SRAM:U_NOS031_OB_SRAM|NOS031__AltSyn_AltiumAlteraDffAsync:State_state_write_pulse|lpm_ff:ff1|dffs[0]                                                                                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0]                                                                                         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsync:UseBadDecode|lpm_ff:ff1|dffs[0]                                                                                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_0|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_1|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_2|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_3|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_4|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_5|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_6|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_1:U_NOS031_OB_WB_INTERCON_1|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_7|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsync:Bad_Decode|lpm_ff:ff1|dffs[0]                                                                                         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsync:UseBadDecode|lpm_ff:ff1|dffs[0]                                                                                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_0|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_1|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_2|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_3|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_4|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_5|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_6|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Configurable_WB_INTERCON_2:U_NOS031_OB_WB_INTERCON_2|NOS031__AltSyn_AltiumAlteraDffAsyncEn:DecodeAddr_7|lpm_ff:ff1|dffs[0]                                                                                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a0~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a1~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a2~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a3~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a4~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a5~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a6~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~porta_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_datain_reg0  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1:Memory_TSK3000A_1_u1_component|altsyncram:altsyncram_component|altsyncram_7bd2:auto_generated|ram_block1a7~portb_we_reg       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~porta_address_reg0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; CLK_BRD ; Rise       ; Memory_TSK3000A_1:U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2:Memory_TSK3000A_1_u2_component|altsyncram:altsyncram_component|altsyncram_8bd2:auto_generated|ram_block1a0~porta_datain_reg0  ;
+--------+--------------+----------------+------------+---------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'JTAG_NEXUS_TCK'                                                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock          ; Clock Edge ; Target                                                                            ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; JTAG_NEXUS_TCK ; Rise       ; JTAG_NEXUS_TCK                                                                    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[10]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[11]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[12]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[13]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[14]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[15]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[1]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[2]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[3]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[4]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[5]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[6]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[7]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[8]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg[9]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|sh_reg_0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg[14]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_0_d0 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_1    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_10   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_11   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_12   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_13   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_15   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_2    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_3    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_4    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_5    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_6    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_7    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_8    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_16:user2_register|up_reg_9    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[10]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[11]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[12]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[13]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[14]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[15]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[16]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[17]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[18]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[19]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[1]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[20]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[21]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[22]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[23]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[24]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[25]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[26]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[27]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[28]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[29]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[2]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[30]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[31]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[3]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[4]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[5]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[6]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[7]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[8]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg[9]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|sh_reg_0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_1    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_10   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_11   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_12   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_13   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_14   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_15   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_16   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_17   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_18   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_19   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_2    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_20   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_21   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_22   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_23   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_24   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_25   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_26   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_27   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_28   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_29   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_3    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_30   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_31   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_4    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_5    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_6    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_7    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_8    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_32:user1_register|up_reg_9    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; JTAG_NEXUS_TCK ; Rise       ; CLKGEN:U3|clkgen_top:U_FREQ|CLKGEN_DATAREG_INOUT_WR_8:control_register|sh_reg[3]  ;
+--------+--------------+----------------+------------+----------------+------------+-----------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------+
; Setup Times                                                                    ;
+----------------+----------------+-------+-------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+----------------+----------------+-------+-------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; 2.180 ; 2.972 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 1.644 ; 2.388 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 2.067 ; 2.824 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 1.643 ; 2.351 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 1.738 ; 2.465 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 1.982 ; 2.719 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 2.171 ; 2.921 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 2.082 ; 2.838 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 1.594 ; 2.278 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 1.686 ; 2.363 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 2.180 ; 2.972 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 2.048 ; 2.799 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 1.984 ; 2.719 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 1.730 ; 2.451 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 1.866 ; 2.591 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 1.889 ; 2.635 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 1.766 ; 2.485 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 2.140 ; 2.910 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 1.431 ; 2.132 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 1.884 ; 2.649 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 1.607 ; 2.309 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 1.771 ; 2.487 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 2.058 ; 2.837 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 2.093 ; 2.845 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 2.039 ; 2.764 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 1.632 ; 2.300 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 1.687 ; 2.419 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 1.869 ; 2.597 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 1.811 ; 2.511 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 1.863 ; 2.605 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 2.140 ; 2.910 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 1.860 ; 2.584 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 2.007 ; 2.754 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 1.669 ; 2.369 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; 2.267 ; 2.954 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; 7.206 ; 7.999 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.145 ; 0.440 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; 1.689 ; 2.440 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; 2.105 ; 2.856 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+-------+-------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Hold Times                                                                       ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; -0.911 ; -1.558 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; -0.911 ; -1.558 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; -1.210 ; -1.886 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; -0.961 ; -1.608 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; -1.054 ; -1.716 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; -1.140 ; -1.802 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; -1.109 ; -1.749 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; -1.125 ; -1.796 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; -0.928 ; -1.560 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; -1.012 ; -1.635 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; -1.350 ; -2.046 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; -1.338 ; -2.037 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; -1.144 ; -1.794 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; -0.912 ; -1.564 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; -0.937 ; -1.587 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; -1.059 ; -1.722 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; -0.990 ; -1.635 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; -0.815 ; -1.458 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; -0.815 ; -1.458 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; -0.991 ; -1.657 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; -0.927 ; -1.573 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; -0.956 ; -1.601 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; -1.106 ; -1.797 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; -1.096 ; -1.751 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; -1.093 ; -1.725 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; -0.969 ; -1.585 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; -1.147 ; -1.818 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; -1.052 ; -1.705 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; -1.113 ; -1.752 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; -1.034 ; -1.675 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; -0.919 ; -1.559 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; -1.038 ; -1.691 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; -1.195 ; -1.879 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; -0.970 ; -1.596 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; -1.002 ; -1.686 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; -2.701 ; -3.277 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.068  ; -0.208 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; -0.902 ; -1.560 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; -0.975 ; -1.630 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Clock to Output Times                                                            ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_A[*]     ; CLK_BRD        ; 9.679  ; 9.976  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[0]    ; CLK_BRD        ; 7.232  ; 7.291  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[1]    ; CLK_BRD        ; 8.326  ; 8.409  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[2]    ; CLK_BRD        ; 7.347  ; 7.392  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[3]    ; CLK_BRD        ; 7.810  ; 7.977  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[4]    ; CLK_BRD        ; 8.448  ; 8.536  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[5]    ; CLK_BRD        ; 8.755  ; 8.847  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[6]    ; CLK_BRD        ; 8.595  ; 8.663  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[7]    ; CLK_BRD        ; 9.679  ; 9.976  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[8]    ; CLK_BRD        ; 8.411  ; 8.449  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[9]    ; CLK_BRD        ; 9.129  ; 9.387  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[10]   ; CLK_BRD        ; 8.750  ; 8.861  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[11]   ; CLK_BRD        ; 8.343  ; 8.385  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[12]   ; CLK_BRD        ; 8.386  ; 8.427  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[13]   ; CLK_BRD        ; 8.929  ; 9.027  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[14]   ; CLK_BRD        ; 9.107  ; 9.395  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[15]   ; CLK_BRD        ; 7.967  ; 8.059  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[16]   ; CLK_BRD        ; 7.600  ; 7.706  ; Rise       ; CLK_BRD         ;
;  SRAM0_A[17]   ; CLK_BRD        ; 7.977  ; 8.104  ; Rise       ; CLK_BRD         ;
; SRAM0_D[*]     ; CLK_BRD        ; 4.527  ; 4.750  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 3.635  ; 3.740  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 4.527  ; 4.750  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 3.909  ; 4.079  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 3.361  ; 3.445  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.222  ; 4.385  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 4.462  ; 4.651  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 3.853  ; 3.933  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 3.703  ; 3.788  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 4.034  ; 4.152  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 3.923  ; 4.029  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.123  ; 4.265  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 3.986  ; 4.076  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 3.914  ; 4.071  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 3.636  ; 3.748  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 3.903  ; 4.023  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 3.810  ; 3.922  ; Rise       ; CLK_BRD         ;
; SRAM0_E        ; CLK_BRD        ; 9.976  ; 9.975  ; Rise       ; CLK_BRD         ;
; SRAM0_LB       ; CLK_BRD        ; 9.692  ; 9.665  ; Rise       ; CLK_BRD         ;
; SRAM0_OE       ; CLK_BRD        ; 8.910  ; 8.778  ; Rise       ; CLK_BRD         ;
; SRAM0_UB       ; CLK_BRD        ; 9.589  ; 9.560  ; Rise       ; CLK_BRD         ;
; SRAM0_W        ; CLK_BRD        ; 3.950  ; 3.838  ; Rise       ; CLK_BRD         ;
; SRAM1_A[*]     ; CLK_BRD        ; 9.378  ; 9.594  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[0]    ; CLK_BRD        ; 7.273  ; 7.326  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[1]    ; CLK_BRD        ; 8.976  ; 9.116  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[2]    ; CLK_BRD        ; 7.623  ; 7.689  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[3]    ; CLK_BRD        ; 7.797  ; 7.962  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[4]    ; CLK_BRD        ; 8.287  ; 8.352  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[5]    ; CLK_BRD        ; 8.406  ; 8.456  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[6]    ; CLK_BRD        ; 9.123  ; 9.314  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[7]    ; CLK_BRD        ; 8.590  ; 8.655  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[8]    ; CLK_BRD        ; 8.259  ; 8.285  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[9]    ; CLK_BRD        ; 8.616  ; 8.750  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[10]   ; CLK_BRD        ; 8.616  ; 8.702  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[11]   ; CLK_BRD        ; 8.378  ; 8.429  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[12]   ; CLK_BRD        ; 8.423  ; 8.487  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[13]   ; CLK_BRD        ; 9.378  ; 9.594  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[14]   ; CLK_BRD        ; 8.823  ; 9.031  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[15]   ; CLK_BRD        ; 8.286  ; 8.419  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[16]   ; CLK_BRD        ; 7.459  ; 7.531  ; Rise       ; CLK_BRD         ;
;  SRAM1_A[17]   ; CLK_BRD        ; 7.961  ; 8.072  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 4.270  ; 4.461  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.824  ; 3.945  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 3.856  ; 3.978  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 3.938  ; 4.079  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 4.109  ; 4.262  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 4.232  ; 4.409  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.209  ; 4.350  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 3.987  ; 4.102  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 4.270  ; 4.461  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 4.055  ; 4.158  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 4.056  ; 4.211  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 4.208  ; 4.384  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 3.984  ; 4.102  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 3.617  ; 3.726  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 3.710  ; 3.835  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.260  ; 4.410  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 3.623  ; 3.729  ; Rise       ; CLK_BRD         ;
; SRAM1_E        ; CLK_BRD        ; 9.789  ; 9.788  ; Rise       ; CLK_BRD         ;
; SRAM1_LB       ; CLK_BRD        ; 10.052 ; 10.073 ; Rise       ; CLK_BRD         ;
; SRAM1_OE       ; CLK_BRD        ; 9.449  ; 9.376  ; Rise       ; CLK_BRD         ;
; SRAM1_UB       ; CLK_BRD        ; 9.834  ; 9.840  ; Rise       ; CLK_BRD         ;
; SRAM1_W        ; CLK_BRD        ; 5.258  ; 4.967  ; Rise       ; CLK_BRD         ;
; DAC_CLK        ; CLK_REF        ; 10.769 ; 10.985 ; Rise       ; CLK_REF         ;
; DAC_CS         ; CLK_REF        ; 11.380 ; 11.597 ; Rise       ; CLK_REF         ;
; DAC_DOUT       ; CLK_REF        ; 11.874 ; 12.179 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ; 5.427  ; 5.775  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                  ;
+----------------+----------------+-------+-------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+----------------+----------------+-------+-------+------------+-----------------+
; SRAM0_A[*]     ; CLK_BRD        ; 3.879 ; 4.013 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[0]    ; CLK_BRD        ; 4.278 ; 4.457 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[1]    ; CLK_BRD        ; 5.123 ; 5.391 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[2]    ; CLK_BRD        ; 3.879 ; 4.013 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[3]    ; CLK_BRD        ; 4.582 ; 4.842 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[4]    ; CLK_BRD        ; 4.898 ; 5.174 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[5]    ; CLK_BRD        ; 5.516 ; 5.812 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[6]    ; CLK_BRD        ; 5.546 ; 5.865 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[7]    ; CLK_BRD        ; 6.854 ; 7.299 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[8]    ; CLK_BRD        ; 4.845 ; 5.069 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[9]    ; CLK_BRD        ; 6.026 ; 6.466 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[10]   ; CLK_BRD        ; 4.702 ; 4.930 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[11]   ; CLK_BRD        ; 4.893 ; 5.134 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[12]   ; CLK_BRD        ; 4.914 ; 5.180 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[13]   ; CLK_BRD        ; 4.842 ; 5.059 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[14]   ; CLK_BRD        ; 5.801 ; 6.195 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[15]   ; CLK_BRD        ; 4.573 ; 4.781 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[16]   ; CLK_BRD        ; 4.072 ; 4.248 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[17]   ; CLK_BRD        ; 4.506 ; 4.734 ; Rise       ; CLK_BRD         ;
; SRAM0_D[*]     ; CLK_BRD        ; 3.289 ; 3.370 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 3.553 ; 3.653 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 4.409 ; 4.623 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 3.816 ; 3.979 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 3.289 ; 3.370 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.123 ; 4.279 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 4.353 ; 4.533 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 3.770 ; 3.845 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 3.623 ; 3.705 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 3.941 ; 4.053 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 3.835 ; 3.936 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.026 ; 4.162 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 3.895 ; 3.982 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 3.819 ; 3.969 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 3.553 ; 3.661 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 3.809 ; 3.925 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 3.719 ; 3.827 ; Rise       ; CLK_BRD         ;
; SRAM0_E        ; CLK_BRD        ; 4.599 ; 4.806 ; Rise       ; CLK_BRD         ;
; SRAM0_LB       ; CLK_BRD        ; 4.326 ; 4.508 ; Rise       ; CLK_BRD         ;
; SRAM0_OE       ; CLK_BRD        ; 3.576 ; 3.656 ; Rise       ; CLK_BRD         ;
; SRAM0_UB       ; CLK_BRD        ; 4.141 ; 4.211 ; Rise       ; CLK_BRD         ;
; SRAM0_W        ; CLK_BRD        ; 3.859 ; 3.752 ; Rise       ; CLK_BRD         ;
; SRAM1_A[*]     ; CLK_BRD        ; 3.936 ; 4.080 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[0]    ; CLK_BRD        ; 4.319 ; 4.492 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[1]    ; CLK_BRD        ; 5.783 ; 6.112 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[2]    ; CLK_BRD        ; 4.145 ; 4.300 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[3]    ; CLK_BRD        ; 4.570 ; 4.828 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[4]    ; CLK_BRD        ; 4.742 ; 4.995 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[5]    ; CLK_BRD        ; 5.181 ; 5.436 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[6]    ; CLK_BRD        ; 6.084 ; 6.528 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[7]    ; CLK_BRD        ; 5.775 ; 5.992 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[8]    ; CLK_BRD        ; 4.699 ; 4.912 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[9]    ; CLK_BRD        ; 5.535 ; 5.854 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[10]   ; CLK_BRD        ; 4.574 ; 4.778 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[11]   ; CLK_BRD        ; 4.927 ; 5.176 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[12]   ; CLK_BRD        ; 4.949 ; 5.237 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[13]   ; CLK_BRD        ; 5.304 ; 5.640 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[14]   ; CLK_BRD        ; 5.496 ; 5.807 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[15]   ; CLK_BRD        ; 4.879 ; 5.125 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[16]   ; CLK_BRD        ; 3.936 ; 4.080 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[17]   ; CLK_BRD        ; 4.491 ; 4.704 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 3.536 ; 3.639 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.732 ; 3.848 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 3.763 ; 3.880 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 3.844 ; 3.979 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 4.006 ; 4.153 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 4.124 ; 4.294 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.109 ; 4.244 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 3.897 ; 4.006 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 4.170 ; 4.352 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 3.961 ; 4.060 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 3.958 ; 4.108 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 4.109 ; 4.277 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 3.895 ; 4.007 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 3.536 ; 3.639 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 3.625 ; 3.744 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.154 ; 4.297 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 3.540 ; 3.641 ; Rise       ; CLK_BRD         ;
; SRAM1_E        ; CLK_BRD        ; 4.419 ; 4.627 ; Rise       ; CLK_BRD         ;
; SRAM1_LB       ; CLK_BRD        ; 4.668 ; 4.707 ; Rise       ; CLK_BRD         ;
; SRAM1_OE       ; CLK_BRD        ; 4.094 ; 4.232 ; Rise       ; CLK_BRD         ;
; SRAM1_UB       ; CLK_BRD        ; 4.385 ; 4.489 ; Rise       ; CLK_BRD         ;
; SRAM1_W        ; CLK_BRD        ; 5.152 ; 4.868 ; Rise       ; CLK_BRD         ;
; DAC_CLK        ; CLK_REF        ; 8.275 ; 8.482 ; Rise       ; CLK_REF         ;
; DAC_CS         ; CLK_REF        ; 8.869 ; 9.078 ; Rise       ; CLK_REF         ;
; DAC_DOUT       ; CLK_REF        ; 9.342 ; 9.634 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ; 4.331 ; 4.486 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+-------+-------+------------+-----------------+


+----------------------------------------------------------------------------+
; Output Enable Times                                                        ;
+--------------+------------+--------+--------+------------+-----------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+--------------+------------+--------+--------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 10.027 ; 10.024 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 10.251 ; 10.248 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 10.702 ; 10.699 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 10.577 ; 10.574 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 10.101 ; 10.098 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 10.345 ; 10.341 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 10.604 ; 10.600 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 10.795 ; 10.791 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 10.748 ; 10.744 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 10.775 ; 10.771 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 10.638 ; 10.634 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 10.345 ; 10.341 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 10.634 ; 10.630 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 10.490 ; 10.487 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 10.027 ; 10.024 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 10.402 ; 10.399 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 10.382 ; 10.379 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 9.976  ; 9.973  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 9.976  ; 9.973  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 10.682 ; 10.679 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 10.572 ; 10.569 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 10.522 ; 10.519 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 10.682 ; 10.679 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 10.591 ; 10.587 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 10.634 ; 10.630 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 10.520 ; 10.516 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 10.628 ; 10.624 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 10.634 ; 10.630 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 10.624 ; 10.620 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 10.968 ; 10.964 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 10.017 ; 10.014 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 10.547 ; 10.544 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 10.557 ; 10.554 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 10.375 ; 10.372 ; Rise       ; CLK_BRD         ;
+--------------+------------+--------+--------+------------+-----------------+


+--------------------------------------------------------------------------+
; Minimum Output Enable Times                                              ;
+--------------+------------+-------+-------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+-------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 3.842 ; 3.842 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 4.056 ; 4.056 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 4.489 ; 4.489 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 4.370 ; 4.370 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 3.911 ; 3.911 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 4.144 ; 4.144 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 4.391 ; 4.391 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 4.577 ; 4.577 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 4.530 ; 4.530 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 4.557 ; 4.557 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 4.426 ; 4.426 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 4.144 ; 4.144 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 4.422 ; 4.422 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 4.285 ; 4.285 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 3.842 ; 3.842 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 4.202 ; 4.202 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 4.182 ; 4.182 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 3.791 ; 3.791 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 3.791 ; 3.791 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 4.469 ; 4.469 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 4.366 ; 4.366 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 4.316 ; 4.316 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 4.469 ; 4.469 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 4.380 ; 4.380 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 4.421 ; 4.421 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 4.314 ; 4.314 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 4.416 ; 4.416 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 4.421 ; 4.421 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 4.412 ; 4.412 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 4.743 ; 4.743 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 3.832 ; 3.832 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 4.342 ; 4.342 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 4.352 ; 4.352 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 4.175 ; 4.175 ; Rise       ; CLK_BRD         ;
+--------------+------------+-------+-------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Output Disable Times                                                             ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 9.931     ; 9.931     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 10.186    ; 10.186    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 10.706    ; 10.706    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 10.543    ; 10.543    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 10.022    ; 10.022    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 10.294    ; 10.294    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 10.579    ; 10.579    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 10.801    ; 10.801    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 10.744    ; 10.744    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 10.776    ; 10.776    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 10.613    ; 10.613    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 10.294    ; 10.294    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 10.619    ; 10.619    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 10.482    ; 10.482    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 9.931     ; 9.931     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 10.343    ; 10.343    ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 10.323    ; 10.323    ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 9.873     ; 9.873     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 9.873     ; 9.873     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 10.686    ; 10.686    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 10.545    ; 10.545    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 10.495    ; 10.495    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 10.686    ; 10.686    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 10.571    ; 10.571    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 10.609    ; 10.609    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 10.507    ; 10.507    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 10.603    ; 10.603    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 10.609    ; 10.609    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 10.609    ; 10.609    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 10.980    ; 10.980    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 9.921     ; 9.921     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 10.516    ; 10.516    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 10.526    ; 10.526    ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 10.320    ; 10.320    ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                     ;
+--------------+------------+-----------+-----------+------------+-----------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+--------------+------------+-----------+-----------+------------+-----------------+
; SRAM0_D[*]   ; CLK_BRD    ; 3.958     ; 4.024     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]  ; CLK_BRD    ; 4.202     ; 4.268     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]  ; CLK_BRD    ; 4.701     ; 4.767     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]  ; CLK_BRD    ; 4.545     ; 4.611     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]  ; CLK_BRD    ; 4.043     ; 4.109     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]  ; CLK_BRD    ; 4.303     ; 4.361     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]  ; CLK_BRD    ; 4.576     ; 4.634     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]  ; CLK_BRD    ; 4.790     ; 4.848     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]  ; CLK_BRD    ; 4.734     ; 4.792     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]  ; CLK_BRD    ; 4.765     ; 4.823     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]  ; CLK_BRD    ; 4.610     ; 4.668     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10] ; CLK_BRD    ; 4.303     ; 4.361     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11] ; CLK_BRD    ; 4.616     ; 4.674     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12] ; CLK_BRD    ; 4.485     ; 4.551     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13] ; CLK_BRD    ; 3.958     ; 4.024     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14] ; CLK_BRD    ; 4.354     ; 4.420     ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15] ; CLK_BRD    ; 4.334     ; 4.400     ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]   ; CLK_BRD    ; 3.901     ; 3.967     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]  ; CLK_BRD    ; 3.901     ; 3.967     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]  ; CLK_BRD    ; 4.681     ; 4.747     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]  ; CLK_BRD    ; 4.547     ; 4.613     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]  ; CLK_BRD    ; 4.497     ; 4.563     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]  ; CLK_BRD    ; 4.681     ; 4.747     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]  ; CLK_BRD    ; 4.569     ; 4.627     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]  ; CLK_BRD    ; 4.606     ; 4.664     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]  ; CLK_BRD    ; 4.509     ; 4.567     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]  ; CLK_BRD    ; 4.600     ; 4.658     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]  ; CLK_BRD    ; 4.606     ; 4.664     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10] ; CLK_BRD    ; 4.606     ; 4.664     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11] ; CLK_BRD    ; 4.962     ; 5.020     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12] ; CLK_BRD    ; 3.948     ; 4.014     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13] ; CLK_BRD    ; 4.519     ; 4.585     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14] ; CLK_BRD    ; 4.529     ; 4.595     ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15] ; CLK_BRD    ; 4.330     ; 4.396     ; Rise       ; CLK_BRD         ;
+--------------+------------+-----------+-----------+------------+-----------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                 ;
+------------------+------------+----------+----------+---------+---------------------+
; Clock            ; Setup      ; Hold     ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+------------+----------+----------+---------+---------------------+
; Worst-case Slack ; -24.053    ; -14.232  ; -3.723   ; 0.486   ; -7.940              ;
;  CLK_BRD         ; -19.081    ; 0.153    ; N/A      ; N/A     ; -4.000              ;
;  CLK_REF         ; -24.053    ; -14.232  ; -2.530   ; 0.716   ; -7.940              ;
;  JTAG_NEXUS_TCK  ; -7.149     ; 0.079    ; -3.723   ; 0.486   ; -3.000              ;
; Design-wide TNS  ; -27914.13  ; -598.797 ; -225.375 ; 0.0     ; -10202.28           ;
;  CLK_BRD         ; -19572.457 ; 0.000    ; N/A      ; N/A     ; -3064.980           ;
;  CLK_REF         ; -3253.348  ; -598.797 ; -83.786  ; 0.000   ; -5190.791           ;
;  JTAG_NEXUS_TCK  ; -5088.325  ; 0.000    ; -141.589 ; 0.000   ; -1946.509           ;
+------------------+------------+----------+----------+---------+---------------------+


+----------------------------------------------------------------------------------+
; Setup Times                                                                      ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; 5.157  ; 5.173  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 3.766  ; 3.956  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 4.780  ; 4.846  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 3.769  ; 3.981  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 4.061  ; 4.225  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.578  ; 4.710  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 5.157  ; 5.173  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 4.897  ; 4.983  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 3.688  ; 3.873  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 3.934  ; 4.096  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 4.877  ; 5.086  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.669  ; 4.880  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 4.570  ; 4.674  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 3.968  ; 4.170  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 4.303  ; 4.425  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 4.373  ; 4.551  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 4.086  ; 4.292  ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 5.079  ; 5.054  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.427  ; 3.513  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 4.376  ; 4.572  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 3.678  ; 3.890  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 4.115  ; 4.291  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 4.876  ; 4.966  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.952  ; 4.997  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 4.750  ; 4.806  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 3.731  ; 3.890  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 3.925  ; 4.046  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 4.346  ; 4.427  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 4.181  ; 4.320  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 4.230  ; 4.443  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 5.079  ; 5.054  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 4.244  ; 4.415  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.647  ; 4.765  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 3.848  ; 4.052  ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; 5.049  ; 5.357  ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; 18.429 ; 17.379 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.261  ; 0.652  ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; 3.937  ; 4.177  ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; 4.717  ; 4.950  ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Hold Times                                                                       ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_D[*]     ; CLK_BRD        ; -0.911 ; -1.558 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; -0.911 ; -1.558 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; -1.210 ; -1.886 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; -0.961 ; -1.608 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; -1.054 ; -1.716 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; -1.140 ; -1.802 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; -1.109 ; -1.749 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; -1.125 ; -1.796 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; -0.928 ; -1.560 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; -1.012 ; -1.635 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; -1.350 ; -2.046 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; -1.338 ; -2.037 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; -1.144 ; -1.794 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; -0.912 ; -1.564 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; -0.937 ; -1.587 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; -1.059 ; -1.722 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; -0.990 ; -1.635 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; -0.815 ; -1.458 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; -0.815 ; -1.458 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; -0.991 ; -1.657 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; -0.927 ; -1.573 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; -0.956 ; -1.601 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; -1.106 ; -1.797 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; -1.096 ; -1.751 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; -1.093 ; -1.725 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; -0.969 ; -1.585 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; -1.147 ; -1.818 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; -1.052 ; -1.705 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; -1.113 ; -1.752 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; -1.034 ; -1.675 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; -0.919 ; -1.559 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; -1.038 ; -1.691 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; -1.195 ; -1.879 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; -0.970 ; -1.596 ; Rise       ; CLK_BRD         ;
; TEST_BUTTON    ; CLK_BRD        ; -1.002 ; -1.686 ; Rise       ; CLK_BRD         ;
; CLK_REF        ; CLK_REF        ; -2.701 ; -3.277 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 0.231  ; 0.008  ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDI ; JTAG_NEXUS_TCK ; -0.902 ; -1.560 ; Rise       ; JTAG_NEXUS_TCK  ;
; JTAG_NEXUS_TMS ; JTAG_NEXUS_TCK ; -0.975 ; -1.630 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+----------------------------------------------------------------------------------+
; Clock to Output Times                                                            ;
+----------------+----------------+--------+--------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+----------------+----------------+--------+--------+------------+-----------------+
; SRAM0_A[*]     ; CLK_BRD        ; 20.873 ; 20.793 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[0]    ; CLK_BRD        ; 16.175 ; 15.854 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[1]    ; CLK_BRD        ; 18.432 ; 18.220 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[2]    ; CLK_BRD        ; 16.298 ; 16.096 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[3]    ; CLK_BRD        ; 17.286 ; 17.197 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[4]    ; CLK_BRD        ; 18.766 ; 18.428 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[5]    ; CLK_BRD        ; 19.319 ; 19.005 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[6]    ; CLK_BRD        ; 18.915 ; 18.624 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[7]    ; CLK_BRD        ; 20.873 ; 20.793 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[8]    ; CLK_BRD        ; 18.533 ; 18.238 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[9]    ; CLK_BRD        ; 20.179 ; 19.969 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[10]   ; CLK_BRD        ; 19.332 ; 19.020 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[11]   ; CLK_BRD        ; 18.322 ; 18.116 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[12]   ; CLK_BRD        ; 18.503 ; 18.255 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[13]   ; CLK_BRD        ; 19.699 ; 19.322 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[14]   ; CLK_BRD        ; 19.724 ; 19.491 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[15]   ; CLK_BRD        ; 17.718 ; 17.372 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[16]   ; CLK_BRD        ; 17.023 ; 16.767 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[17]   ; CLK_BRD        ; 17.748 ; 17.476 ; Rise       ; CLK_BRD         ;
; SRAM0_D[*]     ; CLK_BRD        ; 9.914  ; 9.467  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 7.765  ; 7.580  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 9.914  ; 9.467  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 8.308  ; 8.219  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 7.105  ; 6.989  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 9.006  ; 8.744  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 9.587  ; 9.244  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 7.982  ; 7.845  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 7.700  ; 7.626  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 8.565  ; 8.293  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 8.239  ; 8.039  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 8.707  ; 8.498  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 8.315  ; 8.119  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 8.362  ; 8.247  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 7.709  ; 7.473  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 8.403  ; 8.101  ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 8.140  ; 7.883  ; Rise       ; CLK_BRD         ;
; SRAM0_E        ; CLK_BRD        ; 22.512 ; 22.153 ; Rise       ; CLK_BRD         ;
; SRAM0_LB       ; CLK_BRD        ; 21.697 ; 21.473 ; Rise       ; CLK_BRD         ;
; SRAM0_OE       ; CLK_BRD        ; 19.665 ; 19.650 ; Rise       ; CLK_BRD         ;
; SRAM0_UB       ; CLK_BRD        ; 21.388 ; 21.288 ; Rise       ; CLK_BRD         ;
; SRAM0_W        ; CLK_BRD        ; 7.919  ; 8.032  ; Rise       ; CLK_BRD         ;
; SRAM1_A[*]     ; CLK_BRD        ; 20.268 ; 20.081 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[0]    ; CLK_BRD        ; 16.249 ; 15.912 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[1]    ; CLK_BRD        ; 19.227 ; 19.169 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[2]    ; CLK_BRD        ; 16.981 ; 16.681 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[3]    ; CLK_BRD        ; 17.249 ; 17.168 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[4]    ; CLK_BRD        ; 18.410 ; 18.113 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[5]    ; CLK_BRD        ; 18.505 ; 18.232 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[6]    ; CLK_BRD        ; 19.652 ; 19.558 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[7]    ; CLK_BRD        ; 18.936 ; 18.715 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[8]    ; CLK_BRD        ; 18.150 ; 17.916 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[9]    ; CLK_BRD        ; 18.978 ; 18.806 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[10]   ; CLK_BRD        ; 18.986 ; 18.654 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[11]   ; CLK_BRD        ; 18.379 ; 18.193 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[12]   ; CLK_BRD        ; 18.582 ; 18.388 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[13]   ; CLK_BRD        ; 20.268 ; 20.081 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[14]   ; CLK_BRD        ; 19.657 ; 19.174 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[15]   ; CLK_BRD        ; 18.475 ; 18.064 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[16]   ; CLK_BRD        ; 16.675 ; 16.445 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[17]   ; CLK_BRD        ; 17.701 ; 17.440 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 9.266  ; 8.843  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 8.153  ; 7.955  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 8.341  ; 8.044  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 8.447  ; 8.143  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 8.895  ; 8.579  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 9.266  ; 8.780  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 8.862  ; 8.641  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 8.361  ; 8.226  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 8.948  ; 8.843  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 8.580  ; 8.322  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 8.747  ; 8.451  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 8.832  ; 8.739  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 8.345  ; 8.167  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 7.737  ; 7.557  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 7.894  ; 7.756  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 9.135  ; 8.777  ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 7.728  ; 7.573  ; Rise       ; CLK_BRD         ;
; SRAM1_E        ; CLK_BRD        ; 21.855 ; 21.711 ; Rise       ; CLK_BRD         ;
; SRAM1_LB       ; CLK_BRD        ; 22.511 ; 22.285 ; Rise       ; CLK_BRD         ;
; SRAM1_OE       ; CLK_BRD        ; 20.988 ; 20.802 ; Rise       ; CLK_BRD         ;
; SRAM1_UB       ; CLK_BRD        ; 22.026 ; 21.852 ; Rise       ; CLK_BRD         ;
; SRAM1_W        ; CLK_BRD        ; 10.080 ; 10.159 ; Rise       ; CLK_BRD         ;
; DAC_CLK        ; CLK_REF        ; 25.761 ; 25.617 ; Rise       ; CLK_REF         ;
; DAC_CS         ; CLK_REF        ; 27.160 ; 26.803 ; Rise       ; CLK_REF         ;
; DAC_DOUT       ; CLK_REF        ; 28.411 ; 27.845 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ; 12.132 ; 11.954 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+--------+--------+------------+-----------------+


+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                  ;
+----------------+----------------+-------+-------+------------+-----------------+
; Data Port      ; Clock Port     ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+----------------+----------------+-------+-------+------------+-----------------+
; SRAM0_A[*]     ; CLK_BRD        ; 3.879 ; 4.013 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[0]    ; CLK_BRD        ; 4.278 ; 4.457 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[1]    ; CLK_BRD        ; 5.123 ; 5.391 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[2]    ; CLK_BRD        ; 3.879 ; 4.013 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[3]    ; CLK_BRD        ; 4.582 ; 4.842 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[4]    ; CLK_BRD        ; 4.898 ; 5.174 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[5]    ; CLK_BRD        ; 5.516 ; 5.812 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[6]    ; CLK_BRD        ; 5.546 ; 5.865 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[7]    ; CLK_BRD        ; 6.854 ; 7.299 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[8]    ; CLK_BRD        ; 4.845 ; 5.069 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[9]    ; CLK_BRD        ; 6.026 ; 6.466 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[10]   ; CLK_BRD        ; 4.702 ; 4.930 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[11]   ; CLK_BRD        ; 4.893 ; 5.134 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[12]   ; CLK_BRD        ; 4.914 ; 5.180 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[13]   ; CLK_BRD        ; 4.842 ; 5.059 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[14]   ; CLK_BRD        ; 5.801 ; 6.195 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[15]   ; CLK_BRD        ; 4.573 ; 4.781 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[16]   ; CLK_BRD        ; 4.072 ; 4.248 ; Rise       ; CLK_BRD         ;
;  SRAM0_A[17]   ; CLK_BRD        ; 4.506 ; 4.734 ; Rise       ; CLK_BRD         ;
; SRAM0_D[*]     ; CLK_BRD        ; 3.289 ; 3.370 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[0]    ; CLK_BRD        ; 3.553 ; 3.653 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[1]    ; CLK_BRD        ; 4.409 ; 4.623 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[2]    ; CLK_BRD        ; 3.816 ; 3.979 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[3]    ; CLK_BRD        ; 3.289 ; 3.370 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[4]    ; CLK_BRD        ; 4.123 ; 4.279 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[5]    ; CLK_BRD        ; 4.353 ; 4.533 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[6]    ; CLK_BRD        ; 3.770 ; 3.845 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[7]    ; CLK_BRD        ; 3.623 ; 3.705 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[8]    ; CLK_BRD        ; 3.941 ; 4.053 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[9]    ; CLK_BRD        ; 3.835 ; 3.936 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[10]   ; CLK_BRD        ; 4.026 ; 4.162 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[11]   ; CLK_BRD        ; 3.895 ; 3.982 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[12]   ; CLK_BRD        ; 3.819 ; 3.969 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[13]   ; CLK_BRD        ; 3.553 ; 3.661 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[14]   ; CLK_BRD        ; 3.809 ; 3.925 ; Rise       ; CLK_BRD         ;
;  SRAM0_D[15]   ; CLK_BRD        ; 3.719 ; 3.827 ; Rise       ; CLK_BRD         ;
; SRAM0_E        ; CLK_BRD        ; 4.599 ; 4.806 ; Rise       ; CLK_BRD         ;
; SRAM0_LB       ; CLK_BRD        ; 4.326 ; 4.508 ; Rise       ; CLK_BRD         ;
; SRAM0_OE       ; CLK_BRD        ; 3.576 ; 3.656 ; Rise       ; CLK_BRD         ;
; SRAM0_UB       ; CLK_BRD        ; 4.141 ; 4.211 ; Rise       ; CLK_BRD         ;
; SRAM0_W        ; CLK_BRD        ; 3.859 ; 3.752 ; Rise       ; CLK_BRD         ;
; SRAM1_A[*]     ; CLK_BRD        ; 3.936 ; 4.080 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[0]    ; CLK_BRD        ; 4.319 ; 4.492 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[1]    ; CLK_BRD        ; 5.783 ; 6.112 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[2]    ; CLK_BRD        ; 4.145 ; 4.300 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[3]    ; CLK_BRD        ; 4.570 ; 4.828 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[4]    ; CLK_BRD        ; 4.742 ; 4.995 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[5]    ; CLK_BRD        ; 5.181 ; 5.436 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[6]    ; CLK_BRD        ; 6.084 ; 6.528 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[7]    ; CLK_BRD        ; 5.775 ; 5.992 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[8]    ; CLK_BRD        ; 4.699 ; 4.912 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[9]    ; CLK_BRD        ; 5.535 ; 5.854 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[10]   ; CLK_BRD        ; 4.574 ; 4.778 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[11]   ; CLK_BRD        ; 4.927 ; 5.176 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[12]   ; CLK_BRD        ; 4.949 ; 5.237 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[13]   ; CLK_BRD        ; 5.304 ; 5.640 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[14]   ; CLK_BRD        ; 5.496 ; 5.807 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[15]   ; CLK_BRD        ; 4.879 ; 5.125 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[16]   ; CLK_BRD        ; 3.936 ; 4.080 ; Rise       ; CLK_BRD         ;
;  SRAM1_A[17]   ; CLK_BRD        ; 4.491 ; 4.704 ; Rise       ; CLK_BRD         ;
; SRAM1_D[*]     ; CLK_BRD        ; 3.536 ; 3.639 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[0]    ; CLK_BRD        ; 3.732 ; 3.848 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[1]    ; CLK_BRD        ; 3.763 ; 3.880 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[2]    ; CLK_BRD        ; 3.844 ; 3.979 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[3]    ; CLK_BRD        ; 4.006 ; 4.153 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[4]    ; CLK_BRD        ; 4.124 ; 4.294 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[5]    ; CLK_BRD        ; 4.109 ; 4.244 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[6]    ; CLK_BRD        ; 3.897 ; 4.006 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[7]    ; CLK_BRD        ; 4.170 ; 4.352 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[8]    ; CLK_BRD        ; 3.961 ; 4.060 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[9]    ; CLK_BRD        ; 3.958 ; 4.108 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[10]   ; CLK_BRD        ; 4.109 ; 4.277 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[11]   ; CLK_BRD        ; 3.895 ; 4.007 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[12]   ; CLK_BRD        ; 3.536 ; 3.639 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[13]   ; CLK_BRD        ; 3.625 ; 3.744 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[14]   ; CLK_BRD        ; 4.154 ; 4.297 ; Rise       ; CLK_BRD         ;
;  SRAM1_D[15]   ; CLK_BRD        ; 3.540 ; 3.641 ; Rise       ; CLK_BRD         ;
; SRAM1_E        ; CLK_BRD        ; 4.419 ; 4.627 ; Rise       ; CLK_BRD         ;
; SRAM1_LB       ; CLK_BRD        ; 4.668 ; 4.707 ; Rise       ; CLK_BRD         ;
; SRAM1_OE       ; CLK_BRD        ; 4.094 ; 4.232 ; Rise       ; CLK_BRD         ;
; SRAM1_UB       ; CLK_BRD        ; 4.385 ; 4.489 ; Rise       ; CLK_BRD         ;
; SRAM1_W        ; CLK_BRD        ; 5.152 ; 4.868 ; Rise       ; CLK_BRD         ;
; DAC_CLK        ; CLK_REF        ; 8.275 ; 8.482 ; Rise       ; CLK_REF         ;
; DAC_CS         ; CLK_REF        ; 8.869 ; 9.078 ; Rise       ; CLK_REF         ;
; DAC_DOUT       ; CLK_REF        ; 9.342 ; 9.634 ; Rise       ; CLK_REF         ;
; JTAG_NEXUS_TDO ; JTAG_NEXUS_TCK ; 4.331 ; 4.486 ; Rise       ; JTAG_NEXUS_TCK  ;
+----------------+----------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; DAC_CLK        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DAC_CS         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DAC_DOUT       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[16]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_A[17]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_E        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_LB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_OE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_UB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_W        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[16]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_A[17]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_E        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_LB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_OE       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_UB       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_W        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM0_D[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[10]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[11]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[12]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[13]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[14]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SRAM1_D[15]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; SRAM0_D[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM0_D[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SRAM1_D[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK_REF                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TCK          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TMS          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK_BRD                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; TEST_BUTTON             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; JTAG_NEXUS_TDI          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DCLK~           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DAC_CLK        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; DAC_CS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DOUT       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00616 V          ; 0.065 V                              ; 0.016 V                              ; 6.89e-10 s                  ; 6.77e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00616 V         ; 0.065 V                             ; 0.016 V                             ; 6.89e-10 s                 ; 6.77e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.33 V              ; -0.00201 V          ; 0.092 V                              ; 0.05 V                               ; 3.78e-09 s                  ; 3.59e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.33 V             ; -0.00201 V         ; 0.092 V                             ; 0.05 V                              ; 3.78e-09 s                 ; 3.59e-09 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.33 V              ; -0.00205 V          ; 0.092 V                              ; 0.051 V                              ; 3.98e-09 s                  ; 3.76e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.33 V             ; -0.00205 V         ; 0.092 V                             ; 0.051 V                             ; 3.98e-09 s                 ; 3.76e-09 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00616 V          ; 0.065 V                              ; 0.016 V                              ; 6.89e-10 s                  ; 6.77e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00616 V         ; 0.065 V                             ; 0.016 V                             ; 6.89e-10 s                 ; 6.77e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.95e-07 V                   ; 2.34 V              ; -0.00561 V          ; 0.078 V                              ; 0.022 V                              ; 9.09e-10 s                  ; 8.84e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.95e-07 V                  ; 2.34 V             ; -0.00561 V         ; 0.078 V                             ; 0.022 V                             ; 9.09e-10 s                 ; 8.84e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.9e-07 V                    ; 2.35 V              ; -0.00112 V          ; 0.061 V                              ; 0.002 V                              ; 4.84e-10 s                  ; 4.97e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.9e-07 V                   ; 2.35 V             ; -0.00112 V         ; 0.061 V                             ; 0.002 V                             ; 4.84e-10 s                 ; 4.97e-10 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DAC_CLK        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; DAC_CS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; DAC_DOUT       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; JTAG_NEXUS_TDO ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM0_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM0_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.64 V              ; -0.011 V            ; 0.212 V                              ; 0.198 V                              ; 2.38e-09 s                  ; 2.29e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.64 V             ; -0.011 V           ; 0.212 V                             ; 0.198 V                             ; 2.38e-09 s                 ; 2.29e-09 s                 ; No                        ; Yes                       ;
; SRAM1_A[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM1_A[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM1_A[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_A[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[16]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_A[17]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_E        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_LB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_OE       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_UB       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_W        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
; SRAM0_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM0_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM0_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[10]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[11]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
; SRAM1_D[12]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[13]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[14]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
; SRAM1_D[15]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------+
; Setup Transfers                                                             ;
+----------------+----------------+----------+----------+----------+----------+
; From Clock     ; To Clock       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------+----------------+----------+----------+----------+----------+
; CLK_BRD        ; CLK_BRD        ; 1917342  ; 504      ; 5186     ; 0        ;
; CLK_REF        ; CLK_BRD        ; 2        ; 0        ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; CLK_BRD        ; 25682    ; 1        ; 482      ; 0        ;
; CLK_BRD        ; CLK_REF        ; 83135    ; 0        ; 0        ; 0        ;
; CLK_REF        ; CLK_REF        ; 413734   ; 2880     ; 96       ; 0        ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 212840   ; 1        ; 256      ; 0        ;
; CLK_BRD        ; JTAG_NEXUS_TCK ; 95       ; 0        ; 0        ; 0        ;
; CLK_REF        ; JTAG_NEXUS_TCK ; 1        ; 32       ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 16456    ; 2108     ; 100      ; 0        ;
+----------------+----------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------+
; Hold Transfers                                                              ;
+----------------+----------------+----------+----------+----------+----------+
; From Clock     ; To Clock       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------+----------------+----------+----------+----------+----------+
; CLK_BRD        ; CLK_BRD        ; 1917342  ; 504      ; 5186     ; 0        ;
; CLK_REF        ; CLK_BRD        ; 2        ; 0        ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; CLK_BRD        ; 25682    ; 1        ; 482      ; 0        ;
; CLK_BRD        ; CLK_REF        ; 83135    ; 0        ; 0        ; 0        ;
; CLK_REF        ; CLK_REF        ; 413734   ; 2880     ; 96       ; 0        ;
; JTAG_NEXUS_TCK ; CLK_REF        ; 212840   ; 1        ; 256      ; 0        ;
; CLK_BRD        ; JTAG_NEXUS_TCK ; 95       ; 0        ; 0        ; 0        ;
; CLK_REF        ; JTAG_NEXUS_TCK ; 1        ; 32       ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 16456    ; 2108     ; 100      ; 0        ;
+----------------+----------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------+
; Recovery Transfers                                                          ;
+----------------+----------------+----------+----------+----------+----------+
; From Clock     ; To Clock       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------+----------------+----------+----------+----------+----------+
; JTAG_NEXUS_TCK ; CLK_REF        ; 152      ; 0        ; 0        ; 0        ;
; CLK_BRD        ; JTAG_NEXUS_TCK ; 120      ; 0        ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 163      ; 12       ; 0        ; 8        ;
+----------------+----------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------+
; Removal Transfers                                                           ;
+----------------+----------------+----------+----------+----------+----------+
; From Clock     ; To Clock       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------+----------------+----------+----------+----------+----------+
; JTAG_NEXUS_TCK ; CLK_REF        ; 152      ; 0        ; 0        ; 0        ;
; CLK_BRD        ; JTAG_NEXUS_TCK ; 120      ; 0        ; 0        ; 0        ;
; JTAG_NEXUS_TCK ; JTAG_NEXUS_TCK ; 163      ; 12       ; 0        ; 8        ;
+----------------+----------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 35    ; 35   ;
; Unconstrained Input Port Paths  ; 260   ; 260  ;
; Unconstrained Output Ports      ; 82    ; 82   ;
; Unconstrained Output Port Paths ; 3192  ; 3192 ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Fri Feb 05 21:34:54 2016
Info: Command: quartus_sta NOS031 --sdc=NOS031_sta.sdc
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Warning (335093): TimeQuest Timing Analyzer is analyzing 4 combinational loops as latches.
Info (332104): Reading SDC File: 'NOS031_sta.sdc'
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name JTAG_NEXUS_TCK JTAG_NEXUS_TCK
    Info (332105): create_clock -period 1.000 -name CLK_REF CLK_REF
    Info (332105): create_clock -period 1.000 -name CLK_BRD CLK_BRD
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_25_0_component_c9|U2|clkd|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_9_0_component_c8|U2|clkd|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_9_0_component_c8|U2|clkd|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_9_0_component_c8|U1|clkd_cZ|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_9_0_component_c8|U1|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_3_0_component_c5|clkd_cZ|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_3_0_component_c5|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_5_0_component_c4|clkd_cZ|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_5_0_component_c4|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_3_0_component_c3|clkd_cZ|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_3_0_component_c3|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_5_0_component_c2|clkd_cZ|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_5_0_component_c2|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_3_0_component_c1|clkd_cZ|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_3_0_component_c1|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U4|U_FREQ|divisor_5_0_component_c0|clkd_cZ|combout"
    Warning (332126): Node "U4|U_FREQ|divisor_5_0_component_c0|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_25_0_component_c9|U2|clkd|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_25_0_component_c9|U1|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_9_0_component_c8|U2|clkd|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_9_0_component_c8|U2|clkd|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_9_0_component_c8|U1|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_9_0_component_c8|U1|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c5|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c5|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c4|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c4|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c3|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c3|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c2|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c2|clkd_cZ|dataa"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c1|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_3_0_component_c1|clkd_cZ|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c0|clkd_cZ|combout"
    Warning (332126): Node "U3|U_FREQ|divisor_5_0_component_c0|clkd_cZ|datab"
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: U4|U_FREQ|freq_0_cZ  from: datad  to: combout
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -24.053
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -24.053     -3253.348 CLK_REF 
    Info (332119):   -19.081    -19572.457 CLK_BRD 
    Info (332119):    -7.149     -5088.325 JTAG_NEXUS_TCK 
Info (332146): Worst-case hold slack is -14.232
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -14.232      -558.200 CLK_REF 
    Info (332119):     0.343         0.000 JTAG_NEXUS_TCK 
    Info (332119):     0.448         0.000 CLK_BRD 
Info (332146): Worst-case recovery slack is -3.723
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.723      -141.589 JTAG_NEXUS_TCK 
    Info (332119):    -2.530       -83.786 CLK_REF 
Info (332146): Worst-case removal slack is 1.158
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.158         0.000 JTAG_NEXUS_TCK 
    Info (332119):     1.711         0.000 CLK_REF 
Info (332146): Worst-case minimum pulse width slack is -7.914
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.914     -5190.791 CLK_REF 
    Info (332119):    -4.000     -3064.980 CLK_BRD 
    Info (332119):    -3.000     -1946.509 JTAG_NEXUS_TCK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: U4|U_FREQ|freq_0_cZ  from: datad  to: combout
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -22.936
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -22.936     -3074.914 CLK_REF 
    Info (332119):   -18.159    -18224.853 CLK_BRD 
    Info (332119):    -6.681     -4729.865 JTAG_NEXUS_TCK 
Info (332146): Worst-case hold slack is -13.651
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):   -13.651      -598.797 CLK_REF 
    Info (332119):     0.315         0.000 JTAG_NEXUS_TCK 
    Info (332119):     0.399         0.000 CLK_BRD 
Info (332146): Worst-case recovery slack is -3.327
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.327      -124.319 JTAG_NEXUS_TCK 
    Info (332119):    -2.295       -75.306 CLK_REF 
Info (332146): Worst-case removal slack is 1.069
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.069         0.000 JTAG_NEXUS_TCK 
    Info (332119):     1.510         0.000 CLK_REF 
Info (332146): Worst-case minimum pulse width slack is -7.940
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.940     -4881.689 CLK_REF 
    Info (332119):    -4.000     -3064.980 CLK_BRD 
    Info (332119):    -3.000     -1946.509 JTAG_NEXUS_TCK 
Info: Analyzing Fast 1200mV 0C Model
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: U4|U_FREQ|freq_0_cZ  from: datad  to: combout
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -9.796
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -9.796     -1190.685 CLK_REF 
    Info (332119):    -7.114     -7371.741 CLK_BRD 
    Info (332119):    -2.488     -1711.602 JTAG_NEXUS_TCK 
Info (332146): Worst-case hold slack is -5.532
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -5.532      -191.720 CLK_REF 
    Info (332119):     0.079         0.000 JTAG_NEXUS_TCK 
    Info (332119):     0.153         0.000 CLK_BRD 
Info (332146): Worst-case recovery slack is -1.067
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.067       -31.893 JTAG_NEXUS_TCK 
    Info (332119):    -0.593       -17.677 CLK_REF 
Info (332146): Worst-case removal slack is 0.486
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.486         0.000 JTAG_NEXUS_TCK 
    Info (332119):     0.716         0.000 CLK_REF 
Info (332146): Worst-case minimum pulse width slack is -3.601
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.601     -2113.356 CLK_REF 
    Info (332119):    -3.000     -1972.417 CLK_BRD 
    Info (332119):    -3.000     -1382.907 JTAG_NEXUS_TCK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 65 warnings
    Info: Peak virtual memory: 453 megabytes
    Info: Processing ended: Fri Feb 05 21:35:26 2016
    Info: Elapsed time: 00:00:32
    Info: Total CPU time (on all processors): 00:00:17


