Analysis & Synthesis report for URSO180GLUE
Sat Sep 18 23:27:19 2021
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis IP Cores Summary
  9. Parameter Settings for User Entity Instance: lpm_counter0:inst20|lpm_counter:LPM_COUNTER_component
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Sep 18 23:27:19 2021           ;
; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name               ; URSO180GLUE                                     ;
; Top-level Entity Name       ; URSO180GLUE                                     ;
; Family                      ; MAX7000S                                        ;
; Total macrocells            ; 56                                              ;
; Total pins                  ; 62                                              ;
+-----------------------------+-------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Option                                                                     ; Setting         ; Default Value ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Device                                                                     ; EPM7128SLC84-15 ;               ;
; Top-level entity name                                                      ; URSO180GLUE     ; URSO180GLUE   ;
; Family name                                                                ; MAX7000S        ; Cyclone IV GX ;
; Use smart compilation                                                      ; Off             ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On              ; On            ;
; Enable compact report table                                                ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                                        ; Off             ; Off           ;
; Preserve fewer node names                                                  ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                                  ; Off             ; Off           ;
; Verilog Version                                                            ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                               ; VHDL_1993       ; VHDL_1993     ;
; State Machine Processing                                                   ; Auto            ; Auto          ;
; Safe State Machine                                                         ; Off             ; Off           ;
; Extract Verilog State Machines                                             ; On              ; On            ;
; Extract VHDL State Machines                                                ; On              ; On            ;
; Ignore Verilog initial constructs                                          ; Off             ; Off           ;
; Iteration limit for constant Verilog loops                                 ; 5000            ; 5000          ;
; Iteration limit for non-constant Verilog loops                             ; 250             ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On              ; On            ;
; Infer RAMs from Raw Logic                                                  ; On              ; On            ;
; Parallel Synthesis                                                         ; On              ; On            ;
; NOT Gate Push-Back                                                         ; On              ; On            ;
; Power-Up Don't Care                                                        ; On              ; On            ;
; Remove Duplicate Registers                                                 ; On              ; On            ;
; Ignore CARRY Buffers                                                       ; Off             ; Off           ;
; Ignore CASCADE Buffers                                                     ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                                      ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                                  ; Off             ; Off           ;
; Ignore LCELL Buffers                                                       ; Auto            ; Auto          ;
; Ignore SOFT Buffers                                                        ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                                             ; Off             ; Off           ;
; Optimization Technique                                                     ; Speed           ; Speed         ;
; Allow XOR Gate Usage                                                       ; On              ; On            ;
; Auto Logic Cell Insertion                                                  ; On              ; On            ;
; Parallel Expander Chain Length                                             ; 4               ; 4             ;
; Auto Parallel Expanders                                                    ; On              ; On            ;
; Auto Open-Drain Pins                                                       ; On              ; On            ;
; Auto Resource Sharing                                                      ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell                                               ; 100             ; 100           ;
; Use LogicLock Constraints during Resource Balancing                        ; On              ; On            ;
; Ignore translate_off and synthesis_off directives                          ; Off             ; Off           ;
; Report Parameter Settings                                                  ; On              ; On            ;
; Report Source Assignments                                                  ; On              ; On            ;
; Report Connectivity Checks                                                 ; On              ; On            ;
; HDL message level                                                          ; Level2          ; Level2        ;
; Suppress Register Optimization Related Messages                            ; Off             ; Off           ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000            ; 5000          ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000            ; 5000          ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100             ; 100           ;
; Block Design Naming                                                        ; Auto            ; Auto          ;
; Synthesis Effort                                                           ; Auto            ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On              ; On            ;
; Pre-Mapping Resynthesis Optimization                                       ; Off             ; Off           ;
; Analysis & Synthesis Message Level                                         ; Medium          ; Medium        ;
; Disable Register Merging Across Hierarchies                                ; Auto            ; Auto          ;
; Synthesis Seed                                                             ; 1               ; 1             ;
+----------------------------------------------------------------------------+-----------------+---------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                      ;
+--------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path           ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                                  ; Library ;
+--------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------+---------+
; URSO180GLUE.bdf                            ; yes             ; User Block Diagram/Schematic File  ; P:/Projects/PuProjects/URSO180/Hardware/Glue_Logic/URSO180GLUEB128/URSO180GLUE.bdf                            ;         ;
; output_files/output_files/lpm_counter0.vhd ; yes             ; User Wizard-Generated File         ; P:/Projects/PuProjects/URSO180/Hardware/Glue_Logic/URSO180GLUEB128/output_files/output_files/lpm_counter0.vhd ;         ;
; 74138.bdf                                  ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/others/maxplus2/74138.bdf                                                 ;         ;
; lpm_counter.tdf                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf                                             ;         ;
; lpm_constant.inc                           ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc                                            ;         ;
; lpm_decode.inc                             ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc                                              ;         ;
; lpm_add_sub.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc                                             ;         ;
; cmpconst.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cmpconst.inc                                                ;         ;
; lpm_compare.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc                                             ;         ;
; lpm_counter.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc                                             ;         ;
; dffeea.inc                                 ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffeea.inc                                                  ;         ;
; alt_counter_stratix.inc                    ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_counter_stratix.inc                                     ;         ;
; aglobal130.inc                             ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc                                              ;         ;
+--------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 56                   ;
; Total registers      ; 12                   ;
; I/O pins             ; 62                   ;
; Shareable expanders  ; 2                    ;
; Maximum fan-out node ; inst25~8             ;
; Maximum fan-out      ; 8                    ;
; Total fan-out        ; 105                  ;
; Average fan-out      ; 0.88                 ;
+----------------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                               ;
+-------------------------------------------+------------+------+--------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; Macrocells ; Pins ; Full Hierarchy Name                                                ; Library Name ;
+-------------------------------------------+------------+------+--------------------------------------------------------------------+--------------+
; |URSO180GLUE                              ; 56         ; 62   ; |URSO180GLUE                                                       ; work         ;
;    |lpm_counter0:inst20|                  ; 3          ; 0    ; |URSO180GLUE|lpm_counter0:inst20                                   ; work         ;
;       |lpm_counter:LPM_COUNTER_component| ; 3          ; 0    ; |URSO180GLUE|lpm_counter0:inst20|lpm_counter:LPM_COUNTER_component ; work         ;
+-------------------------------------------+------------+------+--------------------------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                            ;
+--------+--------------+---------+--------------+--------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                  ; IP Include File                                                                                               ;
+--------+--------------+---------+--------------+--------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+
; Altera ; LPM_COUNTER  ; 13.0    ; N/A          ; N/A          ; |URSO180GLUE|lpm_counter0:inst20 ; P:/Projects/PuProjects/URSO180/Hardware/Glue_Logic/URSO180GLUEB128/output_files/output_files/lpm_counter0.vhd ;
+--------+--------------+---------+--------------+--------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter0:inst20|lpm_counter:LPM_COUNTER_component ;
+------------------------+-------------+-------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                        ;
+------------------------+-------------+-------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                              ;
; LPM_WIDTH              ; 3           ; Signed Integer                                              ;
; LPM_DIRECTION          ; UP          ; Untyped                                                     ;
; LPM_MODULUS            ; 0           ; Untyped                                                     ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                                     ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                                     ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                     ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                                                     ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                     ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                          ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                          ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                                     ;
; LABWIDE_SCLR           ; ON          ; Untyped                                                     ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                                     ;
; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                     ;
+------------------------+-------------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Sep 18 23:27:11 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off URSO180GLUEB128 -c URSO180GLUE
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file urso180glue.bdf
    Info (12023): Found entity 1: URSO180GLUE
Info (12021): Found 2 design units, including 1 entities, in source file rsdecoder.vhd
    Info (12022): Found design unit 1: rsdecoder-SYN
    Info (12023): Found entity 1: rsdecoder
Info (12021): Found 2 design units, including 1 entities, in source file rrsdecoder.vhd
    Info (12022): Found design unit 1: rrsdecoder-SYN
    Info (12023): Found entity 1: rrsdecoder
Info (12021): Found 1 design units, including 1 entities, in source file dreg8.bdf
    Info (12023): Found entity 1: dreg8
Info (12021): Found 1 design units, including 1 entities, in source file tribuf8.bdf
    Info (12023): Found entity 1: tribuf8
Info (12021): Found 2 design units, including 1 entities, in source file output_files/output_files/lpm_counter0.vhd
    Info (12022): Found design unit 1: lpm_counter0-SYN
    Info (12023): Found entity 1: lpm_counter0
Info (12127): Elaborating entity "URSO180GLUE" for the top level hierarchy
Warning (275011): Block or symbol "VCC" of instance "inst35" overlaps another block or symbol
Warning (275043): Pin "WDI" is missing source
Warning (275009): Pin "nDRE" not connected
Warning (275009): Pin "nDWE" not connected
Warning (275009): Pin "nBUSACK" not connected
Warning (275009): Pin "nHALT" not connected
Warning (275009): Pin "nLIR" not connected
Warning (275009): Pin "ST" not connected
Warning (275008): Primitive "OR2" of instance "inst24" not used
Warning (275008): Primitive "VCC" of instance "inst34" not used
Warning (275008): Primitive "VCC" of instance "inst35" not used
Info (12128): Elaborating entity "74138" for hierarchy "74138:inst12"
Info (12130): Elaborated megafunction instantiation "74138:inst12"
Info (12128): Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst20"
Info (12128): Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst20|lpm_counter:LPM_COUNTER_component"
Info (12130): Elaborated megafunction instantiation "lpm_counter0:inst20|lpm_counter:LPM_COUNTER_component"
Info (12133): Instantiated megafunction "lpm_counter0:inst20|lpm_counter:LPM_COUNTER_component" with the following parameter:
    Info (12134): Parameter "lpm_direction" = "UP"
    Info (12134): Parameter "lpm_port_updown" = "PORT_UNUSED"
    Info (12134): Parameter "lpm_type" = "LPM_COUNTER"
    Info (12134): Parameter "lpm_width" = "3"
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "DD[7]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "DD[6]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "DD[5]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "DD[4]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "DD[3]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "DD[2]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "DD[1]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "DD[0]" and its non-tri-state driver.
Warning (13039): The following bidir pins have no drivers
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "nME" has no driver
    Warning (13040): Bidir "nWR" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "A" has no driver
    Warning (13040): Bidir "nIOE" has no driver
    Warning (13040): Bidir "D" has no driver
    Warning (13040): Bidir "D" has no driver
    Warning (13040): Bidir "D" has no driver
    Warning (13040): Bidir "D" has no driver
    Warning (13040): Bidir "D" has no driver
    Warning (13040): Bidir "D" has no driver
    Warning (13040): Bidir "D" has no driver
    Warning (13040): Bidir "D" has no driver
    Warning (13040): Bidir "nRD" has no driver
    Warning (13040): Bidir "DRS" has no driver
    Warning (13040): Bidir "DRS" has no driver
    Warning (13040): Bidir "DRS" has no driver
    Warning (13040): Bidir "DRS" has no driver
    Warning (13040): Bidir "DRS" has no driver
Warning (13032): The following tri-state nodes are fed by constants
    Warning (13033): The pin "nWAIT" is fed by VCC
Info (13060): One or more bidirs are fed by always enabled tri-state buffers
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "nWAIT" is moved to its source
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "nWAIT~synth"
    Warning (13010): Node "DD~synth"
    Warning (13010): Node "DD~synth"
    Warning (13010): Node "DD~synth"
    Warning (13010): Node "DD~synth"
    Warning (13010): Node "DD~synth"
    Warning (13010): Node "DD~synth"
    Warning (13010): Node "DD~synth"
    Warning (13010): Node "DD~synth"
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "nBUSREQ" is stuck at VCC
    Warning (13410): Pin "nINT0" is stuck at VCC
    Warning (13410): Pin "WDI" is stuck at GND
Info (280013): Promoted pin-driven signal(s) to global signal
    Info (280015): Promoted clear signal driven by pin "nRESET" to global clear signal
    Info (280014): Promoted clock signal driven by pin "phi" to global clock signal
Warning (21074): Design contains 6 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "nDRE"
    Warning (15610): No output dependent on input pin "nDWE"
    Warning (15610): No output dependent on input pin "nBUSACK"
    Warning (15610): No output dependent on input pin "nHALT"
    Warning (15610): No output dependent on input pin "nLIR"
    Warning (15610): No output dependent on input pin "ST"
Info (21057): Implemented 120 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 8 input pins
    Info (21059): Implemented 8 output pins
    Info (21060): Implemented 46 bidirectional pins
    Info (21063): Implemented 56 macrocells
    Info (21073): Implemented 2 shareable expanders
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 82 warnings
    Info: Peak virtual memory: 4619 megabytes
    Info: Processing ended: Sat Sep 18 23:27:20 2021
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:02


