Synthesis Messages

Report Title	GowinSynthesis Report
Design File	D:\File\Micky\Github\T-FPGA\example\FPGA\i2c-slave\i2c-slave\src\i2c_slave.v D:\File\Micky\Github\T-FPGA\example\FPGA\i2c-slave\i2c-slave\src\led.v D:\File\Micky\Github\T-FPGA\example\FPGA\i2c-slave\i2c-slave\src\i2c.v
GowinSynthesis Constraints File	---
Version	GowinSynthesis V1.9.8.01
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Wed Feb 22 16:34:08 2023
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	i2c
Synthesis Process	Running parser:     CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 216.680MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 216.680MB     Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 216.680MB     Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 216.680MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 216.680MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 216.680MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 216.680MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 216.680MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 216.680MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 216.680MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 216.680MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 216.680MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 216.680MB Generate output files:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 216.680MB
Total Time and Memory Usage	CPU time = 0h 0m 0.326s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 216.680MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	4
I/O Buf	3
IBUF	1
OBUF	1
IOBUF	1
Register	19
DFF	1
DFFNE	8
DFFNP	3
DFFNPE	1
DFFNC	1
DFFNCE	4
DL	1
LUT	31
LUT2	6
LUT3	8
LUT4	17
INV	3
INV	3

Resource Utilization Summary

Resource	Usage	Utilization
Logic	34(34 LUTs, 0 ALUs) / 4608	1%
Register	19 / 3570	1%
--Register as Latch	1 / 3570	1%
--Register as FF	18 / 3570	1%
BSRAM	0 / 10	0%

Timing

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
iic_scl	Base	20.000	50.0	0.000	10.000			iic_scl_ibuf/I
n5_8	Base	20.000	50.0	0.000	10.000			slave/n5_s2/F

Max Frequency Summary:

No.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	iic_scl	50.0(MHz)	159.6(MHz)	3	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	6.867
Data Arrival Time	4.554
Data Required Time	11.421
From	slave/iic_sdar_s0
To	slave/adr_match_s1
Launch Clk	iic_scl[F]
Latch Clk	iic_scl[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				iic_scl
0.000	0.000	tCL	RR	1	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	iic_scl_ibuf/O
1.345	0.363	tNET	RR	1	slave/iic_sdar_s0/CLK
1.803	0.458	tC2Q	RF	11	slave/iic_sdar_s0/Q
2.283	0.480	tNET	FF	1	slave/n198_s1/I3
2.909	0.626	tINS	FF	1	slave/n198_s1/F
3.389	0.480	tNET	FF	1	slave/n198_s0/I2
4.191	0.802	tINS	FR	1	slave/n198_s0/F
4.554	0.363	tNET	RR	1	slave/adr_match_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				iic_scl
10.000	0.000	tCL	FF	1	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	iic_scl_ibuf/O
11.464	0.480	tNET	FF	1	slave/adr_match_s1/CLK
11.421	-0.043	tSu		1	slave/adr_match_s1

Path Statistics:

Clock Skew:	0.120
Setup Relationship:	10.000
Logic Level:	3
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 1.428, 44.495%; route: 1.323, 41.224%; tC2Q: 0.458, 14.281%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:

Slack	16.015
Data Arrival Time	15.406
Data Required Time	31.421
From	slave/op_read_s1
To	slave/mem_0_s1
Launch Clk	iic_scl[F]
Latch Clk	iic_scl[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				iic_scl
10.000	0.000	tCL	FF	1	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	iic_scl_ibuf/O
11.464	0.480	tNET	FF	1	slave/op_read_s1/CLK
11.923	0.458	tC2Q	FF	2	slave/op_read_s1/Q
12.403	0.480	tNET	FF	1	slave/n223_s2/I1
13.502	1.099	tINS	FF	8	slave/n223_s2/F
13.982	0.480	tNET	FF	1	slave/n223_s4/I1
15.043	1.061	tINS	FR	1	slave/n223_s4/F
15.406	0.363	tNET	RR	1	slave/mem_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
30.000	0.000				iic_scl
30.000	0.000	tCL	FF	1	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	iic_scl_ibuf/O
31.464	0.480	tNET	FF	1	slave/mem_0_s1/CLK
31.421	-0.043	tSu		1	slave/mem_0_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	3
Arrival Clock Path Delay:	cell: 0.984, 67.222%; route: 0.480, 32.778%
Arrival Data Path Delay:	cell: 2.160, 54.804%; route: 1.323, 33.567%; tC2Q: 0.458, 11.629%
Required Clock Path Delay:	cell: 0.984, 67.222%; route: 0.480, 32.778%

Path 3

Path Summary:

Slack	16.015
Data Arrival Time	15.406
Data Required Time	31.421
From	slave/op_read_s1
To	slave/mem_4_s1
Launch Clk	iic_scl[F]
Latch Clk	iic_scl[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				iic_scl
10.000	0.000	tCL	FF	1	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	iic_scl_ibuf/O
11.464	0.480	tNET	FF	1	slave/op_read_s1/CLK
11.923	0.458	tC2Q	FF	2	slave/op_read_s1/Q
12.403	0.480	tNET	FF	1	slave/n223_s2/I1
13.502	1.099	tINS	FF	8	slave/n223_s2/F
13.982	0.480	tNET	FF	1	slave/n215_s2/I1
15.043	1.061	tINS	FR	1	slave/n215_s2/F
15.406	0.363	tNET	RR	1	slave/mem_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
30.000	0.000				iic_scl
30.000	0.000	tCL	FF	1	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	iic_scl_ibuf/O
31.464	0.480	tNET	FF	1	slave/mem_4_s1/CLK
31.421	-0.043	tSu		1	slave/mem_4_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	3
Arrival Clock Path Delay:	cell: 0.984, 67.222%; route: 0.480, 32.778%
Arrival Data Path Delay:	cell: 2.160, 54.804%; route: 1.323, 33.567%; tC2Q: 0.458, 11.629%
Required Clock Path Delay:	cell: 0.984, 67.222%; route: 0.480, 32.778%

Path 4

Path Summary:

Slack	16.274
Data Arrival Time	15.147
Data Required Time	31.421
From	slave/op_read_s1
To	slave/mem_1_s1
Launch Clk	iic_scl[F]
Latch Clk	iic_scl[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				iic_scl
10.000	0.000	tCL	FF	1	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	iic_scl_ibuf/O
11.464	0.480	tNET	FF	1	slave/op_read_s1/CLK
11.923	0.458	tC2Q	FF	2	slave/op_read_s1/Q
12.403	0.480	tNET	FF	1	slave/n223_s2/I1
13.502	1.099	tINS	FF	8	slave/n223_s2/F
13.982	0.480	tNET	FF	1	slave/n221_s0/I2
14.784	0.802	tINS	FR	1	slave/n221_s0/F
15.147	0.363	tNET	RR	1	slave/mem_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
30.000	0.000				iic_scl
30.000	0.000	tCL	FF	1	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	iic_scl_ibuf/O
31.464	0.480	tNET	FF	1	slave/mem_1_s1/CLK
31.421	-0.043	tSu		1	slave/mem_1_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	3
Arrival Clock Path Delay:	cell: 0.984, 67.222%; route: 0.480, 32.778%
Arrival Data Path Delay:	cell: 1.901, 51.625%; route: 1.323, 35.928%; tC2Q: 0.458, 12.447%
Required Clock Path Delay:	cell: 0.984, 67.222%; route: 0.480, 32.778%

Path 5

Path Summary:

Slack	16.274
Data Arrival Time	15.147
Data Required Time	31.421
From	slave/op_read_s1
To	slave/mem_2_s1
Launch Clk	iic_scl[F]
Latch Clk	iic_scl[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				iic_scl
10.000	0.000	tCL	FF	1	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	iic_scl_ibuf/O
11.464	0.480	tNET	FF	1	slave/op_read_s1/CLK
11.923	0.458	tC2Q	FF	2	slave/op_read_s1/Q
12.403	0.480	tNET	FF	1	slave/n223_s2/I1
13.502	1.099	tINS	FF	8	slave/n223_s2/F
13.982	0.480	tNET	FF	1	slave/n219_s0/I2
14.784	0.802	tINS	FR	1	slave/n219_s0/F
15.147	0.363	tNET	RR	1	slave/mem_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
30.000	0.000				iic_scl
30.000	0.000	tCL	FF	1	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	iic_scl_ibuf/O
31.464	0.480	tNET	FF	1	slave/mem_2_s1/CLK
31.421	-0.043	tSu		1	slave/mem_2_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	3
Arrival Clock Path Delay:	cell: 0.984, 67.222%; route: 0.480, 32.778%
Arrival Data Path Delay:	cell: 1.901, 51.625%; route: 1.323, 35.928%; tC2Q: 0.458, 12.447%
Required Clock Path Delay:	cell: 0.984, 67.222%; route: 0.480, 32.778%