//Copyright (C)2014-2021 Gowin Semiconductor Corporation. //All rights reserved. 1. PnR Messages : PnR Report : D:\Users\19021\Documents\fpga_project\impl\gwsynthesis\fpga_project.vg : D:\Users\19021\Documents\fpga_project\src\fpga_project.cst : --- : V1.9.8.01 : GW1NSR-LV4CQN48PC6/I5 : GW1NSR-4C :Tue Feb 21 14:47:52 2023 2. PnR Details Running placement: Placement Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Placement Phase 1: CPU time = 0h 0m 0.056s, Elapsed time = 0h 0m 0.055s Placement Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Placement Phase 3: CPU time = 0h 0m 0.748s, Elapsed time = 0h 0m 0.749s Total Placement: CPU time = 0h 0m 0.805s, Elapsed time = 0h 0m 0.805s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.029s, Elapsed time = 0h 0m 0.027s Routing Phase 2: CPU time = 0h 0m 0.013s, Elapsed time = 0h 0m 0.014s Total Routing: CPU time = 0h 0m 0.042s, Elapsed time = 0h 0m 0.041s Generate output files: CPU time = 0h 0m 0.466s, Elapsed time = 0h 0m 0.466s Total Time and Memory Usage: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 146MB 3. Resource Usage Summary ---------------------------------------------------------- Resources | Usage ---------------------------------------------------------- Logic | 1/4608 1% --LUT,ALU,ROM16 | 1(1 LUT, 0 ALU, 0 ROM16) --SSRAM(RAM16) | 0 Register | 1/3570 1% --Logic Register as Latch | 0/3456 0% --Logic Register as FF | 1/3456 1% --I/O Register as Latch | 0/114 0% --I/O Register as FF | 0/114 0% CLS | 1/2304 1% I/O Port | 2 I/O Buf | 2 --Input Buf | 1 --Output Buf | 1 --Inout Buf | 0 IOLOGIC | 0% BSRAM | 0% DSP | 0% PLL | 0/2 0% DCS | 0/4 0% DQCE | 0/12 0% OSC | 0/1 0% CLKDIV | 0/6 0% DLLDLY | 0/6 0% DHCEN | 0/12 0% ========================================================== 4. I/O Bank Usage Summary ----------------------- I/O Bank | Usage ----------------------- bank 0 | 0/10(0%) bank 1 | 1/10(10%) bank 2 | 0/9(0%) bank 3 | 1/24(4%) ======================= 5. Global Clock Usage Summary ------------------------------- Global Clock | Usage ------------------------------- PRIMARY | 1/8(12%) SECONDARY | 0/8(0%) GCLK_PIN | 0/5(0%) PLL | 0/2(0%) CLKDIV | 0/6(0%) DLLDLY | 0/6(0%) =============================== 6. Global Clock Signals ------------------------------------------- Signal | Global Clock | Location ------------------------------------------- clk_d | PRIMARY | RIGHT =========================================== 7. Pinout by Port Name ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Slew Rate | Vref | Single Resistor | Diff Resistor | BankVccio ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ clk | | 46/1 | Y | in | IOT13[B] | LVCMOS33 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 led | | 15/3 | Y | out | IOB5[A] | LVCMOS33 | 8 | NONE | NA | NA | OFF | FAST | NA | NA | NA | 3.3 ================================================================================================================================================================================================================== 8. All Package Pins ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Slew Rate | Vref | Single Resistor | Diff Resistor | Bank Vccio ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ 3/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 4/0 | - | out | IOT2[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | FAST | NA | NA | NA | - 6/0 | - | in | IOT3[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 7/0 | - | in | IOT3[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 8/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 9/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 10/0 | - | in | IOT7[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 1/0 | - | in | IOT10[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 2/0 | - | in | IOT10[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 48/1 | - | in | IOT11[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 47/1 | - | in | IOT11[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 45/1 | - | in | IOT13[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 46/1 | clk | in | IOT13[B] | LVCMOS33 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 43/1 | - | in | IOT17[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 44/1 | - | in | IOT17[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 41/1 | - | in | IOT20[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 42/1 | - | in | IOT20[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 39/1 | - | in | IOT26[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 40/1 | - | in | IOT26[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 1.2 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ 13/3 | - | in | IOB4[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 14/3 | - | in | IOB4[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 15/3 | led | out | IOB5[A] | LVCMOS33 | 8 | NONE | NA | NA | OFF | FAST | NA | NA | NA | 3.3 16/3 | - | in | IOB6[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 17/3 | - | in | IOB6[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 18/3 | - | in | IOB13[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 19/3 | - | in | IOB13[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 20/3 | - | in | IOB16[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 21/3 | - | in | IOB16[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 22/3 | - | in | IOB22[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 23/3 | - | in | IOB22[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | 3.3 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ 35/2 | - | in | IOR2[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 34/2 | - | in | IOR2[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 33/2 | - | in | IOR9[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 32/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 31/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 30/2 | - | in | IOR15[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 29/2 | - | in | IOR15[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 28/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - 27/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | NA | NONE | NA | NA | NA | NA | NA | - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ====================================================================================================================================================================================