DE0-Nano-SoC-HDMI Board Configuration



Pin Assignments:




Pin Assignment Table:



ADC
Name Location Direction Standard
ADC_CONVST U9 output 3.3-V LVTTL
ADC_SCK V10 output 3.3-V LVTTL
ADC_SDI AC4 output 3.3-V LVTTL
ADC_SDO AD4 input 3.3-V LVTTL



ARDUINO
Name Location Direction Standard
ARDUINO_IO[0] AG13 inout 3.3-V LVTTL
ARDUINO_IO[1] AF13 inout 3.3-V LVTTL
ARDUINO_IO[2] AG10 inout 3.3-V LVTTL
ARDUINO_IO[3] AG9 inout 3.3-V LVTTL
ARDUINO_IO[4] U14 inout 3.3-V LVTTL
ARDUINO_IO[5] U13 inout 3.3-V LVTTL
ARDUINO_IO[6] AG8 inout 3.3-V LVTTL
ARDUINO_IO[7] AH8 inout 3.3-V LVTTL
ARDUINO_IO[8] AF17 inout 3.3-V LVTTL
ARDUINO_IO[9] AE15 inout 3.3-V LVTTL
ARDUINO_IO[10] AF15 inout 3.3-V LVTTL
ARDUINO_IO[11] AG16 inout 3.3-V LVTTL
ARDUINO_IO[12] AH11 inout 3.3-V LVTTL
ARDUINO_IO[13] AH12 inout 3.3-V LVTTL
ARDUINO_IO[14] AH9 inout 3.3-V LVTTL
ARDUINO_IO[15] AG11 inout 3.3-V LVTTL
ARDUINO_RESET_N AH7 inout 3.3-V LVTTL



CLOCK
Name Location Direction Standard
FPGA_CLK1_50 V11 input 3.3-V LVTTL
FPGA_CLK2_50 Y13 input 3.3-V LVTTL
FPGA_CLK3_50 E11 input 3.3-V LVTTL



HDMI
Name Location Direction Standard
HDMI_I2C_SCL U10 inout 3.3-V LVTTL
HDMI_I2C_SDA AA4 inout 3.3-V LVTTL
HDMI_I2S T13 inout 3.3-V LVTTL
HDMI_LRCLK T11 inout 3.3-V LVTTL
HDMI_MCLK U11 inout 3.3-V LVTTL
HDMI_SCLK T12 inout 3.3-V LVTTL
HDMI_TX_CLK AG5 output 3.3-V LVTTL
HDMI_TX_DE AD19 output 3.3-V LVTTL
HDMI_TX_D[0] AD12 output 3.3-V LVTTL
HDMI_TX_D[1] AE12 output 3.3-V LVTTL
HDMI_TX_D[2] W8 output 3.3-V LVTTL
HDMI_TX_D[3] Y8 output 3.3-V LVTTL
HDMI_TX_D[4] AD11 output 3.3-V LVTTL
HDMI_TX_D[5] AD10 output 3.3-V LVTTL
HDMI_TX_D[6] AE11 output 3.3-V LVTTL
HDMI_TX_D[7] Y5 output 3.3-V LVTTL
HDMI_TX_D[8] AF10 output 3.3-V LVTTL
HDMI_TX_D[9] Y4 output 3.3-V LVTTL
HDMI_TX_D[10] AE9 output 3.3-V LVTTL
HDMI_TX_D[11] AB4 output 3.3-V LVTTL
HDMI_TX_D[12] AE7 output 3.3-V LVTTL
HDMI_TX_D[13] AF6 output 3.3-V LVTTL
HDMI_TX_D[14] AF8 output 3.3-V LVTTL
HDMI_TX_D[15] AF5 output 3.3-V LVTTL
HDMI_TX_D[16] AE4 output 3.3-V LVTTL
HDMI_TX_D[17] AH2 output 3.3-V LVTTL
HDMI_TX_D[18] AH4 output 3.3-V LVTTL
HDMI_TX_D[19] AH5 output 3.3-V LVTTL
HDMI_TX_D[20] AH6 output 3.3-V LVTTL
HDMI_TX_D[21] AG6 output 3.3-V LVTTL
HDMI_TX_D[22] AF9 output 3.3-V LVTTL
HDMI_TX_D[23] AE8 output 3.3-V LVTTL
HDMI_TX_HS T8 output 3.3-V LVTTL
HDMI_TX_INT AF11 input 3.3-V LVTTL
HDMI_TX_VS V13 output 3.3-V LVTTL



HPS
Name Location Direction Standard
HPS_CONV_USB_N inout 3.3-V LVTTL
HPS_DDR3_ADDR[0] output SSTL-15 Class I
HPS_DDR3_ADDR[1] output SSTL-15 Class I
HPS_DDR3_ADDR[2] output SSTL-15 Class I
HPS_DDR3_ADDR[3] output SSTL-15 Class I
HPS_DDR3_ADDR[4] output SSTL-15 Class I
HPS_DDR3_ADDR[5] output SSTL-15 Class I
HPS_DDR3_ADDR[6] output SSTL-15 Class I
HPS_DDR3_ADDR[7] output SSTL-15 Class I
HPS_DDR3_ADDR[8] output SSTL-15 Class I
HPS_DDR3_ADDR[9] output SSTL-15 Class I
HPS_DDR3_ADDR[10] output SSTL-15 Class I
HPS_DDR3_ADDR[11] output SSTL-15 Class I
HPS_DDR3_ADDR[12] output SSTL-15 Class I
HPS_DDR3_ADDR[13] output SSTL-15 Class I
HPS_DDR3_ADDR[14] output SSTL-15 Class I
HPS_DDR3_BA[0] output SSTL-15 Class I
HPS_DDR3_BA[1] output SSTL-15 Class I
HPS_DDR3_BA[2] output SSTL-15 Class I
HPS_DDR3_CAS_N output SSTL-15 Class I
HPS_DDR3_CKE output SSTL-15 Class I
HPS_DDR3_CK_N output Differential 1.5-V SSTL Class I
HPS_DDR3_CK_P output Differential 1.5-V SSTL Class I
HPS_DDR3_CS_N output SSTL-15 Class I
HPS_DDR3_DM[0] output SSTL-15 Class I
HPS_DDR3_DM[1] output SSTL-15 Class I
HPS_DDR3_DM[2] output SSTL-15 Class I
HPS_DDR3_DM[3] output SSTL-15 Class I
HPS_DDR3_DQ[0] inout SSTL-15 Class I
HPS_DDR3_DQ[1] inout SSTL-15 Class I
HPS_DDR3_DQ[2] inout SSTL-15 Class I
HPS_DDR3_DQ[3] inout SSTL-15 Class I
HPS_DDR3_DQ[4] inout SSTL-15 Class I
HPS_DDR3_DQ[5] inout SSTL-15 Class I
HPS_DDR3_DQ[6] inout SSTL-15 Class I
HPS_DDR3_DQ[7] inout SSTL-15 Class I
HPS_DDR3_DQ[8] inout SSTL-15 Class I
HPS_DDR3_DQ[9] inout SSTL-15 Class I
HPS_DDR3_DQ[10] inout SSTL-15 Class I
HPS_DDR3_DQ[11] inout SSTL-15 Class I
HPS_DDR3_DQ[12] inout SSTL-15 Class I
HPS_DDR3_DQ[13] inout SSTL-15 Class I
HPS_DDR3_DQ[14] inout SSTL-15 Class I
HPS_DDR3_DQ[15] inout SSTL-15 Class I
HPS_DDR3_DQ[16] inout SSTL-15 Class I
HPS_DDR3_DQ[17] inout SSTL-15 Class I
HPS_DDR3_DQ[18] inout SSTL-15 Class I
HPS_DDR3_DQ[19] inout SSTL-15 Class I
HPS_DDR3_DQ[20] inout SSTL-15 Class I
HPS_DDR3_DQ[21] inout SSTL-15 Class I
HPS_DDR3_DQ[22] inout SSTL-15 Class I
HPS_DDR3_DQ[23] inout SSTL-15 Class I
HPS_DDR3_DQ[24] inout SSTL-15 Class I
HPS_DDR3_DQ[25] inout SSTL-15 Class I
HPS_DDR3_DQ[26] inout SSTL-15 Class I
HPS_DDR3_DQ[27] inout SSTL-15 Class I
HPS_DDR3_DQ[28] inout SSTL-15 Class I
HPS_DDR3_DQ[29] inout SSTL-15 Class I
HPS_DDR3_DQ[30] inout SSTL-15 Class I
HPS_DDR3_DQ[31] inout SSTL-15 Class I
HPS_DDR3_DQS_N[0] inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[1] inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[2] inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[3] inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[0] inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[1] inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[2] inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[3] inout Differential 1.5-V SSTL Class I
HPS_DDR3_ODT output SSTL-15 Class I
HPS_DDR3_RAS_N output SSTL-15 Class I
HPS_DDR3_RESET_N output SSTL-15 Class I
HPS_DDR3_RZQ input 1.5 V
HPS_DDR3_WE_N output SSTL-15 Class I
HPS_ENET_GTX_CLK output 3.3-V LVTTL
HPS_ENET_INT_N inout 3.3-V LVTTL
HPS_ENET_MDC output 3.3-V LVTTL
HPS_ENET_MDIO inout 3.3-V LVTTL
HPS_ENET_RX_CLK input 3.3-V LVTTL
HPS_ENET_RX_DATA[0] input 3.3-V LVTTL
HPS_ENET_RX_DATA[1] input 3.3-V LVTTL
HPS_ENET_RX_DATA[2] input 3.3-V LVTTL
HPS_ENET_RX_DATA[3] input 3.3-V LVTTL
HPS_ENET_RX_DV input 3.3-V LVTTL
HPS_ENET_TX_DATA[0] output 3.3-V LVTTL
HPS_ENET_TX_DATA[1] output 3.3-V LVTTL
HPS_ENET_TX_DATA[2] output 3.3-V LVTTL
HPS_ENET_TX_DATA[3] output 3.3-V LVTTL
HPS_ENET_TX_EN output 3.3-V LVTTL
HPS_GSENSOR_INT inout 3.3-V LVTTL
HPS_I2C0_SCLK inout 3.3-V LVTTL
HPS_I2C0_SDAT inout 3.3-V LVTTL
HPS_I2C1_SCLK inout 3.3-V LVTTL
HPS_I2C1_SDAT inout 3.3-V LVTTL
HPS_KEY inout 3.3-V LVTTL
HPS_LED inout 3.3-V LVTTL
HPS_LTC_GPIO inout 3.3-V LVTTL
HPS_SD_CLK output 3.3-V LVTTL
HPS_SD_CMD inout 3.3-V LVTTL
HPS_SD_DATA[0] inout 3.3-V LVTTL
HPS_SD_DATA[1] inout 3.3-V LVTTL
HPS_SD_DATA[2] inout 3.3-V LVTTL
HPS_SD_DATA[3] inout 3.3-V LVTTL
HPS_SPIM_CLK output 3.3-V LVTTL
HPS_SPIM_MISO input 3.3-V LVTTL
HPS_SPIM_MOSI output 3.3-V LVTTL
HPS_SPIM_SS inout 3.3-V LVTTL
HPS_UART_RX input 3.3-V LVTTL
HPS_UART_TX output 3.3-V LVTTL
HPS_USB_CLKOUT input 3.3-V LVTTL
HPS_USB_DATA[0] inout 3.3-V LVTTL
HPS_USB_DATA[1] inout 3.3-V LVTTL
HPS_USB_DATA[2] inout 3.3-V LVTTL
HPS_USB_DATA[3] inout 3.3-V LVTTL
HPS_USB_DATA[4] inout 3.3-V LVTTL
HPS_USB_DATA[5] inout 3.3-V LVTTL
HPS_USB_DATA[6] inout 3.3-V LVTTL
HPS_USB_DATA[7] inout 3.3-V LVTTL
HPS_USB_DIR input 3.3-V LVTTL
HPS_USB_NXT input 3.3-V LVTTL
HPS_USB_STP output 3.3-V LVTTL



KEY
Name Location Direction Standard
KEY[0] AH17 input 3.3-V LVTTL
KEY[1] AH16 input 3.3-V LVTTL



LED
Name Location Direction Standard
LED[0] W15 output 3.3-V LVTTL
LED[1] AA24 output 3.3-V LVTTL
LED[2] V16 output 3.3-V LVTTL
LED[3] V15 output 3.3-V LVTTL
LED[4] AF26 output 3.3-V LVTTL
LED[5] AE26 output 3.3-V LVTTL
LED[6] Y16 output 3.3-V LVTTL
LED[7] AA23 output 3.3-V LVTTL



SW
Name Location Direction Standard
SW[0] Y24 input 3.3-V LVTTL
SW[1] W24 input 3.3-V LVTTL
SW[2] W21 input 3.3-V LVTTL
SW[3] W20 input 3.3-V LVTTL



GPIO connect to D8M-GPIO
Name Location Direction Standard GPIO Pin Index
CAMERA_I2C_SCL AA18 inout 3.3-V LVTTL 31
CAMERA_I2C_SDA W14 inout 3.3-V LVTTL 32
CAMERA_PWDN_n W11 output 3.3-V LVTTL 28
MIPI_CS_n AB23 output 3.3-V LVTTL 26
MIPI_I2C_SCL AB25 inout 3.3-V LVTTL 35
MIPI_I2C_SDA AB26 inout 3.3-V LVTTL 36
MIPI_MCLK Y18 output 3.3-V LVTTL 33
MIPI_PIXEL_CLK V12 input 3.3-V LVTTL 1
MIPI_PIXEL_D[0] D11 input 3.3-V LVTTL 4
MIPI_PIXEL_D[1] D8 input 3.3-V LVTTL 5
MIPI_PIXEL_D[2] AH13 input 3.3-V LVTTL 6
MIPI_PIXEL_D[3] AF7 input 3.3-V LVTTL 7
MIPI_PIXEL_D[4] AH14 input 3.3-V LVTTL 8
MIPI_PIXEL_D[5] AF4 input 3.3-V LVTTL 9
MIPI_PIXEL_D[6] AH3 input 3.3-V LVTTL 10
MIPI_PIXEL_D[7] AD5 input 3.3-V LVTTL 13
MIPI_PIXEL_D[8] AG14 input 3.3-V LVTTL 14
MIPI_PIXEL_D[9] AE23 input 3.3-V LVTTL 15
MIPI_PIXEL_HS Y19 input 3.3-V LVTTL 25
MIPI_PIXEL_VS AC23 input 3.3-V LVTTL 23
MIPI_REFCLK C12 output 3.3-V LVTTL 21
MIPI_RESET_n AA19 output 3.3-V LVTTL 27