(kicad_pcb (version 3) (host pcbnew "(2013-07-07 BZR 4022)-stable")
  (general
    (links 1859)
    (no_connects 0)
    (area 100.317583 -154.030635 377.483585 264.26414)
    (thickness 1.6002)
    (drawings 507)
    (tracks 15516)
    (zones 0)
    (modules 550)
    (nets 480)
  )
  (page A3)
  (layers
    (15 TOP signal)
    (8 GND1 power)
    (7 SIGNAL1-X signal)
    (6 SIGNAL2-Y signal)
    (5 GND2 power)
    (4 SIGNAL3-X signal)
    (3 SIGNAL4-Y signal)
    (2 GND3 power)
    (1 PWR power)
    (0 BOTTOM signal)
    (16 B.Adhes user)
    (17 F.Adhes user hide)
    (18 B.Paste user)
    (19 F.Paste user)
    (20 B.SilkS user)
    (21 F.SilkS user)
    (22 B.Mask user)
    (23 F.Mask user)
    (24 Dwgs.User user)
    (25 Cmts.User user hide)
    (26 Eco1.User user)
    (27 Eco2.User user)
    (28 Edge.Cuts user)
  )
  (setup
    (last_trace_width 0.127)
    (user_trace_width 0.127)
    (user_trace_width 0.2032)
    (user_trace_width 0.2286)
    (user_trace_width 0.254)
    (user_trace_width 0.3048)
    (user_trace_width 0.4064)
    (user_trace_width 0.5334)
    (user_trace_width 0.6096)
    (user_trace_width 0.762)
    (user_trace_width 0.9144)
    (user_trace_width 1.778)
    (trace_clearance 0.10414)
    (zone_clearance 0.127)
    (zone_45_only no)
    (trace_min 0.127)
    (segment_width 0.1)
    (edge_width 0.381)
    (via_size 0.80772)
    (via_drill 0.254)
    (via_min_size 0.4572)
    (via_min_drill 0.254)
    (user_via 0.4572 0.254)
    (user_via 0.5588 0.3048)
    (uvia_size 0.508)
    (uvia_drill 0.127)
    (uvias_allowed no)
    (uvia_min_size 0.508)
    (uvia_min_drill 0.127)
    (pcb_text_width 0.3048)
    (pcb_text_size 1.524 2.032)
    (mod_edge_width 0.381)
    (mod_text_size 1.524 1.524)
    (mod_text_width 0.3048)
    (pad_size 4.0005 4.0005)
    (pad_drill 4.0005)
    (pad_to_mask_clearance 0.254)
    (aux_axis_origin 237.47984 206.11592)
    (visible_elements 7FFFFB8F)
    (pcbplotparams
      (layerselection 284197375)
      (usegerberextensions true)
      (excludeedgelayer true)
      (linewidth 0.150000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 0)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotothertext true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "G:/Manu_Work Folder/Hdmi To Usb/2015/Nov/HDMI2USB_10-11-15_2.54pm/gerber"))
  )
  (net 0 "")
  (net 1 /DDR3/DDR0_A0)
  (net 2 /DDR3/DDR0_A1)
  (net 3 /DDR3/DDR0_A10)
  (net 4 /DDR3/DDR0_A11)
  (net 5 /DDR3/DDR0_A12)
  (net 6 /DDR3/DDR0_A13)
  (net 7 /DDR3/DDR0_A14)
  (net 8 /DDR3/DDR0_A2)
  (net 9 /DDR3/DDR0_A3)
  (net 10 /DDR3/DDR0_A4)
  (net 11 /DDR3/DDR0_A5)
  (net 12 /DDR3/DDR0_A6)
  (net 13 /DDR3/DDR0_A7)
  (net 14 /DDR3/DDR0_A8)
  (net 15 /DDR3/DDR0_A9)
  (net 16 /DDR3/DDR0_BA0)
  (net 17 /DDR3/DDR0_BA1)
  (net 18 /DDR3/DDR0_BA2)
  (net 19 /DDR3/DDR0_CAS_N)
  (net 20 /DDR3/DDR0_CKE)
  (net 21 /DDR3/DDR0_CK_N)
  (net 22 /DDR3/DDR0_CK_P)
  (net 23 /DDR3/DDR0_DQ0)
  (net 24 /DDR3/DDR0_DQ1)
  (net 25 /DDR3/DDR0_DQ10)
  (net 26 /DDR3/DDR0_DQ11)
  (net 27 /DDR3/DDR0_DQ12)
  (net 28 /DDR3/DDR0_DQ13)
  (net 29 /DDR3/DDR0_DQ14)
  (net 30 /DDR3/DDR0_DQ15)
  (net 31 /DDR3/DDR0_DQ2)
  (net 32 /DDR3/DDR0_DQ3)
  (net 33 /DDR3/DDR0_DQ4)
  (net 34 /DDR3/DDR0_DQ5)
  (net 35 /DDR3/DDR0_DQ6)
  (net 36 /DDR3/DDR0_DQ7)
  (net 37 /DDR3/DDR0_DQ8)
  (net 38 /DDR3/DDR0_DQ9)
  (net 39 /DDR3/DDR0_LDM)
  (net 40 /DDR3/DDR0_LDQS_N)
  (net 41 /DDR3/DDR0_LDQS_P)
  (net 42 /DDR3/DDR0_ODT)
  (net 43 /DDR3/DDR0_RAS_N)
  (net 44 /DDR3/DDR0_RESET_N)
  (net 45 /DDR3/DDR0_UDM)
  (net 46 /DDR3/DDR0_UDQS_N)
  (net 47 /DDR3/DDR0_UDQS_P)
  (net 48 /DDR3/DDR0_WE_N)
  (net 49 /DisplayPort/DPRXAUXCH_N)
  (net 50 /DisplayPort/DPRXAUXCH_P)
  (net 51 /DisplayPort/DPRXCONFIG1)
  (net 52 /DisplayPort/DPRXCONFIG2)
  (net 53 /DisplayPort/DPRX_LANEN0)
  (net 54 /DisplayPort/DPRX_LANEN1)
  (net 55 /DisplayPort/DPRX_LANEN2)
  (net 56 /DisplayPort/DPRX_LANEN3)
  (net 57 /DisplayPort/DPRX_LANEP0)
  (net 58 /DisplayPort/DPRX_LANEP1)
  (net 59 /DisplayPort/DPRX_LANEP2)
  (net 60 /DisplayPort/DPRX_LANEP3)
  (net 61 /DisplayPort/DPTXAUXCH_N)
  (net 62 /DisplayPort/DPTXAUXCH_P)
  (net 63 /DisplayPort/DPTXCONFIG1)
  (net 64 /DisplayPort/DPTXCONFIG2)
  (net 65 /DisplayPort/DPTX_LANEN0)
  (net 66 /DisplayPort/DPTX_LANEN1)
  (net 67 /DisplayPort/DPTX_LANEN2)
  (net 68 /DisplayPort/DPTX_LANEN3)
  (net 69 /DisplayPort/DPTX_LANEP0)
  (net 70 /DisplayPort/DPTX_LANEP1)
  (net 71 /DisplayPort/DPTX_LANEP2)
  (net 72 /DisplayPort/DPTX_LANEP3)
  (net 73 /Ethernet/AVDD3V3)
  (net 74 /Ethernet/ETH_INT_B)
  (net 75 /Ethernet/ETH_MDC)
  (net 76 /Ethernet/ETH_MDIO)
  (net 77 /Ethernet/ETH_RESET_B)
  (net 78 /Ethernet/ETH_RXCLK)
  (net 79 /Ethernet/ETH_RXCTL)
  (net 80 /Ethernet/ETH_RXD0)
  (net 81 /Ethernet/ETH_RXD1)
  (net 82 /Ethernet/ETH_RXD2)
  (net 83 /Ethernet/ETH_RXD3)
  (net 84 /Ethernet/ETH_TXCLK)
  (net 85 /Ethernet/ETH_TXCTL)
  (net 86 /Ethernet/ETH_TXD0)
  (net 87 /Ethernet/ETH_TXD1)
  (net 88 /Ethernet/ETH_TXD2)
  (net 89 /Ethernet/ETH_TXD3)
  (net 90 /Ethernet/ETH_VCC1V0)
  (net 91 /Ethernet/ETH_VCC3V3)
  (net 92 /Ethernet/LED0)
  (net 93 /Ethernet/LED1)
  (net 94 /Ethernet/MAC_SCL)
  (net 95 /Ethernet/MAC_SDA)
  (net 96 /Ethernet/MAC_WP)
  (net 97 /Ethernet/VCC1V0)
  (net 98 /Ethernet/XTAL1_50MHZ)
  (net 99 /Ethernet/XTAL2_50MHZ)
  (net 100 /FPGA_Bank_0_3/DEBUG_IO0)
  (net 101 /FPGA_Bank_0_3/DEBUG_IO1)
  (net 102 /FPGA_Bank_0_3/DIFFCLK_A0N)
  (net 103 /FPGA_Bank_0_3/DIFFCLK_A0P)
  (net 104 /FPGA_Bank_0_3/DIFFCLK_A1N)
  (net 105 /FPGA_Bank_0_3/DIFFCLK_A1P)
  (net 106 /FPGA_Bank_0_3/DIFFCLK_B0N)
  (net 107 /FPGA_Bank_0_3/DIFFCLK_B0P)
  (net 108 /FPGA_Bank_0_3/DIFFCLK_B1N)
  (net 109 /FPGA_Bank_0_3/DIFFCLK_B1P)
  (net 110 /FPGA_Bank_0_3/DIFFCLK_XN)
  (net 111 /FPGA_Bank_0_3/DIFFCLK_XP)
  (net 112 /FPGA_Bank_0_3/DIFFIO_A0N)
  (net 113 /FPGA_Bank_0_3/DIFFIO_A0P)
  (net 114 /FPGA_Bank_0_3/DIFFIO_A1N)
  (net 115 /FPGA_Bank_0_3/DIFFIO_A1P)
  (net 116 /FPGA_Bank_0_3/DIFFIO_A2N)
  (net 117 /FPGA_Bank_0_3/DIFFIO_A2P)
  (net 118 /FPGA_Bank_0_3/DIFFIO_A3N)
  (net 119 /FPGA_Bank_0_3/DIFFIO_A3P)
  (net 120 /FPGA_Bank_0_3/DIFFIO_A4N)
  (net 121 /FPGA_Bank_0_3/DIFFIO_A4P)
  (net 122 /FPGA_Bank_0_3/DIFFIO_A5N)
  (net 123 /FPGA_Bank_0_3/DIFFIO_A5P)
  (net 124 /FPGA_Bank_0_3/DIFFIO_A6N)
  (net 125 /FPGA_Bank_0_3/DIFFIO_A6P)
  (net 126 /FPGA_Bank_0_3/DIFFIO_B0N)
  (net 127 /FPGA_Bank_0_3/DIFFIO_B0P)
  (net 128 /FPGA_Bank_0_3/DIFFIO_B1N)
  (net 129 /FPGA_Bank_0_3/DIFFIO_B1P)
  (net 130 /FPGA_Bank_0_3/DIFFIO_B2N)
  (net 131 /FPGA_Bank_0_3/DIFFIO_B2P)
  (net 132 /FPGA_Bank_0_3/DIFFIO_B3N)
  (net 133 /FPGA_Bank_0_3/DIFFIO_B3P)
  (net 134 /FPGA_Bank_0_3/DIFFIO_B4N)
  (net 135 /FPGA_Bank_0_3/DIFFIO_B4P)
  (net 136 /FPGA_Bank_0_3/DIFFIO_B5N)
  (net 137 /FPGA_Bank_0_3/DIFFIO_B5P)
  (net 138 /FPGA_Bank_0_3/DIFFIO_B6N)
  (net 139 /FPGA_Bank_0_3/DIFFIO_B6P)
  (net 140 /FPGA_Bank_0_3/DIFFIO_XN)
  (net 141 /FPGA_Bank_0_3/DIFFIO_XP)
  (net 142 /FPGA_Bank_0_3/DIFFIO_YN)
  (net 143 /FPGA_Bank_0_3/DIFFIO_YP)
  (net 144 /FPGA_Bank_0_3/DIFFIO_ZN)
  (net 145 /FPGA_Bank_0_3/DIFFIO_ZP)
  (net 146 /FPGA_Bank_0_3/HSWAP)
  (net 147 /FPGA_Bank_0_3/MGT135MHz_N)
  (net 148 /FPGA_Bank_0_3/MGT135MHz_P)
  (net 149 /FPGA_Bank_0_3/MGTREFCLK0_101_N)
  (net 150 /FPGA_Bank_0_3/MGTREFCLK0_101_P)
  (net 151 /FPGA_Bank_0_3/MGTSMACLK_N)
  (net 152 /FPGA_Bank_0_3/MGTSMACLK_P)
  (net 153 /FPGA_Bank_0_3/PCIE_RESET)
  (net 154 /FPGA_Bank_0_3/PCIO0)
  (net 155 /FPGA_Bank_0_3/PCIO1)
  (net 156 /FPGA_Bank_0_3/PCIO2)
  (net 157 /FPGA_Bank_0_3/PCIO3)
  (net 158 /FPGA_Bank_0_3/SMCLK)
  (net 159 /FPGA_Bank_0_3/SMDATA)
  (net 160 /FPGA_Bank_0_3/SWITCH)
  (net 161 /FPGA_Bank_1_2/CY-IFCLK)
  (net 162 /FPGA_Bank_1_2/CYPRESS-RESET)
  (net 163 /FPGA_Bank_1_2/CY_CTL0)
  (net 164 /FPGA_Bank_1_2/CY_CTL1)
  (net 165 /FPGA_Bank_1_2/CY_CTL2)
  (net 166 /FPGA_Bank_1_2/CY_CTL3)
  (net 167 /FPGA_Bank_1_2/CY_CTL4)
  (net 168 /FPGA_Bank_1_2/CY_CTL5)
  (net 169 /FPGA_Bank_1_2/CY_FD0)
  (net 170 /FPGA_Bank_1_2/CY_FD1)
  (net 171 /FPGA_Bank_1_2/CY_FD10)
  (net 172 /FPGA_Bank_1_2/CY_FD11)
  (net 173 /FPGA_Bank_1_2/CY_FD12)
  (net 174 /FPGA_Bank_1_2/CY_FD13)
  (net 175 /FPGA_Bank_1_2/CY_FD14)
  (net 176 /FPGA_Bank_1_2/CY_FD15)
  (net 177 /FPGA_Bank_1_2/CY_FD2)
  (net 178 /FPGA_Bank_1_2/CY_FD3)
  (net 179 /FPGA_Bank_1_2/CY_FD4)
  (net 180 /FPGA_Bank_1_2/CY_FD5)
  (net 181 /FPGA_Bank_1_2/CY_FD6)
  (net 182 /FPGA_Bank_1_2/CY_FD7)
  (net 183 /FPGA_Bank_1_2/CY_FD8)
  (net 184 /FPGA_Bank_1_2/CY_FD9)
  (net 185 /FPGA_Bank_1_2/CY_INT5)
  (net 186 /FPGA_Bank_1_2/CY_PA0)
  (net 187 /FPGA_Bank_1_2/CY_PA1)
  (net 188 /FPGA_Bank_1_2/CY_PA2)
  (net 189 /FPGA_Bank_1_2/CY_PA3)
  (net 190 /FPGA_Bank_1_2/CY_PA4)
  (net 191 /FPGA_Bank_1_2/CY_PA5)
  (net 192 /FPGA_Bank_1_2/CY_PA6)
  (net 193 /FPGA_Bank_1_2/CY_PA7)
  (net 194 /FPGA_Bank_1_2/CY_PC0)
  (net 195 /FPGA_Bank_1_2/CY_PC1)
  (net 196 /FPGA_Bank_1_2/CY_PC2)
  (net 197 /FPGA_Bank_1_2/CY_PC3)
  (net 198 /FPGA_Bank_1_2/CY_PC4)
  (net 199 /FPGA_Bank_1_2/CY_PC5)
  (net 200 /FPGA_Bank_1_2/CY_PC6)
  (net 201 /FPGA_Bank_1_2/CY_PC7)
  (net 202 /FPGA_Bank_1_2/CY_RD)
  (net 203 /FPGA_Bank_1_2/CY_RD0)
  (net 204 /FPGA_Bank_1_2/CY_RD1)
  (net 205 /FPGA_Bank_1_2/CY_RD2)
  (net 206 /FPGA_Bank_1_2/CY_RD3)
  (net 207 /FPGA_Bank_1_2/CY_RD4)
  (net 208 /FPGA_Bank_1_2/CY_RD5)
  (net 209 /FPGA_Bank_1_2/CY_RXD0)
  (net 210 /FPGA_Bank_1_2/CY_RXD1)
  (net 211 /FPGA_Bank_1_2/CY_T0)
  (net 212 /FPGA_Bank_1_2/CY_TXD0)
  (net 213 /FPGA_Bank_1_2/CY_TXD1)
  (net 214 /FPGA_Bank_1_2/CY_WR)
  (net 215 /FPGA_Bank_1_2/DPRXHPD)
  (net 216 /FPGA_Bank_1_2/DPTXHPD)
  (net 217 /FPGA_Bank_1_2/FPGA_M0_CMP_MISO)
  (net 218 /FPGA_Bank_1_2/FPGA_M1)
  (net 219 /FPGA_Bank_1_2/INIT_B)
  (net 220 /FPGA_Bank_1_2/SD_CLK)
  (net 221 /FPGA_Bank_1_2/SD_CMD)
  (net 222 /FPGA_Bank_1_2/SD_DAT0)
  (net 223 /FPGA_Bank_1_2/SD_DAT1)
  (net 224 /FPGA_Bank_1_2/SD_DAT2)
  (net 225 /FPGA_Bank_1_2/SD_DAT3)
  (net 226 /FPGA_Bank_1_2/SPI_CLK)
  (net 227 /FPGA_Bank_1_2/SPI_CS_N)
  (net 228 /FPGA_Bank_1_2/SPI_D1_MISO2)
  (net 229 /FPGA_Bank_1_2/SPI_D2_MISO3)
  (net 230 /FPGA_Bank_1_2/SPI_DO_DIN_MISO1)
  (net 231 /FPGA_Bank_1_2/SPI_MOSI_CSI_N_MISO0)
  (net 232 /FPGA_Bank_1_2/TMDS_RX1_0_N)
  (net 233 /FPGA_Bank_1_2/TMDS_RX1_0_P)
  (net 234 /FPGA_Bank_1_2/TMDS_RX1_1_N)
  (net 235 /FPGA_Bank_1_2/TMDS_RX1_1_P)
  (net 236 /FPGA_Bank_1_2/TMDS_RX1_2_N)
  (net 237 /FPGA_Bank_1_2/TMDS_RX1_2_P)
  (net 238 /FPGA_Bank_1_2/TMDS_RX1_CEC)
  (net 239 /FPGA_Bank_1_2/TMDS_RX1_CLK_N)
  (net 240 /FPGA_Bank_1_2/TMDS_RX1_CLK_P)
  (net 241 /FPGA_Bank_1_2/TMDS_RX1_HOT)
  (net 242 /FPGA_Bank_1_2/TMDS_RX1_SCL)
  (net 243 /FPGA_Bank_1_2/TMDS_RX1_SDA)
  (net 244 /FPGA_Bank_1_2/TMDS_RX2_0_N)
  (net 245 /FPGA_Bank_1_2/TMDS_RX2_0_P)
  (net 246 /FPGA_Bank_1_2/TMDS_RX2_1_N)
  (net 247 /FPGA_Bank_1_2/TMDS_RX2_1_P)
  (net 248 /FPGA_Bank_1_2/TMDS_RX2_2_N)
  (net 249 /FPGA_Bank_1_2/TMDS_RX2_2_P)
  (net 250 /FPGA_Bank_1_2/TMDS_RX2_CEC)
  (net 251 /FPGA_Bank_1_2/TMDS_RX2_CLK_N)
  (net 252 /FPGA_Bank_1_2/TMDS_RX2_CLK_P)
  (net 253 /FPGA_Bank_1_2/TMDS_RX2_HOT)
  (net 254 /FPGA_Bank_1_2/TMDS_RX2_SCL)
  (net 255 /FPGA_Bank_1_2/TMDS_RX2_SDA)
  (net 256 /FPGA_Bank_1_2/TMDS_TX1_0_N)
  (net 257 /FPGA_Bank_1_2/TMDS_TX1_0_P)
  (net 258 /FPGA_Bank_1_2/TMDS_TX1_1_N)
  (net 259 /FPGA_Bank_1_2/TMDS_TX1_1_P)
  (net 260 /FPGA_Bank_1_2/TMDS_TX1_2_N)
  (net 261 /FPGA_Bank_1_2/TMDS_TX1_2_P)
  (net 262 /FPGA_Bank_1_2/TMDS_TX1_CEC)
  (net 263 /FPGA_Bank_1_2/TMDS_TX1_CLK_N)
  (net 264 /FPGA_Bank_1_2/TMDS_TX1_CLK_P)
  (net 265 /FPGA_Bank_1_2/TMDS_TX1_HOT)
  (net 266 /FPGA_Bank_1_2/TMDS_TX1_SCL)
  (net 267 /FPGA_Bank_1_2/TMDS_TX1_SDA)
  (net 268 /FPGA_Bank_1_2/TMDS_TX2_0_N)
  (net 269 /FPGA_Bank_1_2/TMDS_TX2_0_P)
  (net 270 /FPGA_Bank_1_2/TMDS_TX2_1_N)
  (net 271 /FPGA_Bank_1_2/TMDS_TX2_1_P)
  (net 272 /FPGA_Bank_1_2/TMDS_TX2_2_N)
  (net 273 /FPGA_Bank_1_2/TMDS_TX2_2_P)
  (net 274 /FPGA_Bank_1_2/TMDS_TX2_CEC)
  (net 275 /FPGA_Bank_1_2/TMDS_TX2_CLK_N)
  (net 276 /FPGA_Bank_1_2/TMDS_TX2_CLK_P)
  (net 277 /FPGA_Bank_1_2/TMDS_TX2_HOT)
  (net 278 /FPGA_Bank_1_2/TMDS_TX2_SCL)
  (net 279 /FPGA_Bank_1_2/TMDS_TX2_SDA)
  (net 280 /FPGA_Bank_1_2/USB_D0)
  (net 281 /FPGA_Bank_1_2/USB_D1)
  (net 282 /FPGA_Bank_1_2/USB_D2)
  (net 283 /FPGA_Bank_1_2/USB_D3)
  (net 284 /FPGA_Bank_1_2/USB_D4)
  (net 285 /FPGA_Bank_1_2/USB_D5)
  (net 286 /FPGA_Bank_1_2/USB_D6)
  (net 287 /FPGA_Bank_1_2/USB_D7)
  (net 288 /FPGA_Bank_1_2/USB_DIR)
  (net 289 /FPGA_Bank_1_2/USB_NXT)
  (net 290 /FPGA_Bank_1_2/USB_REFCLK)
  (net 291 /FPGA_Bank_1_2/USB_RESETB)
  (net 292 /FPGA_Bank_1_2/USB_STP)
  (net 293 /FPGA_Bank_1_2/100MHz)
  (net 294 /FPGA_Power/DONE)
  (net 295 /FPGA_Power/PROG_B)
  (net 296 /FPGA_Power/RFS)
  (net 297 /FPGA_Power/SUSPEND)
  (net 298 /FPGA_Power/TCK)
  (net 299 /FPGA_Power/TMS)
  (net 300 /FPGA_Power/VBATT)
  (net 301 /FPGA_Power/VFS)
  (net 302 /GPIOs/PRSNT)
  (net 303 /HDMI/HDMI-TX1-VCC5V0)
  (net 304 /HDMI/HDMI-TX2-VCC5V0)
  (net 305 /HDMI/HDMI_VCC5V0)
  (net 306 /HDMI/P1-CEC)
  (net 307 /HDMI/P1-HOT)
  (net 308 /HDMI/P1-SCL)
  (net 309 /HDMI/P1-SDA)
  (net 310 /HDMI/P2-CEC)
  (net 311 /HDMI/P2-HOT)
  (net 312 /HDMI/P2-SCL)
  (net 313 /HDMI/P2-SDA)
  (net 314 /HDMI/P3-CEC)
  (net 315 /HDMI/P3-HOT)
  (net 316 /HDMI/P3-SCL)
  (net 317 /HDMI/P3-SDA)
  (net 318 /HDMI/P4-CEC)
  (net 319 /HDMI/P4-HOT)
  (net 320 /HDMI/P4-SCL)
  (net 321 /HDMI/P4-SDA)
  (net 322 "/Power/Conference 12V")
  (net 323 "/Power/Consumer 12V")
  (net 324 "/Power/VIN +48V")
  (net 325 "/Power/VIN -48V")
  (net 326 "/Power/VIN 48")
  (net 327 /SPI_Flash/27MHz)
  (net 328 /SPI_Flash/RST)
  (net 329 /SPI_Flash/TDO-FPGA/TDO-JTAG)
  (net 330 /SPI_Flash/TDO-USB/TDI-FPGA)
  (net 331 /USB/CPEN)
  (net 332 /USB/CYDN)
  (net 333 /USB/CYDP)
  (net 334 /USB/CYP-RESET)
  (net 335 /USB/ID)
  (net 336 /USB/U1-SDA)
  (net 337 /USB/USB_5V)
  (net 338 /USB/USB_DM)
  (net 339 /USB/USB_DP)
  (net 340 /USB/XTALIN)
  (net 341 /USB/XTALIOUT)
  (net 342 GND)
  (net 343 N-00000178)
  (net 344 N-00000182)
  (net 345 N-00000189)
  (net 346 N-00000192)
  (net 347 N-00000193)
  (net 348 N-00000194)
  (net 349 N-00000195)
  (net 350 N-00000198)
  (net 351 N-00000199)
  (net 352 N-00000200)
  (net 353 N-00000202)
  (net 354 N-00000203)
  (net 355 N-00000205)
  (net 356 N-00000206)
  (net 357 N-00000207)
  (net 358 N-00000211)
  (net 359 N-00000213)
  (net 360 N-00000214)
  (net 361 N-00000217)
  (net 362 N-00000218)
  (net 363 N-00000232)
  (net 364 N-00000233)
  (net 365 N-00000235)
  (net 366 N-00000249)
  (net 367 N-00000250)
  (net 368 N-00000251)
  (net 369 N-00000254)
  (net 370 N-00000255)
  (net 371 N-00000256)
  (net 372 N-00000257)
  (net 373 N-00000258)
  (net 374 N-00000259)
  (net 375 N-00000260)
  (net 376 N-00000261)
  (net 377 N-00000262)
  (net 378 N-00000263)
  (net 379 N-00000266)
  (net 380 N-00000268)
  (net 381 N-00000269)
  (net 382 N-00000271)
  (net 383 N-00000275)
  (net 384 N-00000279)
  (net 385 N-00000280)
  (net 386 N-00000288)
  (net 387 N-00000289)
  (net 388 N-00000290)
  (net 389 N-00000292)
  (net 390 N-00000298)
  (net 391 N-00000300)
  (net 392 N-00000301)
  (net 393 N-00000302)
  (net 394 N-00000303)
  (net 395 N-00000304)
  (net 396 N-00000305)
  (net 397 N-00000306)
  (net 398 N-00000308)
  (net 399 N-00000309)
  (net 400 N-00000312)
  (net 401 N-00000313)
  (net 402 N-00000314)
  (net 403 N-00000316)
  (net 404 N-00000319)
  (net 405 N-00000327)
  (net 406 N-00000330)
  (net 407 N-00000331)
  (net 408 N-00000332)
  (net 409 N-00000333)
  (net 410 N-00000335)
  (net 411 N-00000336)
  (net 412 N-00000337)
  (net 413 N-00000339)
  (net 414 N-00000340)
  (net 415 N-00000341)
  (net 416 N-00000342)
  (net 417 N-00000343)
  (net 418 N-00000344)
  (net 419 N-00000345)
  (net 420 N-00000346)
  (net 421 N-00000348)
  (net 422 N-00000349)
  (net 423 N-00000350)
  (net 424 N-00000351)
  (net 425 N-00000352)
  (net 426 N-00000353)
  (net 427 N-00000354)
  (net 428 N-00000357)
  (net 429 N-00000359)
  (net 430 N-00000360)
  (net 431 N-00000361)
  (net 432 N-00000362)
  (net 433 N-00000363)
  (net 434 N-00000364)
  (net 435 N-00000365)
  (net 436 N-00000366)
  (net 437 N-00000367)
  (net 438 N-00000368)
  (net 439 N-00000369)
  (net 440 N-00000370)
  (net 441 N-00000372)
  (net 442 N-00000373)
  (net 443 N-00000377)
  (net 444 N-00000382)
  (net 445 N-00000387)
  (net 446 N-00000388)
  (net 447 N-00000391)
  (net 448 N-00000400)
  (net 449 N-00000409)
  (net 450 N-00000410)
  (net 451 N-00000411)
  (net 452 N-00000412)
  (net 453 N-00000413)
  (net 454 N-00000414)
  (net 455 N-00000415)
  (net 456 N-00000416)
  (net 457 N-00000417)
  (net 458 N-00000418)
  (net 459 N-00000419)
  (net 460 N-00000420)
  (net 461 N-00000421)
  (net 462 N-00000422)
  (net 463 N-00000424)
  (net 464 N-00000425)
  (net 465 N-00000426)
  (net 466 N-00000427)
  (net 467 N-00000428)
  (net 468 N-00000429)
  (net 469 N-00000430)
  (net 470 N-00000431)
  (net 471 N-00000432)
  (net 472 N-00000433)
  (net 473 VCC12V0)
  (net 474 VCC1V2)
  (net 475 VCC1V5)
  (net 476 VCC3V3)
  (net 477 VCC4V0)
  (net 478 VTTDDR0)
  (net 479 VTTREF)
  (net_class Default "This is the default net class."
    (clearance 0.10414)
    (trace_width 0.127)
    (via_dia 0.80772)
    (via_drill 0.254)
    (uvia_dia 0.508)
    (uvia_drill 0.127)
    (add_net "")
    (add_net /DDR3/DDR0_A0)
    (add_net /DDR3/DDR0_A1)
    (add_net /DDR3/DDR0_A10)
    (add_net /DDR3/DDR0_A11)
    (add_net /DDR3/DDR0_A12)
    (add_net /DDR3/DDR0_A13)
    (add_net /DDR3/DDR0_A14)
    (add_net /DDR3/DDR0_A2)
    (add_net /DDR3/DDR0_A3)
    (add_net /DDR3/DDR0_A4)
    (add_net /DDR3/DDR0_A5)
    (add_net /DDR3/DDR0_A6)
    (add_net /DDR3/DDR0_A7)
    (add_net /DDR3/DDR0_A8)
    (add_net /DDR3/DDR0_A9)
    (add_net /DDR3/DDR0_BA0)
    (add_net /DDR3/DDR0_BA1)
    (add_net /DDR3/DDR0_BA2)
    (add_net /DDR3/DDR0_CAS_N)
    (add_net /DDR3/DDR0_CKE)
    (add_net /DDR3/DDR0_CK_N)
    (add_net /DDR3/DDR0_CK_P)
    (add_net /DDR3/DDR0_DQ0)
    (add_net /DDR3/DDR0_DQ1)
    (add_net /DDR3/DDR0_DQ10)
    (add_net /DDR3/DDR0_DQ11)
    (add_net /DDR3/DDR0_DQ12)
    (add_net /DDR3/DDR0_DQ13)
    (add_net /DDR3/DDR0_DQ14)
    (add_net /DDR3/DDR0_DQ15)
    (add_net /DDR3/DDR0_DQ2)
    (add_net /DDR3/DDR0_DQ3)
    (add_net /DDR3/DDR0_DQ4)
    (add_net /DDR3/DDR0_DQ5)
    (add_net /DDR3/DDR0_DQ6)
    (add_net /DDR3/DDR0_DQ7)
    (add_net /DDR3/DDR0_DQ8)
    (add_net /DDR3/DDR0_DQ9)
    (add_net /DDR3/DDR0_LDM)
    (add_net /DDR3/DDR0_LDQS_N)
    (add_net /DDR3/DDR0_LDQS_P)
    (add_net /DDR3/DDR0_ODT)
    (add_net /DDR3/DDR0_RAS_N)
    (add_net /DDR3/DDR0_RESET_N)
    (add_net /DDR3/DDR0_UDM)
    (add_net /DDR3/DDR0_UDQS_N)
    (add_net /DDR3/DDR0_UDQS_P)
    (add_net /DDR3/DDR0_WE_N)
    (add_net /DisplayPort/DPRXAUXCH_N)
    (add_net /DisplayPort/DPRXAUXCH_P)
    (add_net /DisplayPort/DPRXCONFIG1)
    (add_net /DisplayPort/DPRXCONFIG2)
    (add_net /DisplayPort/DPRX_LANEN0)
    (add_net /DisplayPort/DPRX_LANEN1)
    (add_net /DisplayPort/DPRX_LANEN2)
    (add_net /DisplayPort/DPRX_LANEN3)
    (add_net /DisplayPort/DPRX_LANEP0)
    (add_net /DisplayPort/DPRX_LANEP1)
    (add_net /DisplayPort/DPRX_LANEP2)
    (add_net /DisplayPort/DPRX_LANEP3)
    (add_net /DisplayPort/DPTXAUXCH_N)
    (add_net /DisplayPort/DPTXAUXCH_P)
    (add_net /DisplayPort/DPTXCONFIG1)
    (add_net /DisplayPort/DPTXCONFIG2)
    (add_net /DisplayPort/DPTX_LANEN0)
    (add_net /DisplayPort/DPTX_LANEN1)
    (add_net /DisplayPort/DPTX_LANEN2)
    (add_net /DisplayPort/DPTX_LANEN3)
    (add_net /DisplayPort/DPTX_LANEP0)
    (add_net /DisplayPort/DPTX_LANEP1)
    (add_net /DisplayPort/DPTX_LANEP2)
    (add_net /DisplayPort/DPTX_LANEP3)
    (add_net /Ethernet/AVDD3V3)
    (add_net /Ethernet/ETH_INT_B)
    (add_net /Ethernet/ETH_MDC)
    (add_net /Ethernet/ETH_MDIO)
    (add_net /Ethernet/ETH_RESET_B)
    (add_net /Ethernet/ETH_RXCLK)
    (add_net /Ethernet/ETH_RXCTL)
    (add_net /Ethernet/ETH_RXD0)
    (add_net /Ethernet/ETH_RXD1)
    (add_net /Ethernet/ETH_RXD2)
    (add_net /Ethernet/ETH_RXD3)
    (add_net /Ethernet/ETH_TXCLK)
    (add_net /Ethernet/ETH_TXCTL)
    (add_net /Ethernet/ETH_TXD0)
    (add_net /Ethernet/ETH_TXD1)
    (add_net /Ethernet/ETH_TXD2)
    (add_net /Ethernet/ETH_TXD3)
    (add_net /Ethernet/ETH_VCC1V0)
    (add_net /Ethernet/ETH_VCC3V3)
    (add_net /Ethernet/LED0)
    (add_net /Ethernet/LED1)
    (add_net /Ethernet/MAC_SCL)
    (add_net /Ethernet/MAC_SDA)
    (add_net /Ethernet/MAC_WP)
    (add_net /Ethernet/VCC1V0)
    (add_net /Ethernet/XTAL1_50MHZ)
    (add_net /Ethernet/XTAL2_50MHZ)
    (add_net /FPGA_Bank_0_3/DEBUG_IO0)
    (add_net /FPGA_Bank_0_3/DEBUG_IO1)
    (add_net /FPGA_Bank_0_3/DIFFCLK_A0N)
    (add_net /FPGA_Bank_0_3/DIFFCLK_A0P)
    (add_net /FPGA_Bank_0_3/DIFFCLK_A1N)
    (add_net /FPGA_Bank_0_3/DIFFCLK_A1P)
    (add_net /FPGA_Bank_0_3/DIFFCLK_B0N)
    (add_net /FPGA_Bank_0_3/DIFFCLK_B0P)
    (add_net /FPGA_Bank_0_3/DIFFCLK_B1N)
    (add_net /FPGA_Bank_0_3/DIFFCLK_B1P)
    (add_net /FPGA_Bank_0_3/DIFFCLK_XN)
    (add_net /FPGA_Bank_0_3/DIFFCLK_XP)
    (add_net /FPGA_Bank_0_3/DIFFIO_A0N)
    (add_net /FPGA_Bank_0_3/DIFFIO_A0P)
    (add_net /FPGA_Bank_0_3/DIFFIO_A1N)
    (add_net /FPGA_Bank_0_3/DIFFIO_A1P)
    (add_net /FPGA_Bank_0_3/DIFFIO_A2N)
    (add_net /FPGA_Bank_0_3/DIFFIO_A2P)
    (add_net /FPGA_Bank_0_3/DIFFIO_A3N)
    (add_net /FPGA_Bank_0_3/DIFFIO_A3P)
    (add_net /FPGA_Bank_0_3/DIFFIO_A4N)
    (add_net /FPGA_Bank_0_3/DIFFIO_A4P)
    (add_net /FPGA_Bank_0_3/DIFFIO_A5N)
    (add_net /FPGA_Bank_0_3/DIFFIO_A5P)
    (add_net /FPGA_Bank_0_3/DIFFIO_A6N)
    (add_net /FPGA_Bank_0_3/DIFFIO_A6P)
    (add_net /FPGA_Bank_0_3/DIFFIO_B0N)
    (add_net /FPGA_Bank_0_3/DIFFIO_B0P)
    (add_net /FPGA_Bank_0_3/DIFFIO_B1N)
    (add_net /FPGA_Bank_0_3/DIFFIO_B1P)
    (add_net /FPGA_Bank_0_3/DIFFIO_B2N)
    (add_net /FPGA_Bank_0_3/DIFFIO_B2P)
    (add_net /FPGA_Bank_0_3/DIFFIO_B3N)
    (add_net /FPGA_Bank_0_3/DIFFIO_B3P)
    (add_net /FPGA_Bank_0_3/DIFFIO_B4N)
    (add_net /FPGA_Bank_0_3/DIFFIO_B4P)
    (add_net /FPGA_Bank_0_3/DIFFIO_B5N)
    (add_net /FPGA_Bank_0_3/DIFFIO_B5P)
    (add_net /FPGA_Bank_0_3/DIFFIO_B6N)
    (add_net /FPGA_Bank_0_3/DIFFIO_B6P)
    (add_net /FPGA_Bank_0_3/DIFFIO_XN)
    (add_net /FPGA_Bank_0_3/DIFFIO_XP)
    (add_net /FPGA_Bank_0_3/DIFFIO_YN)
    (add_net /FPGA_Bank_0_3/DIFFIO_YP)
    (add_net /FPGA_Bank_0_3/DIFFIO_ZN)
    (add_net /FPGA_Bank_0_3/DIFFIO_ZP)
    (add_net /FPGA_Bank_0_3/HSWAP)
    (add_net /FPGA_Bank_0_3/MGT135MHz_N)
    (add_net /FPGA_Bank_0_3/MGT135MHz_P)
    (add_net /FPGA_Bank_0_3/MGTREFCLK0_101_N)
    (add_net /FPGA_Bank_0_3/MGTREFCLK0_101_P)
    (add_net /FPGA_Bank_0_3/MGTSMACLK_N)
    (add_net /FPGA_Bank_0_3/MGTSMACLK_P)
    (add_net /FPGA_Bank_0_3/PCIE_RESET)
    (add_net /FPGA_Bank_0_3/PCIO0)
    (add_net /FPGA_Bank_0_3/PCIO1)
    (add_net /FPGA_Bank_0_3/PCIO2)
    (add_net /FPGA_Bank_0_3/PCIO3)
    (add_net /FPGA_Bank_0_3/SMCLK)
    (add_net /FPGA_Bank_0_3/SMDATA)
    (add_net /FPGA_Bank_0_3/SWITCH)
    (add_net /FPGA_Bank_1_2/CY-IFCLK)
    (add_net /FPGA_Bank_1_2/CYPRESS-RESET)
    (add_net /FPGA_Bank_1_2/CY_CTL0)
    (add_net /FPGA_Bank_1_2/CY_CTL1)
    (add_net /FPGA_Bank_1_2/CY_CTL2)
    (add_net /FPGA_Bank_1_2/CY_CTL3)
    (add_net /FPGA_Bank_1_2/CY_CTL4)
    (add_net /FPGA_Bank_1_2/CY_CTL5)
    (add_net /FPGA_Bank_1_2/CY_FD0)
    (add_net /FPGA_Bank_1_2/CY_FD1)
    (add_net /FPGA_Bank_1_2/CY_FD10)
    (add_net /FPGA_Bank_1_2/CY_FD11)
    (add_net /FPGA_Bank_1_2/CY_FD12)
    (add_net /FPGA_Bank_1_2/CY_FD13)
    (add_net /FPGA_Bank_1_2/CY_FD14)
    (add_net /FPGA_Bank_1_2/CY_FD15)
    (add_net /FPGA_Bank_1_2/CY_FD2)
    (add_net /FPGA_Bank_1_2/CY_FD3)
    (add_net /FPGA_Bank_1_2/CY_FD4)
    (add_net /FPGA_Bank_1_2/CY_FD5)
    (add_net /FPGA_Bank_1_2/CY_FD6)
    (add_net /FPGA_Bank_1_2/CY_FD7)
    (add_net /FPGA_Bank_1_2/CY_FD8)
    (add_net /FPGA_Bank_1_2/CY_FD9)
    (add_net /FPGA_Bank_1_2/CY_INT5)
    (add_net /FPGA_Bank_1_2/CY_PA0)
    (add_net /FPGA_Bank_1_2/CY_PA1)
    (add_net /FPGA_Bank_1_2/CY_PA2)
    (add_net /FPGA_Bank_1_2/CY_PA3)
    (add_net /FPGA_Bank_1_2/CY_PA4)
    (add_net /FPGA_Bank_1_2/CY_PA5)
    (add_net /FPGA_Bank_1_2/CY_PA6)
    (add_net /FPGA_Bank_1_2/CY_PA7)
    (add_net /FPGA_Bank_1_2/CY_PC0)
    (add_net /FPGA_Bank_1_2/CY_PC1)
    (add_net /FPGA_Bank_1_2/CY_PC2)
    (add_net /FPGA_Bank_1_2/CY_PC3)
    (add_net /FPGA_Bank_1_2/CY_PC4)
    (add_net /FPGA_Bank_1_2/CY_PC5)
    (add_net /FPGA_Bank_1_2/CY_PC6)
    (add_net /FPGA_Bank_1_2/CY_PC7)
    (add_net /FPGA_Bank_1_2/CY_RD)
    (add_net /FPGA_Bank_1_2/CY_RD0)
    (add_net /FPGA_Bank_1_2/CY_RD1)
    (add_net /FPGA_Bank_1_2/CY_RD2)
    (add_net /FPGA_Bank_1_2/CY_RD3)
    (add_net /FPGA_Bank_1_2/CY_RD4)
    (add_net /FPGA_Bank_1_2/CY_RD5)
    (add_net /FPGA_Bank_1_2/CY_RXD0)
    (add_net /FPGA_Bank_1_2/CY_RXD1)
    (add_net /FPGA_Bank_1_2/CY_T0)
    (add_net /FPGA_Bank_1_2/CY_TXD0)
    (add_net /FPGA_Bank_1_2/CY_TXD1)
    (add_net /FPGA_Bank_1_2/CY_WR)
    (add_net /FPGA_Bank_1_2/DPRXHPD)
    (add_net /FPGA_Bank_1_2/DPTXHPD)
    (add_net /FPGA_Bank_1_2/FPGA_M0_CMP_MISO)
    (add_net /FPGA_Bank_1_2/FPGA_M1)
    (add_net /FPGA_Bank_1_2/INIT_B)
    (add_net /FPGA_Bank_1_2/SD_CLK)
    (add_net /FPGA_Bank_1_2/SD_CMD)
    (add_net /FPGA_Bank_1_2/SD_DAT0)
    (add_net /FPGA_Bank_1_2/SD_DAT1)
    (add_net /FPGA_Bank_1_2/SD_DAT2)
    (add_net /FPGA_Bank_1_2/SD_DAT3)
    (add_net /FPGA_Bank_1_2/SPI_CLK)
    (add_net /FPGA_Bank_1_2/SPI_CS_N)
    (add_net /FPGA_Bank_1_2/SPI_D1_MISO2)
    (add_net /FPGA_Bank_1_2/SPI_D2_MISO3)
    (add_net /FPGA_Bank_1_2/SPI_DO_DIN_MISO1)
    (add_net /FPGA_Bank_1_2/SPI_MOSI_CSI_N_MISO0)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_0_N)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_0_P)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_1_N)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_1_P)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_2_N)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_2_P)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_CEC)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_CLK_N)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_CLK_P)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_HOT)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_SCL)
    (add_net /FPGA_Bank_1_2/TMDS_RX1_SDA)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_0_N)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_0_P)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_1_N)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_1_P)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_2_N)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_2_P)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_CEC)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_CLK_N)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_CLK_P)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_HOT)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_SCL)
    (add_net /FPGA_Bank_1_2/TMDS_RX2_SDA)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_0_N)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_0_P)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_1_N)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_1_P)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_2_N)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_2_P)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_CEC)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_CLK_N)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_CLK_P)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_HOT)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_SCL)
    (add_net /FPGA_Bank_1_2/TMDS_TX1_SDA)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_0_N)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_0_P)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_1_N)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_1_P)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_2_N)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_2_P)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_CEC)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_CLK_N)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_CLK_P)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_HOT)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_SCL)
    (add_net /FPGA_Bank_1_2/TMDS_TX2_SDA)
    (add_net /FPGA_Bank_1_2/USB_D0)
    (add_net /FPGA_Bank_1_2/USB_D1)
    (add_net /FPGA_Bank_1_2/USB_D2)
    (add_net /FPGA_Bank_1_2/USB_D3)
    (add_net /FPGA_Bank_1_2/USB_D4)
    (add_net /FPGA_Bank_1_2/USB_D5)
    (add_net /FPGA_Bank_1_2/USB_D6)
    (add_net /FPGA_Bank_1_2/USB_D7)
    (add_net /FPGA_Bank_1_2/USB_DIR)
    (add_net /FPGA_Bank_1_2/USB_NXT)
    (add_net /FPGA_Bank_1_2/USB_REFCLK)
    (add_net /FPGA_Bank_1_2/USB_RESETB)
    (add_net /FPGA_Bank_1_2/USB_STP)
    (add_net /FPGA_Bank_1_2/100MHz)
    (add_net /FPGA_Power/DONE)
    (add_net /FPGA_Power/PROG_B)
    (add_net /FPGA_Power/RFS)
    (add_net /FPGA_Power/SUSPEND)
    (add_net /FPGA_Power/TCK)
    (add_net /FPGA_Power/TMS)
    (add_net /FPGA_Power/VBATT)
    (add_net /FPGA_Power/VFS)
    (add_net /GPIOs/PRSNT)
    (add_net /HDMI/HDMI-TX1-VCC5V0)
    (add_net /HDMI/HDMI-TX2-VCC5V0)
    (add_net /HDMI/HDMI_VCC5V0)
    (add_net /HDMI/P1-CEC)
    (add_net /HDMI/P1-HOT)
    (add_net /HDMI/P1-SCL)
    (add_net /HDMI/P1-SDA)
    (add_net /HDMI/P2-CEC)
    (add_net /HDMI/P2-HOT)
    (add_net /HDMI/P2-SCL)
    (add_net /HDMI/P2-SDA)
    (add_net /HDMI/P3-CEC)
    (add_net /HDMI/P3-HOT)
    (add_net /HDMI/P3-SCL)
    (add_net /HDMI/P3-SDA)
    (add_net /HDMI/P4-CEC)
    (add_net /HDMI/P4-HOT)
    (add_net /HDMI/P4-SCL)
    (add_net /HDMI/P4-SDA)
    (add_net "/Power/Conference 12V")
    (add_net "/Power/Consumer 12V")
    (add_net "/Power/VIN +48V")
    (add_net "/Power/VIN -48V")
    (add_net "/Power/VIN 48")
    (add_net /SPI_Flash/27MHz)
    (add_net /SPI_Flash/RST)
    (add_net /SPI_Flash/TDO-FPGA/TDO-JTAG)
    (add_net /SPI_Flash/TDO-USB/TDI-FPGA)
    (add_net /USB/CPEN)
    (add_net /USB/CYDN)
    (add_net /USB/CYDP)
    (add_net /USB/CYP-RESET)
    (add_net /USB/ID)
    (add_net /USB/U1-SDA)
    (add_net /USB/USB_5V)
    (add_net /USB/USB_DM)
    (add_net /USB/USB_DP)
    (add_net /USB/XTALIN)
    (add_net /USB/XTALIOUT)
    (add_net GND)
    (add_net N-00000178)
    (add_net N-00000182)
    (add_net N-00000189)
    (add_net N-00000192)
    (add_net N-00000193)
    (add_net N-00000194)
    (add_net N-00000195)
    (add_net N-00000198)
    (add_net N-00000199)
    (add_net N-00000200)
    (add_net N-00000202)
    (add_net N-00000203)
    (add_net N-00000205)
    (add_net N-00000206)
    (add_net N-00000207)
    (add_net N-00000211)
    (add_net N-00000213)
    (add_net N-00000214)
    (add_net N-00000217)
    (add_net N-00000218)
    (add_net N-00000232)
    (add_net N-00000233)
    (add_net N-00000235)
    (add_net N-00000249)
    (add_net N-00000250)
    (add_net N-00000251)
    (add_net N-00000254)
    (add_net N-00000255)
    (add_net N-00000256)
    (add_net N-00000257)
    (add_net N-00000258)
    (add_net N-00000259)
    (add_net N-00000260)
    (add_net N-00000261)
    (add_net N-00000262)
    (add_net N-00000263)
    (add_net N-00000266)
    (add_net N-00000268)
    (add_net N-00000269)
    (add_net N-00000271)
    (add_net N-00000275)
    (add_net N-00000279)
    (add_net N-00000280)
    (add_net N-00000288)
    (add_net N-00000289)
    (add_net N-00000290)
    (add_net N-00000292)
    (add_net N-00000298)
    (add_net N-00000300)
    (add_net N-00000301)
    (add_net N-00000302)
    (add_net N-00000303)
    (add_net N-00000304)
    (add_net N-00000305)
    (add_net N-00000306)
    (add_net N-00000308)
    (add_net N-00000309)
    (add_net N-00000312)
    (add_net N-00000313)
    (add_net N-00000314)
    (add_net N-00000316)
    (add_net N-00000319)
    (add_net N-00000327)
    (add_net N-00000330)
    (add_net N-00000331)
    (add_net N-00000332)
    (add_net N-00000333)
    (add_net N-00000335)
    (add_net N-00000336)
    (add_net N-00000337)
    (add_net N-00000339)
    (add_net N-00000340)
    (add_net N-00000341)
    (add_net N-00000342)
    (add_net N-00000343)
    (add_net N-00000344)
    (add_net N-00000345)
    (add_net N-00000346)
    (add_net N-00000348)
    (add_net N-00000349)
    (add_net N-00000350)
    (add_net N-00000351)
    (add_net N-00000352)
    (add_net N-00000353)
    (add_net N-00000354)
    (add_net N-00000357)
    (add_net N-00000359)
    (add_net N-00000360)
    (add_net N-00000361)
    (add_net N-00000362)
    (add_net N-00000363)
    (add_net N-00000364)
    (add_net N-00000365)
    (add_net N-00000366)
    (add_net N-00000367)
    (add_net N-00000368)
    (add_net N-00000369)
    (add_net N-00000370)
    (add_net N-00000372)
    (add_net N-00000373)
    (add_net N-00000377)
    (add_net N-00000382)
    (add_net N-00000387)
    (add_net N-00000388)
    (add_net N-00000391)
    (add_net N-00000400)
    (add_net N-00000409)
    (add_net N-00000410)
    (add_net N-00000411)
    (add_net N-00000412)
    (add_net N-00000413)
    (add_net N-00000414)
    (add_net N-00000415)
    (add_net N-00000416)
    (add_net N-00000417)
    (add_net N-00000418)
    (add_net N-00000419)
    (add_net N-00000420)
    (add_net N-00000421)
    (add_net N-00000422)
    (add_net N-00000424)
    (add_net N-00000425)
    (add_net N-00000426)
    (add_net N-00000427)
    (add_net N-00000428)
    (add_net N-00000429)
    (add_net N-00000430)
    (add_net N-00000431)
    (add_net N-00000432)
    (add_net N-00000433)
    (add_net VCC12V0)
    (add_net VCC1V2)
    (add_net VCC1V5)
    (add_net VCC3V3)
    (add_net VCC4V0)
    (add_net VTTDDR0)
    (add_net VTTREF)
  )
  (module B560C-SMC   locked (layer TOP) (tedit 55260A96)
    (at 271.5148 103.572)
    (fp_text reference D5 (at 5.8039 0) (layer F.SilkS))
    (fp_text value DIODE (at 0 5.4) (layer F.SilkS) hide)
    (pad 1 smd rect (at -3.4 0) (size 2.5 3.3)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 3.4 0) (size 2.5 3.3)
      (layers TOP F.Paste F.Mask)
      (net 437 N-00000367)
    )
  )
  (module pin_array_8x2 (layer TOP) (tedit 56373D7F)
    (at 129.8067 126.51486)
    (descr "Double rangee de contacts 2 x 8 pins")
    (tags CONN)
    (fp_text reference P28 (at -0.56642 -2.1209) (layer F.SilkS))
    (fp_text value eCONN_8 (at 0 3.302) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -8.89 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 223 /FPGA_Bank_1_2/SD_DAT1)
    )
    (pad 2 thru_hole circle (at -6.35 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 222 /FPGA_Bank_1_2/SD_DAT0)
    )
    (pad 3 thru_hole circle (at -3.81 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 220 /FPGA_Bank_1_2/SD_CLK)
    )
    (pad 4 thru_hole circle (at -1.27 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 221 /FPGA_Bank_1_2/SD_CMD)
    )
    (pad 5 thru_hole circle (at 1.27 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 225 /FPGA_Bank_1_2/SD_DAT3)
    )
    (pad 6 thru_hole circle (at 3.81 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 224 /FPGA_Bank_1_2/SD_DAT2)
    )
    (pad 7 thru_hole circle (at 6.35 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (pad 8 thru_hole circle (at 8.89 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_2x08_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552604FB)
    (at 226.949 202.625 270)
    (attr smd)
    (fp_text reference R27 (at 2.607 0.026 270) (layer F.SilkS))
    (fp_text value 330R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 400 N-00000312)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 219 /FPGA_Bank_1_2/INIT_B)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module Display_Port (layer TOP) (tedit 56373E02)
    (at 259.7597 215.73998)
    (descr "Display Port 1.1a")
    (tags 670-2589-1-ND)
    (fp_text reference J9 (at 10.1346 2.9718) (layer F.SilkS))
    (fp_text value DISPLAY_PORT (at 0 5.08) (layer F.SilkS) hide)
    (pad 12 smd rect (at 0 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 456 N-00000416)
    )
    (pad 11 smd rect (at 0.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 10 smd rect (at 1 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 455 N-00000415)
    )
    (pad 9 smd rect (at 1.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 454 N-00000414)
    )
    (pad 8 smd rect (at 2 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at 2.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 453 N-00000413)
    )
    (pad 6 smd rect (at 3 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 449 N-00000409)
    )
    (pad 5 smd rect (at 3.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at 4 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 450 N-00000410)
    )
    (pad 3 smd rect (at 4.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 451 N-00000411)
    )
    (pad 13 smd rect (at -0.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 51 /DisplayPort/DPRXCONFIG1)
    )
    (pad 14 smd rect (at -1 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 52 /DisplayPort/DPRXCONFIG2)
    )
    (pad 15 smd rect (at -1.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 464 N-00000425)
    )
    (pad 16 smd rect (at -2 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 17 smd rect (at -2.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 463 N-00000424)
    )
    (pad 18 smd rect (at -3 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 215 /FPGA_Bank_1_2/DPRXHPD)
    )
    (pad 19 smd rect (at -3.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 20 smd rect (at -4 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 469 N-00000430)
    )
    (pad 0 thru_hole oval (at -8.25 0) (size 1.3 2.3) (drill oval 0.65 1.65)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 8.25 0) (size 1.3 2.3) (drill oval 0.65 1.65)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at -8.25 6.78) (size 1.3 1.9) (drill oval 0.65 1.2)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 8.25 6.78) (size 1.3 1.9) (drill oval 0.65 1.2)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad "" np_thru_hole circle (at 0 7.68) (size 1.45 1.45) (drill 1.45)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad 2 smd rect (at 5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at 5.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 452 N-00000412)
    )
  )
  (module MH-4MM   locked (layer TOP) (tedit 5624E0B1)
    (at 122.809 61.976)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference 1PIN (at 0 -3.81) (layer F.SilkS) hide)
    (fp_text value P*** (at 0 2.794) (layer F.SilkS) hide)
    (pad "" thru_hole circle (at 1.194 -0.251) (size 6 6) (drill 3.97)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module MH-4MM   locked (layer TOP) (tedit 5624E29D)
    (at 277.368 260.731)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference 1PIN (at 0 -3.81) (layer F.SilkS) hide)
    (fp_text value P*** (at 0 2.794) (layer F.SilkS) hide)
    (pad "" thru_hole circle (at 4.115 -44.066) (size 6 6) (drill 3.97)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module MH-4MM   locked (layer TOP) (tedit 5624E0D6)
    (at 301.498 40.894)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference 1PIN (at 0 -3.81) (layer F.SilkS) hide)
    (fp_text value P*** (at 0 2.794) (layer F.SilkS) hide)
    (pad "" thru_hole circle (at -20.015 20.831) (size 6 6) (drill 3.97)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module GBU6B-BP   locked (layer TOP) (tedit 55F1785F)
    (at 276.9489 78.53934 180)
    (fp_text reference U4 (at 7.5946 3.64236 180) (layer F.SilkS))
    (fp_text value GBU15005-G (at 7.112 4.318 180) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0 180) (size 2.3 2.3) (drill 1.3)
      (layers *.Cu *.Mask F.SilkS)
      (net 326 "/Power/VIN 48")
    )
    (pad 2 thru_hole circle (at 5 0 180) (size 2.3 2.3) (drill 1.3)
      (layers *.Cu *.Mask F.SilkS)
      (net 324 "/Power/VIN +48V")
    )
    (pad 3 thru_hole circle (at 10 0 180) (size 2.3 2.3) (drill 1.3)
      (layers *.Cu *.Mask F.SilkS)
      (net 325 "/Power/VIN -48V")
    )
    (pad 4 thru_hole circle (at 15 0 180) (size 2.3 2.3) (drill 1.3)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module "QFN48(RTL8211E)"   locked (layer TOP) (tedit 55F00435)
    (at 141.353 92.989 270)
    (attr smd)
    (fp_text reference U20 (at -7.2108 2.9698 270) (layer F.SilkS))
    (fp_text value RTL8211E-VB (at 4.699 -3.81 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -3 -2.2 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 374 N-00000259)
    )
    (pad 2 smd rect (at -3 -1.8 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 376 N-00000261)
    )
    (pad 3 smd rect (at -3 -1.4 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 4 smd rect (at -3 -1 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 377 N-00000262)
    )
    (pad 5 smd rect (at -3 -0.6 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 368 N-00000251)
    )
    (pad 6 smd rect (at -3 -0.2 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 73 /Ethernet/AVDD3V3)
    )
    (pad 7 smd rect (at -3 0.2 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 370 N-00000255)
    )
    (pad 8 smd rect (at -3 0.6 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 371 N-00000256)
    )
    (pad 9 smd rect (at -3 1 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 10 smd rect (at -3 1.4 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 372 N-00000257)
    )
    (pad 11 smd rect (at -3 1.8 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 369 N-00000254)
    )
    (pad 12 smd rect (at -3 2.2 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
    )
    (pad 33 smd rect (at 3 -1 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
    )
    (pad 34 smd rect (at 3 -1.4 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 375 N-00000260)
    )
    (pad 35 smd rect (at 3 -1.8 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 378 N-00000263)
    )
    (pad 36 smd rect (at 3 -2.2 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 17 smd rect (at -0.6 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 82 /Ethernet/ETH_RXD2)
    )
    (pad 18 smd rect (at -0.2 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 83 /Ethernet/ETH_RXD3)
    )
    (pad 19 smd rect (at 0.2 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 78 /Ethernet/ETH_RXCLK)
    )
    (pad 20 smd rect (at 0.6 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 74 /Ethernet/ETH_INT_B)
    )
    (pad 21 smd rect (at 1 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 22 smd rect (at 1.4 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 84 /Ethernet/ETH_TXCLK)
    )
    (pad 23 smd rect (at 1.8 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 86 /Ethernet/ETH_TXD0)
    )
    (pad 24 smd rect (at 2.2 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 87 /Ethernet/ETH_TXD1)
    )
    (pad P smd rect (at 0 0 270) (size 4.6 4.6)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 13 smd rect (at -2.2 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 79 /Ethernet/ETH_RXCTL)
    )
    (pad 14 smd rect (at -1.8 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 80 /Ethernet/ETH_RXD0)
    )
    (pad 15 smd rect (at -1.4 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 16 smd rect (at -1 3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 81 /Ethernet/ETH_RXD1)
    )
    (pad 25 smd rect (at 3 2.2 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 88 /Ethernet/ETH_TXD2)
    )
    (pad 26 smd rect (at 3 1.8 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 89 /Ethernet/ETH_TXD3)
    )
    (pad 27 smd rect (at 3 1.4 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 85 /Ethernet/ETH_TXCTL)
    )
    (pad 28 smd rect (at 3 1 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 29 smd rect (at 3 0.6 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 77 /Ethernet/ETH_RESET_B)
    )
    (pad 30 smd rect (at 3 0.2 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 75 /Ethernet/ETH_MDC)
    )
    (pad 31 smd rect (at 3 -0.2 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 76 /Ethernet/ETH_MDIO)
    )
    (pad 32 smd rect (at 3 -0.6 270) (size 0.75 0.24892)
      (layers TOP F.Paste F.Mask)
      (net 379 N-00000266)
    )
    (pad 37 smd rect (at 2.2 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 38 smd rect (at 1.8 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 39 smd rect (at 1.4 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 373 N-00000258)
    )
    (pad 40 smd rect (at 1 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 41 smd rect (at 0.6 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 73 /Ethernet/AVDD3V3)
    )
    (pad 42 smd rect (at 0.2 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 98 /Ethernet/XTAL1_50MHZ)
    )
    (pad 43 smd rect (at -0.2 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 99 /Ethernet/XTAL2_50MHZ)
    )
    (pad 44 smd rect (at -0.6 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
    )
    (pad 45 smd rect (at -1 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
    )
    (pad 46 smd rect (at -1.4 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
    )
    (pad 47 smd rect (at -1.8 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 48 smd rect (at -2.2 -3 270) (size 0.24892 0.75)
      (layers TOP F.Paste F.Mask)
    )
  )
  (module MICRO_USB_B   locked (layer TOP) (tedit 56373DAB)
    (at 167.386 58.166 180)
    (fp_text reference J1 (at 5.08 -5.13 180) (layer F.SilkS))
    (fp_text value USB_MICRO_B (at -0.02 2.42 180) (layer F.SilkS) hide)
    (pad 0 thru_hole rect (at -3.6 -0.4 180) (size 2.5 3) (drill oval 0.9 1.4)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
      (clearance 0.01)
    )
    (pad 0 thru_hole rect (at 3.6 -0.4 180) (size 2.5 3) (drill oval 0.9 1.4)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
      (clearance 0.01)
    )
    (pad 3 smd rect (at 0 -3.275 180) (size 0.4 1.6)
      (layers TOP F.Paste F.Mask)
      (net 339 /USB/USB_DP)
    )
    (pad 4 smd rect (at 0.65 -3.275 180) (size 0.4 1.6)
      (layers TOP F.Paste F.Mask)
      (net 335 /USB/ID)
    )
    (pad 2 smd rect (at -0.65 -3.275 180) (size 0.4 1.6)
      (layers TOP F.Paste F.Mask)
      (net 338 /USB/USB_DM)
    )
    (pad 5 smd rect (at 1.3 -3.275 180) (size 0.4 1.6)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at -1.3 -3.275 180) (size 0.4 1.6)
      (layers TOP F.Paste F.Mask)
      (net 337 /USB/USB_5V)
    )
    (pad 0 thru_hole oval (at -2.5 -3.275 180) (size 1.45 1.2) (drill oval 1 0.6)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 2.5 -3.275 180) (size 1.45 1.2) (drill oval 1 0.6)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module SSOP38_ip4776   locked (layer TOP) (tedit 55F17CA3)
    (at 130.3469 206.0788 180)
    (descr SSOP56)
    (attr smd)
    (fp_text reference U13 (at -1.0727 6.0284 180) (layer F.SilkS))
    (fp_text value IP4776CZ38 (at 0.29972 0.55118 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -4.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at -4 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 3 smd rect (at -3.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at -3 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 261 /FPGA_Bank_1_2/TMDS_TX1_2_P)
    )
    (pad 5 smd rect (at -2.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 6 smd rect (at -2 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 260 /FPGA_Bank_1_2/TMDS_TX1_2_N)
    )
    (pad 7 smd rect (at -1.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 259 /FPGA_Bank_1_2/TMDS_TX1_1_P)
    )
    (pad 8 smd rect (at -1 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 9 smd rect (at -0.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 258 /FPGA_Bank_1_2/TMDS_TX1_1_N)
    )
    (pad 10 smd rect (at 0 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 257 /FPGA_Bank_1_2/TMDS_TX1_0_P)
    )
    (pad 11 smd rect (at 0.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at 1 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 256 /FPGA_Bank_1_2/TMDS_TX1_0_N)
    )
    (pad 13 smd rect (at 1.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 264 /FPGA_Bank_1_2/TMDS_TX1_CLK_P)
    )
    (pad 14 smd rect (at 2 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 15 smd rect (at 2.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 263 /FPGA_Bank_1_2/TMDS_TX1_CLK_N)
    )
    (pad 16 smd rect (at 3 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 262 /FPGA_Bank_1_2/TMDS_TX1_CEC)
    )
    (pad 17 smd rect (at 3.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 266 /FPGA_Bank_1_2/TMDS_TX1_SCL)
    )
    (pad 18 smd rect (at 4 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 267 /FPGA_Bank_1_2/TMDS_TX1_SDA)
    )
    (pad 19 smd rect (at 4.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 265 /FPGA_Bank_1_2/TMDS_TX1_HOT)
    )
    (pad 24 smd rect (at 2.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 263 /FPGA_Bank_1_2/TMDS_TX1_CLK_N)
    )
    (pad 23 smd rect (at 3 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 310 /HDMI/P2-CEC)
    )
    (pad 22 smd rect (at 3.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 312 /HDMI/P2-SCL)
    )
    (pad 21 smd rect (at 4 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 313 /HDMI/P2-SDA)
    )
    (pad 25 smd rect (at 2 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 26 smd rect (at 1.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 264 /FPGA_Bank_1_2/TMDS_TX1_CLK_P)
    )
    (pad 27 smd rect (at 1 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 256 /FPGA_Bank_1_2/TMDS_TX1_0_N)
    )
    (pad 28 smd rect (at 0.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 29 smd rect (at 0 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 257 /FPGA_Bank_1_2/TMDS_TX1_0_P)
    )
    (pad 30 smd rect (at -0.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 258 /FPGA_Bank_1_2/TMDS_TX1_1_N)
    )
    (pad 31 smd rect (at -1 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 32 smd rect (at -1.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 259 /FPGA_Bank_1_2/TMDS_TX1_1_P)
    )
    (pad 33 smd rect (at -2 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 260 /FPGA_Bank_1_2/TMDS_TX1_2_N)
    )
    (pad 34 smd rect (at -2.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 35 smd rect (at -3 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 261 /FPGA_Bank_1_2/TMDS_TX1_2_P)
    )
    (pad 20 smd rect (at 4.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 311 /HDMI/P2-HOT)
    )
    (pad 36 smd rect (at -3.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 37 smd rect (at -4 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 447 N-00000391)
    )
    (pad 38 smd rect (at -4.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
    )
  )
  (module "DO-214AC(SMA)"   locked (layer BOTTOM) (tedit 55F282CC)
    (at 250.825 71.247)
    (descr "DO-214AC (SMA)  PACKAGE.")
    (tags "DO-214AC SMA")
    (attr smd)
    (fp_text reference D8 (at 4.4196 0) (layer B.SilkS))
    (fp_text value DIODESCH (at 0 -2.79908) (layer B.SilkS) hide)
    (pad 1 smd rect (at -2.1 0) (size 2 2.19964)
      (layers BOTTOM B.Paste B.Mask)
      (net 323 "/Power/Consumer 12V")
    )
    (pad 2 smd rect (at 2.1 0) (size 2 2.19964)
      (layers BOTTOM B.Paste B.Mask)
      (net 441 N-00000372)
    )
    (model SMD_Packages.3dshapes/DO-214-AC_SMA.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.95 0.95 0.95))
      (rotate (xyz 0 0 0))
    )
  )
  (module "DO-214AC(SMA)"   locked (layer BOTTOM) (tedit 56405925)
    (at 250.063 78.105 90)
    (descr "DO-214AC (SMA)  PACKAGE.")
    (tags "DO-214AC SMA")
    (attr smd)
    (fp_text reference D6 (at -0.07 3.087 90) (layer B.SilkS))
    (fp_text value DIODESCH (at 0 -2.79908 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -2.1 0 90) (size 2 2.19964)
      (layers BOTTOM B.Paste B.Mask)
      (net 322 "/Power/Conference 12V")
    )
    (pad 2 smd rect (at 2.1 0 90) (size 2 2.19964)
      (layers BOTTOM B.Paste B.Mask)
      (net 441 N-00000372)
    )
    (model SMD_Packages.3dshapes/DO-214-AC_SMA.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.95 0.95 0.95))
      (rotate (xyz 0 0 0))
    )
  )
  (module "DO-214AC(SMA)"   locked (layer TOP) (tedit 55279FD4)
    (at 250.063 78.105 90)
    (descr "DO-214AC (SMA)  PACKAGE.")
    (tags "DO-214AC SMA")
    (attr smd)
    (fp_text reference D7 (at 0 -2.794 90) (layer F.SilkS))
    (fp_text value DIODESCH (at 0 2.79908 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.1 0 90) (size 2 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 322 "/Power/Conference 12V")
    )
    (pad 2 smd rect (at 2.1 0 90) (size 2 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 441 N-00000372)
    )
    (model SMD_Packages.3dshapes/DO-214-AC_SMA.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.95 0.95 0.95))
      (rotate (xyz 0 0 0))
    )
  )
  (module "DO-214AC(SMA)"   locked (layer TOP) (tedit 55279FBA)
    (at 250.825 71.247)
    (descr "DO-214AC (SMA)  PACKAGE.")
    (tags "DO-214AC SMA")
    (attr smd)
    (fp_text reference D9 (at 0 -2.794) (layer F.SilkS))
    (fp_text value DIODESCH (at 0 2.79908) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.1 0) (size 2 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 323 "/Power/Consumer 12V")
    )
    (pad 2 smd rect (at 2.1 0) (size 2 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 441 N-00000372)
    )
    (model SMD_Packages.3dshapes/DO-214-AC_SMA.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.95 0.95 0.95))
      (rotate (xyz 0 0 0))
    )
  )
  (module USB_B   locked (layer TOP) (tedit 5626171F)
    (at 216.4842 216.6874)
    (tags USB)
    (fp_text reference J7 (at -7.33806 -6.08838) (layer F.SilkS))
    (fp_text value USB (at 5.9 -11.1) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 1.27 -4.699) (size 1.524 1.524) (drill 0.8128)
      (layers *.Cu *.Mask F.SilkS)
      (net 403 N-00000316)
    )
    (pad 2 thru_hole circle (at -1.27 -4.699) (size 1.524 1.524) (drill 0.8128)
      (layers *.Cu *.Mask F.SilkS)
      (net 332 /USB/CYDN)
    )
    (pad 3 thru_hole circle (at -1.27 -2.70002) (size 1.524 1.524) (drill 0.8128)
      (layers *.Cu *.Mask F.SilkS)
      (net 333 /USB/CYDP)
    )
    (pad 4 thru_hole circle (at 1.27 -2.70002) (size 1.524 1.524) (drill 0.8128)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 5 thru_hole circle (at 5.99948 0) (size 3 3) (drill 2.30124)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 6 thru_hole circle (at -5.99948 0) (size 3 3) (drill 2.30124)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (model connectors.3dshapes/USB_type_B.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.3937 0.3937 0.3937))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526041E)
    (at 234.849 177.733)
    (attr smd)
    (fp_text reference R33 (at 2.768 0.067) (layer F.SilkS))
    (fp_text value 2.2K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 336 /USB/U1-SDA)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5625D9BD)
    (at 218.085 202.625 270)
    (attr smd)
    (fp_text reference R15 (at -1.9015 0.35112 360) (layer F.SilkS))
    (fp_text value 330R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 395 N-00000304)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 295 /FPGA_Power/PROG_B)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262ACE)
    (at 215.672 195.4622)
    (attr smd)
    (fp_text reference C39 (at -0.026 -1.2792) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A93)
    (at 215.672 179.2062)
    (attr smd)
    (fp_text reference C43 (at 3.022 -0.0092) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552604EE)
    (at 223.419 202.625 270)
    (attr smd)
    (fp_text reference R26 (at 2.734 0.026 270) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 394 N-00000303)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 298 /FPGA_Power/TCK)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer TOP) (tedit 55260501)
    (at 228.727 202.625 270)
    (attr smd)
    (fp_text reference R28 (at 2.607 -0.101 270) (layer F.SilkS))
    (fp_text value 330R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 398 N-00000308)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 294 /FPGA_Power/DONE)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526042C)
    (at 234.849 183.067)
    (attr smd)
    (fp_text reference R32 (at 2.768 0.067) (layer F.SilkS))
    (fp_text value 10K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 390 N-00000298)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260505)
    (at 225.197 202.625 270)
    (attr smd)
    (fp_text reference R31 (at 2.607 0.026 270) (layer F.SilkS))
    (fp_text value 1.5K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 401 N-00000313)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 402 N-00000314)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5626175D)
    (at 221.641 202.625 270)
    (attr smd)
    (fp_text reference R24 (at 2.74924 -0.06798 270) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 393 N-00000302)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 299 /FPGA_Power/TMS)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260428)
    (at 234.849 181.289)
    (attr smd)
    (fp_text reference R37 (at 2.768 0.067) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 389 N-00000292)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262AA4)
    (at 227.61 184.3878 180)
    (attr smd)
    (fp_text reference C54 (at 2.947 -0.0162 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260423)
    (at 234.849 179.511)
    (attr smd)
    (fp_text reference R34 (at 2.768 0.067) (layer F.SilkS))
    (fp_text value 2.2K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 94 /Ethernet/MAC_SCL)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A81)
    (at 223.2666 178.368 270)
    (attr smd)
    (fp_text reference C66 (at -0.06 1.5246 270) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5625D8A7)
    (at 216.307 202.625 270)
    (attr smd)
    (fp_text reference R14 (at 0.01366 1.22488 270) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 391 N-00000300)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 329 /SPI_Flash/TDO-FPGA/TDO-JTAG)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5625D9B7)
    (at 219.863 202.625 270)
    (attr smd)
    (fp_text reference R23 (at -1.89134 -0.34484 360) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 392 N-00000301)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 330 /SPI_Flash/TDO-USB/TDI-FPGA)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module "TQFP-100_(CY7C68013A-100AXC)"   locked (layer TOP) (tedit 5626187A)
    (at 221.641 187.3342 180)
    (descr "PQFP100 14x20 / QIP100E CASE 122BV (see ON Semiconductor 122BV.PDF)")
    (tags "QFP 0.65")
    (attr smd)
    (fp_text reference U2 (at -10.9976 -9.338 180) (layer F.SilkS))
    (fp_text value CY7C68013A_100AC (at -0.02 14.55 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -8.15 -9.425 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at -8.15 -8.775 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 3 smd rect (at -8.15 -8.125 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 203 /FPGA_Bank_1_2/CY_RD0)
    )
    (pad 4 smd rect (at -8.15 -7.475 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 204 /FPGA_Bank_1_2/CY_RD1)
    )
    (pad 5 smd rect (at -8.15 -6.825 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 205 /FPGA_Bank_1_2/CY_RD2)
    )
    (pad 6 smd rect (at -8.15 -6.175 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 206 /FPGA_Bank_1_2/CY_RD3)
    )
    (pad 7 smd rect (at -8.15 -5.525 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 207 /FPGA_Bank_1_2/CY_RD4)
    )
    (pad 8 smd rect (at -8.15 -4.875 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 208 /FPGA_Bank_1_2/CY_RD5)
    )
    (pad 9 smd rect (at -8.15 -4.225 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 10 smd rect (at -8.15 -3.575 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 341 /USB/XTALIOUT)
    )
    (pad 11 smd rect (at -8.15 -2.925 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 340 /USB/XTALIN)
    )
    (pad 12 smd rect (at -8.15 -2.275 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 13 smd rect (at -8.15 -1.625 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
    )
    (pad 14 smd rect (at -8.15 -0.975 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
    )
    (pad 15 smd rect (at -8.15 -0.325 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
    )
    (pad 16 smd rect (at -8.15 0.325 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 17 smd rect (at -8.15 0.975 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 333 /USB/CYDP)
    )
    (pad 18 smd rect (at -8.15 1.625 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 332 /USB/CYDN)
    )
    (pad 19 smd rect (at -8.15 2.275 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 20 smd rect (at -8.15 2.925 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 21 smd rect (at -8.15 3.575 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 22 smd rect (at -8.15 4.225 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 390 N-00000298)
    )
    (pad 23 smd rect (at -8.15 4.875 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 211 /FPGA_Bank_1_2/CY_T0)
    )
    (pad 24 smd rect (at -8.15 5.525 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 399 N-00000309)
    )
    (pad 25 smd rect (at -8.15 6.175 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 386 N-00000288)
    )
    (pad 26 smd rect (at -8.15 6.825 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 161 /FPGA_Bank_1_2/CY-IFCLK)
    )
    (pad 27 smd rect (at -8.15 7.475 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 389 N-00000292)
    )
    (pad 28 smd rect (at -8.15 8.125 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 387 N-00000289)
    )
    (pad 29 smd rect (at -8.15 8.775 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 94 /Ethernet/MAC_SCL)
    )
    (pad 30 smd rect (at -8.15 9.425 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 336 /USB/U1-SDA)
    )
    (pad 31 smd rect (at -6.175 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 202 /FPGA_Bank_1_2/CY_RD)
    )
    (pad 32 smd rect (at -5.525 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 214 /FPGA_Bank_1_2/CY_WR)
    )
    (pad 33 smd rect (at -4.875 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 34 smd rect (at -4.225 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 169 /FPGA_Bank_1_2/CY_FD0)
    )
    (pad 35 smd rect (at -3.575 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 170 /FPGA_Bank_1_2/CY_FD1)
    )
    (pad 36 smd rect (at -2.925 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 177 /FPGA_Bank_1_2/CY_FD2)
    )
    (pad 37 smd rect (at -2.275 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 178 /FPGA_Bank_1_2/CY_FD3)
    )
    (pad 38 smd rect (at -1.625 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 39 smd rect (at -0.975 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 40 smd rect (at -0.325 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 212 /FPGA_Bank_1_2/CY_TXD0)
    )
    (pad 41 smd rect (at 0.325 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 209 /FPGA_Bank_1_2/CY_RXD0)
    )
    (pad 42 smd rect (at 0.975 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 213 /FPGA_Bank_1_2/CY_TXD1)
    )
    (pad 43 smd rect (at 1.625 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 210 /FPGA_Bank_1_2/CY_RXD1)
    )
    (pad 44 smd rect (at 2.275 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 179 /FPGA_Bank_1_2/CY_FD4)
    )
    (pad 45 smd rect (at 2.925 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 180 /FPGA_Bank_1_2/CY_FD5)
    )
    (pad 46 smd rect (at 3.575 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 181 /FPGA_Bank_1_2/CY_FD6)
    )
    (pad 47 smd rect (at 4.225 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 182 /FPGA_Bank_1_2/CY_FD7)
    )
    (pad 48 smd rect (at 4.875 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 49 smd rect (at 5.525 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 50 smd rect (at 6.175 11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 51 smd rect (at 8.15 9.425 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 166 /FPGA_Bank_1_2/CY_CTL3)
    )
    (pad 52 smd rect (at 8.15 8.775 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 167 /FPGA_Bank_1_2/CY_CTL4)
    )
    (pad 53 smd rect (at 8.15 8.125 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 54 smd rect (at 8.15 7.475 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 163 /FPGA_Bank_1_2/CY_CTL0)
    )
    (pad 55 smd rect (at 8.15 6.825 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 164 /FPGA_Bank_1_2/CY_CTL1)
    )
    (pad 56 smd rect (at 8.15 6.175 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 165 /FPGA_Bank_1_2/CY_CTL2)
    )
    (pad 57 smd rect (at 8.15 5.525 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 194 /FPGA_Bank_1_2/CY_PC0)
    )
    (pad 58 smd rect (at 8.15 4.875 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 195 /FPGA_Bank_1_2/CY_PC1)
    )
    (pad 59 smd rect (at 8.15 4.225 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 196 /FPGA_Bank_1_2/CY_PC2)
    )
    (pad 60 smd rect (at 8.15 3.575 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 197 /FPGA_Bank_1_2/CY_PC3)
    )
    (pad 61 smd rect (at 8.15 2.925 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 198 /FPGA_Bank_1_2/CY_PC4)
    )
    (pad 62 smd rect (at 8.15 2.275 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 199 /FPGA_Bank_1_2/CY_PC5)
    )
    (pad 63 smd rect (at 8.15 1.625 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 200 /FPGA_Bank_1_2/CY_PC6)
    )
    (pad 64 smd rect (at 8.15 0.975 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 201 /FPGA_Bank_1_2/CY_PC7)
    )
    (pad 65 smd rect (at 8.15 0.325 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 66 smd rect (at 8.15 -0.325 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 67 smd rect (at 8.15 -0.975 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 186 /FPGA_Bank_1_2/CY_PA0)
    )
    (pad 68 smd rect (at 8.15 -1.625 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 187 /FPGA_Bank_1_2/CY_PA1)
    )
    (pad 69 smd rect (at 8.15 -2.275 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 188 /FPGA_Bank_1_2/CY_PA2)
    )
    (pad 70 smd rect (at 8.15 -2.925 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 189 /FPGA_Bank_1_2/CY_PA3)
    )
    (pad 71 smd rect (at 8.15 -3.575 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 190 /FPGA_Bank_1_2/CY_PA4)
    )
    (pad 72 smd rect (at 8.15 -4.225 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 191 /FPGA_Bank_1_2/CY_PA5)
    )
    (pad 73 smd rect (at 8.15 -4.875 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 192 /FPGA_Bank_1_2/CY_PA6)
    )
    (pad 74 smd rect (at 8.15 -5.525 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 193 /FPGA_Bank_1_2/CY_PA7)
    )
    (pad 75 smd rect (at 8.15 -6.175 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 76 smd rect (at 8.15 -6.825 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 168 /FPGA_Bank_1_2/CY_CTL5)
    )
    (pad 77 smd rect (at 8.15 -7.475 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 334 /USB/CYP-RESET)
    )
    (pad 78 smd rect (at 8.15 -8.125 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 79 smd rect (at 8.15 -8.775 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 388 N-00000290)
    )
    (pad 80 smd rect (at 8.15 -9.425 180) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 183 /FPGA_Bank_1_2/CY_FD8)
    )
    (pad 81 smd rect (at 6.175 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 184 /FPGA_Bank_1_2/CY_FD9)
    )
    (pad 82 smd rect (at 5.525 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 171 /FPGA_Bank_1_2/CY_FD10)
    )
    (pad 83 smd rect (at 4.875 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 172 /FPGA_Bank_1_2/CY_FD11)
    )
    (pad 84 smd rect (at 4.225 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 185 /FPGA_Bank_1_2/CY_INT5)
    )
    (pad 85 smd rect (at 3.575 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 86 smd rect (at 2.925 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 391 N-00000300)
    )
    (pad 87 smd rect (at 2.275 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 395 N-00000304)
    )
    (pad 88 smd rect (at 1.625 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 392 N-00000301)
    )
    (pad 89 smd rect (at 0.975 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 393 N-00000302)
    )
    (pad 90 smd rect (at 0.325 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 394 N-00000303)
    )
    (pad 91 smd rect (at -0.325 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 401 N-00000313)
    )
    (pad 92 smd rect (at -0.975 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 400 N-00000312)
    )
    (pad 93 smd rect (at -1.625 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 398 N-00000308)
    )
    (pad 94 smd rect (at -2.275 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 95 smd rect (at -2.925 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 173 /FPGA_Bank_1_2/CY_FD12)
    )
    (pad 96 smd rect (at -3.575 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 174 /FPGA_Bank_1_2/CY_FD13)
    )
    (pad 97 smd rect (at -4.225 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 175 /FPGA_Bank_1_2/CY_FD14)
    )
    (pad 98 smd rect (at -4.875 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 176 /FPGA_Bank_1_2/CY_FD15)
    )
    (pad 99 smd rect (at -5.525 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 100 smd rect (at -6.175 -11.15 270) (size 1.3 0.43)
      (layers TOP F.Paste F.Mask)
    )
    (model Housings_QFP.3dshapes/PQFP-100_14x20mm_Pitch0.65mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A83)
    (at 226.5178 178.368 270)
    (attr smd)
    (fp_text reference C58 (at -0.06 -1.5742 270) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A91)
    (at 214.69604 177.11928 180)
    (attr smd)
    (fp_text reference C41 (at 2.47904 0.08128 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262ACC)
    (at 218.8718 196.85 90)
    (attr smd)
    (fp_text reference C42 (at 0 1.4732 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262AD8)
    (at 230.32466 199.18172 270)
    (attr smd)
    (fp_text reference C44 (at 0.00508 -1.92024 270) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A9C)
    (at 215.7482 187.639)
    (attr smd)
    (fp_text reference C40 (at 0.0248 -1.33) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262AAB)
    (at 227.61 187.004 180)
    (attr smd)
    (fp_text reference C53 (at 2.947 -0.067 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262AB4)
    (at 227.61 191.576 180)
    (attr smd)
    (fp_text reference C52 (at 2.947 0.06 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module HC-49V   locked (layer TOP) (tedit 552603C3)
    (at 237.897 190.5854 90)
    (descr "Quartz boitier HC-49 Vertical")
    (tags "QUARTZ DEV")
    (autoplace_cost180 10)
    (fp_text reference X1 (at -0.0416 4.165 90) (layer F.SilkS))
    (fp_text value CRYSTAL (at 0 3.81 90) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at -2.54 0 90) (size 1.4224 1.4224) (drill 0.762)
      (layers *.Cu *.Mask F.SilkS)
      (net 341 /USB/XTALIOUT)
    )
    (pad 2 thru_hole circle (at 2.54 0 90) (size 1.4224 1.4224) (drill 0.762)
      (layers *.Cu *.Mask F.SilkS)
      (net 340 /USB/XTALIN)
    )
    (model Crystals.3dshapes/Crystal_HC18-U_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262AE7)
    (at 241.453 193.1254)
    (attr smd)
    (fp_text reference C64 (at 2.768 -0.0854) (layer B.SilkS))
    (fp_text value 12pF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 341 /USB/XTALIOUT)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262AEB)
    (at 241.453 188.0454 180)
    (attr smd)
    (fp_text reference C62 (at -2.641 -0.0416 180) (layer B.SilkS))
    (fp_text value 12pF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 340 /USB/XTALIN)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module FXO-HC536R   locked (layer TOP) (tedit 55349F85)
    (at 195.7623 146.7921)
    (fp_text reference U17 (at -4.5003 -3.9171) (layer F.SilkS))
    (fp_text value FXO-HC536R (at 0 3.556) (layer F.SilkS) hide)
    (pad 4 smd rect (at -1.27 -1.12) (size 1.036 1.494)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 3 smd rect (at 1.27 -1.12) (size 1.036 1.494)
      (layers TOP F.Paste F.Mask)
      (net 293 /FPGA_Bank_1_2/100MHz)
    )
    (pad 2 smd rect (at 1.27 1.12) (size 1.036 1.494)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at -1.27 1.12) (size 1.036 1.494)
      (layers TOP F.Paste F.Mask)
      (net 357 N-00000207)
    )
  )
  (module SO8E_N   locked (layer TOP) (tedit 5526033C)
    (at 187.7314 153.8351 270)
    (descr "module CMS SOJ 8 pins etroit")
    (tags "CMS SOJ")
    (attr smd)
    (fp_text reference U3 (at -3.5941 2.5654 360) (layer F.SilkS))
    (fp_text value W25Q128FVEIG (at 0 1.016 270) (layer F.SilkS) hide)
    (pad 8 smd rect (at -1.905 -3.22 270) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 1 smd rect (at -1.905 3.22 270) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 227 /FPGA_Bank_1_2/SPI_CS_N)
    )
    (pad 7 smd rect (at -0.635 -3.22 270) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 229 /FPGA_Bank_1_2/SPI_D2_MISO3)
    )
    (pad 6 smd rect (at 0.635 -3.22 270) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 226 /FPGA_Bank_1_2/SPI_CLK)
    )
    (pad 5 smd rect (at 1.905 -3.22 270) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 231 /FPGA_Bank_1_2/SPI_MOSI_CSI_N_MISO0)
    )
    (pad 2 smd rect (at -0.635 3.22 270) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 347 N-00000193)
    )
    (pad 3 smd rect (at 0.635 3.22 270) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 346 N-00000192)
    )
    (pad 4 smd rect (at 1.905 3.22 270) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/cms_so8.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.5 0.32 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5385C0CC)
    (at 200.6903 134.0921 90)
    (attr smd)
    (fp_text reference R52 (at 0 -2.159 90) (layer B.SilkS))
    (fp_text value 4.7K (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 219 /FPGA_Bank_1_2/INIT_B)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A61)
    (at 187.49518 153.47696 180)
    (attr smd)
    (fp_text reference R19 (at 0.04318 1.58496 180) (layer B.SilkS))
    (fp_text value 10K (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 347 N-00000193)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 53859FDF)
    (at 129.413 116.459)
    (attr smd)
    (fp_text reference R62 (at -2.54 0) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 221 /FPGA_Bank_1_2/SD_CMD)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5624C16B)
    (at 182.50408 105.12044 270)
    (attr smd)
    (fp_text reference C201 (at 3.13436 -0.12192 270) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260122)
    (at 197.53072 68.06184 270)
    (attr smd)
    (fp_text reference R82 (at 2.80416 -0.08128 270) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 352 N-00000200)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 329 /SPI_Flash/TDO-FPGA/TDO-JTAG)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5540A1D1)
    (at 175.77562 100.88372 180)
    (attr smd)
    (fp_text reference C202 (at 0.12954 1.79324 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260128)
    (at 199.56272 68.06184 270)
    (attr smd)
    (fp_text reference R83 (at 2.80416 -0.08128 270) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 348 N-00000194)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 330 /SPI_Flash/TDO-USB/TDI-FPGA)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 56247D73)
    (at 199.3949 146.6143 90)
    (attr smd)
    (fp_text reference C189 (at -3.2203 0.1475 90) (layer F.SilkS))
    (fp_text value 15PF (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 293 /FPGA_Bank_1_2/100MHz)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 53A3D3B7)
    (at 195.3563 142.9821 180)
    (attr smd)
    (fp_text reference C188 (at -3.302 0 180) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 538591BE)
    (at 191.8511 146.8175 270)
    (attr smd)
    (fp_text reference R80 (at 0.1016 1.5748 270) (layer F.SilkS))
    (fp_text value 4K7 (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 357 N-00000207)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 53859FF2)
    (at 129.413 120.015)
    (attr smd)
    (fp_text reference R64 (at -2.54 0) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 223 /FPGA_Bank_1_2/SD_DAT1)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 53859FE9)
    (at 129.413 118.237)
    (attr smd)
    (fp_text reference R63 (at -2.54 -0.127) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
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    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 53859FD2)
    (at 129.413 114.681)
    (attr smd)
    (fp_text reference R61 (at -2.54 0) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 225 /FPGA_Bank_1_2/SD_DAT3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 53859FCA)
    (at 129.413 112.903)
    (attr smd)
    (fp_text reference R60 (at -2.54 0) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 224 /FPGA_Bank_1_2/SD_DAT2)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5385C1E2)
    (at 225.6839 131.36414)
    (attr smd)
    (fp_text reference R53 (at -2.53746 -0.00762) (layer B.SilkS))
    (fp_text value R (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 146 /FPGA_Bank_0_3/HSWAP)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A5D)
    (at 193.02476 152.66416 90)
    (attr smd)
    (fp_text reference R21 (at -2.91084 0.14224 90) (layer B.SilkS))
    (fp_text value 10K (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 229 /FPGA_Bank_1_2/SPI_D2_MISO3)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 53859E19)
    (at 184.49544 152.654 90)
    (attr smd)
    (fp_text reference R18 (at 3.175 -0.127 90) (layer B.SilkS))
    (fp_text value 10K (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 227 /FPGA_Bank_1_2/SPI_CS_N)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526032B)
    (at 192.151 159.9565 180)
    (attr smd)
    (fp_text reference R55 (at 2.54 -0.0635 180) (layer F.SilkS))
    (fp_text value 1K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 345 N-00000189)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260308)
    (at 198.1503 134.0921 90)
    (attr smd)
    (fp_text reference R56 (at -2.5599 -0.0303 90) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0 90) (layer F.SilkS) hide)
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      (layers TOP F.Paste F.Mask)
      (net 295 /FPGA_Power/PROG_B)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 539EBE15)
    (at 215.138 160.655 270)
    (attr smd)
    (fp_text reference R57 (at -2.794 0 270) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0 270) (layer F.SilkS) hide)
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      (layers TOP F.Paste F.Mask)
      (net 296 /FPGA_Power/RFS)
    )
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      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5385C0D4)
    (at 203.2303 131.0441)
    (attr smd)
    (fp_text reference R85 (at -2.667 0) (layer B.SilkS))
    (fp_text value 240E (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 365 N-00000235)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5385B98B)
    (at 224.8457 120.1729 180)
    (attr smd)
    (fp_text reference R1 (at 2.4384 0.0508 180) (layer B.SilkS))
    (fp_text value R (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 6 /DDR3/DDR0_A13)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 53859E2C)
    (at 187.41898 155.7401 180)
    (attr smd)
    (fp_text reference R20 (at 3.175 -0.127 180) (layer B.SilkS))
    (fp_text value 10K (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 346 N-00000192)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 56247D68)
    (at 196.9897 155.10002)
    (attr smd)
    (fp_text reference R17 (at 0.10414 -3.86334) (layer F.SilkS))
    (fp_text value 50R (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
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    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 228 /FPGA_Bank_1_2/SPI_D1_MISO2)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 56247D65)
    (at 197.12686 152.57018)
    (attr smd)
    (fp_text reference R16 (at -0.08382 3.96494) (layer F.SilkS))
    (fp_text value 50R (at 0 0) (layer F.SilkS) hide)
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      (layers TOP F.Paste F.Mask)
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    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
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    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8F8)
    (at 207.67784 134.03876)
    (attr smd)
    (fp_text reference C88 (at 0.63246 -1.08966) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 475 VCC1V5)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8E2)
    (at 218.91734 136.99532 270)
    (attr smd)
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    (fp_text value 0.1uF (at 0.09906 0 270) (layer B.SilkS) hide)
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      (net 475 VCC1V5)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8EA)
    (at 223.5757 134.0159)
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    (fp_text reference C86 (at -0.00254 -1.12014) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
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    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C845)
    (at 208.51114 146.10334 180)
    (attr smd)
    (fp_text reference C90 (at 0 0 180) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C923)
    (at 209.9486 135.92344 90)
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    )
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      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8DF)
    (at 215.53406 135.96662 90)
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    (fp_text reference C94 (at -1.23952 0.84836 90) (layer B.SilkS) hide)
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    )
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      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8DC)
    (at 214.4444 138.70982)
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    (fp_text reference C96 (at 2.68986 0.14732) (layer B.SilkS) hide)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
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    (at 226.5983 118.3441)
    (attr smd)
    (fp_text reference C209 (at 3.3987 0.0199) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8F2)
    (at 212.82134 133.84064 270)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8F5)
    (at 211.3202 133.87112 90)
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
  )
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
  )
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
  )
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    )
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    )
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    )
  )
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    (at 206.75582 131.72228)
    (attr smd)
    (fp_text reference C127 (at 2.57048 -0.04318) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 475 VCC1V5)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C917)
    (at 212.4583 151.68372 90)
    (attr smd)
    (fp_text reference C116 (at -2.7686 -0.04318 90) (layer B.SilkS) hide)
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      (layers BOTTOM B.Paste B.Mask)
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    )
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      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C91E)
    (at 218.24188 155.76296)
    (attr smd)
    (fp_text reference C118 (at 2.8956 0.04064) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
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      (layers BOTTOM B.Paste B.Mask)
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    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8D9)
    (at 221.2897 138.39994 90)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
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    (at 215.1683 145.9666 270)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
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      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
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    (at 213.4411 143.4901 180)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C92E)
    (at 215.10734 141.80608 270)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
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      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385CA88)
    (at 216.5018 145.9666 90)
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
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    (at 212.14316 142.9186 90)
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
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  (module SM0402   locked (layer BOTTOM) (tedit 5385C861)
    (at 217.79212 141.95848 270)
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
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    (at 213.4411 144.4045 180)
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
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    (at 220.5023 140.20588)
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
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    (at 224.42932 142.91564 270)
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
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    (at 227.457 139.827)
    (attr smd)
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    )
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    )
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      (rotate (xyz 0 0 0))
    )
  )
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    (at 220.6039 143.43168)
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
  )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    )
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    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BB31)
    (at 213.8983 105.6441 90)
    (attr smd)
    (fp_text reference C5 (at 1.778 0 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BB42)
    (at 211.8663 105.6441 90)
    (attr smd)
    (fp_text reference C6 (at 1.778 0 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BB11)
    (at 217.2003 105.6441 90)
    (attr smd)
    (fp_text reference C7 (at 1.778 -0.127 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BB1F)
    (at 216.1843 105.6441 90)
    (attr smd)
    (fp_text reference C8 (at 1.778 -0.127 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BB28)
    (at 214.9143 105.6441 90)
    (attr smd)
    (fp_text reference C9 (at 1.778 0 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 552629B0)
    (at 226.5983 110.9781)
    (attr smd)
    (fp_text reference C10 (at 3.5257 -0.1071) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BB4D)
    (at 210.8503 105.6441 90)
    (attr smd)
    (fp_text reference C11 (at 2.159 0 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BABD)
    (at 223.8043 105.6441 90)
    (attr smd)
    (fp_text reference C13 (at 2.032 0 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BAB0)
    (at 225.0743 105.6441 90)
    (attr smd)
    (fp_text reference C14 (at 2.032 0 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 552629AE)
    (at 226.5983 109.9621)
    (attr smd)
    (fp_text reference C15 (at 3.5257 -0.1071) (layer B.SilkS))
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    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 538590F1)
    (at 208.28236 108.35936 270)
    (attr smd)
    (fp_text reference C16 (at -2.08026 -0.02794 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 538590FC)
    (at 209.6438 108.2984 270)
    (attr smd)
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      (layers TOP F.Paste F.Mask)
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    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 53859106)
    (at 211.09922 108.59558 270)
    (attr smd)
    (fp_text reference C18 (at -2.18948 -0.13208 270) (layer F.SilkS))
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552602D5)
    (at 214.84826 108.73274 270)
    (attr smd)
    (fp_text reference C19 (at -2.30674 0.21826 270) (layer F.SilkS))
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      (layers TOP F.Paste F.Mask)
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    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 53A12900)
    (at 205.46804 117.19094)
    (attr smd)
    (fp_text reference C20 (at -1.22174 1.02616) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer F.SilkS) hide)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 53859087)
    (at 206.7355 120.36086 180)
    (attr smd)
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    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552602D8)
    (at 216.5272 108.60574 270)
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    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
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      (layers TOP F.Paste F.Mask)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
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      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552602D1)
    (at 212.92802 108.70988 270)
    (attr smd)
    (fp_text reference C23 (at -2.41088 -0.43198 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
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      (layers TOP F.Paste F.Mask)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 53859070)
    (at 205.402 110.47518 270)
    (attr smd)
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      (layers TOP F.Paste F.Mask)
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    )
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      (layers TOP F.Paste F.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 552629A3)
    (at 226.5983 116.3121)
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    (fp_text reference C207 (at 3.3987 -0.1071) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
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      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 552629B8)
    (at 226.5983 111.9941)
    (attr smd)
    (fp_text reference C174 (at 3.3987 0.0199) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
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      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 552629B5)
    (at 226.5983 113.0101)
    (attr smd)
    (fp_text reference C176 (at 3.3987 0.0199) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
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      (layers BOTTOM B.Paste B.Mask)
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BAD6)
    (at 221.7723 105.6441 90)
    (attr smd)
    (fp_text reference C178 (at 2.413 0 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
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      (layers BOTTOM B.Paste B.Mask)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5526299C)
    (at 227.3603 120.1221)
    (attr smd)
    (fp_text reference C180 (at 3.0177 0.0199) (layer B.SilkS))
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    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 552629BB)
    (at 226.5983 115.2961)
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    (fp_text reference C182 (at 3.3987 -0.2341) (layer B.SilkS))
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      (layers BOTTOM B.Paste B.Mask)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
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      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 552629A8)
    (at 226.5983 114.0261)
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    (fp_text reference C186 (at 3.3987 0.0199) (layer B.SilkS))
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      (layers BOTTOM B.Paste B.Mask)
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
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      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 552629A1)
    (at 226.5983 117.3281)
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    (fp_text reference C184 (at 3.3987 0.0199) (layer B.SilkS))
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    )
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    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
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    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BACB)
    (at 222.7883 105.6441 90)
    (attr smd)
    (fp_text reference C187 (at 2.413 0 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module RES_NET4   locked (layer BOTTOM) (tedit 5385BA53)
    (at 217.9242 108.4762 180)
    (fp_text reference R2 (at 0.2159 -2.5019 180) (layer B.SilkS))
    (fp_text value 49.9E (at 0.508 -2.8702 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.19888 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at -1.19888 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 4 /DDR3/DDR0_A11)
    )
    (pad 3 smd rect (at -0.39878 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 4 smd rect (at -0.39878 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 10 /DDR3/DDR0_A4)
    )
    (pad 5 smd rect (at 0.39878 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 6 smd rect (at 0.39878 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 5 /DDR3/DDR0_A12)
    )
    (pad 7 smd rect (at 1.19888 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 8 smd rect (at 1.19888 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 19 /DDR3/DDR0_CAS_N)
    )
  )
  (module RES_NET4   locked (layer BOTTOM) (tedit 5385B99F)
    (at 223.7916 116.8201 90)
    (fp_text reference R3 (at 0 -2.4003 90) (layer B.SilkS))
    (fp_text value 49.9E (at 0.508 -2.8702 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.19888 0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at -1.19888 -0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 16 /DDR3/DDR0_BA0)
    )
    (pad 3 smd rect (at -0.39878 0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 4 smd rect (at -0.39878 -0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 11 /DDR3/DDR0_A5)
    )
    (pad 5 smd rect (at 0.39878 0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 6 smd rect (at 0.39878 -0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 13 /DDR3/DDR0_A7)
    )
    (pad 7 smd rect (at 1.19888 0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 8 smd rect (at 1.19888 -0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 9 /DDR3/DDR0_A3)
    )
  )
  (module RES_NET4   locked (layer BOTTOM) (tedit 5385BA06)
    (at 223.8551 112.591 90)
    (fp_text reference R8 (at -0.0381 -2.4638 90) (layer B.SilkS))
    (fp_text value 49.9E (at 0.508 -2.8702 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.19888 0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at -1.19888 -0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 18 /DDR3/DDR0_BA2)
    )
    (pad 3 smd rect (at -0.39878 0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 4 smd rect (at -0.39878 -0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 8 /DDR3/DDR0_A2)
    )
    (pad 5 smd rect (at 0.39878 0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 6 smd rect (at 0.39878 -0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 15 /DDR3/DDR0_A9)
    )
    (pad 7 smd rect (at 1.19888 0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 8 smd rect (at 1.19888 -0.79756 90) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 1 /DDR3/DDR0_A0)
    )
  )
  (module RES_NET4   locked (layer BOTTOM) (tedit 5385B8E2)
    (at 222.42 108.5397 180)
    (fp_text reference R9 (at -2.9083 -0.0254 180) (layer B.SilkS))
    (fp_text value 49.9E (at 0.508 -2.8702 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.19888 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at -1.19888 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 2 /DDR3/DDR0_A1)
    )
    (pad 3 smd rect (at -0.39878 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 4 smd rect (at -0.39878 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 7 /DDR3/DDR0_A14)
    )
    (pad 5 smd rect (at 0.39878 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 6 smd rect (at 0.39878 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 14 /DDR3/DDR0_A8)
    )
    (pad 7 smd rect (at 1.19888 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 8 smd rect (at 1.19888 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 12 /DDR3/DDR0_A6)
    )
  )
  (module RES_NET4   locked (layer BOTTOM) (tedit 5385BB5C)
    (at 213.6697 108.4127 180)
    (fp_text reference R10 (at 3.8354 -0.9144 180) (layer B.SilkS))
    (fp_text value 49.9E (at 0.508 -2.8702 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.19888 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 2 smd rect (at -1.19888 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 17 /DDR3/DDR0_BA1)
    )
    (pad 3 smd rect (at -0.39878 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 4 smd rect (at -0.39878 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 3 /DDR3/DDR0_A10)
    )
    (pad 5 smd rect (at 0.39878 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 6 smd rect (at 0.39878 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 48 /DDR3/DDR0_WE_N)
    )
    (pad 7 smd rect (at 1.19888 0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (pad 8 smd rect (at 1.19888 -0.79756 180) (size 0.508 0.9144)
      (layers BOTTOM B.Paste B.Mask)
      (net 43 /DDR3/DDR0_RAS_N)
    )
  )
  (module LED-0805   locked (layer TOP) (tedit 5526032F)
    (at 196.5325 159.9565)
    (descr "LED 0805 smd package")
    (tags "LED 0805 SMD")
    (attr smd)
    (fp_text reference D1 (at -0.0635 1.5875) (layer F.SilkS))
    (fp_text value LED (at 0 1.27) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.04902 0) (size 1.19888 1.19888)
      (layers TOP F.Paste F.Mask)
      (net 345 N-00000189)
    )
    (pad 2 smd rect (at 1.04902 0) (size 1.19888 1.19888)
      (layers TOP F.Paste F.Mask)
      (net 294 /FPGA_Power/DONE)
    )
  )
  (module GS2   locked (layer TOP) (tedit 55260364)
    (at 203.7256 160.68082)
    (descr "Pontet Goute de soudure")
    (attr virtual)
    (fp_text reference JP2 (at -0.0176 -2.81982 90) (layer F.SilkS))
    (fp_text value JUMPER (at 1.524 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at 0 -0.635) (size 1.27 0.9652)
      (layers TOP F.Paste F.Mask)
      (net 218 /FPGA_Bank_1_2/FPGA_M1)
    )
    (pad 2 smd rect (at 0 0.635) (size 1.27 0.9652)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module GS2   locked (layer TOP) (tedit 5526035F)
    (at 206.0116 160.68082)
    (descr "Pontet Goute de soudure")
    (attr virtual)
    (fp_text reference JP1 (at -0.0176 -2.81982 90) (layer F.SilkS))
    (fp_text value JUMPER (at 1.524 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at 0 -0.635) (size 1.27 0.9652)
      (layers TOP F.Paste F.Mask)
      (net 217 /FPGA_Bank_1_2/FPGA_M0_CMP_MISO)
    )
    (pad 2 smd rect (at 0 0.635) (size 1.27 0.9652)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module BGA_484_1mm   locked (layer TOP) (tedit 55260300)
    (at 213.5173 143.9091 270)
    (attr smd)
    (fp_text reference U10 (at -13.9881 12.0953 360) (layer F.SilkS))
    (fp_text value XC6SLX45T (at 0 12.7 270) (layer F.SilkS) hide)
    (pad A1 smd circle (at -10.50036 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad A2 smd circle (at -9.4996 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 124 /FPGA_Bank_0_3/DIFFIO_A6N)
    )
    (pad A3 smd circle (at -8.49884 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 138 /FPGA_Bank_0_3/DIFFIO_B6N)
    )
    (pad A4 smd circle (at -7.50062 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 122 /FPGA_Bank_0_3/DIFFIO_A5N)
    )
    (pad A5 smd circle (at -6.49986 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 136 /FPGA_Bank_0_3/DIFFIO_B5N)
    )
    (pad A6 smd circle (at -5.4991 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 65 /DisplayPort/DPTX_LANEN0)
    )
    (pad A7 smd circle (at -4.50088 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad A8 smd circle (at -3.50012 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 66 /DisplayPort/DPTX_LANEN1)
    )
    (pad A9 smd circle (at -2.49936 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad A10 smd circle (at -1.4986 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 364 N-00000233)
    )
    (pad A11 smd circle (at -0.50038 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad A12 smd circle (at 0.50038 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad A13 smd circle (at 1.50114 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad A14 smd circle (at 2.49936 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 67 /DisplayPort/DPTX_LANEN2)
    )
    (pad A15 smd circle (at 3.50012 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad A16 smd circle (at 4.50088 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 68 /DisplayPort/DPTX_LANEN3)
    )
    (pad B1 smd circle (at -10.50036 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 479 VTTREF)
    )
    (pad C1 smd circle (at -10.50036 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 95 /Ethernet/MAC_SDA)
    )
    (pad D1 smd circle (at -10.50036 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad E1 smd circle (at -10.50036 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 4 /DDR3/DDR0_A11)
    )
    (pad F1 smd circle (at -10.50036 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 5 /DDR3/DDR0_A12)
    )
    (pad G1 smd circle (at -10.50036 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 15 /DDR3/DDR0_A9)
    )
    (pad H1 smd circle (at -10.50036 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 18 /DDR3/DDR0_BA2)
    )
    (pad J1 smd circle (at -10.50036 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 17 /DDR3/DDR0_BA1)
    )
    (pad B16 smd circle (at 4.50088 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 72 /DisplayPort/DPTX_LANEP3)
    )
    (pad B15 smd circle (at 3.50012 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad B14 smd circle (at 2.49936 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 71 /DisplayPort/DPTX_LANEP2)
    )
    (pad B13 smd circle (at 1.50114 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad B12 smd circle (at 0.50038 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad B11 smd circle (at -0.50038 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad B10 smd circle (at -1.4986 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 362 N-00000218)
    )
    (pad B9 smd circle (at -2.49936 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad B8 smd circle (at -3.50012 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 70 /DisplayPort/DPTX_LANEP1)
    )
    (pad B7 smd circle (at -4.50088 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad B6 smd circle (at -5.4991 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 69 /DisplayPort/DPTX_LANEP0)
    )
    (pad B5 smd circle (at -6.49986 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad B2 smd circle (at -9.4996 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 125 /FPGA_Bank_0_3/DIFFIO_A6P)
    )
    (pad B3 smd circle (at -8.49884 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 139 /FPGA_Bank_0_3/DIFFIO_B6P)
    )
    (pad B4 smd circle (at -7.50062 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad C2 smd circle (at -9.4996 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad C3 smd circle (at -8.49884 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 146 /FPGA_Bank_0_3/HSWAP)
    )
    (pad C4 smd circle (at -7.50062 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 123 /FPGA_Bank_0_3/DIFFIO_A5P)
    )
    (pad C5 smd circle (at -6.49986 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 137 /FPGA_Bank_0_3/DIFFIO_B5P)
    )
    (pad C6 smd circle (at -5.4991 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad C7 smd circle (at -4.50088 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 56 /DisplayPort/DPRX_LANEN3)
    )
    (pad C8 smd circle (at -3.50012 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad C9 smd circle (at -2.49936 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 55 /DisplayPort/DPRX_LANEN2)
    )
    (pad D2 smd circle (at -9.4996 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad D3 smd circle (at -8.49884 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 153 /FPGA_Bank_0_3/PCIE_RESET)
    )
    (pad D4 smd circle (at -7.50062 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 135 /FPGA_Bank_0_3/DIFFIO_B4P)
    )
    (pad D5 smd circle (at -6.49986 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 134 /FPGA_Bank_0_3/DIFFIO_B4N)
    )
    (pad D6 smd circle (at -5.4991 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad D7 smd circle (at -4.50088 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 60 /DisplayPort/DPRX_LANEP3)
    )
    (pad D8 smd circle (at -3.50012 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad D9 smd circle (at -2.49936 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 59 /DisplayPort/DPRX_LANEP2)
    )
    (pad E2 smd circle (at -9.4996 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad E3 smd circle (at -8.49884 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 44 /DDR3/DDR0_RESET_N)
    )
    (pad E4 smd circle (at -7.50062 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad C10 smd circle (at -1.4986 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad D10 smd circle (at -1.4986 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad C11 smd circle (at -0.50038 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 152 /FPGA_Bank_0_3/MGTSMACLK_P)
    )
    (pad D11 smd circle (at -0.50038 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 151 /FPGA_Bank_0_3/MGTSMACLK_N)
    )
    (pad D12 smd circle (at 0.50038 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad C12 smd circle (at 0.50038 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad C13 smd circle (at 1.50114 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 54 /DisplayPort/DPRX_LANEN1)
    )
    (pad C14 smd circle (at 2.49936 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad D14 smd circle (at 2.49936 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad D13 smd circle (at 1.50114 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 58 /DisplayPort/DPRX_LANEP1)
    )
    (pad C15 smd circle (at 3.50012 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 53 /DisplayPort/DPRX_LANEN0)
    )
    (pad D15 smd circle (at 3.50012 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 57 /DisplayPort/DPRX_LANEP0)
    )
    (pad D16 smd circle (at 4.50088 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad C16 smd circle (at 4.50088 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad E13 smd circle (at 1.50114 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad F13 smd circle (at 1.50114 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad F14 smd circle (at 2.49936 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 103 /FPGA_Bank_0_3/DIFFCLK_A0P)
    )
    (pad E14 smd circle (at 2.49936 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad E15 smd circle (at 3.50012 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad F15 smd circle (at 3.50012 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 102 /FPGA_Bank_0_3/DIFFCLK_A0N)
    )
    (pad G15 smd circle (at 3.50012 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 116 /FPGA_Bank_0_3/DIFFIO_A2N)
    )
    (pad G16 smd circle (at 4.50088 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 129 /FPGA_Bank_0_3/DIFFIO_B1P)
    )
    (pad F16 smd circle (at 4.50088 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 107 /FPGA_Bank_0_3/DIFFCLK_B0P)
    )
    (pad E16 smd circle (at 4.50088 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 106 /FPGA_Bank_0_3/DIFFCLK_B0N)
    )
    (pad F2 smd circle (at -9.4996 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 20 /DDR3/DDR0_CKE)
    )
    (pad F3 smd circle (at -8.49884 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad F4 smd circle (at -7.50062 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad G4 smd circle (at -7.50062 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad G3 smd circle (at -8.49884 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 14 /DDR3/DDR0_A8)
    )
    (pad G2 smd circle (at -9.4996 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad H2 smd circle (at -9.4996 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 48 /DDR3/DDR0_WE_N)
    )
    (pad H3 smd circle (at -8.49884 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 10 /DDR3/DDR0_A4)
    )
    (pad H4 smd circle (at -7.50062 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad J4 smd circle (at -7.50062 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 3 /DDR3/DDR0_A10)
    )
    (pad J3 smd circle (at -8.49884 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 16 /DDR3/DDR0_BA0)
    )
    (pad J2 smd circle (at -9.4996 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad K1 smd circle (at -10.50036 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 2 /DDR3/DDR0_A1)
    )
    (pad K2 smd circle (at -9.4996 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 1 /DDR3/DDR0_A0)
    )
    (pad K3 smd circle (at -8.49884 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 21 /DDR3/DDR0_CK_N)
    )
    (pad K4 smd circle (at -7.50062 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 22 /DDR3/DDR0_CK_P)
    )
    (pad L4 smd circle (at -7.50062 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 12 /DDR3/DDR0_A6)
    )
    (pad L3 smd circle (at -8.49884 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 33 /DDR3/DDR0_DQ4)
    )
    (pad L2 smd circle (at -9.4996 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad L1 smd circle (at -10.50036 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 34 /DDR3/DDR0_DQ5)
    )
    (pad M1 smd circle (at -10.50036 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 36 /DDR3/DDR0_DQ7)
    )
    (pad M2 smd circle (at -9.4996 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 35 /DDR3/DDR0_DQ6)
    )
    (pad M3 smd circle (at -8.49884 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 11 /DDR3/DDR0_A5)
    )
    (pad M4 smd circle (at -7.50062 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 19 /DDR3/DDR0_CAS_N)
    )
    (pad N4 smd circle (at -7.50062 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 39 /DDR3/DDR0_LDM)
    )
    (pad P4 smd circle (at -7.50062 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad R4 smd circle (at -7.50062 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad R3 smd circle (at -8.49884 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 23 /DDR3/DDR0_DQ0)
    )
    (pad P3 smd circle (at -8.49884 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 45 /DDR3/DDR0_UDM)
    )
    (pad N3 smd circle (at -8.49884 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 41 /DDR3/DDR0_LDQS_P)
    )
    (pad N2 smd circle (at -9.4996 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad P2 smd circle (at -9.4996 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 31 /DDR3/DDR0_DQ2)
    )
    (pad R2 smd circle (at -9.4996 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad N1 smd circle (at -10.50036 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 40 /DDR3/DDR0_LDQS_N)
    )
    (pad P1 smd circle (at -10.50036 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 32 /DDR3/DDR0_DQ3)
    )
    (pad R1 smd circle (at -10.50036 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 24 /DDR3/DDR0_DQ1)
    )
    (pad T1 smd circle (at -10.50036 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 38 /DDR3/DDR0_DQ9)
    )
    (pad T2 smd circle (at -9.4996 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 37 /DDR3/DDR0_DQ8)
    )
    (pad T3 smd circle (at -8.49884 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad T4 smd circle (at -7.50062 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad E8 smd circle (at -3.50012 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad E7 smd circle (at -4.50088 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad E6 smd circle (at -5.4991 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 120 /FPGA_Bank_0_3/DIFFIO_A4N)
    )
    (pad E5 smd circle (at -6.49986 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 121 /FPGA_Bank_0_3/DIFFIO_A4P)
    )
    (pad F5 smd circle (at -6.49986 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 157 /FPGA_Bank_0_3/PCIO3)
    )
    (pad F6 smd circle (at -5.4991 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad F7 smd circle (at -4.50088 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 143 /FPGA_Bank_0_3/DIFFIO_YP)
    )
    (pad F8 smd circle (at -3.50012 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 142 /FPGA_Bank_0_3/DIFFIO_YN)
    )
    (pad G5 smd circle (at -6.49986 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad G6 smd circle (at -5.4991 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 94 /Ethernet/MAC_SCL)
    )
    (pad G7 smd circle (at -4.50088 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 154 /FPGA_Bank_0_3/PCIO0)
    )
    (pad H5 smd circle (at -6.49986 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 7 /DDR3/DDR0_A14)
    )
    (pad H6 smd circle (at -5.4991 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad J5 smd circle (at -6.49986 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad J6 smd circle (at -5.4991 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 6 /DDR3/DDR0_A13)
    )
    (pad K5 smd circle (at -6.49986 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 8 /DDR3/DDR0_A2)
    )
    (pad K6 smd circle (at -5.4991 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 13 /DDR3/DDR0_A7)
    )
    (pad L5 smd circle (at -6.49986 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad L6 smd circle (at -5.4991 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 42 /DDR3/DDR0_ODT)
    )
    (pad M5 smd circle (at -6.49986 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 43 /DDR3/DDR0_RAS_N)
    )
    (pad M6 smd circle (at -5.4991 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 9 /DDR3/DDR0_A3)
    )
    (pad P5 smd circle (at -6.49986 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad P6 smd circle (at -5.4991 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad R5 smd circle (at -6.49986 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad R6 smd circle (at -5.4991 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad T5 smd circle (at -6.49986 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad T6 smd circle (at -5.4991 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad N5 smd circle (at -6.49986 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad N6 smd circle (at -5.4991 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 158 /FPGA_Bank_0_3/SMCLK)
    )
    (pad R7 smd circle (at -4.50088 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 365 N-00000235)
    )
    (pad R8 smd circle (at -3.50012 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 81 /Ethernet/ETH_RXD1)
    )
    (pad R9 smd circle (at -2.49936 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 80 /Ethernet/ETH_RXD0)
    )
    (pad R10 smd circle (at -1.4986 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad R11 smd circle (at -0.50038 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 50 /DisplayPort/DPRXAUXCH_P)
    )
    (pad T7 smd circle (at -4.50088 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 220 /FPGA_Bank_1_2/SD_CLK)
    )
    (pad T8 smd circle (at -3.50012 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 76 /Ethernet/ETH_MDIO)
    )
    (pad T9 smd circle (at -2.49936 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad T10 smd circle (at -1.4986 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 50 /DisplayPort/DPRXAUXCH_P)
    )
    (pad T11 smd circle (at -0.50038 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 49 /DisplayPort/DPRXAUXCH_N)
    )
    (pad E9 smd circle (at -2.49936 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 363 N-00000232)
    )
    (pad E10 smd circle (at -1.4986 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad E11 smd circle (at -0.50038 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad E12 smd circle (at 0.50038 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 148 /FPGA_Bank_0_3/MGT135MHz_P)
    )
    (pad F9 smd circle (at -2.49936 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 144 /FPGA_Bank_0_3/DIFFIO_ZN)
    )
    (pad F10 smd circle (at -1.4986 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 105 /FPGA_Bank_0_3/DIFFCLK_A1P)
    )
    (pad F11 smd circle (at -0.50038 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad F12 smd circle (at 0.50038 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 147 /FPGA_Bank_0_3/MGT135MHz_N)
    )
    (pad R12 smd circle (at 0.50038 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad T12 smd circle (at 0.50038 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 276 /FPGA_Bank_1_2/TMDS_TX2_CLK_P)
    )
    (pad R13 smd circle (at 1.50114 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 228 /FPGA_Bank_1_2/SPI_D1_MISO2)
    )
    (pad T13 smd circle (at 1.50114 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad T14 smd circle (at 2.49936 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 229 /FPGA_Bank_1_2/SPI_D2_MISO3)
    )
    (pad R14 smd circle (at 2.49936 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad H15 smd circle (at 3.50012 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad J15 smd circle (at 3.50012 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad K15 smd circle (at 3.50012 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
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      (layers TOP F.Paste F.Mask)
      (net 177 /FPGA_Bank_1_2/CY_FD2)
    )
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      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
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      (layers TOP F.Paste F.Mask)
      (net 206 /FPGA_Bank_1_2/CY_RD3)
    )
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      (layers TOP F.Paste F.Mask)
      (net 296 /FPGA_Power/RFS)
    )
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      (layers TOP F.Paste F.Mask)
      (net 165 /FPGA_Bank_1_2/CY_CTL2)
    )
    (pad T15 smd circle (at 3.50012 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 62 /DisplayPort/DPTXAUXCH_P)
    )
    (pad T16 smd circle (at 4.50088 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 300 /FPGA_Power/VBATT)
    )
    (pad R16 smd circle (at 4.50088 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 168 /FPGA_Bank_1_2/CY_CTL5)
    )
    (pad P16 smd circle (at 4.50088 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 164 /FPGA_Bank_1_2/CY_CTL1)
    )
    (pad N16 smd circle (at 4.50088 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 163 /FPGA_Bank_1_2/CY_CTL0)
    )
    (pad M16 smd circle (at 4.50088 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 205 /FPGA_Bank_1_2/CY_RD2)
    )
    (pad L16 smd circle (at 4.50088 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad K16 smd circle (at 4.50088 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 178 /FPGA_Bank_1_2/CY_FD3)
    )
    (pad J16 smd circle (at 4.50088 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 192 /FPGA_Bank_1_2/CY_PA6)
    )
    (pad H16 smd circle (at 4.50088 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 188 /FPGA_Bank_1_2/CY_PA2)
    )
    (pad A17 smd circle (at 5.4991 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 130 /FPGA_Bank_0_3/DIFFIO_B2N)
    )
    (pad A18 smd circle (at 6.49986 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 114 /FPGA_Bank_0_3/DIFFIO_A1N)
    )
    (pad A19 smd circle (at 7.50062 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 140 /FPGA_Bank_0_3/DIFFIO_XN)
    )
    (pad A20 smd circle (at 8.50138 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 126 /FPGA_Bank_0_3/DIFFIO_B0N)
    )
    (pad B17 smd circle (at 5.4991 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad B18 smd circle (at 6.49986 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 115 /FPGA_Bank_0_3/DIFFIO_A1P)
    )
    (pad B19 smd circle (at 7.50062 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad B20 smd circle (at 8.50138 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 127 /FPGA_Bank_0_3/DIFFIO_B0P)
    )
    (pad C17 smd circle (at 5.4991 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 131 /FPGA_Bank_0_3/DIFFIO_B2P)
    )
    (pad C18 smd circle (at 6.49986 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 112 /FPGA_Bank_0_3/DIFFIO_A0N)
    )
    (pad C19 smd circle (at 7.50062 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 141 /FPGA_Bank_0_3/DIFFIO_XP)
    )
    (pad C20 smd circle (at 8.50138 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 169 /FPGA_Bank_1_2/CY_FD0)
    )
    (pad D17 smd circle (at 5.4991 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 113 /FPGA_Bank_0_3/DIFFIO_A0P)
    )
    (pad D18 smd circle (at 6.49986 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 111 /FPGA_Bank_0_3/DIFFCLK_XP)
    )
    (pad D19 smd circle (at 7.50062 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 110 /FPGA_Bank_0_3/DIFFCLK_XN)
    )
    (pad D20 smd circle (at 8.50138 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 299 /FPGA_Power/TMS)
    )
    (pad E17 smd circle (at 5.4991 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad E18 smd circle (at 6.49986 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 330 /SPI_Flash/TDO-USB/TDI-FPGA)
    )
    (pad E19 smd circle (at 7.50062 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad E20 smd circle (at 8.50138 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 173 /FPGA_Bank_1_2/CY_FD12)
    )
    (pad F17 smd circle (at 5.4991 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 128 /FPGA_Bank_0_3/DIFFIO_B1N)
    )
    (pad F18 smd circle (at 6.49986 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 186 /FPGA_Bank_1_2/CY_PA0)
    )
    (pad F19 smd circle (at 7.50062 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 187 /FPGA_Bank_1_2/CY_PA1)
    )
    (pad F20 smd circle (at 8.50138 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 182 /FPGA_Bank_1_2/CY_FD7)
    )
    (pad G17 smd circle (at 5.4991 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 329 /SPI_Flash/TDO-FPGA/TDO-JTAG)
    )
    (pad G18 smd circle (at 6.49986 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad G19 smd circle (at 7.50062 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 181 /FPGA_Bank_1_2/CY_FD6)
    )
    (pad G20 smd circle (at 8.50138 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 211 /FPGA_Bank_1_2/CY_T0)
    )
    (pad H17 smd circle (at 5.4991 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 189 /FPGA_Bank_1_2/CY_PA3)
    )
    (pad H18 smd circle (at 6.49986 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 183 /FPGA_Bank_1_2/CY_FD8)
    )
    (pad H19 smd circle (at 7.50062 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 184 /FPGA_Bank_1_2/CY_FD9)
    )
    (pad H20 smd circle (at 8.50138 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 176 /FPGA_Bank_1_2/CY_FD15)
    )
    (pad J17 smd circle (at 5.4991 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 193 /FPGA_Bank_1_2/CY_PA7)
    )
    (pad J18 smd circle (at 6.49986 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad J19 smd circle (at 7.50062 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 175 /FPGA_Bank_1_2/CY_FD14)
    )
    (pad J20 smd circle (at 8.50138 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 233 /FPGA_Bank_1_2/TMDS_RX1_0_P)
    )
    (pad K17 smd circle (at 5.4991 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 238 /FPGA_Bank_1_2/TMDS_RX1_CEC)
    )
    (pad K18 smd circle (at 6.49986 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 214 /FPGA_Bank_1_2/CY_WR)
    )
    (pad K19 smd circle (at 7.50062 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 202 /FPGA_Bank_1_2/CY_RD)
    )
    (pad K20 smd circle (at 8.50138 -1.4986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 237 /FPGA_Bank_1_2/TMDS_RX1_2_P)
    )
    (pad L17 smd circle (at 5.4991 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 242 /FPGA_Bank_1_2/TMDS_RX1_SCL)
    )
    (pad L18 smd circle (at 6.49986 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad L19 smd circle (at 7.50062 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 236 /FPGA_Bank_1_2/TMDS_RX1_2_N)
    )
    (pad L20 smd circle (at 8.50138 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 252 /FPGA_Bank_1_2/TMDS_RX2_CLK_P)
    )
    (pad M17 smd circle (at 5.4991 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 167 /FPGA_Bank_1_2/CY_CTL4)
    )
    (pad M18 smd circle (at 6.49986 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 166 /FPGA_Bank_1_2/CY_CTL3)
    )
    (pad M19 smd circle (at 7.50062 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 239 /FPGA_Bank_1_2/TMDS_RX1_CLK_N)
    )
    (pad M20 smd circle (at 8.50138 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 240 /FPGA_Bank_1_2/TMDS_RX1_CLK_P)
    )
    (pad N17 smd circle (at 5.4991 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad N18 smd circle (at 6.49986 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad N19 smd circle (at 7.50062 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 327 /SPI_Flash/27MHz)
    )
    (pad N20 smd circle (at 8.50138 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 247 /FPGA_Bank_1_2/TMDS_RX2_1_P)
    )
    (pad P17 smd circle (at 5.4991 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 210 /FPGA_Bank_1_2/CY_RXD1)
    )
    (pad P18 smd circle (at 6.49986 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 209 /FPGA_Bank_1_2/CY_RXD0)
    )
    (pad P19 smd circle (at 7.50062 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 203 /FPGA_Bank_1_2/CY_RD0)
    )
    (pad P20 smd circle (at 8.50138 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 161 /FPGA_Bank_1_2/CY-IFCLK)
    )
    (pad R17 smd circle (at 5.4991 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 213 /FPGA_Bank_1_2/CY_TXD1)
    )
    (pad R18 smd circle (at 6.49986 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad R19 smd circle (at 7.50062 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 204 /FPGA_Bank_1_2/CY_RD1)
    )
    (pad R20 smd circle (at 8.50138 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 253 /FPGA_Bank_1_2/TMDS_RX2_HOT)
    )
    (pad T17 smd circle (at 5.4991 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 212 /FPGA_Bank_1_2/CY_TXD0)
    )
    (pad T18 smd circle (at 6.49986 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 243 /FPGA_Bank_1_2/TMDS_RX1_SDA)
    )
    (pad T19 smd circle (at 7.50062 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 185 /FPGA_Bank_1_2/CY_INT5)
    )
    (pad T20 smd circle (at 8.50138 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 208 /FPGA_Bank_1_2/CY_RD5)
    )
    (pad U1 smd circle (at -10.50036 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 26 /DDR3/DDR0_DQ11)
    )
    (pad V1 smd circle (at -10.50036 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 46 /DDR3/DDR0_UDQS_N)
    )
    (pad W1 smd circle (at -10.50036 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 28 /DDR3/DDR0_DQ13)
    )
    (pad Y1 smd circle (at -10.50036 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 30 /DDR3/DDR0_DQ15)
    )
    (pad Y2 smd circle (at -9.4996 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 29 /DDR3/DDR0_DQ14)
    )
    (pad Y3 smd circle (at -8.49884 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 160 /FPGA_Bank_0_3/SWITCH)
    )
    (pad Y4 smd circle (at -7.50062 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 219 /FPGA_Bank_1_2/INIT_B)
    )
    (pad Y5 smd circle (at -6.49986 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 225 /FPGA_Bank_1_2/SD_DAT3)
    )
    (pad Y6 smd circle (at -5.4991 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 83 /Ethernet/ETH_RXD3)
    )
    (pad Y7 smd circle (at -4.50088 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 266 /FPGA_Bank_1_2/TMDS_TX1_SCL)
    )
    (pad Y8 smd circle (at -3.50012 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 87 /Ethernet/ETH_TXD1)
    )
    (pad Y9 smd circle (at -2.49936 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 261 /FPGA_Bank_1_2/TMDS_TX1_2_P)
    )
    (pad Y10 smd circle (at -1.4986 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 267 /FPGA_Bank_1_2/TMDS_TX1_SDA)
    )
    (pad Y11 smd circle (at -0.50038 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 264 /FPGA_Bank_1_2/TMDS_TX1_CLK_P)
    )
    (pad Y12 smd circle (at 0.50038 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 256 /FPGA_Bank_1_2/TMDS_TX1_0_N)
    )
    (pad Y13 smd circle (at 1.50114 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 290 /FPGA_Bank_1_2/USB_REFCLK)
    )
    (pad Y14 smd circle (at 2.49936 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 280 /FPGA_Bank_1_2/USB_D0)
    )
    (pad Y15 smd circle (at 3.50012 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 269 /FPGA_Bank_1_2/TMDS_TX2_0_P)
    )
    (pad Y16 smd circle (at 4.50088 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 286 /FPGA_Bank_1_2/USB_D6)
    )
    (pad Y17 smd circle (at 5.4991 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 278 /FPGA_Bank_1_2/TMDS_TX2_SCL)
    )
    (pad Y18 smd circle (at 6.49986 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 282 /FPGA_Bank_1_2/USB_D2)
    )
    (pad Y19 smd circle (at 7.50062 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 218 /FPGA_Bank_1_2/FPGA_M1)
    )
    (pad Y20 smd circle (at 8.50138 8.50138 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 226 /FPGA_Bank_1_2/SPI_CLK)
    )
    (pad W2 smd circle (at -9.4996 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad W3 smd circle (at -8.49884 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 27 /DDR3/DDR0_DQ12)
    )
    (pad W4 smd circle (at -7.50062 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad W5 smd circle (at -6.49986 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad W6 smd circle (at -5.4991 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 82 /Ethernet/ETH_RXD2)
    )
    (pad W7 smd circle (at -4.50088 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad W8 smd circle (at -3.50012 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 85 /Ethernet/ETH_TXCTL)
    )
    (pad W9 smd circle (at -2.49936 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 86 /Ethernet/ETH_TXD0)
    )
    (pad W10 smd circle (at -1.4986 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 262 /FPGA_Bank_1_2/TMDS_TX1_CEC)
    )
    (pad W11 smd circle (at -0.50038 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 215 /FPGA_Bank_1_2/DPRXHPD)
    )
    (pad W12 smd circle (at 0.50038 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 257 /FPGA_Bank_1_2/TMDS_TX1_0_P)
    )
    (pad W13 smd circle (at 1.50114 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 288 /FPGA_Bank_1_2/USB_DIR)
    )
    (pad W14 smd circle (at 2.49936 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 281 /FPGA_Bank_1_2/USB_D1)
    )
    (pad W15 smd circle (at 3.50012 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 287 /FPGA_Bank_1_2/USB_D7)
    )
    (pad W16 smd circle (at 4.50088 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad W17 smd circle (at 5.4991 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 283 /FPGA_Bank_1_2/USB_D3)
    )
    (pad W18 smd circle (at 6.49986 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 292 /FPGA_Bank_1_2/USB_STP)
    )
    (pad W19 smd circle (at 7.50062 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad W20 smd circle (at 8.50138 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 198 /FPGA_Bank_1_2/CY_PC4)
    )
    (pad V2 smd circle (at -9.4996 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 47 /DDR3/DDR0_UDQS_P)
    )
    (pad V3 smd circle (at -8.49884 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad V4 smd circle (at -7.50062 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad V5 smd circle (at -6.49986 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad V6 smd circle (at -5.4991 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad V7 smd circle (at -4.50088 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 75 /Ethernet/ETH_MDC)
    )
    (pad V8 smd circle (at -3.50012 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad V9 smd circle (at -2.49936 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 74 /Ethernet/ETH_INT_B)
    )
    (pad V10 smd circle (at -1.4986 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad V11 smd circle (at -0.50038 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 216 /FPGA_Bank_1_2/DPTXHPD)
    )
    (pad V12 smd circle (at 0.50038 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad V13 smd circle (at 1.50114 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 289 /FPGA_Bank_1_2/USB_NXT)
    )
    (pad V14 smd circle (at 2.49936 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad V15 smd circle (at 3.50012 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 61 /DisplayPort/DPTXAUXCH_N)
    )
    (pad V16 smd circle (at 4.50088 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad V17 smd circle (at 5.4991 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 291 /FPGA_Bank_1_2/USB_RESETB)
    )
    (pad V18 smd circle (at 6.49986 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad V19 smd circle (at 7.50062 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 241 /FPGA_Bank_1_2/TMDS_RX1_HOT)
    )
    (pad V20 smd circle (at 8.50138 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 63 /DisplayPort/DPTXCONFIG1)
    )
    (pad U2 smd circle (at -9.4996 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad U3 smd circle (at -8.49884 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 25 /DDR3/DDR0_DQ10)
    )
    (pad U4 smd circle (at -7.50062 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad U5 smd circle (at -6.49986 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad U6 smd circle (at -5.4991 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 221 /FPGA_Bank_1_2/SD_CMD)
    )
    (pad U7 smd circle (at -4.50088 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad U8 smd circle (at -3.50012 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 77 /Ethernet/ETH_RESET_B)
    )
    (pad U9 smd circle (at -2.49936 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 79 /Ethernet/ETH_RXCTL)
    )
    (pad U10 smd circle (at -1.4986 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 49 /DisplayPort/DPRXAUXCH_N)
    )
    (pad U11 smd circle (at -0.50038 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad U12 smd circle (at 0.50038 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 275 /FPGA_Bank_1_2/TMDS_TX2_CLK_N)
    )
    (pad U13 smd circle (at 1.50114 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 272 /FPGA_Bank_1_2/TMDS_TX2_2_N)
    )
    (pad U14 smd circle (at 2.49936 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 273 /FPGA_Bank_1_2/TMDS_TX2_2_P)
    )
    (pad U15 smd circle (at 3.50012 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 61 /DisplayPort/DPTXAUXCH_N)
    )
    (pad U16 smd circle (at 4.50088 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 62 /DisplayPort/DPTXAUXCH_P)
    )
    (pad U17 smd circle (at 5.4991 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 301 /FPGA_Power/VFS)
    )
    (pad U18 smd circle (at 6.49986 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad U19 smd circle (at 7.50062 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 207 /FPGA_Bank_1_2/CY_RD4)
    )
    (pad U20 smd circle (at 8.50138 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 194 /FPGA_Bank_1_2/CY_PC0)
    )
    (pad AA1 smd circle (at -10.50036 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 101 /FPGA_Bank_0_3/DEBUG_IO1)
    )
    (pad AA2 smd circle (at -9.4996 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 100 /FPGA_Bank_0_3/DEBUG_IO0)
    )
    (pad AA3 smd circle (at -8.49884 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 227 /FPGA_Bank_1_2/SPI_CS_N)
    )
    (pad AA4 smd circle (at -7.50062 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 222 /FPGA_Bank_1_2/SD_DAT0)
    )
    (pad AA5 smd circle (at -6.49986 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad AA6 smd circle (at -5.4991 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 88 /Ethernet/ETH_TXD2)
    )
    (pad AA7 smd circle (at -4.50088 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad AA8 smd circle (at -3.50012 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 51 /DisplayPort/DPRXCONFIG1)
    )
    (pad AA9 smd circle (at -2.49936 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad AA10 smd circle (at -1.50114 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 259 /FPGA_Bank_1_2/TMDS_TX1_1_P)
    )
    (pad AA11 smd circle (at -0.50038 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad AA12 smd circle (at 0.50038 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 78 /Ethernet/ETH_RXCLK)
    )
    (pad AA13 smd circle (at 1.50114 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad AA14 smd circle (at 2.49936 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 284 /FPGA_Bank_1_2/USB_D4)
    )
    (pad AA15 smd circle (at 3.50012 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad AA16 smd circle (at 4.50088 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 271 /FPGA_Bank_1_2/TMDS_TX2_1_P)
    )
    (pad AA17 smd circle (at 5.4991 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad AA18 smd circle (at 6.49986 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 274 /FPGA_Bank_1_2/TMDS_TX2_CEC)
    )
    (pad AA19 smd circle (at 7.50062 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad AA20 smd circle (at 8.49884 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 230 /FPGA_Bank_1_2/SPI_DO_DIN_MISO1)
    )
    (pad AA21 smd circle (at 9.4996 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 217 /FPGA_Bank_1_2/FPGA_M0_CMP_MISO)
    )
    (pad AA22 smd circle (at 10.50036 9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 297 /FPGA_Power/SUSPEND)
    )
    (pad AB1 smd circle (at -10.50036 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad AB2 smd circle (at -9.4996 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 295 /FPGA_Power/PROG_B)
    )
    (pad AB3 smd circle (at -8.49884 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad AB4 smd circle (at -7.50062 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 223 /FPGA_Bank_1_2/SD_DAT1)
    )
    (pad AB5 smd circle (at -6.49986 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 224 /FPGA_Bank_1_2/SD_DAT2)
    )
    (pad AB6 smd circle (at -5.4991 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 89 /Ethernet/ETH_TXD3)
    )
    (pad AB7 smd circle (at -4.50088 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 265 /FPGA_Bank_1_2/TMDS_TX1_HOT)
    )
    (pad AB8 smd circle (at -3.50012 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 52 /DisplayPort/DPRXCONFIG2)
    )
    (pad AB9 smd circle (at -2.49936 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 260 /FPGA_Bank_1_2/TMDS_TX1_2_N)
    )
    (pad AB10 smd circle (at -1.50114 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 258 /FPGA_Bank_1_2/TMDS_TX1_1_N)
    )
    (pad AB11 smd circle (at -0.50038 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 263 /FPGA_Bank_1_2/TMDS_TX1_CLK_N)
    )
    (pad AB12 smd circle (at 0.50038 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 84 /Ethernet/ETH_TXCLK)
    )
    (pad AB13 smd circle (at 1.50114 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 293 /FPGA_Bank_1_2/100MHz)
    )
    (pad AB14 smd circle (at 2.49936 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 285 /FPGA_Bank_1_2/USB_D5)
    )
    (pad AB15 smd circle (at 3.50012 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 268 /FPGA_Bank_1_2/TMDS_TX2_0_N)
    )
    (pad AB16 smd circle (at 4.50088 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 270 /FPGA_Bank_1_2/TMDS_TX2_1_N)
    )
    (pad AB17 smd circle (at 5.4991 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 279 /FPGA_Bank_1_2/TMDS_TX2_SDA)
    )
    (pad AB18 smd circle (at 6.49986 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 277 /FPGA_Bank_1_2/TMDS_TX2_HOT)
    )
    (pad AB19 smd circle (at 7.50062 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 64 /DisplayPort/DPTXCONFIG2)
    )
    (pad AB20 smd circle (at 8.49884 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 231 /FPGA_Bank_1_2/SPI_MOSI_CSI_N_MISO0)
    )
    (pad AB21 smd circle (at 9.4996 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 294 /FPGA_Power/DONE)
    )
    (pad AB22 smd circle (at 10.50036 10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad P7 smd circle (at -4.50088 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad P8 smd circle (at -3.50012 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 479 VTTREF)
    )
    (pad P9 smd circle (at -2.49936 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad P10 smd circle (at -1.50114 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad P11 smd circle (at -0.50038 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad P12 smd circle (at 0.50038 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad P13 smd circle (at 1.50114 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad P14 smd circle (at 2.49936 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad N7 smd circle (at -4.50088 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 159 /FPGA_Bank_0_3/SMDATA)
    )
    (pad N8 smd circle (at -3.50012 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad N9 smd circle (at -2.49936 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad N10 smd circle (at -1.50114 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad N11 smd circle (at -0.50038 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad N12 smd circle (at 0.50038 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad N13 smd circle (at 1.50114 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad N14 smd circle (at 2.49936 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad M7 smd circle (at -4.50088 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad M8 smd circle (at -3.50012 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 479 VTTREF)
    )
    (pad M9 smd circle (at -2.49936 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad M10 smd circle (at -1.50114 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad M11 smd circle (at -0.50038 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad M12 smd circle (at 0.50038 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad M13 smd circle (at 1.50114 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad M14 smd circle (at 2.49936 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad L7 smd circle (at -4.50088 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad L8 smd circle (at -3.50012 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad L9 smd circle (at -2.49936 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad L10 smd circle (at -1.50114 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad L11 smd circle (at -0.50038 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad L12 smd circle (at 0.50038 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad L13 smd circle (at 1.50114 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad L14 smd circle (at 2.49936 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad K7 smd circle (at -4.50088 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
    )
    (pad K8 smd circle (at -3.50012 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 479 VTTREF)
    )
    (pad K9 smd circle (at -2.49936 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad K10 smd circle (at -1.50114 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad K11 smd circle (at -0.50038 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad K12 smd circle (at 0.50038 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad K13 smd circle (at 1.50114 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad K14 smd circle (at 2.49936 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad G8 smd circle (at -3.50012 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 145 /FPGA_Bank_0_3/DIFFIO_ZP)
    )
    (pad G9 smd circle (at -2.49936 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 104 /FPGA_Bank_0_3/DIFFCLK_A1N)
    )
    (pad G10 smd circle (at -1.50114 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad G11 smd circle (at -0.50038 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 108 /FPGA_Bank_0_3/DIFFCLK_B1N)
    )
    (pad G12 smd circle (at 0.50038 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad G13 smd circle (at 1.50114 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 118 /FPGA_Bank_0_3/DIFFIO_A3N)
    )
    (pad G14 smd circle (at 2.49936 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad H7 smd circle (at -4.50088 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad H8 smd circle (at -3.50012 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 156 /FPGA_Bank_0_3/PCIO2)
    )
    (pad H9 smd circle (at -2.49936 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad H10 smd circle (at -1.50114 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 133 /FPGA_Bank_0_3/DIFFIO_B3P)
    )
    (pad H11 smd circle (at -0.50038 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 132 /FPGA_Bank_0_3/DIFFIO_B3N)
    )
    (pad H12 smd circle (at 0.50038 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 109 /FPGA_Bank_0_3/DIFFCLK_B1P)
    )
    (pad H13 smd circle (at 1.50114 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 119 /FPGA_Bank_0_3/DIFFIO_A3P)
    )
    (pad H14 smd circle (at 2.49936 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 117 /FPGA_Bank_0_3/DIFFIO_A2P)
    )
    (pad J7 smd circle (at -4.50088 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 155 /FPGA_Bank_0_3/PCIO1)
    )
    (pad J8 smd circle (at -3.50012 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad J9 smd circle (at -2.49936 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad J10 smd circle (at -1.50114 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad J11 smd circle (at -0.50038 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad J12 smd circle (at 0.50038 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad J13 smd circle (at 1.50114 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad J14 smd circle (at 2.49936 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad A21 smd circle (at 9.4996 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 298 /FPGA_Power/TCK)
    )
    (pad A22 smd circle (at 10.50036 -10.50036 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad B21 smd circle (at 9.4996 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 190 /FPGA_Bank_1_2/CY_PA4)
    )
    (pad B22 smd circle (at 10.50036 -9.4996 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 191 /FPGA_Bank_1_2/CY_PA5)
    )
    (pad C21 smd circle (at 9.4996 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad C22 smd circle (at 10.50036 -8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 170 /FPGA_Bank_1_2/CY_FD1)
    )
    (pad D21 smd circle (at 9.4996 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 179 /FPGA_Bank_1_2/CY_FD4)
    )
    (pad D22 smd circle (at 10.50036 -7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 180 /FPGA_Bank_1_2/CY_FD5)
    )
    (pad E21 smd circle (at 9.4996 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad E22 smd circle (at 10.50036 -6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 174 /FPGA_Bank_1_2/CY_FD13)
    )
    (pad F21 smd circle (at 9.4996 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 171 /FPGA_Bank_1_2/CY_FD10)
    )
    (pad F22 smd circle (at 10.50036 -5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 172 /FPGA_Bank_1_2/CY_FD11)
    )
    (pad G21 smd circle (at 9.4996 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad G22 smd circle (at 10.50036 -4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 162 /FPGA_Bank_1_2/CYPRESS-RESET)
    )
    (pad H21 smd circle (at 9.4996 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 235 /FPGA_Bank_1_2/TMDS_RX1_1_P)
    )
    (pad H22 smd circle (at 10.50036 -3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 234 /FPGA_Bank_1_2/TMDS_RX1_1_N)
    )
    (pad J21 smd circle (at 9.4996 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad J22 smd circle (at 10.50036 -2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 232 /FPGA_Bank_1_2/TMDS_RX1_0_N)
    )
    (pad K21 smd circle (at 9.4996 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 150 /FPGA_Bank_0_3/MGTREFCLK0_101_P)
    )
    (pad K22 smd circle (at 10.50036 -1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 149 /FPGA_Bank_0_3/MGTREFCLK0_101_N)
    )
    (pad L21 smd circle (at 9.4996 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad L22 smd circle (at 10.50036 -0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 251 /FPGA_Bank_1_2/TMDS_RX2_CLK_N)
    )
    (pad M21 smd circle (at 9.4996 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 245 /FPGA_Bank_1_2/TMDS_RX2_0_P)
    )
    (pad M22 smd circle (at 10.50036 0.50038 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 244 /FPGA_Bank_1_2/TMDS_RX2_0_N)
    )
    (pad N21 smd circle (at 9.4996 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad N22 smd circle (at 10.50036 1.50114 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 246 /FPGA_Bank_1_2/TMDS_RX2_1_N)
    )
    (pad P21 smd circle (at 9.4996 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 249 /FPGA_Bank_1_2/TMDS_RX2_2_P)
    )
    (pad P22 smd circle (at 10.50036 2.49936 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 248 /FPGA_Bank_1_2/TMDS_RX2_2_N)
    )
    (pad R21 smd circle (at 9.4996 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad R22 smd circle (at 10.50036 3.50012 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 255 /FPGA_Bank_1_2/TMDS_RX2_SDA)
    )
    (pad T21 smd circle (at 9.4996 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 254 /FPGA_Bank_1_2/TMDS_RX2_SCL)
    )
    (pad T22 smd circle (at 10.50036 4.50088 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 250 /FPGA_Bank_1_2/TMDS_RX2_CEC)
    )
    (pad U21 smd circle (at 9.4996 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad U22 smd circle (at 10.50036 5.4991 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 195 /FPGA_Bank_1_2/CY_PC1)
    )
    (pad V21 smd circle (at 9.4996 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 196 /FPGA_Bank_1_2/CY_PC2)
    )
    (pad V22 smd circle (at 10.50036 6.49986 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 197 /FPGA_Bank_1_2/CY_PC3)
    )
    (pad W21 smd circle (at 9.4996 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad W22 smd circle (at 10.50036 7.50062 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 199 /FPGA_Bank_1_2/CY_PC5)
    )
    (pad Y21 smd circle (at 9.4996 8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 200 /FPGA_Bank_1_2/CY_PC6)
    )
    (pad Y22 smd circle (at 10.50036 8.49884 270) (size 0.50038 0.50038)
      (layers TOP F.Paste F.Mask)
      (net 201 /FPGA_Bank_1_2/CY_PC7)
    )
  )
  (module BGA96-0.8   locked (layer TOP) (tedit 552602DF)
    (at 213.3393 114.6611 90)
    (attr smd)
    (fp_text reference U1 (at 6.4571 -7.3453 180) (layer F.SilkS))
    (fp_text value MT41J128M16 (at -5.08 0 180) (layer F.SilkS) hide)
    (pad A1 smd circle (at -3.2004 -5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad A2 smd circle (at -2.4003 -5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 28 /DDR3/DDR0_DQ13)
    )
    (pad A3 smd circle (at -1.6002 -5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 30 /DDR3/DDR0_DQ15)
    )
    (pad A7 smd circle (at 1.6002 -5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 27 /DDR3/DDR0_DQ12)
    )
    (pad A8 smd circle (at 2.4003 -5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad A9 smd circle (at 3.2004 -5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad B1 smd circle (at -3.2004 -4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad C1 smd circle (at -3.2004 -4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad D1 smd circle (at -3.2004 -3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad E1 smd circle (at -3.2004 -2.40284 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad F1 smd circle (at -3.2004 -1.60274 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad G1 smd circle (at -3.2004 -0.80264 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad H1 smd circle (at -3.2004 -0.00254 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 479 VTTREF)
    )
    (pad H2 smd circle (at -2.4003 -0.00254 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad H3 smd circle (at -1.6002 -0.00254 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 33 /DDR3/DDR0_DQ4)
    )
    (pad H7 smd circle (at 1.59766 0 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 36 /DDR3/DDR0_DQ7)
    )
    (pad H8 smd circle (at 2.39776 0 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 34 /DDR3/DDR0_DQ5)
    )
    (pad H9 smd circle (at 3.19786 0 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad G9 smd circle (at 3.19786 -0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad F9 smd circle (at 3.19786 -1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad E9 smd circle (at 3.19786 -2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad D9 smd circle (at 3.19786 -3.19786 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad C9 smd circle (at 3.19786 -3.99796 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad B9 smd circle (at 3.19786 -4.79806 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad D3 smd circle (at -1.6002 -3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 45 /DDR3/DDR0_UDM)
    )
    (pad E3 smd circle (at -1.6002 -2.40284 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 23 /DDR3/DDR0_DQ0)
    )
    (pad E7 smd circle (at 1.59766 -2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 39 /DDR3/DDR0_LDM)
    )
    (pad D7 smd circle (at 1.59766 -3.19786 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 37 /DDR3/DDR0_DQ8)
    )
    (pad C7 smd circle (at 1.59766 -3.99796 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 47 /DDR3/DDR0_UDQS_P)
    )
    (pad C3 smd circle (at -1.6002 -4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 38 /DDR3/DDR0_DQ9)
    )
    (pad C2 smd circle (at -2.4003 -4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 26 /DDR3/DDR0_DQ11)
    )
    (pad D2 smd circle (at -2.4003 -3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad E2 smd circle (at -2.4003 -2.40284 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad F2 smd circle (at -2.4003 -1.60274 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 31 /DDR3/DDR0_DQ2)
    )
    (pad G2 smd circle (at -2.4003 -0.80264 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 35 /DDR3/DDR0_DQ6)
    )
    (pad G3 smd circle (at -1.6002 -0.80264 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 40 /DDR3/DDR0_LDQS_N)
    )
    (pad F3 smd circle (at -1.6002 -1.60274 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 41 /DDR3/DDR0_LDQS_P)
    )
    (pad F7 smd circle (at 1.59766 -1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 24 /DDR3/DDR0_DQ1)
    )
    (pad G7 smd circle (at 1.59766 -0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad G8 smd circle (at 2.39776 -0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad F8 smd circle (at 2.39776 -1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 32 /DDR3/DDR0_DQ3)
    )
    (pad E8 smd circle (at 2.39776 -2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad D8 smd circle (at 2.39776 -3.19786 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad C8 smd circle (at 2.39776 -3.99796 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 25 /DDR3/DDR0_DQ10)
    )
    (pad B8 smd circle (at 2.39776 -4.79806 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 29 /DDR3/DDR0_DQ14)
    )
    (pad B7 smd circle (at 1.59766 -4.79806 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 46 /DDR3/DDR0_UDQS_N)
    )
    (pad B3 smd circle (at -1.6002 -4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad B2 smd circle (at -2.4003 -4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad R1 smd circle (at -3.2004 5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad R9 smd circle (at 3.2004 5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad J1 smd circle (at -3.2004 0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
    )
    (pad J2 smd circle (at -2.4003 0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad J3 smd circle (at -1.6002 0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 43 /DDR3/DDR0_RAS_N)
    )
    (pad J7 smd circle (at 1.6002 0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 22 /DDR3/DDR0_CK_P)
    )
    (pad J8 smd circle (at 2.4003 0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad J9 smd circle (at 3.2004 0.8001 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
    )
    (pad K1 smd circle (at -3.2004 1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 42 /DDR3/DDR0_ODT)
    )
    (pad K2 smd circle (at -2.4003 1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad K3 smd circle (at -1.6002 1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 19 /DDR3/DDR0_CAS_N)
    )
    (pad K7 smd circle (at 1.6002 1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 21 /DDR3/DDR0_CK_N)
    )
    (pad K8 smd circle (at 2.4003 1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad K9 smd circle (at 3.2004 1.6002 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 20 /DDR3/DDR0_CKE)
    )
    (pad L1 smd circle (at -3.2004 2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
    )
    (pad L2 smd circle (at -2.4003 2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 344 N-00000182)
    )
    (pad L3 smd circle (at -1.6002 2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 48 /DDR3/DDR0_WE_N)
    )
    (pad L7 smd circle (at 1.6002 2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 3 /DDR3/DDR0_A10)
    )
    (pad L8 smd circle (at 2.4003 2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 343 N-00000178)
    )
    (pad L9 smd circle (at 3.2004 2.4003 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
    )
    (pad M1 smd circle (at -3.2004 3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad M2 smd circle (at -2.4003 3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 16 /DDR3/DDR0_BA0)
    )
    (pad M3 smd circle (at -1.6002 3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 18 /DDR3/DDR0_BA2)
    )
    (pad M7 smd circle (at 1.6002 3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
    )
    (pad M8 smd circle (at 2.4003 3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 479 VTTREF)
    )
    (pad M9 smd circle (at 3.2004 3.2004 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad N1 smd circle (at -3.2004 4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad N2 smd circle (at -2.4003 4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 9 /DDR3/DDR0_A3)
    )
    (pad N3 smd circle (at -1.6002 4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 1 /DDR3/DDR0_A0)
    )
    (pad N7 smd circle (at 1.6002 4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 5 /DDR3/DDR0_A12)
    )
    (pad N8 smd circle (at 2.4003 4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 17 /DDR3/DDR0_BA1)
    )
    (pad N9 smd circle (at 3.2004 4.0005 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad P1 smd circle (at -3.2004 4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad P2 smd circle (at -2.4003 4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 11 /DDR3/DDR0_A5)
    )
    (pad P3 smd circle (at -1.6002 4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 8 /DDR3/DDR0_A2)
    )
    (pad P7 smd circle (at 1.6002 4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 2 /DDR3/DDR0_A1)
    )
    (pad P8 smd circle (at 2.4003 4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 10 /DDR3/DDR0_A4)
    )
    (pad P9 smd circle (at 3.2004 4.8006 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad R2 smd circle (at -2.4003 5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 13 /DDR3/DDR0_A7)
    )
    (pad R3 smd circle (at -1.6002 5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 15 /DDR3/DDR0_A9)
    )
    (pad R7 smd circle (at 1.6002 5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 4 /DDR3/DDR0_A11)
    )
    (pad R8 smd circle (at 2.4003 5.6007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 12 /DDR3/DDR0_A6)
    )
    (pad T1 smd circle (at -3.2004 6.4007 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad T2 smd circle (at -2.4 6.4 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 44 /DDR3/DDR0_RESET_N)
    )
    (pad T3 smd circle (at -1.6 6.4 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 6 /DDR3/DDR0_A13)
    )
    (pad T7 smd circle (at 1.6 6.4 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 7 /DDR3/DDR0_A14)
    )
    (pad T8 smd circle (at 2.4 6.4 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 14 /DDR3/DDR0_A8)
    )
    (pad T9 smd circle (at 3.2 6.4 90) (size 0.39878 0.39878)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5385B395)
    (at 199.263 175.895)
    (attr smd)
    (fp_text reference R86 (at 2.5908 0.1016) (layer F.SilkS))
    (fp_text value 4K7 (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 349 N-00000195)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module JTAG   locked (layer TOP) (tedit 5624AFEB)
    (at 196.5579 61.2648)
    (descr "Double rangee de contacts 2 x 7 pins")
    (tags CONN)
    (fp_text reference P3 (at -11.9507 5.6642) (layer F.SilkS))
    (fp_text value CONN_7X2 (at 9.0424 5.334) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -7.62 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 2 thru_hole circle (at -7.62 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (pad 3 thru_hole circle (at -5.08 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 4 thru_hole circle (at -5.08 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 350 N-00000198)
    )
    (pad 5 thru_hole circle (at -2.54 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 6 thru_hole circle (at -2.54 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 351 N-00000199)
    )
    (pad 7 thru_hole circle (at 0 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 8 thru_hole circle (at 0 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 352 N-00000200)
    )
    (pad 9 thru_hole circle (at 2.54 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 10 thru_hole circle (at 2.54 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 348 N-00000194)
    )
    (pad 11 thru_hole circle (at 5.08 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 12 thru_hole circle (at 5.08 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad 13 thru_hole circle (at 7.62 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 14 thru_hole circle (at 7.62 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_2x08_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BB67)
    (at 214.88382 114.36646 180)
    (attr smd)
    (fp_text reference R4 (at -1.80848 0.08636 180) (layer B.SilkS))
    (fp_text value 100E (at 0.09906 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 21 /DDR3/DDR0_CK_N)
    )
    (pad 2 smd rect (at 0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 22 /DDR3/DDR0_CK_P)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BA91)
    (at 217.14188 119.2712 180)
    (attr smd)
    (fp_text reference R11 (at -2.34442 0.0381 180) (layer B.SilkS))
    (fp_text value 100E (at 0.09906 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 344 N-00000182)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BA75)
    (at 212.8061 114.3563 180)
    (attr smd)
    (fp_text reference R12 (at 2.2098 -0.0508 180) (layer B.SilkS))
    (fp_text value 240R (at 0.09906 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 343 N-00000178)
    )
    (pad 2 smd rect (at 0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 538590DA)
    (at 222.05932 120.15004 90)
    (attr smd)
    (fp_text reference R5 (at -1.75006 -0.03302 90) (layer F.SilkS))
    (fp_text value 4K7 (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 44 /DDR3/DDR0_RESET_N)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552602E9)
    (at 215.41214 122.1922 180)
    (attr smd)
    (fp_text reference R6 (at 0.02014 -1.1248 180) (layer F.SilkS))
    (fp_text value 4K7 (at 0.09906 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 180) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 42 /DDR3/DDR0_ODT)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385BA62)
    (at 213.7967 110.9146)
    (attr smd)
    (fp_text reference R7 (at -2.1844 -0.0635) (layer B.SilkS))
    (fp_text value 4K7 (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 20 /DDR3/DDR0_CKE)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5385B5DF)
    (at 190.97752 152.69972 90)
    (attr smd)
    (fp_text reference C36 (at -2.9718 -0.0254 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C8E5)
    (at 223.46902 137.61254 180)
    (attr smd)
    (fp_text reference C213 (at -2.70256 0.762 180) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C7FB)
    (at 211.5107 144.8998 270)
    (attr smd)
    (fp_text reference C215 (at 0 0.54864 270) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 474 VCC1V2)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C830)
    (at 213.47158 145.60846)
    (attr smd)
    (fp_text reference C221 (at 0 0) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 474 VCC1V2)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5385C85B)
    (at 216.95138 143.99302 270)
    (attr smd)
    (fp_text reference C236 (at 0 0 270) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 474 VCC1V2)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260958)
    (at 227.457 138.811)
    (attr smd)
    (fp_text reference C237 (at 0 -2.286) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603_Resistor   locked (layer TOP) (tedit 55260368)
    (at 208.79308 160.67786 90)
    (attr smd)
    (fp_text reference R29 (at -2.64414 -0.00508 90) (layer F.SilkS))
    (fp_text value 4.7K (at -1.69926 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 297 /FPGA_Power/SUSPEND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526036C)
    (at 206.38516 163.74872)
    (attr smd)
    (fp_text reference R40 (at -0.01016 1.47828) (layer F.SilkS))
    (fp_text value 10K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 217 /FPGA_Bank_1_2/FPGA_M0_CMP_MISO)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526036F)
    (at 203.2889 163.74872)
    (attr smd)
    (fp_text reference R41 (at -2.5019 -0.04572) (layer F.SilkS))
    (fp_text value 10K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 218 /FPGA_Bank_1_2/FPGA_M1)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 53859D66)
    (at 189.14364 136.90854 180)
    (attr smd)
    (fp_text reference R54 (at 2.55778 -0.03556 180) (layer F.SilkS))
    (fp_text value 1K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 160 /FPGA_Bank_0_3/SWITCH)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 366 N-00000249)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5387284D)
    (at 227.26124 133.546 270)
    (attr smd)
    (fp_text reference C113 (at 0 0 270) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 479 VTTREF)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 5387273A)
    (at 216.55006 137.00802 90)
    (attr smd)
    (fp_text reference C192 (at 0 0 90) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 479 VTTREF)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 539EBE04)
    (at 213.106 160.655 270)
    (attr smd)
    (fp_text reference R59 (at -2.794 0 270) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 300 /FPGA_Power/VBATT)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 539EBE13)
    (at 211.074 160.655 270)
    (attr smd)
    (fp_text reference R58 (at -2.794 0 270) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 301 /FPGA_Power/VFS)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55262319)
    (at 122.047 92.964)
    (attr smd)
    (fp_text reference R22 (at -2.794 0) (layer F.SilkS))
    (fp_text value 1K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 380 N-00000268)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 539EF56E)
    (at 207.49006 154.5463 180)
    (attr smd)
    (fp_text reference C243 (at -2.921 1.016 180) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 539EF56C)
    (at 211.3915 153.90368 180)
    (attr smd)
    (fp_text reference C242 (at -3.048 1.397 180) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 180) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55260C97)
    (at 237.5843 108.1694)
    (attr smd)
    (fp_text reference C76 (at -3.6503 0.0346) (layer F.SilkS))
    (fp_text value 10uF (at 0 0.381) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer BOTTOM) (tedit 5526297E)
    (at 237.5763 113.0434)
    (attr smd)
    (fp_text reference C168 (at -3.5153 -0.0134) (layer B.SilkS))
    (fp_text value 10uF (at 0 -0.381) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55261392)
    (at 131.9073 103.88252 270)
    (attr smd)
    (fp_text reference C228 (at 3.68648 -0.1727 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55261303)
    (at 157.22948 76.1797 180)
    (attr smd)
    (fp_text reference C224 (at -3.67952 -0.0203 180) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.381 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 73 /Ethernet/AVDD3V3)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer BOTTOM) (tedit 5626108D)
    (at 222.5548 211.75218 90)
    (attr smd)
    (fp_text reference R36 (at -0.00254 1.41224 90) (layer B.SilkS))
    (fp_text value 10K (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 403 N-00000316)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526135A)
    (at 140.16374 99.34688 180)
    (attr smd)
    (fp_text reference R51 (at 3.13074 0.03288 180) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 77 /Ethernet/ETH_RESET_B)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552603AB)
    (at 209.042 196.088 180)
    (attr smd)
    (fp_text reference R35 (at 2.4892 0.0254 180) (layer F.SilkS))
    (fp_text value 10K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 388 N-00000290)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552622DF)
    (at 134.243 89.131)
    (attr smd)
    (fp_text reference R49 (at -2.671 0.023) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 80 /Ethernet/ETH_RXD0)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer TOP) (tedit 5624BBE1)
    (at 251.81044 209.33918 270)
    (attr smd)
    (fp_text reference R25 (at -0.03048 -1.64846 270) (layer F.SilkS))
    (fp_text value 100K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 469 N-00000430)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260A7A)
    (at 278.1188 115.002 180)
    (attr smd)
    (fp_text reference R87 (at -2.5512 -0.06 180) (layer F.SilkS))
    (fp_text value 30.1K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 428 N-00000357)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 429 N-00000359)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526025E)
    (at 171.7421 98.9711 90)
    (attr smd)
    (fp_text reference R30 (at -0.0889 -1.5621 90) (layer F.SilkS))
    (fp_text value "20K5%- 0.05W" (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 396 N-00000305)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 337 /USB/USB_5V)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526135D)
    (at 140.085 101.323)
    (attr smd)
    (fp_text reference R50 (at -3.179 0.023) (layer F.SilkS))
    (fp_text value 1.5K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 76 /Ethernet/ETH_MDIO)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552622DA)
    (at 134.243 91.163)
    (attr smd)
    (fp_text reference R65 (at -2.671 0.023) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 81 /Ethernet/ETH_RXD1)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552622DC)
    (at 127.9525 91.694 180)
    (attr smd)
    (fp_text reference R39 (at -0.6985 1.397 180) (layer F.SilkS))
    (fp_text value 27K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 382 N-00000271)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526011A)
    (at 195.49872 68.06184 270)
    (attr smd)
    (fp_text reference R81 (at 2.80416 -0.08128 270) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 351 N-00000199)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 298 /FPGA_Power/TCK)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262C28)
    (at 195.7451 220.05036 180)
    (attr smd)
    (fp_text reference R84 (at -0.0889 1.54686 180) (layer B.SilkS))
    (fp_text value 100K (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 445 N-00000387)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260276)
    (at 175.50892 101.39172 270)
    (attr smd)
    (fp_text reference R13 (at 3.25628 -0.00508 270) (layer F.SilkS))
    (fp_text value 8.06K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 404 N-00000319)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552613B3)
    (at 127.9525 93.726)
    (attr smd)
    (fp_text reference R38 (at 0.8255 1.524) (layer F.SilkS))
    (fp_text value 39K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 382 N-00000271)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 97 /Ethernet/VCC1V0)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260CA0)
    (at 243.1723 108.1694 90)
    (attr smd)
    (fp_text reference C146 (at 2.5054 0.0327 90) (layer F.SilkS))
    (fp_text value 0.001uF (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 409 N-00000333)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260748)
    (at 181.0766 212.1662 270)
    (attr smd)
    (fp_text reference C179 (at 0.0508 -1.4224 270) (layer F.SilkS))
    (fp_text value 1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 443 N-00000377)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260736)
    (at 167.9702 212.217 90)
    (attr smd)
    (fp_text reference C185 (at 2.54 0.0508 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 315 /HDMI/P3-HOT)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B2B)
    (at 159.58312 200.48474 90)
    (attr smd)
    (fp_text reference R126 (at -0.04826 1.57988 90) (layer B.SilkS))
    (fp_text value 100K (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 274 /FPGA_Bank_1_2/TMDS_TX2_CEC)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B24)
    (at 159.9565 197.4977 270)
    (attr smd)
    (fp_text reference R133 (at -3.1877 -0.0635 270) (layer B.SilkS))
    (fp_text value 47K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 279 /FPGA_Bank_1_2/TMDS_TX2_SDA)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5625C48C)
    (at 157.8229 197.92442 270)
    (attr smd)
    (fp_text reference R129 (at -3.41122 -0.01016 270) (layer B.SilkS))
    (fp_text value 47K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 278 /FPGA_Bank_1_2/TMDS_TX2_SCL)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260794)
    (at 191.389 206.121)
    (attr smd)
    (fp_text reference R132 (at -3.048 0) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 238 /FPGA_Bank_1_2/TMDS_RX1_CEC)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260777)
    (at 168.529 206.121)
    (attr smd)
    (fp_text reference R192 (at -3.302 0) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 250 /FPGA_Bank_1_2/TMDS_RX2_CEC)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260771)
    (at 168.529 201.549)
    (attr smd)
    (fp_text reference R194 (at -3.302 0) (layer F.SilkS))
    (fp_text value 47K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 255 /FPGA_Bank_1_2/TMDS_RX2_SDA)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260774)
    (at 168.529 203.835)
    (attr smd)
    (fp_text reference R193 (at -3.302 0) (layer F.SilkS))
    (fp_text value 47K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 254 /FPGA_Bank_1_2/TMDS_RX2_SCL)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260799)
    (at 191.389 201.549)
    (attr smd)
    (fp_text reference R136 (at -3.048 0) (layer F.SilkS))
    (fp_text value 47K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 243 /FPGA_Bank_1_2/TMDS_RX1_SDA)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260796)
    (at 191.389 203.835)
    (attr smd)
    (fp_text reference R135 (at -3.048 0.127) (layer F.SilkS))
    (fp_text value 47K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 242 /FPGA_Bank_1_2/TMDS_RX1_SCL)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5624D280)
    (at 127.98552 200.57364 270)
    (attr smd)
    (fp_text reference R127 (at -1.94564 -0.53848 360) (layer B.SilkS))
    (fp_text value 100K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 262 /FPGA_Bank_1_2/TMDS_TX1_CEC)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B7D)
    (at 126.8095 204.26426 90)
    (attr smd)
    (fp_text reference R134 (at -1.72974 1.4605 90) (layer B.SilkS))
    (fp_text value 47K (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 266 /FPGA_Bank_1_2/TMDS_TX1_SCL)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5624D278)
    (at 125.984 200.55332 270)
    (attr smd)
    (fp_text reference R130 (at -1.98882 1.0795 360) (layer B.SilkS))
    (fp_text value 47K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 267 /FPGA_Bank_1_2/TMDS_TX1_SDA)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552600D3)
    (at 152.36698 64.0334)
    (attr smd)
    (fp_text reference R92 (at 0.03302 -1.4224) (layer F.SilkS))
    (fp_text value 330R (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 383 N-00000275)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552609AC)
    (at 263.652 133.858 90)
    (attr smd)
    (fp_text reference R116 (at -3.302 0 90) (layer F.SilkS))
    (fp_text value 100R (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 354 N-00000203)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552609B1)
    (at 260.858 133.858 90)
    (attr smd)
    (fp_text reference R93 (at -3.175 0 90) (layer F.SilkS))
    (fp_text value 100R (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 355 N-00000205)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module MicroSD   locked (layer BOTTOM) (tedit 5624C07E)
    (at 124.5235 120.269 270)
    (fp_text reference U11 (at 2.54 -10.7823 360) (layer B.SilkS))
    (fp_text value MICRO_SD (at -4.25196 -4.36626 270) (layer B.SilkS) hide)
    (pad 8 connect rect (at 0 0 270) (size 0.8001 1.50114)
      (layers BOTTOM B.Mask)
      (net 223 /FPGA_Bank_1_2/SD_DAT1)
    )
    (pad 7 connect rect (at -1.09982 0 270) (size 0.8001 1.50114)
      (layers BOTTOM B.Mask)
      (net 222 /FPGA_Bank_1_2/SD_DAT0)
    )
    (pad 6 connect rect (at -2.19964 0.20066 270) (size 0.8001 1.50114)
      (layers BOTTOM B.Mask)
      (net 342 GND)
    )
    (pad 5 connect rect (at -3.29946 0 270) (size 0.8001 1.50114)
      (layers BOTTOM B.Mask)
      (net 220 /FPGA_Bank_1_2/SD_CLK)
    )
    (pad 4 connect rect (at -4.39928 0.20066 270) (size 0.8001 1.50114)
      (layers BOTTOM B.Mask)
      (net 476 VCC3V3)
    )
    (pad 3 connect rect (at -5.4991 0 270) (size 0.8001 1.50114)
      (layers BOTTOM B.Mask)
      (net 221 /FPGA_Bank_1_2/SD_CMD)
    )
    (pad 2 connect rect (at -6.59892 -0.39878 270) (size 0.8001 1.50114)
      (layers BOTTOM B.Mask)
      (net 225 /FPGA_Bank_1_2/SD_DAT3)
    )
    (pad 1 connect rect (at -7.69874 0 270) (size 0.8001 1.50114)
      (layers BOTTOM B.Mask)
      (net 224 /FPGA_Bank_1_2/SD_DAT2)
    )
    (pad 9 connect rect (at 0.89916 2.89052 270) (size 1.39954 1.89992)
      (layers BOTTOM B.Mask)
      (net 342 GND)
    )
    (pad 10 connect rect (at -12.49934 3.87858 270) (size 1.39954 1.89992)
      (layers BOTTOM B.Mask)
      (net 342 GND)
    )
    (pad 12 connect rect (at -0.80518 -10.668 270) (size 1.80086 1.39954)
      (layers BOTTOM B.Mask)
      (net 342 GND)
    )
    (pad 11 connect rect (at -6.50494 -10.668 270) (size 1.80086 1.39954)
      (layers BOTTOM B.Mask)
      (net 342 GND)
    )
  )
  (module IND202   locked (layer TOP) (tedit 5535D54A)
    (at 224.2533 96.5877 180)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference L4 (at 6.1943 -2.4723 180) (layer F.SilkS))
    (fp_text value 1.5UH (at 0 0.508 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.54 0 180) (size 3.5 2.5)
      (layers TOP F.Paste F.Mask)
      (net 419 N-00000345)
    )
    (pad 2 smd rect (at 2.54 0 180) (size 3.5 2.5)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module IND202   locked (layer TOP) (tedit 5537246E)
    (at 165.95344 136.76122 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference L5 (at -1.37922 -4.73456 360) (layer F.SilkS))
    (fp_text value 1.5UH (at 0 0.508 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.54 0 270) (size 3.5 2.5)
      (layers TOP F.Paste F.Mask)
      (net 438 N-00000368)
    )
    (pad 2 smd rect (at 2.54 0 270) (size 3.5 2.5)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module HDMI_TH   locked (layer TOP) (tedit 56373DDC)
    (at 175.597 218.948)
    (fp_text reference J5 (at 8.807 2.855) (layer F.SilkS))
    (fp_text value HDMI (at 0 5.08) (layer F.SilkS) hide)
    (pad 10 smd rect (at 0 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 252 /FPGA_Bank_1_2/TMDS_RX2_CLK_P)
    )
    (pad 9 smd rect (at 0.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 244 /FPGA_Bank_1_2/TMDS_RX2_0_N)
    )
    (pad 8 smd rect (at 1 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at 1.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 245 /FPGA_Bank_1_2/TMDS_RX2_0_P)
    )
    (pad 6 smd rect (at 2 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 246 /FPGA_Bank_1_2/TMDS_RX2_1_N)
    )
    (pad 5 smd rect (at 2.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at 3 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 247 /FPGA_Bank_1_2/TMDS_RX2_1_P)
    )
    (pad 3 smd rect (at 3.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 248 /FPGA_Bank_1_2/TMDS_RX2_2_N)
    )
    (pad 2 smd rect (at 4 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at 4.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 249 /FPGA_Bank_1_2/TMDS_RX2_2_P)
    )
    (pad 11 smd rect (at -0.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at -1 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 251 /FPGA_Bank_1_2/TMDS_RX2_CLK_N)
    )
    (pad 13 smd rect (at -1.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 314 /HDMI/P3-CEC)
    )
    (pad 14 smd rect (at -2 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
    )
    (pad 15 smd rect (at -2.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 316 /HDMI/P3-SCL)
    )
    (pad 16 smd rect (at -3 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 317 /HDMI/P3-SDA)
    )
    (pad 17 smd rect (at -3.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 18 smd rect (at -4 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 446 N-00000388)
    )
    (pad 19 smd rect (at -4.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 315 /HDMI/P3-HOT)
    )
    (pad 0 thru_hole oval (at -7.55 0) (size 1.8 3.5) (drill oval 1.1 2.75)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 7.25 0) (size 1.8 3.5) (drill oval 1.1 2.75)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at -8.15 5.96) (size 1.8 2.35) (drill oval 1.1 1.8)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 7.85 5.96) (size 1.8 2.35) (drill oval 1.1 1.8)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module HDMI_TH   locked (layer TOP) (tedit 56373DD0)
    (at 152.229 218.948)
    (fp_text reference J2 (at 9.823 2.601) (layer F.SilkS))
    (fp_text value HDMI (at 0 5.08) (layer F.SilkS) hide)
    (pad 10 smd rect (at 0 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 276 /FPGA_Bank_1_2/TMDS_TX2_CLK_P)
    )
    (pad 9 smd rect (at 0.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 268 /FPGA_Bank_1_2/TMDS_TX2_0_N)
    )
    (pad 8 smd rect (at 1 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at 1.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 269 /FPGA_Bank_1_2/TMDS_TX2_0_P)
    )
    (pad 6 smd rect (at 2 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 270 /FPGA_Bank_1_2/TMDS_TX2_1_N)
    )
    (pad 5 smd rect (at 2.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at 3 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 271 /FPGA_Bank_1_2/TMDS_TX2_1_P)
    )
    (pad 3 smd rect (at 3.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 272 /FPGA_Bank_1_2/TMDS_TX2_2_N)
    )
    (pad 2 smd rect (at 4 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at 4.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 273 /FPGA_Bank_1_2/TMDS_TX2_2_P)
    )
    (pad 11 smd rect (at -0.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at -1 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 275 /FPGA_Bank_1_2/TMDS_TX2_CLK_N)
    )
    (pad 13 smd rect (at -1.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 318 /HDMI/P4-CEC)
    )
    (pad 14 smd rect (at -2 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
    )
    (pad 15 smd rect (at -2.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 320 /HDMI/P4-SCL)
    )
    (pad 16 smd rect (at -3 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 321 /HDMI/P4-SDA)
    )
    (pad 17 smd rect (at -3.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 18 smd rect (at -4 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 304 /HDMI/HDMI-TX2-VCC5V0)
    )
    (pad 19 smd rect (at -4.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 319 /HDMI/P4-HOT)
    )
    (pad 0 thru_hole oval (at -7.55 0) (size 1.8 3.5) (drill oval 1.1 2.75)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 7.25 0) (size 1.8 3.5) (drill oval 1.1 2.75)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at -8.15 5.96) (size 1.8 2.35) (drill oval 1.1 1.8)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 7.85 5.96) (size 1.8 2.35) (drill oval 1.1 1.8)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module HDMI_TH   locked (layer TOP) (tedit 56373DC3)
    (at 128.861 218.948)
    (fp_text reference J3 (at 9.061 2.601) (layer F.SilkS))
    (fp_text value HDMI (at 0 5.08) (layer F.SilkS) hide)
    (pad 10 smd rect (at 0 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 264 /FPGA_Bank_1_2/TMDS_TX1_CLK_P)
    )
    (pad 9 smd rect (at 0.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 256 /FPGA_Bank_1_2/TMDS_TX1_0_N)
    )
    (pad 8 smd rect (at 1 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at 1.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 257 /FPGA_Bank_1_2/TMDS_TX1_0_P)
    )
    (pad 6 smd rect (at 2 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 258 /FPGA_Bank_1_2/TMDS_TX1_1_N)
    )
    (pad 5 smd rect (at 2.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at 3 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 259 /FPGA_Bank_1_2/TMDS_TX1_1_P)
    )
    (pad 3 smd rect (at 3.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 260 /FPGA_Bank_1_2/TMDS_TX1_2_N)
    )
    (pad 2 smd rect (at 4 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at 4.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 261 /FPGA_Bank_1_2/TMDS_TX1_2_P)
    )
    (pad 11 smd rect (at -0.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at -1 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 263 /FPGA_Bank_1_2/TMDS_TX1_CLK_N)
    )
    (pad 13 smd rect (at -1.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 310 /HDMI/P2-CEC)
    )
    (pad 14 smd rect (at -2 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
    )
    (pad 15 smd rect (at -2.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 312 /HDMI/P2-SCL)
    )
    (pad 16 smd rect (at -3 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 313 /HDMI/P2-SDA)
    )
    (pad 17 smd rect (at -3.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 18 smd rect (at -4 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 303 /HDMI/HDMI-TX1-VCC5V0)
    )
    (pad 19 smd rect (at -4.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 311 /HDMI/P2-HOT)
    )
    (pad 0 thru_hole oval (at -7.55 0) (size 1.8 3.5) (drill oval 1.1 2.75)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 7.25 0) (size 1.8 3.5) (drill oval 1.1 2.75)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at -8.15 5.96) (size 1.8 2.35) (drill oval 1.1 1.8)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 7.85 5.96) (size 1.8 2.35) (drill oval 1.1 1.8)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module HDMI_TH   locked (layer TOP) (tedit 56373DE9)
    (at 198.965 218.948)
    (fp_text reference J4 (at 9.061 2.601) (layer F.SilkS))
    (fp_text value HDMI (at 0 5.08) (layer F.SilkS) hide)
    (pad 10 smd rect (at 0 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 240 /FPGA_Bank_1_2/TMDS_RX1_CLK_P)
    )
    (pad 9 smd rect (at 0.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 232 /FPGA_Bank_1_2/TMDS_RX1_0_N)
    )
    (pad 8 smd rect (at 1 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at 1.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 233 /FPGA_Bank_1_2/TMDS_RX1_0_P)
    )
    (pad 6 smd rect (at 2 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 234 /FPGA_Bank_1_2/TMDS_RX1_1_N)
    )
    (pad 5 smd rect (at 2.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at 3 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 235 /FPGA_Bank_1_2/TMDS_RX1_1_P)
    )
    (pad 3 smd rect (at 3.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 236 /FPGA_Bank_1_2/TMDS_RX1_2_N)
    )
    (pad 2 smd rect (at 4 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at 4.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 237 /FPGA_Bank_1_2/TMDS_RX1_2_P)
    )
    (pad 11 smd rect (at -0.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at -1 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 239 /FPGA_Bank_1_2/TMDS_RX1_CLK_N)
    )
    (pad 13 smd rect (at -1.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 306 /HDMI/P1-CEC)
    )
    (pad 14 smd rect (at -2 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
    )
    (pad 15 smd rect (at -2.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 308 /HDMI/P1-SCL)
    )
    (pad 16 smd rect (at -3 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 309 /HDMI/P1-SDA)
    )
    (pad 17 smd rect (at -3.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 18 smd rect (at -4 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 445 N-00000387)
    )
    (pad 19 smd rect (at -4.5 -1.3) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 307 /HDMI/P1-HOT)
    )
    (pad 0 thru_hole oval (at -7.55 0) (size 1.8 3.5) (drill oval 1.1 2.75)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 7.25 0) (size 1.8 3.5) (drill oval 1.1 2.75)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at -8.15 5.96) (size 1.8 2.35) (drill oval 1.1 1.8)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 7.85 5.96) (size 1.8 2.35) (drill oval 1.1 1.8)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552627D1)
    (at 140.16374 99.34688 180)
    (attr smd)
    (fp_text reference C222 (at 3.25774 0.03288 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 77 /Ethernet/ETH_RESET_B)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552627E3)
    (at 140.76064 96.21252 90)
    (attr smd)
    (fp_text reference C229 (at -0.05348 -2.45764 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262810)
    (at 145.37436 92.67952 90)
    (attr smd)
    (fp_text reference C232 (at 2.89052 0.04064 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262820)
    (at 157.40018 90.4391)
    (attr smd)
    (fp_text reference C235 (at 3.38182 -0.0151) (layer B.SilkS))
    (fp_text value 12pF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 99 /Ethernet/XTAL2_50MHZ)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552626BA)
    (at 140.337 87.909 90)
    (attr smd)
    (fp_text reference C234 (at 3.2 0.252 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552626C4)
    (at 142.623 87.909 90)
    (attr smd)
    (fp_text reference C233 (at 3.2 0.252 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552627F5)
    (at 145.419 99.799 270)
    (attr smd)
    (fp_text reference R70 (at 2.436 0.004 270) (layer B.SilkS))
    (fp_text value 390R (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 375 N-00000260)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 92 /Ethernet/LED0)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55261344)
    (at 145.419 99.799 270)
    (attr smd)
    (fp_text reference R71 (at 2.563 0.004 270) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 375 N-00000260)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526133A)
    (at 148.719 94.767)
    (attr smd)
    (fp_text reference R69 (at -0.002 -1.422) (layer F.SilkS))
    (fp_text value 2.49K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 373 N-00000258)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552622E2)
    (at 134.241 87.147)
    (attr smd)
    (fp_text reference R48 (at -2.669 -0.025) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 79 /Ethernet/ETH_RXCTL)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262826)
    (at 157.32144 95.5191)
    (attr smd)
    (fp_text reference C238 (at 3.46056 -0.0151) (layer B.SilkS))
    (fp_text value 12pF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 98 /Ethernet/XTAL1_50MHZ)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A74)
    (at 228.43744 168.90492 180)
    (attr smd)
    (fp_text reference C239 (at 2.75844 -0.00508 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526134E)
    (at 143.387 99.799 270)
    (attr smd)
    (fp_text reference R75 (at 2.563 0.004 270) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 379 N-00000266)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552627FC)
    (at 148.975 98.275)
    (attr smd)
    (fp_text reference R73 (at 2.536 0.023) (layer B.SilkS))
    (fp_text value 390R (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 378 N-00000263)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 93 /Ethernet/LED1)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55261338)
    (at 148.975 98.275)
    (attr smd)
    (fp_text reference R74 (at -0.004 -1.374) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 378 N-00000263)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552622D5)
    (at 134.243 95.227)
    (attr smd)
    (fp_text reference R67 (at -2.671 0.023) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 83 /Ethernet/ETH_RXD3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552622D7)
    (at 134.241 93.243)
    (attr smd)
    (fp_text reference R66 (at -2.669 0.102) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 82 /Ethernet/ETH_RXD2)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SOT223-5   locked (layer TOP) (tedit 5526231D)
    (at 124.079 86.487)
    (descr "module CMS SOT223 4 pins")
    (tags "CMS SOT")
    (attr smd)
    (fp_text reference U19 (at -4.572 -2.54) (layer F.SilkS))
    (fp_text value MCP1825 (at 7.62 0) (layer F.SilkS) hide)
    (pad 6 smd rect (at 0 -3.2) (size 3.3 2.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 3 smd rect (at 0 3) (size 0.65 2.032)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 5 smd rect (at 2.54 3) (size 0.65 2.032)
      (layers TOP F.Paste F.Mask)
      (net 382 N-00000271)
    )
    (pad 2 smd rect (at -1.27 3) (size 0.65 2.032)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 4 smd rect (at 1.27 3) (size 0.65 2.032)
      (layers TOP F.Paste F.Mask)
      (net 97 /Ethernet/VCC1V0)
    )
    (pad 1 smd rect (at -2.54 3) (size 0.65 2.032)
      (layers TOP F.Paste F.Mask)
      (net 380 N-00000268)
    )
    (model TO_SOT_Packages_SMD.3dshapes/SOT-223.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.4 0.4 0.4))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 552613A8)
    (at 125.2855 96.52 270)
    (attr smd)
    (fp_text reference C204 (at 0 -1.7145 270) (layer F.SilkS))
    (fp_text value 1uF (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 97 /Ethernet/VCC1V0)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 552613A6)
    (at 122.809 96.52 270)
    (attr smd)
    (fp_text reference C203 (at 0 1.778 270) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module RJ45_10P-10C   locked (layer TOP) (tedit 55262309)
    (at 141.607 68.097 180)
    (solder_mask_margin 0.254)
    (solder_paste_margin -2.032)
    (fp_text reference J6 (at 8.638 -11.913 180) (layer F.SilkS))
    (fp_text value "RJ45(HFJ11-1GO1ERL)" (at -12.58824 -0.00762 270) (layer F.SilkS) hide)
    (pad 0 thru_hole circle (at 7.745 -3.05 180) (size 2.6 2.6) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole circle (at -7.745 -3.05 180) (size 2.6 2.6) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad "" np_thru_hole circle (at 5.715 0 180) (size 3.55 3.55) (drill 3.5)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad "" np_thru_hole circle (at -5.715 0 180) (size 3.55 3.55) (drill 3.5)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad 4 thru_hole circle (at -1.9 -6.35 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 370 N-00000255)
    )
    (pad 1 thru_hole circle (at -5.71 -8.89 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 374 N-00000259)
    )
    (pad 3 thru_hole circle (at -3.17 -8.89 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 377 N-00000262)
    )
    (pad 5 thru_hole circle (at -0.63 -8.89 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 371 N-00000256)
    )
    (pad 7 thru_hole circle (at 1.91 -8.89 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 372 N-00000257)
    )
    (pad 6 thru_hole circle (at 0.64 -6.35 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 368 N-00000251)
    )
    (pad 8 thru_hole circle (at 3.18 -6.35 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 369 N-00000254)
    )
    (pad 2 thru_hole circle (at -4.44 -6.35 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 376 N-00000261)
    )
    (pad 11 thru_hole circle (at -6.63 4.06 180) (size 2 2) (drill 1.1)
      (layers *.Cu *.Mask F.SilkS)
      (net 383 N-00000275)
    )
    (pad 12 thru_hole circle (at -4.09 4.06 180) (size 2 2) (drill 1.1)
      (layers *.Cu *.Mask F.SilkS)
      (net 92 /Ethernet/LED0)
    )
    (pad 13 thru_hole circle (at 4.09 4.06 180) (size 2 2) (drill 1.1)
      (layers *.Cu *.Mask F.SilkS)
      (net 93 /Ethernet/LED1)
    )
    (pad 14 thru_hole circle (at 6.63 4.06 180) (size 2 2) (drill 1.1)
      (layers *.Cu *.Mask F.SilkS)
      (net 385 N-00000280)
    )
    (pad 10 thru_hole circle (at 5.72 -6.35 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 9 thru_hole circle (at 4.45 -8.89 180) (size 1.91 1.91) (drill 0.91)
      (layers *.Cu *.Mask F.SilkS)
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552622D1)
    (at 134.243 97.259)
    (attr smd)
    (fp_text reference C216 (at -3.052 0.023) (layer F.SilkS))
    (fp_text value 27pF (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 78 /Ethernet/ETH_RXCLK)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552627EC)
    (at 143.11522 95.23462 90)
    (attr smd)
    (fp_text reference C226 (at -2.80938 0.01378 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55261387)
    (at 120.2233 103.88252 270)
    (attr smd)
    (fp_text reference C211 (at 3.55948 0.5893 270) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 5526138A)
    (at 122.7633 103.88252 270)
    (attr smd)
    (fp_text reference C218 (at 3.55948 -0.0457 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55261390)
    (at 129.3673 103.88252 270)
    (attr smd)
    (fp_text reference C225 (at 3.68648 -0.0457 270) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55261394)
    (at 134.4473 103.88252 270)
    (attr smd)
    (fp_text reference C231 (at 3.68648 -0.0457 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 552612EA)
    (at 157.22948 67.0357 180)
    (attr smd)
    (fp_text reference C210 (at -3.67952 -0.0203 180) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.381 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 552612EE)
    (at 157.22948 69.5757 180)
    (attr smd)
    (fp_text reference C217 (at -3.67952 -0.0203 180) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55261311)
    (at 157.22948 78.7197 180)
    (attr smd)
    (fp_text reference C227 (at -3.67952 -0.0203 180) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 73 /Ethernet/AVDD3V3)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 5526131A)
    (at 157.22948 81.2597 180)
    (attr smd)
    (fp_text reference C230 (at -3.67952 -0.0203 180) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 73 /Ethernet/AVDD3V3)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 552622FE)
    (at 121.0869 77.26332 270)
    (attr smd)
    (fp_text reference C212 (at -3.85732 -0.0711 270) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.381 360) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 97 /Ethernet/VCC1V0)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55262303)
    (at 127.6909 77.26332 270)
    (attr smd)
    (fp_text reference C223 (at -3.73032 0.0559 270) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 552612F8)
    (at 158.24548 72.8777 270)
    (attr smd)
    (fp_text reference L6 (at 0.0203 -2.02852 360) (layer F.SilkS))
    (fp_text value INDUCTOR (at 0 0.381 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 73 /Ethernet/AVDD3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 5526138E)
    (at 126.0653 102.86652)
    (attr smd)
    (fp_text reference L7 (at -0.0813 -1.77452) (layer F.SilkS))
    (fp_text value INDUCTOR (at 0 0.381) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55262302)
    (at 124.3889 76.24732)
    (attr smd)
    (fp_text reference L1 (at -0.0559 -1.82532) (layer F.SilkS))
    (fp_text value INDUCTOR (at 0 0.381) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 97 /Ethernet/VCC1V0)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 90 /Ethernet/ETH_VCC1V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526019F)
    (at 152.2509 135.2639 90)
    (attr smd)
    (fp_text reference R103 (at -2.9121 0.0221 90) (layer F.SilkS))
    (fp_text value 10K (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 425 N-00000352)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260BFE)
    (at 136.8298 153.1874 180)
    (attr smd)
    (fp_text reference R111 (at -0.7112 1.4224 180) (layer F.SilkS))
    (fp_text value 10K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 408 N-00000332)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260BF3)
    (at 131.4958 151.1554 180)
    (attr smd)
    (fp_text reference R110 (at 0.0508 1.5494 180) (layer F.SilkS))
    (fp_text value 46.4K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 408 N-00000332)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 477 VCC4V0)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260C02)
    (at 133.7818 155.2194)
    (attr smd)
    (fp_text reference R109 (at -2.9718 0.1016) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 407 N-00000331)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 411 N-00000336)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260CA8)
    (at 247.9983 111.9794)
    (attr smd)
    (fp_text reference R106 (at 3.4617 0.0346) (layer F.SilkS))
    (fp_text value 100K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 439 N-00000369)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552629E9)
    (at 137.8458 151.4094)
    (attr smd)
    (fp_text reference R97 (at -2.8448 0.1016) (layer B.SilkS))
    (fp_text value 1K (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 426 N-00000353)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 422 N-00000349)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552629E7)
    (at 137.8458 149.6314 180)
    (attr smd)
    (fp_text reference R96 (at 2.8448 0.0254 180) (layer B.SilkS))
    (fp_text value 86.6K (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 422 N-00000349)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552629EB)
    (at 140.8938 151.4094 180)
    (attr smd)
    (fp_text reference R95 (at -2.9972 0.0254 180) (layer B.SilkS))
    (fp_text value 200K (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 422 N-00000349)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A08)
    (at 148.5138 154.2034 90)
    (attr smd)
    (fp_text reference R98 (at 3.3274 0.0762 90) (layer B.SilkS))
    (fp_text value 205K (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 410 N-00000335)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260C16)
    (at 143.6878 153.1874 180)
    (attr smd)
    (fp_text reference R108 (at -0.9652 1.4224 180) (layer F.SilkS))
    (fp_text value 100K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 421 N-00000348)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 423 N-00000350)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A06)
    (at 150.5458 154.2034 270)
    (attr smd)
    (fp_text reference R107 (at -2.9464 0.0508 270) (layer B.SilkS))
    (fp_text value 100K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 427 N-00000354)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5526286F)
    (at 151.2349 132.9779)
    (attr smd)
    (fp_text reference R104 (at -2.7719 -0.0089) (layer B.SilkS))
    (fp_text value 100K (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 413 N-00000339)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 424 N-00000351)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552601D6)
    (at 150.4729 128.9139 180)
    (attr smd)
    (fp_text reference R115 (at 2.8989 0.0089 180) (layer F.SilkS))
    (fp_text value 22.1K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 432 N-00000362)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552601A9)
    (at 150.4729 132.4699)
    (attr smd)
    (fp_text reference R114 (at -2.8989 -0.0089) (layer F.SilkS))
    (fp_text value 12.7K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 432 N-00000362)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A0C)
    (at 146.4818 154.2034 90)
    (attr smd)
    (fp_text reference R99 (at 3.3274 0.0762 90) (layer B.SilkS))
    (fp_text value ? (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 434 N-00000364)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260D0C)
    (at 224.7613 81.0937)
    (attr smd)
    (fp_text reference R100 (at -3.7813 0.0593) (layer F.SilkS))
    (fp_text value 10K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 417 N-00000343)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552628C1)
    (at 226.9203 80.0777 270)
    (attr smd)
    (fp_text reference R102 (at -2.9887 -0.0287 270) (layer B.SilkS))
    (fp_text value 100K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 406 N-00000330)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 420 N-00000346)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260D17)
    (at 231.6193 79.0617 90)
    (attr smd)
    (fp_text reference R113 (at 2.9887 0.0287 90) (layer F.SilkS))
    (fp_text value 22.1K (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 433 N-00000363)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260D12)
    (at 229.5873 79.0617 270)
    (attr smd)
    (fp_text reference R112 (at -2.9887 -0.0287 270) (layer F.SilkS))
    (fp_text value 21.5K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 433 N-00000363)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260C9E)
    (at 241.9023 108.1694 90)
    (attr smd)
    (fp_text reference R105 (at 2.5054 0.0327 90) (layer F.SilkS))
    (fp_text value 10K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 409 N-00000333)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260C9C)
    (at 240.6323 108.1694 270)
    (attr smd)
    (fp_text reference R101 (at -2.5054 -0.0327 270) (layer F.SilkS))
    (fp_text value 10K (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 409 N-00000333)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module HC-49V   locked (layer TOP) (tedit 56247D85)
    (at 153.53684 92.9791 270)
    (descr "Quartz boitier HC-49 Vertical")
    (tags "QUARTZ DEV")
    (autoplace_cost180 10)
    (fp_text reference X2 (at -0.00748 -3.98126 270) (layer F.SilkS))
    (fp_text value 50MHz (at 0 3.81 270) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at -2.54 0 270) (size 1.4224 1.4224) (drill 0.762)
      (layers *.Cu *.Mask F.SilkS)
      (net 99 /Ethernet/XTAL2_50MHZ)
    )
    (pad 2 thru_hole circle (at 2.54 0 270) (size 1.4224 1.4224) (drill 0.762)
      (layers *.Cu *.Mask F.SilkS)
      (net 98 /Ethernet/XTAL1_50MHZ)
    )
    (model Crystals.3dshapes/Crystal_HC18-U_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module "QFN-32(USB3340)"   locked (layer TOP) (tedit 5624C176)
    (at 180.3319 100.6348 180)
    (descr "UH Package; 32-Lead Plastic QFN (5mm x 5mm); (see Linear Technology QFN_32_05-08-1693.pdf)")
    (tags "QFN 0.5")
    (attr smd)
    (fp_text reference U18 (at -5.5707 0.3048 180) (layer F.SilkS))
    (fp_text value USB3340 (at 0 5 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.4 -1.75 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at -2.4 -1.25 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 289 /FPGA_Bank_1_2/USB_NXT)
    )
    (pad 3 smd rect (at -2.4 -0.75 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 280 /FPGA_Bank_1_2/USB_D0)
    )
    (pad 4 smd rect (at -2.4 -0.25 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 281 /FPGA_Bank_1_2/USB_D1)
    )
    (pad 5 smd rect (at -2.4 0.25 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 282 /FPGA_Bank_1_2/USB_D2)
    )
    (pad 6 smd rect (at -2.4 0.75 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 283 /FPGA_Bank_1_2/USB_D3)
    )
    (pad 7 smd rect (at -2.4 1.25 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 284 /FPGA_Bank_1_2/USB_D4)
    )
    (pad 8 smd rect (at -2.4 1.75 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 9 smd rect (at -1.75 2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 285 /FPGA_Bank_1_2/USB_D5)
    )
    (pad 10 smd rect (at -1.25 2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 286 /FPGA_Bank_1_2/USB_D6)
    )
    (pad 11 smd rect (at -0.75 2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at -0.25 2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
    )
    (pad 13 smd rect (at 0.25 2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 287 /FPGA_Bank_1_2/USB_D7)
    )
    (pad 14 smd rect (at 0.75 2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 15 smd rect (at 1.25 2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
    )
    (pad 16 smd rect (at 1.75 2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
    )
    (pad 17 smd rect (at 2.4 1.75 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 331 /USB/CPEN)
    )
    (pad 18 smd rect (at 2.4 1.25 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 339 /USB/USB_DP)
    )
    (pad 19 smd rect (at 2.4 0.75 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 338 /USB/USB_DM)
    )
    (pad 20 smd rect (at 2.4 0.25 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 397 N-00000306)
    )
    (pad 21 smd rect (at 2.4 -0.25 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 22 smd rect (at 2.4 -0.75 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 396 N-00000305)
    )
    (pad 23 smd rect (at 2.4 -1.25 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 335 /USB/ID)
    )
    (pad 24 smd rect (at 2.4 -1.75 180) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 404 N-00000319)
    )
    (pad 25 smd rect (at 1.75 -2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
    )
    (pad 26 smd rect (at 1.25 -2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 290 /FPGA_Bank_1_2/USB_REFCLK)
    )
    (pad 27 smd rect (at 0.75 -2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 291 /FPGA_Bank_1_2/USB_RESETB)
    )
    (pad 28 smd rect (at 0.25 -2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 405 N-00000327)
    )
    (pad 29 smd rect (at -0.25 -2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 292 /FPGA_Bank_1_2/USB_STP)
    )
    (pad 30 smd rect (at -0.75 -2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 405 N-00000327)
    )
    (pad 31 smd rect (at -1.25 -2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 288 /FPGA_Bank_1_2/USB_DIR)
    )
    (pad 32 smd rect (at -1.75 -2.4 270) (size 0.8 0.28)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 33 smd rect (at 0.8625 0.8625 180) (size 1.725 1.725)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
      (solder_paste_margin_ratio -0.2)
    )
    (pad 33 smd rect (at 0.8625 -0.8625 180) (size 1.725 1.725)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
      (solder_paste_margin_ratio -0.2)
    )
    (pad 33 smd rect (at -0.8625 0.8625 180) (size 1.725 1.725)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
      (solder_paste_margin_ratio -0.2)
    )
    (pad 33 smd rect (at -0.8625 -0.8625 180) (size 1.725 1.725)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
      (solder_paste_margin_ratio -0.2)
    )
    (model Housings_DFN_QFN.3dshapes/QFN-32-1EP_5x5mm_Pitch0.5mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260C22)
    (at 147.2438 160.2994 180)
    (attr smd)
    (fp_text reference C77 (at -2.8702 0.0254 180) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 55262A38)
    (at 141.6558 163.0934)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C75 (at -0.0508 -2.3114) (layer B.SilkS))
    (fp_text value 22uF (at 0 -0.508) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 55262A34)
    (at 141.6558 167.1574)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C74 (at 0.0762 2.6416) (layer B.SilkS))
    (fp_text value 22uF (at 0 -0.508) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260BC5)
    (at 141.6558 163.0934)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C73 (at -3.9878 0.1016) (layer F.SilkS))
    (fp_text value 22uF (at 0 0.508) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260BC9)
    (at 141.6558 167.1574)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C72 (at 0.0762 3.0226) (layer F.SilkS))
    (fp_text value 22uF (at 0 0.508) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A1F)
    (at 134.0358 155.4734 180)
    (attr smd)
    (fp_text reference C149 (at 2.7178 0.0254 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 412 N-00000337)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 411 N-00000336)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262A15)
    (at 145.9738 157.2514 180)
    (attr smd)
    (fp_text reference C148 (at -3.2512 0.0254 180) (layer B.SilkS))
    (fp_text value 1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 421 N-00000348)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 5535D3C9)
    (at 129.2098 167.6654 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C163 (at -3.6576 0.0762 180) (layer F.SilkS))
    (fp_text value 100uF (at 0 0.508 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 477 VCC4V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 55371FDE)
    (at 131.4958 167.6654 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C160 (at 0.0254 2.4892 90) (layer B.SilkS))
    (fp_text value 100uF (at 0 -0.508 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 90) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 90) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 477 VCC4V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55260BF0)
    (at 129.2098 153.1874)
    (attr smd)
    (fp_text reference C154 (at -3.3528 -0.0254) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 477 VCC4V0)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 407 N-00000331)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55260BF7)
    (at 133.2738 153.1874 180)
    (attr smd)
    (fp_text reference C151 (at -1.0922 1.4224 180) (layer F.SilkS))
    (fp_text value 1NF (at 0 0.381 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 408 N-00000332)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 407 N-00000331)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 5535D3D5)
    (at 127.4318 167.6654 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C157 (at 0.0254 -2.2098 90) (layer B.SilkS))
    (fp_text value 100uF (at 0 -0.508 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 90) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 90) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 477 VCC4V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module "DQP-22(tps53319)"   locked (layer TOP) (tedit 55260C0B)
    (at 139.8778 157.7594)
    (fp_text reference U7 (at 5.4102 -1.2954) (layer F.SilkS))
    (fp_text value TPS53319 (at 0 3.556) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.474976 -2.499995) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 408 N-00000332)
    )
    (pad 2 smd rect (at -2.474976 -2.000123) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 426 N-00000353)
    )
    (pad 3 smd rect (at -2.474976 -1.500251) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 423 N-00000350)
    )
    (pad 4 smd rect (at -2.474976 -1.000379) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 412 N-00000337)
    )
    (pad 5 smd rect (at -2.474976 -0.500507) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
    )
    (pad 6 smd rect (at -2.474976 0.000635) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 411 N-00000336)
    )
    (pad 7 smd rect (at -2.474976 0.503809) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 411 N-00000336)
    )
    (pad 8 smd rect (at -2.474976 1.003681) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 411 N-00000336)
    )
    (pad 9 smd rect (at -2.474976 1.503553) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 411 N-00000336)
    )
    (pad 10 smd rect (at -2.474976 2.003425) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 411 N-00000336)
    )
    (pad 11 smd rect (at -2.474976 2.503297) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 411 N-00000336)
    )
    (pad 12 smd rect (at 2.474976 2.503297) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 13 smd rect (at 2.474976 2.003425) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 14 smd rect (at 2.474976 1.503553) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 15 smd rect (at 2.474976 1.003681) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 16 smd rect (at 2.474976 0.503809) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 17 smd rect (at 2.474976 -0.000635) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 18 smd rect (at 2.474976 -0.500507) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 421 N-00000348)
    )
    (pad 19 smd rect (at 2.474976 -1.000379) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 20 smd rect (at 2.474976 -1.500251) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 427 N-00000354)
    )
    (pad 21 smd rect (at 2.474976 -2.000123) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 410 N-00000335)
    )
    (pad 22 smd rect (at 2.474976 -2.499995) (size 0.8509 0.2794)
      (layers TOP F.Paste F.Mask)
      (net 434 N-00000364)
    )
    (pad 23 smd rect (at 0 0) (size 3.2512 5.4864)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module "PDSO_G14(tps54625)"   locked (layer TOP) (tedit 55372079)
    (at 157.3309 131.7079 270)
    (fp_text reference U9 (at -3.8189 3.0259 360) (layer F.SilkS))
    (fp_text value TPS54625 (at 0.508 5.334 270) (layer F.SilkS) hide)
    (pad 14 smd rect (at -1.95 -2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 13 smd rect (at -1.3 -2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 12 smd rect (at -0.65 -2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 415 N-00000341)
    )
    (pad 11 smd rect (at 0 -2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 438 N-00000368)
    )
    (pad 10 smd rect (at 0.65 -2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 438 N-00000368)
    )
    (pad 9 smd rect (at 1.3 -2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 8 smd rect (at 1.95 -2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at 1.95 2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 425 N-00000352)
    )
    (pad 6 smd rect (at 1.3 2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 424 N-00000351)
    )
    (pad 5 smd rect (at 0.65 2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at 0 2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 414 N-00000340)
    )
    (pad 3 smd rect (at -0.65 2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 413 N-00000339)
    )
    (pad 2 smd rect (at -1.3 2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 432 N-00000362)
    )
    (pad 1 smd rect (at -1.95 2.9 270) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad 15 smd rect (at 0 0 270) (size 4.5 2.3)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module "PDSO_G14(tps54625)"   locked (layer TOP) (tedit 55260D22)
    (at 228.3173 86.6817 180)
    (fp_text reference U8 (at -4.4737 3.8777 180) (layer F.SilkS))
    (fp_text value TPS54625 (at 0.508 5.334 180) (layer F.SilkS) hide)
    (pad 14 smd rect (at -1.95 -2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 13 smd rect (at -1.3 -2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 12 smd rect (at -0.65 -2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 418 N-00000344)
    )
    (pad 11 smd rect (at 0 -2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 419 N-00000345)
    )
    (pad 10 smd rect (at 0.65 -2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 419 N-00000345)
    )
    (pad 9 smd rect (at 1.3 -2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 8 smd rect (at 1.95 -2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at 1.95 2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 417 N-00000343)
    )
    (pad 6 smd rect (at 1.3 2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 420 N-00000346)
    )
    (pad 5 smd rect (at 0.65 2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at 0 2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 416 N-00000342)
    )
    (pad 3 smd rect (at -0.65 2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 406 N-00000330)
    )
    (pad 2 smd rect (at -1.3 2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 433 N-00000363)
    )
    (pad 1 smd rect (at -1.95 2.9 180) (size 0.3 1.2)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad 15 smd rect (at 0 0 180) (size 4.5 2.3)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module "SON_10(tps51200)"   locked (layer TOP) (tedit 54E723A3)
    (at 242.4103 112.4874 90)
    (fp_text reference U12 (at 4.591 4.061 180) (layer F.SilkS))
    (fp_text value TPS51200 (at 0 -3.9 90) (layer F.SilkS) hide)
    (pad 3 smd rect (at 0 -1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 478 VTTDDR0)
    )
    (pad 8 smd rect (at 0 1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.5 -1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (pad 1 smd rect (at 1 -1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 409 N-00000333)
    )
    (pad 4 smd rect (at -0.5 -1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 5 smd rect (at -1 -1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 478 VTTDDR0)
    )
    (pad 7 smd rect (at -0.5 1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 6 smd rect (at -1 1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 479 VTTREF)
    )
    (pad 9 smd rect (at 0.5 1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 439 N-00000369)
    )
    (pad 10 smd rect (at 1 1.68 90) (size 0.28 0.8)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 11 smd rect (at 0 0 90) (size 3.5 1.65)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module TPS54560   locked (layer TOP) (tedit 55260A8E)
    (at 271.5148 112.208 270)
    (fp_text reference U6 (at 3.616 -3.4402 360) (layer F.SilkS))
    (fp_text value TPS54560 (at 0 4.6 270) (layer F.SilkS) hide)
    (pad 8 smd rect (at -1.905 -2.7 270) (size 0.51 1.2)
      (layers TOP F.Paste F.Mask)
      (net 437 N-00000367)
    )
    (pad 7 smd rect (at -0.635 -2.7 270) (size 0.51 1.2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 6 smd rect (at 0.635 -2.7 270) (size 0.51 1.2)
      (layers TOP F.Paste F.Mask)
      (net 429 N-00000359)
    )
    (pad 5 smd rect (at 1.905 -2.7 270) (size 0.51 1.2)
      (layers TOP F.Paste F.Mask)
      (net 430 N-00000360)
    )
    (pad 4 smd rect (at 1.905 2.7 270) (size 0.51 1.2)
      (layers TOP F.Paste F.Mask)
      (net 435 N-00000365)
    )
    (pad 3 smd rect (at 0.635 2.7 270) (size 0.51 1.2)
      (layers TOP F.Paste F.Mask)
      (net 436 N-00000366)
    )
    (pad 2 smd rect (at -0.635 2.7 270) (size 0.51 1.2)
      (layers TOP F.Paste F.Mask)
      (net 326 "/Power/VIN 48")
    )
    (pad 1 smd rect (at -1.905 2.7 270) (size 0.51 1.2)
      (layers TOP F.Paste F.Mask)
      (net 431 N-00000361)
    )
    (pad 9 smd rect (at 0 0 270) (size 3.1 2.4)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module SM0603_Resistor   locked (layer TOP) (tedit 564046B6)
    (at 277.6108 117.542)
    (attr smd)
    (fp_text reference R90 (at 0.4892 1.683) (layer F.SilkS))
    (fp_text value 143K (at -1.69926 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 430 N-00000360)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 322 "/Power/Conference 12V")
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603_Resistor   locked (layer TOP) (tedit 55260A75)
    (at 274.3088 117.542)
    (attr smd)
    (fp_text reference R91 (at 0.9002 1.711) (layer F.SilkS))
    (fp_text value 10.2K (at -1.69926 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 430 N-00000360)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260AAE)
    (at 263.6408 110.176)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C57 (at -4.6878 0.06) (layer F.SilkS))
    (fp_text value 2.2uF (at 0 0.508) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 326 "/Power/VIN 48")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603_Capa   locked (layer TOP) (tedit 55260A85)
    (at 279.1348 112.208 90)
    (attr smd)
    (fp_text reference C63 (at 2.48 0.0112 90) (layer F.SilkS))
    (fp_text value 6.2nF (at -1.651 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 428 N-00000357)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603_Capa   locked (layer TOP) (tedit 55260A83)
    (at 277.1028 112.208 270)
    (attr smd)
    (fp_text reference C65 (at -2.607 -0.0112 270) (layer F.SilkS))
    (fp_text value 4.7uF (at -1.651 0 360) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 429 N-00000359)
    )
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603_Capa   locked (layer TOP) (tedit 55260AA6)
    (at 268.2128 108.144)
    (attr smd)
    (fp_text reference C60 (at -2.5288 -0.956) (layer F.SilkS))
    (fp_text value 0.1uF (at -1.651 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 431 N-00000361)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 437 N-00000367)
    )
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 5526292A)
    (at 257.429 88.011 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C71 (at 0 2.413 270) (layer B.SilkS))
    (fp_text value 47uF (at 0 -0.508 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 270) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 270) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 322 "/Power/Conference 12V")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 553DCE71)
    (at 255.0048 97.476 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C70 (at -3.743 -1.0048 90) (layer F.SilkS))
    (fp_text value 47uF (at 0 0.508 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 322 "/Power/Conference 12V")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260AE4)
    (at 258.8148 97.476 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C68 (at -3.743 -0.8778 90) (layer F.SilkS))
    (fp_text value 47uF (at 0 0.508 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 322 "/Power/Conference 12V")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260AEA)
    (at 262.6248 97.476 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C67 (at -3.743 -1.0048 90) (layer F.SilkS))
    (fp_text value 47uF (at 0 0.508 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 322 "/Power/Conference 12V")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 564046AF)
    (at 283.845 119.38 180)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C45 (at 0.095 2.455 180) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.508 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 180) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 180) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 326 "/Power/VIN 48")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603_Capa   locked (layer TOP) (tedit 5535D190)
    (at 271.0068 116.526)
    (attr smd)
    (fp_text reference R79 (at -2.5288 -0.956) (layer F.SilkS))
    (fp_text value 243K (at -1.651 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 435 N-00000365)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55261267)
    (at 283.845 123.444 180)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C51 (at 4.445 0 180) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.508 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 180) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 180) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 326 "/Power/VIN 48")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260A4F)
    (at 263.6408 117.288)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C48 (at -4.6878 -0.067) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.508) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 326 "/Power/VIN 48")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260A46)
    (at 263.6408 113.732)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C55 (at -4.6878 0.06) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.508) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 326 "/Power/VIN 48")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 5526293F)
    (at 283.845 119.38 180)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C56 (at 0 -2.794 180) (layer B.SilkS))
    (fp_text value 4.7uF (at 0 -0.508 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 180) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 180) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 326 "/Power/VIN 48")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 55262934)
    (at 261.239 88.011 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C69 (at 0 -2.667 270) (layer B.SilkS))
    (fp_text value 47uF (at 0 -0.508 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 270) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 270) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 322 "/Power/Conference 12V")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603_Capa   locked (layer TOP) (tedit 5535D17A)
    (at 271.0068 118.558)
    (attr smd)
    (fp_text reference R78 (at 0.0112 1.584) (layer F.SilkS))
    (fp_text value 92.3K (at -1.651 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 436 N-00000366)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603_Capa   locked (layer TOP) (tedit 553DB44D)
    (at 267.9588 117.796 270)
    (attr smd)
    (fp_text reference R77 (at 2.346 1.3858 360) (layer F.SilkS))
    (fp_text value 442K (at -1.651 0 360) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 436 N-00000366)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 326 "/Power/VIN 48")
    )
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module Power_Inductor   locked (layer TOP) (tedit 55260AB8)
    (at 275.5788 93.158 270)
    (fp_text reference L2 (at 0.06 -3.1862 360) (layer F.SilkS))
    (fp_text value 7.2uH (at 0.2 11.2 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at 0 0 270) (size 3.4 2.4)
      (layers TOP F.Paste F.Mask)
      (net 437 N-00000367)
    )
    (pad 2 smd rect (at 0 8.2 270) (size 3.4 2.4)
      (layers TOP F.Paste F.Mask)
      (net 322 "/Power/Conference 12V")
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260D2A)
    (at 238.4773 88.2057 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C79 (at -4.1317 0.3523 270) (layer F.SilkS))
    (fp_text value 10uF (at 0 0.508 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 270) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0 270) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer BOTTOM) (tedit 55262984)
    (at 237.5763 108.2174)
    (attr smd)
    (fp_text reference C81 (at -3.1343 -0.0134) (layer B.SilkS))
    (fp_text value 10uF (at 0 -0.381) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 475 VCC1V5)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1812   locked (layer TOP) (tedit 552601EA)
    (at 158.0929 139.8359)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C167 (at 0.0221 4.9441 90) (layer F.SilkS))
    (fp_text value 47uF (at 0.762 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.286 0) (size 1.397 3.81)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 2.286 0) (size 1.397 3.81)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.21 0.3 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260D26)
    (at 234.4133 88.2057 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C78 (at 4.1317 1.0447 90) (layer F.SilkS))
    (fp_text value 10uF (at 0 0.508 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 1.524 0 90) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526022C)
    (at 164.1889 126.8819)
    (attr smd)
    (fp_text reference C80 (at 2.8161 -0.0089) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer BOTTOM) (tedit 55262863)
    (at 152.2509 136.0259)
    (attr smd)
    (fp_text reference C144 (at 0.0221 1.6421) (layer B.SilkS))
    (fp_text value 8.2NF (at 0 -0.381) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 414 N-00000340)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55260232)
    (at 164.9509 129.9299 180)
    (attr smd)
    (fp_text reference C152 (at -3.1971 0.0089 180) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 438 N-00000368)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 415 N-00000341)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1812   locked (layer BOTTOM) (tedit 552628AD)
    (at 221.4593 87.6977 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C161 (at -0.0677 4.2893 360) (layer B.SilkS))
    (fp_text value 47uF (at 0.762 0 360) (layer B.SilkS) hide)
    (pad 1 smd rect (at -2.286 0 270) (size 1.397 3.81)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 2.286 0 270) (size 1.397 3.81)
      (layers BOTTOM B.Paste B.Mask)
      (net 475 VCC1V5)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.21 0.3 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1206   locked (layer BOTTOM) (tedit 5526291D)
    (at 238.4773 88.2057 270)
    (attr smd)
    (fp_text reference C133 (at 0.0593 -2.5687 270) (layer B.SilkS))
    (fp_text value 10uF (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.651 0 270) (size 1.524 2.032)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.651 0 270) (size 1.524 2.032)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.16 0.16))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262871)
    (at 151.9969 130.1839 270)
    (attr smd)
    (fp_text reference C141 (at -2.8029 -0.0221 270) (layer B.SilkS))
    (fp_text value 1uF (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 413 N-00000339)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552628CA)
    (at 229.3333 80.5857 180)
    (attr smd)
    (fp_text reference C137 (at -2.9497 -0.0593 180) (layer B.SilkS))
    (fp_text value 1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 406 N-00000330)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer BOTTOM) (tedit 552628B9)
    (at 223.9993 81.5382 270)
    (attr smd)
    (fp_text reference C143 (at -0.0042 1.8763 270) (layer B.SilkS))
    (fp_text value 8.2NF (at 0 -0.381 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 270) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0 270) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 416 N-00000342)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1206   locked (layer BOTTOM) (tedit 5526288C)
    (at 158.8549 121.8019)
    (attr smd)
    (fp_text reference C140 (at 0.0221 -3.3109) (layer B.SilkS))
    (fp_text value 10uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.651 0) (size 1.524 2.032)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.651 0) (size 1.524 2.032)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.16 0.16))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 55262885)
    (at 158.8549 125.6119)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C134 (at 0.0221 3.2931) (layer B.SilkS))
    (fp_text value 10uF (at 0 -0.508) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 5535D108)
    (at 231.3653 96.5877 90)
    (attr smd)
    (fp_text reference C150 (at -3.2343 0.0287 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 419 N-00000345)
    )
    (pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 418 N-00000344)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1812   locked (layer BOTTOM) (tedit 55262857)
    (at 158.0929 139.8359)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C164 (at 0.0221 4.4361 90) (layer B.SilkS))
    (fp_text value 47uF (at 0.762 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -2.286 0) (size 1.397 3.81)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 2.286 0) (size 1.397 3.81)
      (layers BOTTOM B.Paste B.Mask)
      (net 474 VCC1V2)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.21 0.3 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55260C92)
    (at 237.5843 110.4554)
    (attr smd)
    (fp_text reference C138 (at -3.6503 0.0346) (layer F.SilkS))
    (fp_text value 10uF (at 0 0.381) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260D30)
    (at 233.6513 92.7777 270)
    (attr smd)
    (fp_text reference C142 (at 3.2343 -0.0287 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260D0F)
    (at 227.5553 79.0617 90)
    (attr smd)
    (fp_text reference C155 (at 2.9887 0.0287 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 433 N-00000363)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260213)
    (at 158.8549 121.8019)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C139 (at -6.0739 -0.0089) (layer F.SilkS))
    (fp_text value 10uF (at 0 0.508) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer BOTTOM) (tedit 5526297B)
    (at 237.5763 115.0754)
    (attr smd)
    (fp_text reference C166 (at -3.5153 -0.0134) (layer B.SilkS))
    (fp_text value 10uF (at 0 -0.381) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer BOTTOM) (tedit 55262981)
    (at 237.5763 110.5034 180)
    (attr smd)
    (fp_text reference C136 (at 3.5153 0.0134 180) (layer B.SilkS))
    (fp_text value 10uF (at 0 -0.381 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 475 VCC1V5)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer TOP) (tedit 55260202)
    (at 158.8549 125.6119)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C145 (at -6.0739 -0.0089) (layer F.SilkS))
    (fp_text value 10uF (at 0 0.508) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.524 0) (size 1.27 2.54)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55260C8F)
    (at 237.5843 112.9954)
    (attr smd)
    (fp_text reference C156 (at -3.6503 0.0346) (layer F.SilkS))
    (fp_text value 10uF (at 0 0.381) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 478 VTTDDR0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1812   locked (layer TOP) (tedit 55260D1E)
    (at 221.4593 87.6977 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C165 (at -0.0677 4.2893 360) (layer F.SilkS))
    (fp_text value 47uF (at 0.762 0 360) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.286 0 270) (size 1.397 3.81)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 2.286 0 270) (size 1.397 3.81)
      (layers TOP F.Paste F.Mask)
      (net 475 VCC1V5)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.21 0.3 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer BOTTOM) (tedit 55262979)
    (at 237.5763 117.1074)
    (attr smd)
    (fp_text reference C159 (at -3.5153 -0.0134) (layer B.SilkS))
    (fp_text value 10uF (at 0 -0.381) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers BOTTOM B.Paste B.Mask)
      (net 478 VTTDDR0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55260C8C)
    (at 237.5843 115.0274)
    (attr smd)
    (fp_text reference C162 (at -3.6503 0.0346) (layer F.SilkS))
    (fp_text value 10uF (at 0 0.381) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 478 VTTDDR0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 55260CA5)
    (at 248.2523 109.9474 180)
    (attr smd)
    (fp_text reference C147 (at -3.2077 -0.0346 180) (layer F.SilkS))
    (fp_text value 4.7uF (at 0 0.381 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0805   locked (layer TOP) (tedit 5535D130)
    (at 246.7283 116.5514 90)
    (attr smd)
    (fp_text reference C153 (at -2.8286 -0.0943 180) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0.381 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397)
      (layers TOP F.Paste F.Mask)
      (net 479 VTTREF)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.1 0.1 0.1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210   locked (layer BOTTOM) (tedit 55262919)
    (at 234.4133 88.2057 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C135 (at -4.2503 0.0287 90) (layer B.SilkS))
    (fp_text value 10uF (at 0 -0.508 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.524 0 90) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 1.524 0 90) (size 1.27 2.54)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552601D1)
    (at 150.4729 130.6919)
    (attr smd)
    (fp_text reference C158 (at -2.8989 -0.0089) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 474 VCC1V2)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 432 N-00000362)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module IND202   locked (layer TOP) (tedit 55372019)
    (at 130.4798 160.5534 180)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference L3 (at -5.0292 -2.6416 180) (layer F.SilkS))
    (fp_text value 2.2UH (at 0 0.508 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.54 0 180) (size 3.5 2.5)
      (layers TOP F.Paste F.Mask)
      (net 411 N-00000336)
    )
    (pad 2 smd rect (at 2.54 0 180) (size 3.5 2.5)
      (layers TOP F.Paste F.Mask)
      (net 477 VCC4V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.17 0.2 0.17))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260272)
    (at 173.67504 101.40188 90)
    (attr smd)
    (fp_text reference C37 (at -3.24612 0.06096 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 397 N-00000306)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552602A4)
    (at 181.0939 106.4768 270)
    (attr smd)
    (fp_text reference C34 (at 2.8702 -0.0081 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 405 N-00000327)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526029E)
    (at 179.0619 106.4768 270)
    (attr smd)
    (fp_text reference C35 (at 2.8702 -0.0081 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 405 N-00000327)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module Display_Port (layer TOP) (tedit 56373DF5)
    (at 236.93882 215.73998)
    (descr "Display Port 1.1a")
    (tags 670-2589-1-ND)
    (fp_text reference J8 (at 10.06348 4.03352) (layer F.SilkS))
    (fp_text value DISPLAY_PORT (at 0 5.08) (layer F.SilkS) hide)
    (pad 12 smd rect (at 0 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 467 N-00000428)
    )
    (pad 11 smd rect (at 0.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 10 smd rect (at 1 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 468 N-00000429)
    )
    (pad 9 smd rect (at 1.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 458 N-00000418)
    )
    (pad 8 smd rect (at 2 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at 2.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 462 N-00000422)
    )
    (pad 6 smd rect (at 3 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 461 N-00000421)
    )
    (pad 5 smd rect (at 3.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at 4 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 460 N-00000420)
    )
    (pad 3 smd rect (at 4.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 459 N-00000419)
    )
    (pad 13 smd rect (at -0.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 63 /DisplayPort/DPTXCONFIG1)
    )
    (pad 14 smd rect (at -1 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 64 /DisplayPort/DPTXCONFIG2)
    )
    (pad 15 smd rect (at -1.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 465 N-00000426)
    )
    (pad 16 smd rect (at -2 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 17 smd rect (at -2.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 466 N-00000427)
    )
    (pad 18 smd rect (at -3 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 216 /FPGA_Bank_1_2/DPTXHPD)
    )
    (pad 19 smd rect (at -3.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 20 smd rect (at -4 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 470 N-00000431)
    )
    (pad 0 thru_hole oval (at -8.25 0) (size 1.3 2.3) (drill oval 0.65 1.65)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 8.25 0) (size 1.3 2.3) (drill oval 0.65 1.65)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at -8.25 6.78) (size 1.3 1.9) (drill oval 0.65 1.2)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 0 thru_hole oval (at 8.25 6.78) (size 1.3 1.9) (drill oval 0.65 1.2)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad "" np_thru_hole circle (at 0 7.68) (size 1.45 1.45) (drill 1.45)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad 2 smd rect (at 5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at 5.5 -2.6) (size 0.3302 2.75)
      (layers TOP F.Paste F.Mask)
      (net 457 N-00000417)
    )
  )
  (module SO8E_N   locked (layer TOP) (tedit 5534A6D8)
    (at 231.521 167.005 90)
    (descr "module CMS SOJ 8 pins etroit")
    (tags "CMS SOJ")
    (attr smd)
    (fp_text reference U23 (at 0.127 -6.731 180) (layer F.SilkS))
    (fp_text value 24AA02E48 (at 0 1.016 90) (layer F.SilkS) hide)
    (pad 8 smd rect (at -1.905 -3.22 90) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 1 smd rect (at -1.905 3.22 90) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 7 smd rect (at -0.635 -3.22 90) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 96 /Ethernet/MAC_WP)
    )
    (pad 6 smd rect (at 0.635 -3.22 90) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 94 /Ethernet/MAC_SCL)
    )
    (pad 5 smd rect (at 1.905 -3.22 90) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 95 /Ethernet/MAC_SDA)
    )
    (pad 2 smd rect (at -0.635 3.22 90) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 3 smd rect (at 0.635 3.22 90) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 384 N-00000279)
    )
    (pad 4 smd rect (at 1.905 3.22 90) (size 0.59944 2.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/cms_so8.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.5 0.32 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM2512   locked (layer TOP) (tedit 55260B19)
    (at 245.1862 88.4936 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference F1 (at 0.1524 -3.4798 360) (layer F.SilkS))
    (fp_text value FUSE (at 0.89916 0 360) (layer F.SilkS) hide)
    (fp_text user + (at -4.59994 2.30124 270) (layer F.SilkS))
    (pad 1 smd rect (at -2.99974 0 270) (size 1.99898 2.99974)
      (layers TOP F.Paste F.Mask)
      (net 441 N-00000372)
    )
    (pad 2 smd rect (at 2.99974 0 270) (size 1.99898 2.99974)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_smd_pol_wide.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.35 0.35 0.35))
      (rotate (xyz 0 0 0))
    )
  )
  (module ScrewTerm2   locked (layer TOP) (tedit 553743BA)
    (at 250.44908 60.43422)
    (fp_text reference P1 (at 9.4615 4.6101) (layer F.SilkS))
    (fp_text value CONN_2 (at 2.54 6.985) (layer F.SilkS) hide)
    (pad 1 thru_hole oval (at 0 0) (size 2.032 4.064) (drill 1.3208)
      (layers *.Cu *.Mask F.SilkS)
      (net 325 "/Power/VIN -48V")
    )
    (pad 2 thru_hole oval (at 5.08 0) (size 2.032 4.064) (drill 1.3208)
      (layers *.Cu *.Mask F.SilkS)
      (net 324 "/Power/VIN +48V")
    )
  )
  (module BARREL_JACK   locked (layer TOP) (tedit 5624D23A)
    (at 270.45412 64.77508 270)
    (descr "DC Barrel Jack")
    (tags "Power Jack")
    (fp_text reference CON1 (at 6.34492 -7.29488 360) (layer F.SilkS))
    (fp_text value BARREL_JACK (at 0 -5.99948 270) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at 6.20014 0 270) (size 3.50012 3.50012) (drill oval 1.1 3.2)
      (layers *.Cu *.Mask F.SilkS)
      (net 324 "/Power/VIN +48V")
    )
    (pad 2 thru_hole rect (at 0.20066 0 270) (size 3.50012 3.50012) (drill oval 1.00076 2.99974)
      (layers *.Cu *.Mask F.SilkS)
      (net 325 "/Power/VIN -48V")
    )
    (pad 3 thru_hole rect (at 3.2004 4.699 270) (size 3.50012 3.50012) (drill oval 2.99974 1.00076)
      (layers *.Cu *.Mask F.SilkS)
      (net 325 "/Power/VIN -48V")
    )
  )
  (module BARREL_JACK   locked (layer TOP) (tedit 56388202)
    (at 239.22228 64.65316 270)
    (descr "DC Barrel Jack")
    (tags "Power Jack")
    (fp_text reference CON2 (at 5.18414 -5.77596 270) (layer F.SilkS))
    (fp_text value BARREL_JACK (at 0 -5.99948 270) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at 6.20014 0 270) (size 3.50012 3.50012) (drill oval 1.1 3.2)
      (layers *.Cu *.Mask F.SilkS)
      (net 323 "/Power/Consumer 12V")
    )
    (pad 2 thru_hole rect (at 0.20066 0 270) (size 3.50012 3.50012) (drill oval 1.00076 2.99974)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 3 thru_hole rect (at 3.2004 4.699 270) (size 3.50012 3.50012) (drill oval 2.99974 1.00076)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552607D7)
    (at 192.615 212.217 90)
    (attr smd)
    (fp_text reference R141 (at 2.54 0.044 90) (layer F.SilkS))
    (fp_text value 49K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 309 /HDMI/P1-SDA)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5624EAD5)
    (at 247.13946 181.6608)
    (attr smd)
    (fp_text reference R151 (at 0.0889 1.10236) (layer F.SilkS))
    (fp_text value 4.7K (at 0.09906 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 96 /Ethernet/MAC_WP)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 381 N-00000269)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552607DA)
    (at 193.885 212.217 90)
    (attr smd)
    (fp_text reference R142 (at 2.54 0.044 90) (layer F.SilkS))
    (fp_text value 49K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 308 /HDMI/P1-SCL)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552607DE)
    (at 195.155 212.217 90)
    (attr smd)
    (fp_text reference R146 (at 0 1.441 90) (layer F.SilkS))
    (fp_text value 27K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 306 /HDMI/P1-CEC)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260714)
    (at 169.247 212.217 90)
    (attr smd)
    (fp_text reference R196 (at 2.54 0.044 90) (layer F.SilkS))
    (fp_text value 49K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 317 /HDMI/P3-SDA)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260710)
    (at 170.517 212.217 90)
    (attr smd)
    (fp_text reference R197 (at 2.54 0.044 90) (layer F.SilkS))
    (fp_text value 49K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 316 /HDMI/P3-SCL)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5526070D)
    (at 171.787 212.217 90)
    (attr smd)
    (fp_text reference R199 (at 0 1.187 90) (layer F.SilkS))
    (fp_text value 27K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 314 /HDMI/P3-CEC)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5526064F)
    (at 145.879 212.217 90)
    (attr smd)
    (fp_text reference R138 (at 2.54 0.044 90) (layer F.SilkS))
    (fp_text value 1.5K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 321 /HDMI/P4-SDA)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5526064D)
    (at 147.149 212.217 90)
    (attr smd)
    (fp_text reference R140 (at 2.54 0.044 90) (layer F.SilkS))
    (fp_text value 1.5K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 320 /HDMI/P4-SCL)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5526064B)
    (at 148.419 212.217 90)
    (attr smd)
    (fp_text reference R144 (at 0 1.314 90) (layer F.SilkS))
    (fp_text value 27K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 318 /HDMI/P4-CEC)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5534AB07)
    (at 144.609 212.217 90)
    (attr smd)
    (fp_text reference R149 (at 0 -1.099 90) (layer F.SilkS))
    (fp_text value 15K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 319 /HDMI/P4-HOT)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552605E5)
    (at 121.241 212.217 90)
    (attr smd)
    (fp_text reference R148 (at 0 -0.972 90) (layer F.SilkS))
    (fp_text value 15K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 311 /HDMI/P2-HOT)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552605E9)
    (at 125.051 212.217 90)
    (attr smd)
    (fp_text reference R143 (at 0 1.314 90) (layer F.SilkS))
    (fp_text value 27K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 310 /HDMI/P2-CEC)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552605ED)
    (at 123.781 212.217 90)
    (attr smd)
    (fp_text reference R139 (at 2.667 0.044 90) (layer F.SilkS))
    (fp_text value 1.5K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 312 /HDMI/P2-SCL)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552605F2)
    (at 122.511 212.217 90)
    (attr smd)
    (fp_text reference R137 (at 2.667 0.044 90) (layer F.SilkS))
    (fp_text value 1.5K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 313 /HDMI/P2-SDA)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5624B405)
    (at 166.7002 212.2424 90)
    (attr smd)
    (fp_text reference R205 (at 2.3368 0.0762 90) (layer F.SilkS))
    (fp_text value 1K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 315 /HDMI/P3-HOT)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5624BAEF)
    (at 190.0682 212.217 90)
    (attr smd)
    (fp_text reference R153 (at 2.5654 0 90) (layer F.SilkS))
    (fp_text value 1K (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 307 /HDMI/P1-HOT)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552607D4)
    (at 191.3382 212.217 90)
    (attr smd)
    (fp_text reference C172 (at 2.54 0.044 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 307 /HDMI/P1-HOT)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260117)
    (at 193.421 68.06184 270)
    (attr smd)
    (fp_text reference R76 (at 2.80416 0 270) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 350 N-00000198)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 299 /FPGA_Power/TMS)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module PCIe_98Pos   locked (layer TOP) (tedit 553765C6)
    (at 279.713 169.725 90)
    (fp_text reference U25 (at -17.727 3.624 180) (layer F.SilkS))
    (fp_text value TIMVIDEOS-PCIE-8X (at 0.1 11.3 90) (layer F.SilkS) hide)
    (pad "" np_thru_hole circle (at 40.15 0 90) (size 2.45 2.45) (drill 2.45)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad "" np_thru_hole circle (at 0 0 90) (size 2.45 2.45) (drill 2.45)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad A1 thru_hole rect (at -11.65 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 302 /GPIOs/PRSNT)
    )
    (pad A2 thru_hole circle (at -10.65 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 473 VCC12V0)
    )
    (pad A3 thru_hole circle (at -9.65 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 473 VCC12V0)
    )
    (pad A4 thru_hole circle (at -8.65 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A5 thru_hole circle (at -7.65 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 113 /FPGA_Bank_0_3/DIFFIO_A0P)
    )
    (pad A6 thru_hole circle (at -6.65 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 112 /FPGA_Bank_0_3/DIFFIO_A0N)
    )
    (pad A7 thru_hole circle (at -5.65 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 127 /FPGA_Bank_0_3/DIFFIO_B0P)
    )
    (pad A8 thru_hole circle (at -4.65 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 126 /FPGA_Bank_0_3/DIFFIO_B0N)
    )
    (pad A9 thru_hole circle (at -3.65 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (pad A10 thru_hole circle (at -2.65 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (pad A11 thru_hole circle (at -1.65 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 153 /FPGA_Bank_0_3/PCIE_RESET)
    )
    (pad A12 thru_hole circle (at 1.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A13 thru_hole circle (at 2.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 111 /FPGA_Bank_0_3/DIFFCLK_XP)
    )
    (pad A14 thru_hole circle (at 3.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 110 /FPGA_Bank_0_3/DIFFCLK_XN)
    )
    (pad A15 thru_hole circle (at 4.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A16 thru_hole circle (at 5.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 115 /FPGA_Bank_0_3/DIFFIO_A1P)
    )
    (pad A17 thru_hole circle (at 6.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 114 /FPGA_Bank_0_3/DIFFIO_A1N)
    )
    (pad A18 thru_hole circle (at 7.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A19 thru_hole circle (at 8.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 143 /FPGA_Bank_0_3/DIFFIO_YP)
    )
    (pad A20 thru_hole circle (at 9.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A21 thru_hole circle (at 10.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 117 /FPGA_Bank_0_3/DIFFIO_A2P)
    )
    (pad A22 thru_hole circle (at 11.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 116 /FPGA_Bank_0_3/DIFFIO_A2N)
    )
    (pad A23 thru_hole circle (at 12.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A24 thru_hole circle (at 13.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A25 thru_hole circle (at 14.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 119 /FPGA_Bank_0_3/DIFFIO_A3P)
    )
    (pad A26 thru_hole circle (at 15.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 118 /FPGA_Bank_0_3/DIFFIO_A3N)
    )
    (pad A27 thru_hole circle (at 16.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A28 thru_hole circle (at 17.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A29 thru_hole circle (at 18.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 103 /FPGA_Bank_0_3/DIFFCLK_A0P)
    )
    (pad A30 thru_hole circle (at 19.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 102 /FPGA_Bank_0_3/DIFFCLK_A0N)
    )
    (pad A31 thru_hole circle (at 20.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A32 thru_hole circle (at 21.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 145 /FPGA_Bank_0_3/DIFFIO_ZP)
    )
    (pad A33 thru_hole circle (at 22.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad A34 thru_hole circle (at 23.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A35 thru_hole circle (at 24.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 121 /FPGA_Bank_0_3/DIFFIO_A4P)
    )
    (pad A36 thru_hole circle (at 25.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 120 /FPGA_Bank_0_3/DIFFIO_A4N)
    )
    (pad A37 thru_hole circle (at 26.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A38 thru_hole circle (at 27.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A39 thru_hole circle (at 28.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 123 /FPGA_Bank_0_3/DIFFIO_A5P)
    )
    (pad A40 thru_hole circle (at 29.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 122 /FPGA_Bank_0_3/DIFFIO_A5N)
    )
    (pad A41 thru_hole circle (at 30.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A42 thru_hole circle (at 31.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A43 thru_hole circle (at 32.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 125 /FPGA_Bank_0_3/DIFFIO_A6P)
    )
    (pad A44 thru_hole circle (at 33.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 124 /FPGA_Bank_0_3/DIFFIO_A6N)
    )
    (pad A45 thru_hole circle (at 34.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A46 thru_hole circle (at 35.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad A47 thru_hole circle (at 36.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 105 /FPGA_Bank_0_3/DIFFCLK_A1P)
    )
    (pad A48 thru_hole circle (at 37.35 -3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 104 /FPGA_Bank_0_3/DIFFCLK_A1N)
    )
    (pad B1 thru_hole circle (at -11.65 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 473 VCC12V0)
    )
    (pad B2 thru_hole circle (at -10.65 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 473 VCC12V0)
    )
    (pad B3 thru_hole circle (at -9.65 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 473 VCC12V0)
    )
    (pad B4 thru_hole circle (at -8.65 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B5 thru_hole circle (at -7.65 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 158 /FPGA_Bank_0_3/SMCLK)
    )
    (pad B6 thru_hole circle (at -6.65 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 159 /FPGA_Bank_0_3/SMDATA)
    )
    (pad B7 thru_hole circle (at -5.65 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B8 thru_hole circle (at -4.65 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (pad B9 thru_hole circle (at -3.65 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 141 /FPGA_Bank_0_3/DIFFIO_XP)
    )
    (pad B10 thru_hole circle (at -2.65 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (pad B11 thru_hole circle (at -1.65 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 140 /FPGA_Bank_0_3/DIFFIO_XN)
    )
    (pad B12 thru_hole circle (at 1.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 142 /FPGA_Bank_0_3/DIFFIO_YN)
    )
    (pad B13 thru_hole circle (at 2.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B14 thru_hole circle (at 3.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 129 /FPGA_Bank_0_3/DIFFIO_B1P)
    )
    (pad B15 thru_hole circle (at 4.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 128 /FPGA_Bank_0_3/DIFFIO_B1N)
    )
    (pad B16 thru_hole circle (at 5.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B17 thru_hole circle (at 6.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 302 /GPIOs/PRSNT)
    )
    (pad B18 thru_hole circle (at 7.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B19 thru_hole circle (at 8.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 131 /FPGA_Bank_0_3/DIFFIO_B2P)
    )
    (pad B20 thru_hole circle (at 9.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 130 /FPGA_Bank_0_3/DIFFIO_B2N)
    )
    (pad B21 thru_hole circle (at 10.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B22 thru_hole circle (at 11.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
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      (layers *.Cu *.Mask F.SilkS)
      (net 133 /FPGA_Bank_0_3/DIFFIO_B3P)
    )
    (pad B24 thru_hole circle (at 13.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 132 /FPGA_Bank_0_3/DIFFIO_B3N)
    )
    (pad B25 thru_hole circle (at 14.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B26 thru_hole circle (at 15.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
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      (layers *.Cu *.Mask F.SilkS)
      (net 107 /FPGA_Bank_0_3/DIFFCLK_B0P)
    )
    (pad B28 thru_hole circle (at 17.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 106 /FPGA_Bank_0_3/DIFFCLK_B0N)
    )
    (pad B29 thru_hole circle (at 18.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
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      (layers *.Cu *.Mask F.SilkS)
      (net 144 /FPGA_Bank_0_3/DIFFIO_ZN)
    )
    (pad B31 thru_hole circle (at 20.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 302 /GPIOs/PRSNT)
    )
    (pad B32 thru_hole circle (at 21.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
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      (layers *.Cu *.Mask F.SilkS)
      (net 135 /FPGA_Bank_0_3/DIFFIO_B4P)
    )
    (pad B34 thru_hole circle (at 23.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 134 /FPGA_Bank_0_3/DIFFIO_B4N)
    )
    (pad B35 thru_hole circle (at 24.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B36 thru_hole circle (at 25.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B37 thru_hole circle (at 26.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 137 /FPGA_Bank_0_3/DIFFIO_B5P)
    )
    (pad B38 thru_hole circle (at 27.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 136 /FPGA_Bank_0_3/DIFFIO_B5N)
    )
    (pad B39 thru_hole circle (at 28.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B40 thru_hole circle (at 29.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B41 thru_hole circle (at 30.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 139 /FPGA_Bank_0_3/DIFFIO_B6P)
    )
    (pad B42 thru_hole circle (at 31.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 138 /FPGA_Bank_0_3/DIFFIO_B6N)
    )
    (pad B43 thru_hole circle (at 32.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B44 thru_hole circle (at 33.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B45 thru_hole circle (at 34.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 109 /FPGA_Bank_0_3/DIFFCLK_B1P)
    )
    (pad B46 thru_hole circle (at 35.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 108 /FPGA_Bank_0_3/DIFFCLK_B1N)
    )
    (pad B47 thru_hole circle (at 36.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B48 thru_hole circle (at 37.35 3.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 302 /GPIOs/PRSNT)
    )
    (pad A49 thru_hole circle (at 38.35 -1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad B49 thru_hole circle (at 38.35 1.25 90) (size 1.2 1.2) (drill 0.78)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module "8-HTSOP-J_(BD50GA5WEFJ-E2)"   locked (layer TOP) (tedit 55260252)
    (at 177.5841 91.3511 270)
    (descr BD50GA5WEFJ-E2)
    (tags CONN)
    (fp_text reference U24 (at -3.8481 2.3241 360) (layer F.SilkS))
    (fp_text value BDXXGA5WEFJ_ (at 0 7.239 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.905 3 270) (size 0.5 1.2)
      (layers TOP F.Paste F.Mask)
      (net 337 /USB/USB_5V)
    )
    (pad 8 smd rect (at -1.905 -3 270) (size 0.5 1.2)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at -0.635 3 270) (size 0.5 1.2)
      (layers TOP F.Paste F.Mask)
      (net 337 /USB/USB_5V)
    )
    (pad 7 smd rect (at -0.635 -3 270) (size 0.5 1.2)
      (layers TOP F.Paste F.Mask)
    )
    (pad 3 smd rect (at 0.635 3 270) (size 0.5 1.2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 6 smd rect (at 0.635 -3 270) (size 0.5 1.2)
      (layers TOP F.Paste F.Mask)
    )
    (pad 4 smd rect (at 1.905 3 270) (size 0.5 1.2)
      (layers TOP F.Paste F.Mask)
    )
    (pad 5 smd rect (at 1.905 -3 270) (size 0.5 1.2)
      (layers TOP F.Paste F.Mask)
      (net 331 /USB/CPEN)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_2x04_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module μA78L00   locked (layer TOP) (tedit 5370B763)
    (at 166.243 190.881)
    (descr "module CMS SOT223 4 pins")
    (tags "CMS SOT")
    (attr smd)
    (fp_text reference U30 (at 4.191 -2.794) (layer F.SilkS))
    (fp_text value ΜA78L00 (at -0.0889 4.0386) (layer F.SilkS) hide)
    (pad 2 smd rect (at 0 -2.125) (size 1.9 1.7)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 3 smd rect (at 1.5 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 1 smd rect (at -1.5 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (model TO_SOT_Packages_SMD.3dshapes/SOT-223.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.4 0.4 0.4))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552609B3)
    (at 257.302 133.858 270)
    (attr smd)
    (fp_text reference R118 (at 3.302 0 270) (layer F.SilkS))
    (fp_text value 100R (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 356 N-00000206)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 154 /FPGA_Bank_0_3/PCIO0)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B4E)
    (at 120.523 200.787)
    (attr smd)
    (fp_text reference R195 (at 2.921 0) (layer B.SilkS))
    (fp_text value 100K (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 303 /HDMI/HDMI-TX1-VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262BB2)
    (at 141.351 201.041)
    (attr smd)
    (fp_text reference R202 (at -2.921 0) (layer B.SilkS))
    (fp_text value 100K (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 304 /HDMI/HDMI-TX2-VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer BOTTOM) (tedit 5625C454)
    (at 232.9561 212.98154 270)
    (attr smd)
    (fp_text reference R44 (at -3.13944 0.0254 270) (layer B.SilkS))
    (fp_text value 100K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 216 /FPGA_Bank_1_2/DPTXHPD)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer BOTTOM) (tedit 55262C18)
    (at 256.27838 213.43874 270)
    (attr smd)
    (fp_text reference R47 (at 2.97688 -0.05588 270) (layer B.SilkS))
    (fp_text value 100K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 215 /FPGA_Bank_1_2/DPRXHPD)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer BOTTOM) (tedit 55262C1A)
    (at 258.0513 213.4362 270)
    (attr smd)
    (fp_text reference R46 (at 2.98196 0.06096 270) (layer B.SilkS))
    (fp_text value 5M (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 52 /DisplayPort/DPRXCONFIG2)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer BOTTOM) (tedit 55262C1C)
    (at 260.26618 213.4362 270)
    (attr smd)
    (fp_text reference R45 (at 2.99212 -0.09652 270) (layer B.SilkS))
    (fp_text value 1M (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 51 /DisplayPort/DPRXCONFIG1)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer BOTTOM) (tedit 5625C460)
    (at 235.01858 212.95106 270)
    (attr smd)
    (fp_text reference R43 (at -3.10896 -0.04572 270) (layer B.SilkS))
    (fp_text value 5M (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 64 /DisplayPort/DPTXCONFIG2)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer BOTTOM) (tedit 5625C45B)
    (at 237.2995 212.96122 270)
    (attr smd)
    (fp_text reference R42 (at -3.09372 -0.127 270) (layer B.SilkS))
    (fp_text value 1M (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 63 /DisplayPort/DPTXCONFIG1)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 553DB4A0)
    (at 266.954 122.555)
    (attr smd)
    (fp_text reference R119 (at 0 -1.524) (layer B.SilkS))
    (fp_text value 1K (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 353 N-00000202)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 553DB4A3)
    (at 262.89 122.555 180)
    (attr smd)
    (fp_text reference R117 (at 0 1.524 180) (layer B.SilkS))
    (fp_text value 1M (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 157 /FPGA_Bank_0_3/PCIO3)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 475 VCC1V5)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B15)
    (at 165.481 187.325)
    (attr smd)
    (fp_text reference R121 (at -2.921 0) (layer B.SilkS))
    (fp_text value 100K (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 55260B05)
    (at 245.1481 96.4819)
    (attr smd)
    (fp_text reference R94 (at 2.7559 0.1651) (layer F.SilkS))
    (fp_text value 2.2K (at 0 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 440 N-00000370)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552608E0)
    (at 242.4811 148.23948 270)
    (attr smd)
    (fp_text reference R120 (at -0.03048 -1.7399 270) (layer F.SilkS))
    (fp_text value 4.7K (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 367 N-00000250)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260926)
    (at 227.076 143.383 90)
    (attr smd)
    (fp_text reference C245 (at 0.381 -1.143 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 150 /FPGA_Bank_0_3/MGTREFCLK0_101_P)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 364 N-00000233)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260922)
    (at 228.219 143.383 90)
    (attr smd)
    (fp_text reference C246 (at 0.508 1.143 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 149 /FPGA_Bank_0_3/MGTREFCLK0_101_N)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 362 N-00000218)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260937)
    (at 229.3874 147.828)
    (attr smd)
    (fp_text reference C248 (at 2.3876 0) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 148 /FPGA_Bank_0_3/MGT135MHz_P)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 358 N-00000211)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260930)
    (at 229.4128 146.1516)
    (attr smd)
    (fp_text reference C247 (at 2.3622 0.0254) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 147 /FPGA_Bank_0_3/MGT135MHz_N)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 360 N-00000214)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5526092C)
    (at 231.775 142.494 90)
    (attr smd)
    (fp_text reference C250 (at 2.54 0.127 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 151 /FPGA_Bank_0_3/MGTSMACLK_N)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 361 N-00000217)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 55260920)
    (at 230.632 142.494 90)
    (attr smd)
    (fp_text reference C249 (at 2.54 0.127 90) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 152 /FPGA_Bank_0_3/MGTSMACLK_P)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 359 N-00000213)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module PIN_ARRAY_5x2   locked (layer TOP) (tedit 5534A740)
    (at 263.58088 126.96952)
    (descr "Double rangee de contacts 2 x 5 pins")
    (tags CONN)
    (fp_text reference P14 (at 5.91312 4.34848) (layer F.SilkS))
    (fp_text value CONN_5X2 (at 0 -3.81) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -5.08 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 355 N-00000205)
    )
    (pad 2 thru_hole circle (at -5.08 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 356 N-00000206)
    )
    (pad 3 thru_hole circle (at -2.54 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 155 /FPGA_Bank_0_3/PCIO1)
    )
    (pad 4 thru_hole circle (at -2.54 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 156 /FPGA_Bank_0_3/PCIO2)
    )
    (pad 5 thru_hole circle (at 0 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 354 N-00000203)
    )
    (pad 6 thru_hole circle (at 0 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 157 /FPGA_Bank_0_3/PCIO3)
    )
    (pad 7 thru_hole circle (at 2.54 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 328 /SPI_Flash/RST)
    )
    (pad 8 thru_hole circle (at 2.54 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 353 N-00000202)
    )
    (pad 9 thru_hole circle (at 5.08 1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad 10 thru_hole circle (at 5.08 -1.27) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_2x05_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module PIN_ARRAY_5x1   locked (layer TOP) (tedit 5624AFE1)
    (at 174.9806 64.3636 270)
    (descr "Double rangee de contacts 2 x 5 pins")
    (tags CONN)
    (fp_text reference P16 (at 9.70788 0.00762 360) (layer F.SilkS))
    (fp_text value CONN_5 (at 0 2.54 270) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -5.08 0 270) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 337 /USB/USB_5V)
    )
    (pad 2 thru_hole circle (at -2.54 0 270) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 338 /USB/USB_DM)
    )
    (pad 3 thru_hole circle (at 0 0 270) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 339 /USB/USB_DP)
    )
    (pad 4 thru_hole circle (at 2.54 0 270) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 5 thru_hole circle (at 5.08 0 270) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x05_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module PIN_ARRAY_5x1   locked (layer TOP) (tedit 5625D8E7)
    (at 214.48014 206.44358 180)
    (descr "Double rangee de contacts 2 x 5 pins")
    (tags CONN)
    (fp_text reference P17 (at 7.35584 0.01778 270) (layer F.SilkS))
    (fp_text value CONN_5 (at 0 2.54 180) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -5.08 0 180) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 403 N-00000316)
    )
    (pad 2 thru_hole circle (at -2.54 0 180) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 332 /USB/CYDN)
    )
    (pad 3 thru_hole circle (at 0 0 180) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 333 /USB/CYDP)
    )
    (pad 4 thru_hole circle (at 2.54 0 180) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 5 thru_hole circle (at 5.08 0 180) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x05_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module PIN_ARRAY_5x1   locked (layer TOP) (tedit 552602C2)
    (at 190.93688 119.4816 90)
    (descr "Double rangee de contacts 2 x 5 pins")
    (tags CONN)
    (fp_text reference P15 (at -0.0254 -3.10388 90) (layer F.SilkS))
    (fp_text value CONN_5 (at 0 2.54 90) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -5.08 0 90) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (pad 2 thru_hole circle (at -2.54 0 90) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 475 VCC1V5)
    )
    (pad 3 thru_hole circle (at 0 0 90) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 100 /FPGA_Bank_0_3/DEBUG_IO0)
    )
    (pad 4 thru_hole circle (at 2.54 0 90) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 101 /FPGA_Bank_0_3/DEBUG_IO1)
    )
    (pad 5 thru_hole circle (at 5.08 0 90) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x05_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module PIN_ARRAY_3X1   locked (layer TOP) (tedit 5534A6A1)
    (at 239.60074 168.41978 90)
    (descr "Connecteur 3 pins")
    (tags "CONN DEV")
    (fp_text reference K1 (at -4.55422 2.46126 180) (layer F.SilkS))
    (fp_text value CONN_3 (at 0 -2.159 90) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -2.54 0 90) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (pad 2 thru_hole circle (at 0 0 90) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 384 N-00000279)
    )
    (pad 3 thru_hole circle (at 2.54 0 90) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x03_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module PIN_ARRAY_2X1   locked (layer TOP) (tedit 5526089C)
    (at 234.87126 172.90034)
    (descr "Connecteurs 2 pins")
    (tags "CONN DEV")
    (fp_text reference P18 (at 0.07874 2.48666) (layer F.SilkS))
    (fp_text value CONN_2 (at 0 -1.905) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -1.27 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 336 /USB/U1-SDA)
    )
    (pad 2 thru_hole circle (at 1.27 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 95 /Ethernet/MAC_SDA)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module LED-0805   locked (layer TOP) (tedit 55260B0C)
    (at 245.09476 98.91776 180)
    (descr "LED 0805 smd package")
    (tags "LED 0805 SMD")
    (attr smd)
    (fp_text reference D10 (at -3.19024 -0.01524 180) (layer F.SilkS))
    (fp_text value LED (at 0 1.27 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.04902 0 180) (size 1.19888 1.19888)
      (layers TOP F.Paste F.Mask)
      (net 440 N-00000370)
    )
    (pad 2 smd rect (at 1.04902 0 180) (size 1.19888 1.19888)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module GS2   locked (layer TOP) (tedit 552603F9)
    (at 233.2228 186.32424)
    (descr "Pontet Goute de soudure")
    (attr virtual)
    (fp_text reference GS2 (at -0.0508 2.90576 90) (layer F.SilkS))
    (fp_text value GS2 (at 1.524 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at 0 -0.635) (size 1.27 0.9652)
      (layers TOP F.Paste F.Mask)
      (net 390 N-00000298)
    )
    (pad 2 smd rect (at 0 0.635) (size 1.27 0.9652)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
  )
  (module "DO-214AC(SMA)" (layer TOP) (tedit 5626188B)
    (at 253.08806 203.48067 270)
    (descr "DO-214AC (SMA)  PACKAGE.")
    (tags "DO-214AC SMA")
    (attr smd)
    (fp_text reference D11 (at -3.58013 0.11422 360) (layer F.SilkS))
    (fp_text value DIODE (at 0 2.79908 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.89992 0 270) (size 1.6002 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 471 N-00000432)
    )
    (pad 2 smd rect (at 1.89992 0 270) (size 1.6002 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 469 N-00000430)
    )
    (model SMD_Packages.3dshapes/DO-214-AC_SMA.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.95 0.95 0.95))
      (rotate (xyz 0 0 0))
    )
  )
  (module "DO-214AC(SMA)" (layer TOP) (tedit 55F2B295)
    (at 236.474 201.549 270)
    (descr "DO-214AC (SMA)  PACKAGE.")
    (tags "DO-214AC SMA")
    (attr smd)
    (fp_text reference D3 (at -3.54584 0.06604 360) (layer F.SilkS))
    (fp_text value DIODE (at 0 2.79908 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.89992 0 270) (size 1.6002 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 472 N-00000433)
    )
    (pad 2 smd rect (at 1.89992 0 270) (size 1.6002 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 470 N-00000431)
    )
    (model SMD_Packages.3dshapes/DO-214-AC_SMA.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.95 0.95 0.95))
      (rotate (xyz 0 0 0))
    )
  )
  (module "DO-214AC(SMA)"   locked (layer TOP) (tedit 55260BA1)
    (at 129.5146 178.0286)
    (descr "DO-214AC (SMA)  PACKAGE.")
    (tags "DO-214AC SMA")
    (attr smd)
    (fp_text reference D4 (at 0.0254 3.0734) (layer F.SilkS))
    (fp_text value DIODE (at 0 2.79908) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.89992 0) (size 1.6002 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 477 VCC4V0)
    )
    (pad 2 smd rect (at 1.89992 0) (size 1.6002 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model SMD_Packages.3dshapes/DO-214-AC_SMA.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.95 0.95 0.95))
      (rotate (xyz 0 0 0))
    )
  )
  (module μA78L00   locked (layer TOP) (tedit 55F17C9F)
    (at 142.113 204.851)
    (descr "module CMS SOT223 4 pins")
    (tags "CMS SOT")
    (attr smd)
    (fp_text reference U22 (at -3.048 -2.4384) (layer F.SilkS))
    (fp_text value ΜA78L00 (at -0.0889 4.0386) (layer F.SilkS) hide)
    (pad 2 smd rect (at 0 -2.125) (size 1.9 1.7)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 3 smd rect (at 1.5 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 1 smd rect (at -1.5 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 304 /HDMI/HDMI-TX2-VCC5V0)
    )
    (model TO_SOT_Packages_SMD.3dshapes/SOT-223.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.4 0.4 0.4))
      (rotate (xyz 0 0 0))
    )
  )
  (module μA78L00   locked (layer TOP) (tedit 5526059D)
    (at 121.285 204.851)
    (descr "module CMS SOT223 4 pins")
    (tags "CMS SOT")
    (attr smd)
    (fp_text reference U16 (at 0 -4.445) (layer F.SilkS))
    (fp_text value ΜA78L00 (at -0.0889 4.0386) (layer F.SilkS) hide)
    (pad 2 smd rect (at 0 -2.125) (size 1.9 1.7)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 3 smd rect (at 1.5 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (pad 1 smd rect (at -1.5 1.95) (size 0.58 1.3)
      (layers TOP F.Paste F.Mask)
      (net 303 /HDMI/HDMI-TX1-VCC5V0)
    )
    (model TO_SOT_Packages_SMD.3dshapes/SOT-223.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.4 0.4 0.4))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262877)
    (at 180.10124 89.44102 180)
    (attr smd)
    (fp_text reference C38 (at 0.01524 1.43002 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552627C7)
    (at 139.05484 91.5035)
    (attr smd)
    (fp_text reference C220 (at 0.01016 -1.3335) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 552627C4)
    (at 138.84656 93.38564)
    (attr smd)
    (fp_text reference C219 (at -2.70256 -0.92964) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262807)
    (at 146.26082 95.21444)
    (attr smd)
    (fp_text reference C214 (at 2.96418 -0.34544) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 91 /Ethernet/ETH_VCC3V3)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552607ED)
    (at 204.4446 212.217 270)
    (attr smd)
    (fp_text reference C171 (at 0 -1.5494 270) (layer F.SilkS))
    (fp_text value 1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 444 N-00000382)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module LED-0603   locked (layer TOP) (tedit 5626172E)
    (at 225.96602 207.2386)
    (descr "LED 0603 smd package")
    (tags "LED led 0603 SMD smd SMT smt smdled SMDLED smtled SMTLED")
    (attr smd)
    (fp_text reference D2 (at -2.29362 0.00508) (layer F.SilkS))
    (fp_text value LED (at 0 1.016) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.7493 0) (size 0.79756 0.79756)
      (layers TOP F.Paste F.Mask)
      (net 402 N-00000314)
    )
    (pad 2 smd rect (at 0.7493 0) (size 0.79756 0.79756)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module SM1210L   locked (layer BOTTOM) (tedit 553743BE)
    (at 244.602 78.11516 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C61 (at 0.06096 -2.7686 90) (layer B.SilkS))
    (fp_text value 47uF (at 0 -0.762 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -1.778 0 90) (size 1.778 2.794)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.778 0 90) (size 1.778 2.794)
      (layers BOTTOM B.Paste B.Mask)
      (net 323 "/Power/Consumer 12V")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.2 0.2 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210L   locked (layer TOP) (tedit 55260D63)
    (at 244.602 78.12024 90)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C59 (at 0.06604 -2.6416 90) (layer F.SilkS))
    (fp_text value 47uF (at 0 0.762 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.778 0 90) (size 1.778 2.794)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.778 0 90) (size 1.778 2.794)
      (layers TOP F.Paste F.Mask)
      (net 323 "/Power/Consumer 12V")
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.2 0.2 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 552606C9)
    (at 157.70606 212.217 270)
    (attr smd)
    (fp_text reference C170 (at 0 -1.42494 270) (layer F.SilkS))
    (fp_text value 1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 448 N-00000400)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer TOP) (tedit 5526061D)
    (at 134.33044 212.217 270)
    (attr smd)
    (fp_text reference C169 (at 0 -1.30556 270) (layer F.SilkS))
    (fp_text value 1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 447 N-00000391)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5526287A)
    (at 175.8823 90.11666)
    (attr smd)
    (fp_text reference C240 (at 0.0127 -1.47066) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 337 /USB/USB_5V)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263C4A)
    (at 203.4667 200.5838 90)
    (attr smd)
    (fp_text reference R131 (at 2.73558 0.12954 90) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 237 /FPGA_Bank_1_2/TMDS_RX1_2_P)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263C4C)
    (at 202.44562 200.5838 90)
    (attr smd)
    (fp_text reference R152 (at 2.73558 -0.0127 90) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 236 /FPGA_Bank_1_2/TMDS_RX1_2_N)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263C43)
    (at 201.95032 203.12 270)
    (attr smd)
    (fp_text reference R128 (at 3.29184 -0.23368 270) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 235 /FPGA_Bank_1_2/TMDS_RX1_1_P)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263C45)
    (at 200.9521 203.12 270)
    (attr smd)
    (fp_text reference R150 (at 3.2893 -0.0889 270) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 234 /FPGA_Bank_1_2/TMDS_RX1_1_N)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263C24)
    (at 200.46442 200.5838 90)
    (attr smd)
    (fp_text reference R125 (at 2.73558 0.08636 90) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 233 /FPGA_Bank_1_2/TMDS_RX1_0_P)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263C21)
    (at 199.44588 200.5838 90)
    (attr smd)
    (fp_text reference R147 (at 2.73558 -0.06604 90) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 232 /FPGA_Bank_1_2/TMDS_RX1_0_N)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263C50)
    (at 197.94982 203.12 270)
    (attr smd)
    (fp_text reference R145 (at 3.1496 0.08382 270) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 239 /FPGA_Bank_1_2/TMDS_RX1_CLK_N)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263C56)
    (at 198.95312 203.12 270)
    (attr smd)
    (fp_text reference R124 (at 3.15722 -0.05588 270) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 240 /FPGA_Bank_1_2/TMDS_RX1_CLK_P)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263BEE)
    (at 180.09108 200.57364 90)
    (attr smd)
    (fp_text reference R188 (at 2.89052 0.12954 90) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 249 /FPGA_Bank_1_2/TMDS_RX2_2_P)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263BEC)
    (at 179.0827 200.54316 270)
    (attr smd)
    (fp_text reference R198 (at -2.89052 0.013 270) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 248 /FPGA_Bank_1_2/TMDS_RX2_2_N)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263BFB)
    (at 178.5874 203.12 270)
    (attr smd)
    (fp_text reference R189 (at 3.2766 -0.3556 270) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 247 /FPGA_Bank_1_2/TMDS_RX2_1_P)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263BF8)
    (at 177.583 203.12 90)
    (attr smd)
    (fp_text reference R200 (at -3.2766 -0.037 90) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 246 /FPGA_Bank_1_2/TMDS_RX2_1_N)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263BE7)
    (at 177.10404 200.66 90)
    (attr smd)
    (fp_text reference R190 (at 2.89052 0.072 90) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 245 /FPGA_Bank_1_2/TMDS_RX2_0_P)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263BE9)
    (at 176.07788 200.67016 270)
    (attr smd)
    (fp_text reference R201 (at -2.89052 0.061 270) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 244 /FPGA_Bank_1_2/TMDS_RX2_0_N)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263BF4)
    (at 175.583 203.12 270)
    (attr smd)
    (fp_text reference R191 (at 3.2766 -0.312 270) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 252 /FPGA_Bank_1_2/TMDS_RX2_CLK_P)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263BF5)
    (at 174.583 203.12 90)
    (attr smd)
    (fp_text reference R203 (at -3.2766 -0.085 90) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (pad 2 smd rect (at 0.44958 0 90) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 251 /FPGA_Bank_1_2/TMDS_RX2_CLK_N)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SMAJACKRightAngled   locked (layer TOP) (tedit 55349B62)
    (at 250.063 126.746)
    (fp_text reference U28 (at 0 -5.207) (layer F.SilkS))
    (fp_text value SMA_CON (at 0 4.826) (layer F.SilkS) hide)
    (pad 2 thru_hole circle (at 0 0) (size 2.2 2.2) (drill 1.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 361 N-00000217)
    )
    (pad 1 thru_hole rect (at 2.55 -2.55) (size 2.2 2.2) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 1 thru_hole rect (at 2.55 2.55) (size 2.2 2.2) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 1 thru_hole rect (at -2.55 2.55) (size 2.2 2.2) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 1 thru_hole rect (at -2.55 -2.55) (size 2.2 2.2) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module SMAJACKRightAngled   locked (layer TOP) (tedit 55349B66)
    (at 238.506 126.746)
    (fp_text reference U29 (at 0 -5.207) (layer F.SilkS))
    (fp_text value SMA_CON (at 0 4.826) (layer F.SilkS) hide)
    (pad 2 thru_hole circle (at 0 0) (size 2.2 2.2) (drill 1.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 359 N-00000213)
    )
    (pad 1 thru_hole rect (at 2.55 -2.55) (size 2.2 2.2) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 1 thru_hole rect (at 2.55 2.55) (size 2.2 2.2) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 1 thru_hole rect (at -2.55 2.55) (size 2.2 2.2) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 1 thru_hole rect (at -2.55 -2.55) (size 2.2 2.2) (drill 1.7)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module CB3LV-3I   locked (layer TOP) (tedit 55349CCC)
    (at 199.34682 169.96664 90)
    (fp_text reference U26 (at -4.02336 5.75818 180) (layer F.SilkS))
    (fp_text value CB3LV-3I-27M0000 (at 0.2 7.9 90) (layer F.SilkS) hide)
    (pad 3 smd rect (at 2.54 -2.1 90) (size 1.85 2.05)
      (layers TOP F.Paste F.Mask)
      (net 327 /SPI_Flash/27MHz)
    )
    (pad 4 smd rect (at -2.54 -2.1 90) (size 1.85 2.05)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 1 smd rect (at -2.54 2.1 90) (size 1.85 2.05)
      (layers TOP F.Paste F.Mask)
      (net 349 N-00000195)
    )
    (pad 2 smd rect (at 2.54 2.1 90) (size 1.85 2.05)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262AF7)
    (at 198.0184 167.0558 180)
    (attr smd)
    (fp_text reference C244 (at 3.0734 0.0508 180) (layer B.SilkS))
    (fp_text value 15PF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 327 /SPI_Flash/27MHz)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 5526038F)
    (at 193.802 171.7294 270)
    (attr smd)
    (fp_text reference C241 (at -3.2004 0 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module FXO-LC73   locked (layer TOP) (tedit 5526093A)
    (at 237.236 148.23948 180)
    (fp_text reference U27 (at -3.429 -4.66852 180) (layer F.SilkS))
    (fp_text value FXO-LC73 (at 0 5.4 180) (layer F.SilkS) hide)
    (pad 6 smd rect (at -2.54 -2.1 180) (size 1.8 2)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 4 smd rect (at 2.54 -2.1 180) (size 1.8 2)
      (layers TOP F.Paste F.Mask)
      (net 358 N-00000211)
    )
    (pad 3 smd rect (at 2.54 2.1 180) (size 1.8 2)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 1 smd rect (at -2.54 2.1 180) (size 1.8 2)
      (layers TOP F.Paste F.Mask)
      (net 367 N-00000250)
    )
    (pad 5 smd rect (at 0 -2.1 180) (size 1.8 2)
      (layers TOP F.Paste F.Mask)
      (net 360 N-00000214)
    )
    (pad 2 smd rect (at 0 2.1 180) (size 1.8 2)
      (layers TOP F.Paste F.Mask)
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552600BE)
    (at 129.91084 64.04864 180)
    (attr smd)
    (fp_text reference R89 (at -0.00762 1.76784 180) (layer F.SilkS))
    (fp_text value 330R (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 385 N-00000280)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262BBB)
    (at 144.399 204.851 180)
    (attr smd)
    (fp_text reference C177 (at -2.921 0 180) (layer B.SilkS))
    (fp_text value 0.33uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262BB8)
    (at 141.351 204.851)
    (attr smd)
    (fp_text reference C181 (at -2.921 0) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 304 /HDMI/HDMI-TX2-VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262BB5)
    (at 141.36116 202.9968)
    (attr smd)
    (fp_text reference C252 (at -2.93116 -0.0508) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 304 /HDMI/HDMI-TX2-VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B7A)
    (at 120.523 204.851)
    (attr smd)
    (fp_text reference C205 (at 0.127 1.905) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 303 /HDMI/HDMI-TX1-VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B4F)
    (at 120.523 202.565)
    (attr smd)
    (fp_text reference C175 (at 2.921 0) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 303 /HDMI/HDMI-TX1-VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B78)
    (at 123.317 204.851 180)
    (attr smd)
    (fp_text reference C173 (at -1.651 -1.778 180) (layer B.SilkS))
    (fp_text value 0.33uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262C31)
    (at 172.35678 220.0402 180)
    (attr smd)
    (fp_text reference R88 (at 0.02286 1.67894 180) (layer B.SilkS))
    (fp_text value 100K (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 446 N-00000388)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B0C)
    (at 168.275 190.881 180)
    (attr smd)
    (fp_text reference C183 (at -2.921 0 180) (layer B.SilkS))
    (fp_text value 0.33uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 473 VCC12V0)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B0F)
    (at 165.481 190.881)
    (attr smd)
    (fp_text reference C208 (at -2.921 0) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262B11)
    (at 165.481 189.103)
    (attr smd)
    (fp_text reference C206 (at -2.921 0) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at 0.762 0) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55263AA1)
    (at 220.32722 141.8844 270)
    (attr smd)
    (fp_text reference R68 (at -0.0254 -6.24078 360) (layer B.SilkS))
    (fp_text value 50R (at 0.09906 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 474 VCC1V2)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 363 N-00000232)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402   locked (layer BOTTOM) (tedit 55262A59)
    (at 207.37322 150.89124)
    (attr smd)
    (fp_text reference C132 (at 0 0) (layer B.SilkS) hide)
    (fp_text value 0.1uF (at 0.09906 0) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 5624C16D)
    (at 184.19064 103.54564 90)
    (attr smd)
    (fp_text reference C190 (at -2.95656 0.11176 90) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 0 90) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer TOP) (tedit 552603AE)
    (at 209.042 194.31 180)
    (attr smd)
    (fp_text reference R72 (at 2.47396 -0.03556 180) (layer F.SilkS))
    (fp_text value 100K (at 0 0 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 334 /USB/CYP-RESET)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603   locked (layer BOTTOM) (tedit 55262ABE)
    (at 209.042 194.31 180)
    (attr smd)
    (fp_text reference C46 (at 2.47396 -0.04572 180) (layer B.SilkS))
    (fp_text value 4.7uF (at 0 0 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 334 /USB/CYP-RESET)
    )
    (pad 2 smd rect (at 0.762 0 180) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module 1Pin_N (layer TOP) (tedit 555B14F7)
    (at 130.14198 187.452)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P6 (at 0 -2.159) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 266 /FPGA_Bank_1_2/TMDS_TX1_SCL)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B1506)
    (at 150.114 196.85)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P4 (at 0 -1.905) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 278 /FPGA_Bank_1_2/TMDS_TX2_SCL)
    )
  )
  (module 1Pin_N (layer TOP) (tedit 555B14F1)
    (at 132.29844 184.77484)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P5 (at 0 -2.159) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 267 /FPGA_Bank_1_2/TMDS_TX1_SDA)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B151F)
    (at 185.039 203.962)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P7 (at 0 -1.778) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 243 /FPGA_Bank_1_2/TMDS_RX1_SDA)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B1525)
    (at 185.039 206.629)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P8 (at 0 1.905) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 242 /FPGA_Bank_1_2/TMDS_RX1_SCL)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B1510)
    (at 162.433 202.946)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P9 (at -1.905 0) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 255 /FPGA_Bank_1_2/TMDS_RX2_SDA)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B1515)
    (at 162.433 205.486)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P10 (at -2.159 0) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 254 /FPGA_Bank_1_2/TMDS_RX2_SCL)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B1501)
    (at 147.574 196.85)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P2 (at 0 -1.905) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 279 /FPGA_Bank_1_2/TMDS_TX2_SDA)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B1532)
    (at 239.776 182.245)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P11 (at 2.54 0) (layer F.SilkS))
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 399 N-00000309)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B1537)
    (at 239.776 179.07)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P12 (at 2.54 0) (layer F.SilkS))
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 386 N-00000288)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 555B153D)
    (at 239.776 175.768)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P13 (at 2.54 0) (layer F.SilkS))
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 387 N-00000289)
    )
  )
  (module Switch_SMD   locked (layer TOP) (tedit 5624AFA0)
    (at 130.81508 136.23544 180)
    (fp_text reference SW1 (at 0.10668 -3.33756 180) (layer F.SilkS))
    (fp_text value SW_PUSH (at 0 -11.43 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -3.048 0 180) (size 2.4892 1.905)
      (layers TOP F.Paste F.Mask)
      (net 366 N-00000249)
    )
    (pad 2 smd rect (at 3.31978 0 180) (size 2.4892 1.905)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
  )
  (module SSOP38_ip4776   locked (layer TOP) (tedit 55F17CB5)
    (at 153.7149 206.0788 180)
    (descr SSOP56)
    (attr smd)
    (fp_text reference U14 (at -5.5177 5.76678 180) (layer F.SilkS))
    (fp_text value IP4776CZ38 (at 0.29972 0.55118 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -4.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at -4 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 3 smd rect (at -3.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at -3 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 273 /FPGA_Bank_1_2/TMDS_TX2_2_P)
    )
    (pad 5 smd rect (at -2.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 6 smd rect (at -2 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 272 /FPGA_Bank_1_2/TMDS_TX2_2_N)
    )
    (pad 7 smd rect (at -1.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 271 /FPGA_Bank_1_2/TMDS_TX2_1_P)
    )
    (pad 8 smd rect (at -1 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 9 smd rect (at -0.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 270 /FPGA_Bank_1_2/TMDS_TX2_1_N)
    )
    (pad 10 smd rect (at 0 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 269 /FPGA_Bank_1_2/TMDS_TX2_0_P)
    )
    (pad 11 smd rect (at 0.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at 1 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 268 /FPGA_Bank_1_2/TMDS_TX2_0_N)
    )
    (pad 13 smd rect (at 1.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 276 /FPGA_Bank_1_2/TMDS_TX2_CLK_P)
    )
    (pad 14 smd rect (at 2 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 15 smd rect (at 2.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 275 /FPGA_Bank_1_2/TMDS_TX2_CLK_N)
    )
    (pad 16 smd rect (at 3 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 274 /FPGA_Bank_1_2/TMDS_TX2_CEC)
    )
    (pad 17 smd rect (at 3.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 278 /FPGA_Bank_1_2/TMDS_TX2_SCL)
    )
    (pad 18 smd rect (at 4 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 279 /FPGA_Bank_1_2/TMDS_TX2_SDA)
    )
    (pad 19 smd rect (at 4.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 277 /FPGA_Bank_1_2/TMDS_TX2_HOT)
    )
    (pad 24 smd rect (at 2.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 275 /FPGA_Bank_1_2/TMDS_TX2_CLK_N)
    )
    (pad 23 smd rect (at 3 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 318 /HDMI/P4-CEC)
    )
    (pad 22 smd rect (at 3.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 320 /HDMI/P4-SCL)
    )
    (pad 21 smd rect (at 4 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 321 /HDMI/P4-SDA)
    )
    (pad 25 smd rect (at 2 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 26 smd rect (at 1.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 276 /FPGA_Bank_1_2/TMDS_TX2_CLK_P)
    )
    (pad 27 smd rect (at 1 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 268 /FPGA_Bank_1_2/TMDS_TX2_0_N)
    )
    (pad 28 smd rect (at 0.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 29 smd rect (at 0 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 269 /FPGA_Bank_1_2/TMDS_TX2_0_P)
    )
    (pad 30 smd rect (at -0.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 270 /FPGA_Bank_1_2/TMDS_TX2_1_N)
    )
    (pad 31 smd rect (at -1 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 32 smd rect (at -1.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 271 /FPGA_Bank_1_2/TMDS_TX2_1_P)
    )
    (pad 33 smd rect (at -2 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 272 /FPGA_Bank_1_2/TMDS_TX2_2_N)
    )
    (pad 34 smd rect (at -2.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 35 smd rect (at -3 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 273 /FPGA_Bank_1_2/TMDS_TX2_2_P)
    )
    (pad 20 smd rect (at 4.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 319 /HDMI/P4-HOT)
    )
    (pad 36 smd rect (at -3.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 37 smd rect (at -4 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 448 N-00000400)
    )
    (pad 38 smd rect (at -4.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
    )
  )
  (module SSOP38_ip4776   locked (layer TOP) (tedit 5527A15F)
    (at 177.0829 206.0788 180)
    (descr SSOP56)
    (attr smd)
    (fp_text reference U21 (at -5.4161 5.9268 180) (layer F.SilkS))
    (fp_text value IP4776CZ38 (at 0.29972 0.55118 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -4.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at -4 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 3 smd rect (at -3.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at -3 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 249 /FPGA_Bank_1_2/TMDS_RX2_2_P)
    )
    (pad 5 smd rect (at -2.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 6 smd rect (at -2 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 248 /FPGA_Bank_1_2/TMDS_RX2_2_N)
    )
    (pad 7 smd rect (at -1.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 247 /FPGA_Bank_1_2/TMDS_RX2_1_P)
    )
    (pad 8 smd rect (at -1 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 9 smd rect (at -0.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 246 /FPGA_Bank_1_2/TMDS_RX2_1_N)
    )
    (pad 10 smd rect (at 0 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 245 /FPGA_Bank_1_2/TMDS_RX2_0_P)
    )
    (pad 11 smd rect (at 0.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at 1 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 244 /FPGA_Bank_1_2/TMDS_RX2_0_N)
    )
    (pad 13 smd rect (at 1.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 252 /FPGA_Bank_1_2/TMDS_RX2_CLK_P)
    )
    (pad 14 smd rect (at 2 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 15 smd rect (at 2.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 251 /FPGA_Bank_1_2/TMDS_RX2_CLK_N)
    )
    (pad 16 smd rect (at 3 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 250 /FPGA_Bank_1_2/TMDS_RX2_CEC)
    )
    (pad 17 smd rect (at 3.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 254 /FPGA_Bank_1_2/TMDS_RX2_SCL)
    )
    (pad 18 smd rect (at 4 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 255 /FPGA_Bank_1_2/TMDS_RX2_SDA)
    )
    (pad 19 smd rect (at 4.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 253 /FPGA_Bank_1_2/TMDS_RX2_HOT)
    )
    (pad 24 smd rect (at 2.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 251 /FPGA_Bank_1_2/TMDS_RX2_CLK_N)
    )
    (pad 23 smd rect (at 3 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 314 /HDMI/P3-CEC)
    )
    (pad 22 smd rect (at 3.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 316 /HDMI/P3-SCL)
    )
    (pad 21 smd rect (at 4 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 317 /HDMI/P3-SDA)
    )
    (pad 25 smd rect (at 2 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 26 smd rect (at 1.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 252 /FPGA_Bank_1_2/TMDS_RX2_CLK_P)
    )
    (pad 27 smd rect (at 1 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 244 /FPGA_Bank_1_2/TMDS_RX2_0_N)
    )
    (pad 28 smd rect (at 0.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 29 smd rect (at 0 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 245 /FPGA_Bank_1_2/TMDS_RX2_0_P)
    )
    (pad 30 smd rect (at -0.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 246 /FPGA_Bank_1_2/TMDS_RX2_1_N)
    )
    (pad 31 smd rect (at -1 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 32 smd rect (at -1.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 247 /FPGA_Bank_1_2/TMDS_RX2_1_P)
    )
    (pad 33 smd rect (at -2 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 248 /FPGA_Bank_1_2/TMDS_RX2_2_N)
    )
    (pad 34 smd rect (at -2.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 35 smd rect (at -3 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 249 /FPGA_Bank_1_2/TMDS_RX2_2_P)
    )
    (pad 20 smd rect (at 4.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 315 /HDMI/P3-HOT)
    )
    (pad 36 smd rect (at -3.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 37 smd rect (at -4 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 443 N-00000377)
    )
    (pad 38 smd rect (at -4.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
    )
  )
  (module SSOP38_ip4776   locked (layer TOP) (tedit 5625D8D6)
    (at 200.4509 206.0788 180)
    (descr SSOP56)
    (attr smd)
    (fp_text reference U15 (at 5.86658 1.07032 270) (layer F.SilkS))
    (fp_text value IP4776CZ38 (at 0.29972 0.55118 180) (layer F.SilkS) hide)
    (pad 1 smd rect (at -4.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 305 /HDMI/HDMI_VCC5V0)
    )
    (pad 2 smd rect (at -4 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 476 VCC3V3)
    )
    (pad 3 smd rect (at -3.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 4 smd rect (at -3 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 237 /FPGA_Bank_1_2/TMDS_RX1_2_P)
    )
    (pad 5 smd rect (at -2.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 6 smd rect (at -2 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 236 /FPGA_Bank_1_2/TMDS_RX1_2_N)
    )
    (pad 7 smd rect (at -1.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 235 /FPGA_Bank_1_2/TMDS_RX1_1_P)
    )
    (pad 8 smd rect (at -1 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 9 smd rect (at -0.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 234 /FPGA_Bank_1_2/TMDS_RX1_1_N)
    )
    (pad 10 smd rect (at 0 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 233 /FPGA_Bank_1_2/TMDS_RX1_0_P)
    )
    (pad 11 smd rect (at 0.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 12 smd rect (at 1 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 232 /FPGA_Bank_1_2/TMDS_RX1_0_N)
    )
    (pad 13 smd rect (at 1.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 240 /FPGA_Bank_1_2/TMDS_RX1_CLK_P)
    )
    (pad 14 smd rect (at 2 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 15 smd rect (at 2.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 239 /FPGA_Bank_1_2/TMDS_RX1_CLK_N)
    )
    (pad 16 smd rect (at 3 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 238 /FPGA_Bank_1_2/TMDS_RX1_CEC)
    )
    (pad 17 smd rect (at 3.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 242 /FPGA_Bank_1_2/TMDS_RX1_SCL)
    )
    (pad 18 smd rect (at 4 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 243 /FPGA_Bank_1_2/TMDS_RX1_SDA)
    )
    (pad 19 smd rect (at 4.5 2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 241 /FPGA_Bank_1_2/TMDS_RX1_HOT)
    )
    (pad 24 smd rect (at 2.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 239 /FPGA_Bank_1_2/TMDS_RX1_CLK_N)
    )
    (pad 23 smd rect (at 3 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 306 /HDMI/P1-CEC)
    )
    (pad 22 smd rect (at 3.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 308 /HDMI/P1-SCL)
    )
    (pad 21 smd rect (at 4 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 309 /HDMI/P1-SDA)
    )
    (pad 25 smd rect (at 2 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 26 smd rect (at 1.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 240 /FPGA_Bank_1_2/TMDS_RX1_CLK_P)
    )
    (pad 27 smd rect (at 1 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 232 /FPGA_Bank_1_2/TMDS_RX1_0_N)
    )
    (pad 28 smd rect (at 0.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 29 smd rect (at 0 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 233 /FPGA_Bank_1_2/TMDS_RX1_0_P)
    )
    (pad 30 smd rect (at -0.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 234 /FPGA_Bank_1_2/TMDS_RX1_1_N)
    )
    (pad 31 smd rect (at -1 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 32 smd rect (at -1.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 235 /FPGA_Bank_1_2/TMDS_RX1_1_P)
    )
    (pad 33 smd rect (at -2 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 236 /FPGA_Bank_1_2/TMDS_RX1_2_N)
    )
    (pad 34 smd rect (at -2.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 35 smd rect (at -3 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 237 /FPGA_Bank_1_2/TMDS_RX1_2_P)
    )
    (pad 20 smd rect (at 4.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 307 /HDMI/P1-HOT)
    )
    (pad 36 smd rect (at -3.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 37 smd rect (at -4 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
      (net 444 N-00000382)
    )
    (pad 38 smd rect (at -4.5 -2.85 180) (size 0.25908 1.5)
      (layers TOP F.Paste F.Mask)
    )
  )
  (module DO214-AC   locked (layer TOP) (tedit 5527AC0F)
    (at 202.057 186.055 90)
    (attr smd)
    (fp_text reference D13 (at 5.588 0 90) (layer F.SilkS))
    (fp_text value DIODESCH (at -0.05 2.15 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.05 0 90) (size 2.6 1.7)
      (layers TOP F.Paste F.Mask)
      (net 295 /FPGA_Power/PROG_B)
    )
    (pad 2 smd rect (at 2.05 0 90) (size 2.6 1.7)
      (layers TOP F.Paste F.Mask)
      (net 328 /SPI_Flash/RST)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module DO214-AC   locked (layer TOP) (tedit 5527AC0A)
    (at 205.867 186.055 90)
    (attr smd)
    (fp_text reference D12 (at 5.588 0 90) (layer F.SilkS))
    (fp_text value DIODESCH (at -0.05 2.15 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -2.05 0 90) (size 2.6 1.7)
      (layers TOP F.Paste F.Mask)
      (net 334 /USB/CYP-RESET)
    )
    (pad 2 smd rect (at 2.05 0 90) (size 2.6 1.7)
      (layers TOP F.Paste F.Mask)
      (net 328 /SPI_Flash/RST)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer TOP) (tedit 56261737)
    (at 229.362 209.169 90)
    (attr smd)
    (fp_text reference C47 (at 0.01524 -1.28524 90) (layer F.SilkS))
    (fp_text value 0.01uF (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 470 N-00000431)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer TOP) (tedit 55F2B0A0)
    (at 250.03371 209.34045 270)
    (attr smd)
    (fp_text reference C49 (at -0.01905 1.28905 270) (layer F.SilkS))
    (fp_text value 0.01uF (at 0 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 469 N-00000430)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer TOP) (tedit 56261873)
    (at 232.918 200.406 90)
    (attr smd)
    (fp_text reference F3 (at 0.01524 -1.5621 180) (layer F.SilkS))
    (fp_text value FUSE (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 477 VCC4V0)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 472 N-00000433)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer TOP) (tedit 56261885)
    (at 249.5727 202.36434 90)
    (attr smd)
    (fp_text reference F2 (at -0.00762 -1.55694 180) (layer F.SilkS))
    (fp_text value FUSE (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 477 VCC4V0)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 471 N-00000432)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210L   locked (layer TOP) (tedit 5640464A)
    (at 216.1032 74.0664 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C268 (at 3.7336 -0.0968 360) (layer F.SilkS))
    (fp_text value 47uF (at 0 0.762 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.778 0 270) (size 1.778 2.794)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.778 0 270) (size 1.778 2.794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.2 0.2 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM1210L   locked (layer TOP) (tedit 5640464C)
    (at 220.1418 74.0664 270)
    (tags "CMS SM")
    (attr smd)
    (fp_text reference C269 (at 3.7086 -0.0082 360) (layer F.SilkS))
    (fp_text value 47uF (at 0 0.762 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.778 0 270) (size 1.778 2.794)
      (layers TOP F.Paste F.Mask)
      (net 342 GND)
    )
    (pad 2 smd rect (at 1.778 0 270) (size 1.778 2.794)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.2 0.2 0.2))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer TOP) (tedit 55F00FC2)
    (at 231.14 209.169 90)
    (attr smd)
    (fp_text reference R123 (at 2.794 0.0508 90) (layer F.SilkS))
    (fp_text value 100K (at 0 0 90) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 470 N-00000431)
    )
    (pad 2 smd rect (at 0.762 0 90) (size 0.635 1.143)
      (layers TOP F.Paste F.Mask)
      (net 466 N-00000427)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0603 (layer BOTTOM) (tedit 5625C46A)
    (at 235.44022 216.5731 270)
    (attr smd)
    (fp_text reference R122 (at 0.0254 1.49352 270) (layer B.SilkS))
    (fp_text value 100K (at 0 0 270) (layer B.SilkS) hide)
    (pad 1 smd rect (at -0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 465 N-00000426)
    )
    (pad 2 smd rect (at 0.762 0 270) (size 0.635 1.143)
      (layers BOTTOM B.Paste B.Mask)
      (net 342 GND)
    )
    (model Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0.001))
      (scale (xyz 0.5 0.5 0.5))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 56261849)
    (at 242.3033 206.8195 270)
    (attr smd)
    (fp_text reference C255 (at -2.794 -0.04826 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 65 /DisplayPort/DPTX_LANEN0)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 459 N-00000419)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B1E5)
    (at 256.4323 206.8195 270)
    (attr smd)
    (fp_text reference C259 (at -2.667 0 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 49 /DisplayPort/DPRXAUXCH_N)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 463 N-00000424)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B1E2)
    (at 257.4483 206.8195 270)
    (attr smd)
    (fp_text reference C258 (at -2.667 0 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 50 /DisplayPort/DPRXAUXCH_P)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 464 N-00000425)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 562617CB)
    (at 233.7943 206.8195 270)
    (attr smd)
    (fp_text reference C100 (at -7.12216 -6.13664 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 61 /DisplayPort/DPTXAUXCH_N)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 466 N-00000427)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 562617C3)
    (at 234.8103 206.8195 270)
    (attr smd)
    (fp_text reference C50 (at -6.74116 -6.16458 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 62 /DisplayPort/DPTXAUXCH_P)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 465 N-00000426)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 5626182E)
    (at 236.2073 206.8195 270)
    (attr smd)
    (fp_text reference C253 (at -7.12216 -6.1849 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 68 /DisplayPort/DPTX_LANEN3)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 467 N-00000428)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 56261829)
    (at 237.2233 206.8195 270)
    (attr smd)
    (fp_text reference C251 (at -7.11454 -6.20522 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 72 /DisplayPort/DPTX_LANEP3)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 468 N-00000429)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 56261824)
    (at 238.2393 206.8195 270)
    (attr smd)
    (fp_text reference C257 (at -7.09168 -6.2484 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 67 /DisplayPort/DPTX_LANEN2)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 458 N-00000418)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 56261859)
    (at 239.2553 206.8195 270)
    (attr smd)
    (fp_text reference C256 (at -2.794 -0.02032 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 71 /DisplayPort/DPTX_LANEP2)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 462 N-00000422)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 56261855)
    (at 240.2713 206.8195 270)
    (attr smd)
    (fp_text reference C106 (at -2.81686 -0.03302 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 66 /DisplayPort/DPTX_LANEN1)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 461 N-00000421)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 5626184E)
    (at 241.2873 206.8195 270)
    (attr smd)
    (fp_text reference C104 (at -2.794 -0.03556 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 70 /DisplayPort/DPTX_LANEP1)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 460 N-00000420)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 56261843)
    (at 243.3193 206.8195 270)
    (attr smd)
    (fp_text reference C254 (at -2.82702 -0.08382 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 69 /DisplayPort/DPTX_LANEP0)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 457 N-00000417)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B1DE)
    (at 258.985 206.8195 270)
    (attr smd)
    (fp_text reference C263 (at -2.667 0.0127 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 57 /DisplayPort/DPRX_LANEP0)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 456 N-00000416)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B1F1)
    (at 260.001 206.8195 270)
    (attr smd)
    (fp_text reference C262 (at -2.667 0.0127 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 53 /DisplayPort/DPRX_LANEN0)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 455 N-00000415)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B1F5)
    (at 261.017 206.8195 270)
    (attr smd)
    (fp_text reference C267 (at -2.667 0.0127 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 58 /DisplayPort/DPRX_LANEP1)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 454 N-00000414)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B1FA)
    (at 262.033 206.8195 270)
    (attr smd)
    (fp_text reference C266 (at -2.667 0.0127 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 54 /DisplayPort/DPRX_LANEN1)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 453 N-00000413)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B200)
    (at 263.049 206.8195 270)
    (attr smd)
    (fp_text reference C261 (at -2.667 0.0127 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 59 /DisplayPort/DPRX_LANEP2)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 449 N-00000409)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B205)
    (at 264.065 206.8195 270)
    (attr smd)
    (fp_text reference C260 (at -2.667 0.0127 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 55 /DisplayPort/DPRX_LANEN2)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 450 N-00000410)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B208)
    (at 265.081 206.8195 270)
    (attr smd)
    (fp_text reference C265 (at -2.667 0.0127 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 60 /DisplayPort/DPRX_LANEP3)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 451 N-00000411)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module SM0402 (layer TOP) (tedit 55F2B20F)
    (at 266.097 206.8195 270)
    (attr smd)
    (fp_text reference C264 (at -2.667 0.0127 270) (layer F.SilkS))
    (fp_text value 0.1uF (at 0.09906 0 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 56 /DisplayPort/DPRX_LANEN3)
    )
    (pad 2 smd rect (at 0.44958 0 270) (size 0.39878 0.59944)
      (layers TOP F.Paste F.Mask)
      (net 452 N-00000412)
    )
    (model smd.3dshapes/chip_cms.wrl
      (at (xyz 0 0 0.002))
      (scale (xyz 0.05 0.05 0.05))
      (rotate (xyz 0 0 0))
    )
  )
  (module "DO-214AC(SMA)"   locked (layer TOP) (tedit 55F009F4)
    (at 211.4804 73.9394 270)
    (descr "DO-214AC (SMA)  PACKAGE.")
    (tags "DO-214AC SMA")
    (attr smd)
    (fp_text reference D14 (at 0.1016 2.9718 270) (layer F.SilkS))
    (fp_text value DIODESCH (at 0 2.79908 270) (layer F.SilkS) hide)
    (pad 1 smd rect (at -1.89992 0 270) (size 1.6002 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 442 N-00000373)
    )
    (pad 2 smd rect (at 1.89992 0 270) (size 1.6002 2.19964)
      (layers TOP F.Paste F.Mask)
      (net 473 VCC12V0)
    )
    (model SMD_Packages.3dshapes/DO-214-AC_SMA.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.95 0.95 0.95))
      (rotate (xyz 0 0 0))
    )
  )
  (module 3x2PIN_MOLEX   locked (layer TOP) (tedit 56388543)
    (at 221.50324 63.01232 180)
    (descr "Double rangee de contacts 2 x 5 pins")
    (tags CONN)
    (fp_text reference P27 (at 7.88924 -6.96468 180) (layer F.SilkS))
    (fp_text value ATX_POWER_SUPPLY (at 0.25 7.25 180) (layer F.SilkS) hide)
    (pad 4 thru_hole circle (at -4.191 -2.286 180) (size 3.81 3.81) (drill 2.032)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 5 thru_hole circle (at 0 -2.286 180) (size 3.81 3.81) (drill 2.032)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 6 thru_hole circle (at 4.191 -2.286 180) (size 3.81 3.81) (drill 2.032)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 3 thru_hole circle (at 4.191 2.286 180) (size 3.81 3.81) (drill 2.032)
      (layers *.Cu *.Mask F.SilkS)
      (net 442 N-00000373)
    )
    (pad 2 thru_hole circle (at 0 2.286 180) (size 3.81 3.81) (drill 2.032)
      (layers *.Cu *.Mask F.SilkS)
      (net 442 N-00000373)
    )
    (pad 1 thru_hole rect (at -4.191 2.286 180) (size 3.81 3.81) (drill 2.032)
      (layers *.Cu *.Mask F.SilkS)
      (net 442 N-00000373)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x04_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 55F17C2A)
    (at 186.8424 194.2084)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P24 (at 0 -1.2446) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 241 /FPGA_Bank_1_2/TMDS_RX1_HOT)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 55F17C2D)
    (at 188.9252 195.6308)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P19 (at 0.0254 1.397) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 238 /FPGA_Bank_1_2/TMDS_RX1_CEC)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 55F01323)
    (at 174.0916 197.6882)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P25 (at 0 -1.1938) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 250 /FPGA_Bank_1_2/TMDS_RX2_CEC)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 55F01320)
    (at 171.8818 200.025)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P26 (at 0 -1.27) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 253 /FPGA_Bank_1_2/TMDS_RX2_HOT)
    )
  )
  (module 1Pin_N (layer TOP) (tedit 55F0123F)
    (at 132.33654 187.48756)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P20 (at 0 -1.2954) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 262 /FPGA_Bank_1_2/TMDS_TX1_CEC)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 55F0123D)
    (at 130.302 184.8104)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P21 (at 0.0254 -1.1938) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 265 /FPGA_Bank_1_2/TMDS_TX1_HOT)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 55F01243)
    (at 149.225 199.3392)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P23 (at -1.7272 -0.5334) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 277 /FPGA_Bank_1_2/TMDS_TX2_HOT)
    )
  )
  (module 1Pin_N   locked (layer TOP) (tedit 55F01246)
    (at 150.7236 200.4314)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference P22 (at 1.4224 -1.016) (layer F.SilkS) hide)
    (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide)
    (pad 1 thru_hole circle (at 0 0) (size 1 1) (drill 0.5)
      (layers *.Cu *.Mask F.SilkS)
      (net 274 /FPGA_Bank_1_2/TMDS_TX2_CEC)
    )
  )
  (module PIN_ARRAY_3X1   locked (layer TOP) (tedit 562490BE)
    (at 251.7394 181.66588 270)
    (descr "Connecteur 3 pins")
    (tags "CONN DEV")
    (fp_text reference K2 (at 0.00254 -2.36474 360) (layer F.SilkS))
    (fp_text value CONN_3 (at 0 -2.159 270) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -2.54 0 270) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
    (pad 2 thru_hole circle (at 0 0 270) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 381 N-00000269)
    )
    (pad 3 thru_hole circle (at 2.54 0 270) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 476 VCC3V3)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x03_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module PIN_ARRAY_3X1   locked (layer TOP) (tedit 56261927)
    (at 210.53298 201.1807)
    (descr "Connecteur 3 pins")
    (tags "CONN DEV")
    (fp_text reference K3 (at -4.75488 0.00254) (layer F.SilkS))
    (fp_text value CONN_3 (at 0 -2.159) (layer F.SilkS) hide)
    (pad 1 thru_hole rect (at -2.54 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
    )
    (pad 2 thru_hole circle (at 0 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 162 /FPGA_Bank_1_2/CYPRESS-RESET)
    )
    (pad 3 thru_hole circle (at 2.54 0) (size 1.524 1.524) (drill 1.016)
      (layers *.Cu *.Mask F.SilkS)
      (net 334 /USB/CYP-RESET)
    )
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x03_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module LOGO   locked (layer TOP) (tedit 536B815A)
    (at 156.1084 168.1099)
    (fp_text reference G*** (at 0 3.38582) (layer F.SilkS) hide)
    (fp_text value LOGO (at 0 -3.6195) (layer F.SilkS) hide)
  )
  (module MH-4MM   locked (layer TOP) (tedit 5624E0A2)
    (at 102.8065 258.826)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference 1PIN (at 0 -3.81) (layer F.SilkS) hide)
    (fp_text value P*** (at 0 2.794) (layer F.SilkS) hide)
    (pad "" thru_hole circle (at 21.1965 -65.021) (size 6 6) (drill 3.97)
      (layers *.Cu *.Mask F.SilkS)
      (net 342 GND)
    )
  )
  (module MH-4MM   locked (layer TOP) (tedit 530C966E)
    (at 174.625 132.842)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference 1PIN (at 0 -3.81) (layer F.SilkS) hide)
    (fp_text value P*** (at 0 2.794) (layer F.SilkS) hide)
    (pad "" np_thru_hole circle (at 0 0) (size 4.0005 4.0005) (drill 4.0005)
      (layers *.Cu *.Mask F.SilkS)
    )
  )
  (module MH-4MM   locked (layer TOP) (tedit 530C966E)
    (at 183.515 190.246)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference 1PIN (at 0 -3.81) (layer F.SilkS) hide)
    (fp_text value P*** (at 0 2.794) (layer F.SilkS) hide)
    (pad "" np_thru_hole circle (at 0 0) (size 4.0005 4.0005) (drill 4.0005)
      (layers *.Cu *.Mask F.SilkS)
    )
  )
  (module Micro_SD_O   locked (layer BOTTOM) (tedit 555B06A0)
    (at 126.7968 102.362 90)
    (fp_text reference Micro_SD (at -0.65 18.15 90) (layer B.SilkS) hide)
    (fp_text value VAL** (at 8.9 14.4 90) (layer B.SilkS) hide)
  )
  (module MH-4MM   locked (layer TOP) (tedit 530C966E)
    (at 230.251 126.5047)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference 1PIN (at 0 -3.81) (layer F.SilkS) hide)
    (fp_text value P*** (at 0 2.794) (layer F.SilkS) hide)
    (pad "" np_thru_hole circle (at 0 0) (size 4.0005 4.0005) (drill 4.0005)
      (layers *.Cu *.Mask F.SilkS)
    )
  )
  (module MH-4MM   locked (layer TOP) (tedit 56384469)
    (at 234.94492 161.06902)
    (descr "module 1 pin (ou trou mecanique de percage)")
    (tags DEV)
    (fp_text reference 1PIN (at 0 -3.81) (layer F.SilkS) hide)
    (fp_text value P*** (at 0 2.794) (layer F.SilkS) hide)
    (pad "" np_thru_hole circle (at -0.00092 -0.00002) (size 4.0005 4.0005) (drill 4.0005)
      (layers *.Cu *.Mask F.SilkS)
    )
  )
  (gr_text . (at 268.775 108.725) (layer F.SilkS))
  (gr_text C12V-2 (at 227.076 70.358) (layer F.SilkS))
  (gr_text "1Gb Ethernet" (at 141.478 60.071) (layer B.SilkS))
  (gr_text VCC (at 254.508 184.277) (layer F.SilkS))
  (gr_text GND (at 254.508 179.197) (layer F.SilkS))
  (gr_text 12V (at 212.34654 60.8076 90) (layer B.SilkS))
  (gr_text 12V (at 212.34654 60.8076 90) (layer F.SilkS))
  (gr_text GND (at 212.41766 65.2526 90) (layer F.SilkS))
  (gr_text GND (at 212.41766 65.2526 90) (layer B.SilkS))
  (gr_text 1 (at 119.14632 126.56058) (layer F.SilkS))
  (gr_text 8 (at 140.47978 126.55804) (layer F.SilkS))
  (gr_text GND (at 138.70686 131.58216 90) (layer B.SilkS))
  (gr_text GND (at 138.71448 131.58216 90) (layer F.SilkS))
  (gr_text VCC3V3 (at 136.1694 130.52298 90) (layer F.SilkS))
  (gr_text VCC3V3 (at 136.17702 130.59918 90) (layer B.SilkS))
  (gr_text * (at 239.79886 201.74966) (layer F.SilkS))
  (gr_text * (at 233.81208 205.62824) (layer F.SilkS))
  (dimension 150.58136 (width 0.3048) (layer Dwgs.User)
    (gr_text "150.581 mm" (at 192.965921 239.239997 359.9980671) (layer Dwgs.User))
    (feature1 (pts (xy 268.25702 226.822) (xy 268.256547 240.868137)))
    (feature2 (pts (xy 117.67566 226.81692) (xy 117.675187 240.863057)))
    (crossbar (pts (xy 117.675296 237.611857) (xy 268.256656 237.616937)))
    (arrow1a (pts (xy 268.256656 237.616937) (xy 267.130133 238.203319)))
    (arrow1b (pts (xy 268.256656 237.616937) (xy 267.130173 237.030479)))
    (arrow2a (pts (xy 117.675296 237.611857) (xy 118.801779 238.198315)))
    (arrow2b (pts (xy 117.675296 237.611857) (xy 118.801819 237.025475)))
  )
  (dimension 5.811522 (width 0.3048) (layer Dwgs.User)
    (gr_text "5.812 mm" (at 234.46486 228.79558 359.9499163) (layer Dwgs.User))
    (feature1 (pts (xy 228.38156 226.8093) (xy 228.377221 231.774916)))
    (feature2 (pts (xy 222.57004 226.80422) (xy 222.565701 231.769836)))
    (crossbar (pts (xy 222.568542 228.518638) (xy 228.380062 228.523718)))
    (arrow1a (pts (xy 228.380062 228.523718) (xy 227.253047 229.109153)))
    (arrow1b (pts (xy 228.380062 228.523718) (xy 227.254072 227.936313)))
    (arrow2a (pts (xy 222.568542 228.518638) (xy 223.694532 229.106043)))
    (arrow2b (pts (xy 222.568542 228.518638) (xy 223.695557 227.933203)))
  )
  (dimension 5.811522 (width 0.3048) (layer Dwgs.User)
    (gr_text "5.812 mm" (at 257.40106 228.68636 359.9499163) (layer Dwgs.User))
    (feature1 (pts (xy 251.24918 226.62134) (xy 251.244841 231.586956)))
    (feature2 (pts (xy 245.43766 226.61626) (xy 245.433321 231.581876)))
    (crossbar (pts (xy 245.436162 228.330678) (xy 251.247682 228.335758)))
    (arrow1a (pts (xy 251.247682 228.335758) (xy 250.120667 228.921193)))
    (arrow1b (pts (xy 251.247682 228.335758) (xy 250.121692 227.748353)))
    (arrow2a (pts (xy 245.436162 228.330678) (xy 246.562152 228.918083)))
    (arrow2b (pts (xy 245.436162 228.330678) (xy 246.563177 227.745243)))
  )
  (gr_text www.numato.com (at 170.4848 169.799) (layer F.SilkS))
  (gr_text OPSIS (at 152.527 183.261) (layer F.SilkS))
  (gr_text SD_DAT2 (at 133.604 130.4544 90) (layer B.SilkS))
  (gr_text SD_DAT3 (at 131.064 130.4544 90) (layer B.SilkS))
  (gr_text SD_CMD (at 128.4986 130.6322 90) (layer B.SilkS))
  (gr_text SD_CLK (at 125.984 130.7592 90) (layer B.SilkS))
  (gr_text SD_DAT0 (at 123.4948 130.4544 90) (layer B.SilkS))
  (gr_text SD_DAT1 (at 120.9294 130.4544 90) (layer B.SilkS))
  (gr_text SD_DAT2 (at 133.6294 130.429 90) (layer F.SilkS))
  (gr_text SD_DAT3 (at 131.064 130.4544 90) (layer F.SilkS))
  (gr_text SD_CMD (at 128.4986 130.6322 90) (layer F.SilkS))
  (gr_text SD_CLK (at 125.984 130.7592 90) (layer F.SilkS))
  (gr_text SD_DAT0 (at 123.4948 130.4544 90) (layer F.SilkS))
  (gr_text SD_DAT1 (at 120.9294 130.4544 90) (layer F.SilkS))
  (gr_text 2 (at 210.5152 199.2122) (layer F.SilkS))
  (gr_text 1 (at 249.682 179.07) (layer F.SilkS))
  (gr_text 2 (at 249.682 181.737) (layer F.SilkS))
  (gr_text 3 (at 249.682 184.277) (layer F.SilkS))
  (gr_text 1 (at 208.0006 199.2122) (layer F.SilkS))
  (gr_text 3 (at 213.0552 199.1868) (layer F.SilkS))
  (gr_text JFX2-RST (at 210.44408 203.4921) (layer F.SilkS))
  (gr_text 135MHz (at 238.5441 143.6878) (layer F.SilkS))
  (gr_text 135MHz (at 238.5441 143.6878) (layer B.SilkS))
  (gr_text RX1-CEC (at 192.27292 195.63334) (layer B.SilkS))
  (gr_text RX1-HOT (at 190.1571 194.17538) (layer B.SilkS))
  (gr_text RX1-SCL (at 185.04154 209.89036 90) (layer B.SilkS))
  (gr_text "RX1 SDA" (at 185.05424 200.66508 90) (layer B.SilkS))
  (gr_text RX2-CEC (at 170.58132 197.69328) (layer B.SilkS))
  (gr_text RX2-SCL (at 162.44316 208.89976 90) (layer B.SilkS))
  (gr_text "RX2 SDA" (at 162.40506 199.4916 90) (layer B.SilkS))
  (gr_text RX2-HOT (at 168.49852 200.04532) (layer B.SilkS))
  (gr_text TX2-CEC (at 154.03576 200.46696) (layer B.SilkS))
  (gr_text TX2-SCL (at 153.39822 196.83984) (layer B.SilkS))
  (gr_text TX2-HOT (at 145.92808 199.3773) (layer B.SilkS))
  (gr_text TX2-SDA (at 144.21104 196.88048) (layer B.SilkS))
  (gr_text TX1-CEC (at 135.89 187.452) (layer B.SilkS))
  (gr_text TX1-HOT (at 126.66472 184.76976) (layer B.SilkS))
  (gr_text TX1-SDA (at 135.89 184.785) (layer B.SilkS))
  (gr_text TX1-SCL (at 126.746 187.452) (layer B.SilkS))
  (gr_text TX2-HOT (at 145.91538 199.30872) (layer F.SilkS))
  (gr_text TX2-CEC (at 154.00782 200.44918) (layer F.SilkS))
  (gr_text RX2-HOT (at 168.42994 200.04278) (layer F.SilkS))
  (gr_text RX2-CEC (at 177.42916 197.7517) (layer F.SilkS))
  (gr_text RX1-HOT (at 190.15964 194.17792) (layer F.SilkS))
  (gr_text RX1-CEC (at 192.27292 195.6308) (layer F.SilkS))
  (gr_text TX1-CEC (at 135.89 187.452) (layer F.SilkS))
  (gr_text TX1-HOT (at 126.62916 184.7342) (layer F.SilkS))
  (gr_text 1 (at 172.90161 69.43725) (layer F.SilkS))
  (gr_text 5 (at 173.0121 59.29884) (layer F.SilkS))
  (gr_text 5 (at 207.264 206.375) (layer F.SilkS))
  (gr_text 1 (at 221.615 206.502) (layer F.SilkS))
  (gr_text IO0 (at 195.1482 119.5705) (layer F.SilkS))
  (gr_text IO1 (at 195.1482 116.967) (layer F.SilkS))
  (gr_text GND (at 195.0847 114.4905) (layer F.SilkS))
  (gr_text 1V5 (at 195.0212 122.1105) (layer F.SilkS))
  (gr_text 3V3 (at 195.0212 124.841) (layer F.SilkS))
  (gr_text "10\n\n9" (at 271.3228 125.6792) (layer F.SilkS))
  (gr_text "2\n\n1" (at 256.1082 125.7046) (layer F.SilkS))
  (gr_text 5 (at 190.9572 112.1918) (layer F.SilkS))
  (gr_text 1 (at 190.9064 127.0254) (layer F.SilkS))
  (gr_text "MICRO SD" (at 125.6538 96.2152) (layer B.SilkS))
  (gr_text DONE (at 196.469 158.496) (layer F.SilkS))
  (gr_text GND (at 261.97052 82.03692) (layer F.SilkS))
  (gr_text -48V (at 266.93114 82.12582) (layer F.SilkS))
  (gr_text +48V (at 271.87398 82.1436) (layer F.SilkS))
  (gr_text 48V (at 276.95906 82.01914) (layer F.SilkS))
  (gr_text "EXPANSION IOs" (at 272.034 147.32 270) (layer F.SilkS))
  (gr_text -48V (at 267.335 82.1436) (layer B.SilkS))
  (gr_text +48V (at 272.161 82.2706) (layer B.SilkS))
  (gr_text GND (at 262.382 82.1436) (layer B.SilkS))
  (gr_text 48V (at 277.114 82.2706) (layer B.SilkS))
  (gr_text 48V (at 273.88312 70.74662 90) (layer B.SilkS))
  (gr_text GND (at 262.6614 67.9958 90) (layer B.SilkS))
  (gr_text GND (at 267.26896 63.75908 90) (layer B.SilkS))
  (gr_text 48V (at 259.89534 60.44184 180) (layer B.SilkS))
  (gr_text GND (at 245.99646 60.45454 180) (layer B.SilkS))
  (gr_text 12V (at 242.2906 70.866 90) (layer B.SilkS))
  (gr_text GND (at 235.88726 63.97244 90) (layer B.SilkS))
  (gr_text GND (at 231.6734 67.8942 90) (layer B.SilkS))
  (gr_text GND (at 273.09318 58.9788 90) (layer B.SilkS))
  (gr_text 48V (at 267.75918 58.9788 90) (layer B.SilkS))
  (gr_text 48V (at 263.03986 58.56478 180) (layer F.SilkS))
  (gr_text GND (at 263.03986 63.89878 180) (layer F.SilkS))
  (gr_text GND (at 242.00866 58.85942 90) (layer B.SilkS))
  (gr_text 12V (at 236.67466 58.85942 90) (layer B.SilkS))
  (gr_text 12V (at 231.99344 58.68924 180) (layer F.SilkS))
  (gr_text GND (at 231.99344 64.02324 180) (layer F.SilkS))
  (gr_text 48V (at 259.97916 60.50534 180) (layer F.SilkS))
  (gr_text GND (at 245.90502 60.45327 180) (layer F.SilkS))
  (gr_text VOUT:4V0 (at 124.714 160.528 270) (layer B.SilkS))
  (gr_text VOUT:12V (at 255.651 91.44) (layer B.SilkS))
  (gr_text VIN:48V (at 257.556 119.888) (layer B.SilkS))
  (gr_text VOUT:0V75 (at 241.046 119.38) (layer B.SilkS))
  (gr_text VIN:3V3 (at 251.206 104.521) (layer B.SilkS))
  (gr_text VOUT:1V5 (at 218.186 101.092) (layer B.SilkS))
  (gr_text VIN:12V (at 239.649 81.915) (layer B.SilkS))
  (gr_text VIN:12V (at 169.164 118.364) (layer B.SilkS))
  (gr_text VOUT:1V2 (at 168.656 145.669) (layer B.SilkS))
  (gr_text VIN:12V (at 149.987 148.971) (layer B.SilkS))
  (gr_text VOUT:0V75 (at 241.046 119.38) (layer F.SilkS))
  (gr_text VIN:3V3 (at 251.206 104.521) (layer F.SilkS))
  (gr_text VOUT:4V0 (at 124.714 160.528 270) (layer F.SilkS))
  (gr_text VIN:12V (at 149.987 148.971) (layer F.SilkS))
  (gr_text VIN:12V (at 169.164 118.364) (layer F.SilkS))
  (gr_text VOUT:1V2 (at 168.656 145.669) (layer F.SilkS))
  (gr_text VOUT:1V5 (at 218.186 101.092) (layer F.SilkS))
  (gr_text VIN:12V (at 239.649 81.915) (layer F.SilkS))
  (gr_text VIN:48V (at 257.556 119.888) (layer F.SilkS))
  (gr_text VOUT:12V (at 259.969 93.218) (layer F.SilkS))
  (gr_text RX1-SCL (at 185.04408 209.8929 90) (layer F.SilkS))
  (gr_text "RX1 SDA" (at 185.05424 200.66508 90) (layer F.SilkS))
  (gr_text "RX2 SDA" (at 162.38728 199.5805 90) (layer F.SilkS))
  (gr_text RX2-SCL (at 162.433 208.99882 90) (layer F.SilkS))
  (gr_text TX1-SCL (at 126.619 187.452) (layer F.SilkS))
  (gr_text TX1-SDA (at 135.89 184.785) (layer F.SilkS))
  (gr_text "13  14" (at 203.52512 77.27188 90) (layer F.SilkS))
  (gr_text "1    2" (at 191.07912 77.01788 90) (layer F.SilkS))
  (gr_text JTAG (at 201.23912 81.08188) (layer F.SilkS))
  (gr_text GND (at 197.17512 78.41488 90) (layer F.SilkS))
  (gr_text NC (at 201.87412 76.12888 90) (layer F.SilkS))
  (gr_text NC (at 200.35012 76.12888 90) (layer F.SilkS))
  (gr_text TDI (at 198.82612 76.12888 90) (layer F.SilkS))
  (gr_text TDO (at 197.30212 75.87488 90) (layer F.SilkS))
  (gr_text TCK (at 195.77812 75.87488 90) (layer F.SilkS))
  (gr_text TMS (at 194.25412 75.87488 90) (layer F.SilkS))
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