| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| U_System_SOFT_TERMINAL|U_terminal|RegisterAcknowledge |
8 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL|U_terminal|RegisterConfiguration |
9 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL|U_terminal|RegisterStatus |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL|U_terminal|RegisterWriteFromInstrument |
8 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL|U_terminal|RegisterReadFromInstrument |
14 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL|U_terminal|control_register |
8 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL|U_terminal|TAP1|id_reg_unit |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL|U_terminal|TAP1 |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL|U_terminal |
21 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_SOFT_TERMINAL |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_System_RTC_SubPart_Port|U_spi |
49 |
0 |
0 |
0 |
45 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_RTC_SubPart_Port |
49 |
8 |
0 |
8 |
37 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|Timer_4 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|Timer_3 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|Timer_2 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|Timer_1 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|Timer_0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|State_state_write_setup |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|State_state_write_pulse |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|State_state_write_hold |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|State_state_write_ack |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|State_state_read_ack |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|State_state_addresssetup |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|i512|lpm_add_sub_inst|auto_generated |
9 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM|i512 |
9 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| U_System_MEM |
61 |
0 |
2 |
0 |
79 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_Shifter|U_Shift_Barrel |
40 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_Shifter |
43 |
1 |
3 |
1 |
33 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugSignalController |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_ControlRegister |
12 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_DebugDataRegister |
40 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_SubstituteRegister |
41 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_TapController |
8 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort |
72 |
0 |
0 |
0 |
76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_OCDS|U_JtagDebugUnit |
73 |
0 |
0 |
0 |
75 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_OCDS |
72 |
2 |
0 |
2 |
71 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|right_mult|pre_result |
22 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|right_mult |
34 |
0 |
9 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|left_mult|pre_result |
18 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|left_mult |
30 |
0 |
9 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1 |
48 |
9 |
0 |
9 |
36 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated |
41 |
0 |
3 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MDU|U_MultDiv |
79 |
0 |
0 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MDU |
71 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_InputSynchronizer |
34 |
0 |
0 |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|ProgramCounter |
139 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_DataHazardResolverA |
185 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_ALU |
76 |
0 |
0 |
0 |
47 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_Bus_MuxB |
50 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_CalculateEffectiveAddress |
48 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_Execute_Mux |
116 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_ExecuteBusy |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_MDU_EnableControl |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_BranchComparator |
74 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_BranchTarget_Relative |
46 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_MakeReturnPC |
33 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl |
184 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_ShiftAmountMux |
11 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_Shifter_EnableControl |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute|U_WriteSteering |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Execute |
257 |
0 |
0 |
0 |
191 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_InterruptController |
92 |
0 |
0 |
0 |
117 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_MemoryManager |
232 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_PipeLineController |
27 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_PipeStage_Decode |
30 |
0 |
0 |
0 |
91 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_ReadSteering|U_ReadSteering_Mux |
58 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_ReadSteering |
58 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_RegisterFile |
277 |
0 |
0 |
0 |
200 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Registers_GP|ram|auto_generated |
45 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Registers_GP|ram_1|auto_generated |
45 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Registers_GP |
49 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Registers_SP |
222 |
0 |
0 |
0 |
86 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Regs_EX_MEM |
323 |
0 |
0 |
0 |
154 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Regs_ID_EX |
226 |
0 |
0 |
0 |
159 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Regs_IF_ID |
48 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU|U_Regs_MEM_WB |
55 |
0 |
0 |
0 |
49 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU|U_MCU |
339 |
0 |
0 |
0 |
309 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_MCU |
333 |
65 |
0 |
65 |
377 |
65 |
65 |
65 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|AND2_componentB4 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|AND2_componentB3 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|AND2_componentB2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|AND2_componentB1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|AND2_componentA4 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|AND2_componentA3 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|AND2_componentA2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|AND2_componentA1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|Memory_MCU_u4_component|altsyncram_component|auto_generated |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|Memory_MCU_u4_component |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|Memory_MCU_u3_component|altsyncram_component|auto_generated |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|Memory_MCU_u3_component |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|Memory_MCU_u2_component|altsyncram_component|auto_generated |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|Memory_MCU_u2_component |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|Memory_MCU_u1_component|altsyncram_component|auto_generated |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory|Memory_MCU_u1_component |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_MCU_SubPart_BootMemory |
104 |
38 |
0 |
38 |
65 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|UseBadDecode |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|LPM_COMPARE_8_8_2|auto_generated |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|DecodeAddr_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|DecodeAddr_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|DecodeAddr_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|DecodeAddr_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|DecodeAddr_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|DecodeAddr_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|DecodeAddr_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|DecodeAddr_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM|Bad_Decode |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_MEM |
105 |
0 |
4 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|UseBadDecode |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|LPM_COMPARE_8_8_1|auto_generated |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|DecodeAddr_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|DecodeAddr_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|DecodeAddr_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|DecodeAddr_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|DecodeAddr_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|DecodeAddr_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|DecodeAddr_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|DecodeAddr_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO|Bad_Decode |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_System_INTERCON_IO |
106 |
0 |
11 |
0 |
86 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U7|U_FPGA_STARTUP8_CTRL |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U7 |
9 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |