| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| nios_reset_clk_ex_domain_synch |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| nios_reset_altpll_0_c0_out_domain_synch |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600|the_uart_9600_regs |
41 |
13 |
6 |
13 |
44 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600|the_uart_9600_rx|the_uart_9600_rx_stimulus_source |
18 |
0 |
17 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600|the_uart_9600_rx |
20 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600|the_uart_9600_tx |
28 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600 |
26 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_uart_9600_s1 |
82 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_touch_irq |
5 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_touch_irq_s1 |
63 |
1 |
2 |
1 |
40 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_touch_cs |
38 |
31 |
31 |
31 |
33 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| the_touch_cs_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_sysid |
3 |
14 |
1 |
14 |
32 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| the_sysid_control_slave |
63 |
1 |
2 |
1 |
39 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_spi_touch |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_spi_touch_spi_control_port |
83 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_spi_sdcard |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_spi_sdcard_spi_control_port |
83 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_spi_lcd22 |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_spi_lcd22_spi_control_port |
83 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_sdram_0|the_sdram_0_input_efifo_module |
47 |
0 |
0 |
0 |
47 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_sdram_0 |
47 |
1 |
1 |
1 |
40 |
1 |
1 |
1 |
16 |
0 |
0 |
0 |
0 |
| the_sdram_0_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_0_s1 |
7 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| the_sdram_0_s1|rdv_fifo_for_cpu_data_master_to_sdram_0_s1 |
7 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| the_sdram_0_s1 |
104 |
0 |
6 |
0 |
76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_sd_cs |
38 |
31 |
31 |
31 |
33 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| the_sd_cs_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_reset |
38 |
31 |
31 |
31 |
33 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| the_reset_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_pd |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| the_pd_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_pc |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| the_pc_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_pb |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| the_pb_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_pa |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| the_pa_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0|endofpacket_bit_pipe |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0|master_FSM |
5 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0|write_request_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0|read_request_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0|slave_FSM |
6 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0|write_done_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0|read_done_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0 |
82 |
1 |
0 |
1 |
78 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0_out |
81 |
0 |
41 |
0 |
38 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_nios_clock_0_in |
102 |
1 |
0 |
1 |
84 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_lcd_wr |
38 |
31 |
31 |
31 |
33 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| the_lcd_wr_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_lcd_rs |
38 |
31 |
31 |
31 |
33 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| the_lcd_rs_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_lcd_cs |
38 |
31 |
31 |
31 |
33 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| the_lcd_cs_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0|the_jtag_uart_0_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0 |
38 |
10 |
23 |
10 |
36 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| the_jtag_uart_0_avalon_jtag_slave |
100 |
1 |
2 |
1 |
78 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_epcs_flash_controller_0|the_boot_copier_rom|auto_generated |
9 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_epcs_flash_controller_0|the_epcs_flash_controller_0_sub |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_epcs_flash_controller_0 |
47 |
0 |
16 |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_epcs_flash_controller_0_epcs_control_port |
129 |
1 |
4 |
1 |
90 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_cpu |
150 |
0 |
26 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_cpu_instruction_master |
127 |
1 |
3 |
1 |
64 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_cpu_data_master |
809 |
27 |
64 |
27 |
111 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
| the_cpu_jtag_debug_module |
132 |
1 |
4 |
1 |
92 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_altpll_0|sd1 |
3 |
1 |
0 |
1 |
6 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_altpll_0|stdsync2|dffpipe3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_altpll_0|stdsync2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| the_altpll_0 |
38 |
31 |
30 |
31 |
36 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| the_altpll_0_pll_slave |
72 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| the_DS18B20 |
38 |
0 |
31 |
0 |
32 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| the_DS18B20_s1 |
96 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |