| userDefinedSettings |
|
| tightlyCoupledInstructionMaster3MapParam |
|
| tightlyCoupledInstructionMaster3AddrWidth |
1 |
| tightlyCoupledInstructionMaster2MapParam |
|
| tightlyCoupledInstructionMaster2AddrWidth |
1 |
| tightlyCoupledInstructionMaster1MapParam |
|
| tightlyCoupledInstructionMaster1AddrWidth |
1 |
| tightlyCoupledInstructionMaster0MapParam |
|
| tightlyCoupledInstructionMaster0AddrWidth |
1 |
| tightlyCoupledDataMaster3MapParam |
|
| tightlyCoupledDataMaster3AddrWidth |
1 |
| tightlyCoupledDataMaster2MapParam |
|
| tightlyCoupledDataMaster2AddrWidth |
1 |
| tightlyCoupledDataMaster1MapParam |
|
| tightlyCoupledDataMaster1AddrWidth |
1 |
| tightlyCoupledDataMaster0MapParam |
|
| tightlyCoupledDataMaster0AddrWidth |
1 |
| setting_showUnpublishedSettings |
false |
| setting_showInternalSettings |
false |
| setting_shadowRegisterSets |
0 |
| setting_preciseSlaveAccessErrorException |
false |
| setting_preciseIllegalMemAccessException |
false |
| setting_preciseDivisionErrorException |
false |
| setting_performanceCounter |
false |
| setting_perfCounterWidth |
_32 |
| setting_interruptControllerType |
Internal |
| setting_illegalMemAccessDetection |
false |
| setting_illegalInstructionsTrap |
false |
| setting_fullWaveformSignals |
false |
| setting_extraExceptionInfo |
false |
| setting_exportPCB |
false |
| setting_debugSimGen |
false |
| setting_clearXBitsLDNonBypass |
true |
| setting_branchPredictionType |
Automatic |
| setting_bit31BypassDCache |
true |
| setting_bigEndian |
false |
| setting_bhtPtrSz |
_8 |
| setting_bhtIndexPcOnly |
false |
| setting_avalonDebugPortPresent |
false |
| setting_alwaysEncrypt |
true |
| setting_allowFullAddressRange |
false |
| setting_activateTrace |
true |
| setting_activateTestEndChecker |
false |
| setting_activateMonitors |
true |
| setting_activateModelChecker |
false |
| setting_HDLSimCachesCleared |
true |
| setting_HBreakTest |
false |
| resetSlave |
epcs_flash_controller_0.epcs_control_port |
| resetOffset |
0 |
| muldiv_multiplierType |
EmbeddedMulFast |
| muldiv_divider |
false |
| mpu_useLimit |
false |
| mpu_numOfInstRegion |
8 |
| mpu_numOfDataRegion |
8 |
| mpu_minInstRegionSize |
_12 |
| mpu_minDataRegionSize |
_12 |
| mpu_enabled |
false |
| mmu_uitlbNumEntries |
_4 |
| mmu_udtlbNumEntries |
_6 |
| mmu_tlbPtrSz |
_7 |
| mmu_tlbNumWays |
_16 |
| mmu_processIDNumBits |
_8 |
| mmu_enabled |
false |
| mmu_autoAssignTlbPtrSz |
true |
| mmu_TLBMissExcSlave |
|
| mmu_TLBMissExcOffset |
0 |
| manuallyAssignCpuID |
false |
| internalIrqMaskSystemInfo |
3 |
| instSlaveMapParam |
<address-map><slave name='sdram_0.s1' start='0x2000000' end='0x4000000' /><slave name='cpu_0.jtag_debug_module' start='0x4001000' end='0x4001800' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x4001800' end='0x4002000' /></address-map> |
| instAddrWidth |
27 |
| impl |
Fast |
| icache_size |
_4096 |
| icache_ramBlockType |
Automatic |
| icache_numTCIM |
_0 |
| icache_burstType |
None |
| exceptionSlave |
sdram_0.s1 |
| exceptionOffset |
32 |
| deviceFeaturesSystemInfo |
M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 |
| deviceFamilyName |
Cyclone III |
| debug_triggerArming |
true |
| debug_level |
Level2 |
| debug_jtagInstanceID |
0 |
| debug_embeddedPLL |
true |
| debug_debugReqSignals |
false |
| debug_assignJtagInstanceID |
false |
| debug_OCIOnchipTrace |
_128 |
| dcache_size |
_0 |
| dcache_ramBlockType |
Automatic |
| dcache_omitDataMaster |
false |
| dcache_numTCDM |
_0 |
| dcache_lineSize |
_32 |
| dcache_bursts |
false |
| dataSlaveMapParam |
<address-map><slave name='sdram_0.s1' start='0x2000000' end='0x4000000' /><slave name='cpu_0.jtag_debug_module' start='0x4001000' end='0x4001800' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x4001800' end='0x4002000' /><slave name='altpll_0.pll_slave' start='0x4002000' end='0x4002010' /><slave name='pio_0.s1' start='0x4002010' end='0x4002020' /><slave name='sysid.control_slave' start='0x4002020' end='0x4002028' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x4002028' end='0x4002030' /></address-map> |
| dataAddrWidth |
27 |
| customInstSlavesSystemInfo |
<info/> |
| cpuReset |
false |
| cpuID |
0 |
| clockFrequency |
50000000 |
| breakSlave |
cpu_0.jtag_debug_module |
| breakOffset |
32 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |