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clk_0

clock_source v11.0

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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cpu_0

altera_nios2 v11.0

Parameters userDefinedSettings tightlyCoupledInstructionMaster3MapParam tightlyCoupledInstructionMaster3AddrWidth 1 tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledDataMaster3MapParam tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster0AddrWidth 1 setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave epcs_flash_controller_0.epcs_control_port resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false internalIrqMaskSystemInfo 31 instSlaveMapParam <address-map><slave name='epcs_flash_controller_0.epcs_control_port' start='0x0' end='0x800' /><slave name='cpu_0.jtag_debug_module' start='0x1000' end='0x1800' /><slave name='sdram_0.s1' start='0x4000000' end='0x6000000' /></address-map> instAddrWidth 27 impl Fast icache_size _4096 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave sdram_0.s1 exceptionOffset 32 deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 deviceFamilyName Cyclone III debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _0 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false dataSlaveMapParam <address-map><slave name='epcs_flash_controller_0.epcs_control_port' start='0x0' end='0x800' /><slave name='cpu_0.jtag_debug_module' start='0x1000' end='0x1800' /><slave name='spi_touch.spi_control_port' start='0x1800' end='0x1820' /><slave name='spi_lcd22.spi_control_port' start='0x1820' end='0x1840' /><slave name='uart_0.s1' start='0x1840' end='0x1860' /><slave name='LED.s1' start='0x1860' end='0x1870' /><slave name='pc.s1' start='0x1870' end='0x1880' /><slave name='sysid_0.control_slave' start='0x1880' end='0x1888' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1888' end='0x1890' /><slave name='sdram_0.s1' start='0x4000000' end='0x6000000' /></address-map> dataAddrWidth 27 customInstSlavesSystemInfo <info/> cpuReset false cpuID 0 clockFrequency 50000000 breakSlave cpu_0.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 50000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 DCACHE_LINE_SIZE 0 DCACHE_LINE_SIZE_LOG2 0 DCACHE_SIZE 0 FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x4000020 RESET_ADDR 0x0 BREAK_ADDR 0x1020 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 27 DATA_ADDR_WIDTH 27 NUM_OF_SHADOW_REG_SETS 0

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sdram_0

altera_avalon_new_sdram_controller v11.0

Parameters TAC 5.5 TMRD 3 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 casLatency 3 clockRate 50000000 columnWidth 9 dataWidth 16 generateSimulationModel true initNOPDelay 0.0 initRefreshCommands 2 masteredTristateBridgeSlave model custom numberOfBanks 4 numberOfChipSelects 1 pinsSharedViaTriState false powerUpDelay 100.0 refreshPeriod 15.625 registerDataIn true rowWidth 13 size 33554432 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_DATA_IN 1 SIM_MODEL_BASE 1 SDRAM_DATA_WIDTH 16 SDRAM_ADDR_WIDTH 24 SDRAM_ROW_WIDTH 13 SDRAM_COL_WIDTH 9 SDRAM_NUM_CHIPSELECTS 1 SDRAM_NUM_BANKS 4 REFRESH_PERIOD 15.625 POWERUP_DELAY 100.0 CAS_LATENCY 3 T_RFC 70.0 T_RP 20.0 T_MRD 3 T_RCD 20.0 T_AC 5.5 T_WR 14.0 INIT_REFRESH_COMMANDS 2 INIT_NOP_DELAY 0.0 SHARED_DATA 0 STARVATION_INDICATOR 0 TRISTATE_BRIDGE_SLAVE "" IS_INITIALIZED 1 SDRAM_BANK_WIDTH 2 CONTENTS_INFO ""

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sysid_0

altera_avalon_sysid v11.0

Parameters id 0 timestamp 1328516957 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 0u TIMESTAMP 1328516957u

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jtag_uart_0

altera_avalon_jtag_uart v11.0

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

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epcs_flash_controller_0

altera_avalon_epcs_flash_controller v11.0

Parameters autoSelectASMIAtom true deviceFamilyString Cyclone III useASMIAtom false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_OFFSET 1024

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LED

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 4 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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spi_touch

altera_avalon_spi v11.0

Parameters actualClockRate 125000.0 actualSlaveSelectToSClkDelay 0.0 clockPhase 0 clockPolarity 0 dataWidth 8 disableAvalonFlowControl false inputClockRate 50000000 insertDelayBetweenSlaveSelectAndSClk false insertSync false lsbOrderedFirst false masterSPI true numberOfSlaves 1 syncRegDepth 2 targetClockRate 125000 targetSlaveSelectToSClkDelay 0.0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DATABITS 8 DATAWIDTH 16 TARGETCLOCK 125000u CLOCKUNITS "Hz" CLOCKMULT 1 NUMSLAVES 1 ISMASTER 1 CLOCKPOLARITY 0 CLOCKPHASE 0 LSBFIRST 0 EXTRADELAY 0 INSERT_SYNC 0 SYNC_REG_DEPTH 2 TARGETSSDELAY "0.0" DELAYUNITS "ns" DELAYMULT "1.0E-9" PREFIX "spi_"

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spi_lcd22

altera_avalon_spi v11.0

Parameters actualClockRate 3571428.0 actualSlaveSelectToSClkDelay 0.0 clockPhase 0 clockPolarity 0 dataWidth 8 disableAvalonFlowControl false inputClockRate 50000000 insertDelayBetweenSlaveSelectAndSClk false insertSync false lsbOrderedFirst false masterSPI true numberOfSlaves 1 syncRegDepth 2 targetClockRate 4000000 targetSlaveSelectToSClkDelay 0.0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DATABITS 8 DATAWIDTH 16 TARGETCLOCK 4000000u CLOCKUNITS "Hz" CLOCKMULT 1 NUMSLAVES 1 ISMASTER 1 CLOCKPOLARITY 0 CLOCKPHASE 0 LSBFIRST 0 EXTRADELAY 0 INSERT_SYNC 0 SYNC_REG_DEPTH 2 TARGETSSDELAY "0.0" DELAYUNITS "ns" DELAYMULT "1.0E-9" PREFIX "spi_"

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pc

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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uart_0

altera_avalon_uart v11.0

Parameters baud 115200 baudError 0.01 clockRate 50000000 dataBits 8 fixedBaud true parity NONE simCharStream simInteractiveInputEnable false simInteractiveOutputEnable false simTrueBaud false stopBits 1 syncRegDepth 2 useCtsRts false useEopRegister false useRelativePathForSimFile false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BAUD 115200 DATA_BITS 8 FIXED_BAUD 1 PARITY 'N' STOP_BITS 1 SYNC_REG_DEPTH 2 USE_CTS_RTS 0 USE_EOP_REGISTER 0 SIM_TRUE_BAUD 0 SIM_CHAR_STREAM "" FREQ 50000000u