| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| inst|base_cro_reset_clk_0_domain_synch |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_uart_0|the_uart_0_regs |
41 |
9 |
6 |
9 |
40 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| inst|the_uart_0|the_uart_0_rx|the_uart_0_rx_stimulus_source |
14 |
0 |
13 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_uart_0|the_uart_0_rx |
16 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_uart_0|the_uart_0_tx |
24 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_uart_0 |
26 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_uart_0_s1 |
82 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_sysid_0 |
3 |
13 |
1 |
13 |
32 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|the_sysid_0_control_slave |
63 |
1 |
2 |
1 |
39 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_spi_touch |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_spi_touch_spi_control_port |
83 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_spi_lcd22 |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_spi_lcd22_spi_control_port |
83 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_sdram_0|the_sdram_0_input_efifo_module |
47 |
0 |
0 |
0 |
47 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_sdram_0 |
47 |
1 |
1 |
1 |
40 |
1 |
1 |
1 |
16 |
0 |
0 |
0 |
0 |
| inst|the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1 |
7 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1 |
7 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|the_sdram_0_s1 |
102 |
0 |
6 |
0 |
76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_pc |
38 |
0 |
24 |
0 |
32 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| inst|the_pc_s1 |
95 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0 |
38 |
10 |
23 |
10 |
36 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst|the_jtag_uart_0_avalon_jtag_slave |
99 |
1 |
2 |
1 |
78 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_epcs_flash_controller_0|the_boot_copier_rom|auto_generated |
9 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_epcs_flash_controller_0|the_epcs_flash_controller_0_sub |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_epcs_flash_controller_0 |
47 |
0 |
16 |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_epcs_flash_controller_0_epcs_control_port |
129 |
1 |
4 |
1 |
90 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0 |
150 |
0 |
27 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0_instruction_master |
127 |
1 |
3 |
1 |
64 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0_data_master |
383 |
28 |
24 |
28 |
110 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
| inst|the_cpu_0_jtag_debug_module |
131 |
1 |
4 |
1 |
92 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|the_LED |
38 |
0 |
28 |
0 |
32 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
| inst|the_LED_s1 |
95 |
1 |
2 |
1 |
74 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst |
6 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
0 |
| inst1|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst1 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |