| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| U_spia|INST_sdi |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|INST_sck |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_9|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_8|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_7|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_6|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_5|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_4|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_33|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_32|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_31|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_30|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_3|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_29|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_28|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_27|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_26|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_25|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_24|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_23|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_22|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_21|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_20|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_2|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_19|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_18|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_17|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_16|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_15|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_14|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_13|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_12|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_11|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_10|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|LPM_COMPARE_32_32_1|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|k_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_9 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_8 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_7 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_6 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_5 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_4 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_31 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_30 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_3 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_29 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_28 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_27 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_26 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_25 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_24 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_23 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_22 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_21 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_20 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_2 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_19 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_18 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_17 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_16 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_15 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_14 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_13 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_12 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_11 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_10 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_1 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i_0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i3311|lpm_add_sub_inst|auto_generated |
65 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i3311 |
65 |
33 |
0 |
33 |
32 |
33 |
33 |
33 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i3310|lpm_add_sub_inst|auto_generated |
65 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_spia|i3310 |
65 |
33 |
0 |
33 |
32 |
33 |
33 |
33 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|data_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|INST_cs |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia|INST_busy |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_spia |
18 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|UseBadDecode |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|LPM_COMPARE_8_8_34|auto_generated |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|DecodeAddr_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|DecodeAddr_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|DecodeAddr_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|DecodeAddr_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|DecodeAddr_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|DecodeAddr_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|DecodeAddr_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|DecodeAddr_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2|Bad_Decode |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_2 |
132 |
0 |
11 |
0 |
121 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|UseBadDecode |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|LPM_COMPARE_8_8_35|auto_generated |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|DecodeAddr_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|DecodeAddr_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|DecodeAddr_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|DecodeAddr_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|DecodeAddr_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|DecodeAddr_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|DecodeAddr_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|DecodeAddr_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1|Bad_Decode |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_WB_INTERCON_1 |
105 |
0 |
4 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_Shifter|U_Shift_Barrel |
40 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_Shifter |
43 |
1 |
3 |
1 |
33 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugSignalController |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_ControlRegister |
12 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_DebugDataRegister |
40 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_SubstituteRegister |
41 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_TapController |
8 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort |
72 |
0 |
0 |
0 |
76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit |
73 |
0 |
0 |
0 |
75 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_OCDS |
72 |
2 |
0 |
2 |
71 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|right_mult|pre_result |
22 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|right_mult |
34 |
0 |
9 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|left_mult|pre_result |
18 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|left_mult |
30 |
0 |
9 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1 |
48 |
9 |
0 |
9 |
36 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated |
41 |
0 |
3 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MDU|U_MultDiv |
79 |
0 |
0 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MDU |
71 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_InputSynchronizer |
34 |
0 |
0 |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|ProgramCounter |
139 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_DataHazardResolverA |
185 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ALU |
76 |
0 |
0 |
0 |
47 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_Bus_MuxB |
50 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_CalculateEffectiveAddress |
48 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_Execute_Mux |
116 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ExecuteBusy |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_MDU_EnableControl |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_BranchComparator |
74 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_BranchTarget_Relative |
46 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_MakeReturnPC |
33 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl |
184 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ShiftAmountMux |
11 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_Shifter_EnableControl |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_WriteSteering |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute |
257 |
0 |
0 |
0 |
191 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_InterruptController |
92 |
0 |
0 |
0 |
117 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_MemoryManager |
232 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_PipeLineController |
27 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_PipeStage_Decode |
30 |
0 |
0 |
0 |
91 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_ReadSteering|U_ReadSteering_Mux |
58 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_ReadSteering |
58 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_RegisterFile |
277 |
0 |
0 |
0 |
200 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Registers_GP|ram|auto_generated |
45 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Registers_GP|ram_1|auto_generated |
45 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Registers_GP |
49 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Registers_SP |
222 |
0 |
0 |
0 |
86 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Regs_EX_MEM |
323 |
0 |
0 |
0 |
154 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Regs_ID_EX |
226 |
0 |
0 |
0 |
159 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Regs_IF_ID |
48 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU|U_Regs_MEM_WB |
55 |
0 |
0 |
0 |
49 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU|U_MCU |
339 |
0 |
0 |
0 |
309 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_MCU |
333 |
65 |
0 |
65 |
377 |
65 |
65 |
65 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|AND2_componentB4 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|AND2_componentB3 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|AND2_componentB2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|AND2_componentB1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|AND2_componentA4 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|AND2_componentA3 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|AND2_componentA2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|AND2_componentA1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4_component|altsyncram_component|auto_generated |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4_component |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3_component|altsyncram_component|auto_generated |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3_component |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2_component|altsyncram_component|auto_generated |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2_component |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1_component|altsyncram_component|auto_generated |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1_component |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TSK3000A_1_SubPart_BootMemory |
104 |
38 |
0 |
38 |
65 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal|RegisterAcknowledge |
8 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal|RegisterConfiguration |
9 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal|RegisterStatus |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal|RegisterWriteFromInstrument |
8 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal|RegisterReadFromInstrument |
14 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal|control_register |
8 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal|TAP1|id_reg_unit |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal|TAP1 |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1|U_terminal |
21 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_TERMINAL_1 |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|Timer_4 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|Timer_3 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|Timer_2 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|Timer_1 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|Timer_0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|State_state_write_setup |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|State_state_write_pulse |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|State_state_write_hold |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|State_state_write_ack |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|State_state_read_ack |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|State_state_addresssetup |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|i531|lpm_add_sub_inst|auto_generated |
11 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM|i531 |
11 |
6 |
0 |
6 |
5 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SRAM |
61 |
0 |
2 |
0 |
79 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|load0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_9 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_8 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_7 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_6 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_5 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_4 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_3 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_2 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_15 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_14 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_13 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_12 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_11 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_10 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_1 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|dataout0_0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST|clk0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPIDACTEST |
24 |
15 |
0 |
15 |
34 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPI_DAC_SubPart_Port|U_spi |
49 |
0 |
0 |
0 |
45 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_SPI_DAC_SubPart_Port |
49 |
9 |
0 |
9 |
33 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|YIN_Reg_7 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|YIN_Reg_6 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|YIN_Reg_5 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|YIN_Reg_4 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|YIN_Reg_3 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|YIN_Reg_2 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|YIN_Reg_1 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|YIN_Reg_0 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|XIN_Reg_7 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|XIN_Reg_6 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|XIN_Reg_5 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|XIN_Reg_4 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|XIN_Reg_3 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|XIN_Reg_2 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|XIN_Reg_1 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|XIN_Reg_0 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|up_ireg_3 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|up_ireg_2 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|up_ireg_1 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|up_ireg_0 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|tapstate_r_3 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|tapstate_r_2 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|tapstate_r_1 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|tapstate_r_0 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|shiftir_r |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|shiftdr_r |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|sh_ireg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|sh_ireg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|sh_ireg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|sh_ireg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|reset_r |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit|sh_reg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|id_reg_unit |
36 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1|byp_reg |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|TAP1 |
37 |
32 |
0 |
32 |
6 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|StartUpCounter_3 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|StartUpCounter_2 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|StartUpCounter_1 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|StartUpCounter_0 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_18 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_17 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_16 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|up_reg_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value|sh_reg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Value |
46 |
19 |
0 |
19 |
20 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|up_reg_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length|sh_reg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterOutput_Length |
40 |
33 |
0 |
33 |
1 |
33 |
33 |
33 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|up_reg_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value|sh_reg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Value |
40 |
17 |
0 |
17 |
1 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|up_reg_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length|sh_reg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterInput_Length |
40 |
33 |
0 |
33 |
1 |
33 |
33 |
33 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_31 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_30 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_29 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_28 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_27 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_26 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_25 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_24 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_23 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_22 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_21 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_20 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_19 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_18 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_17 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_16 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|up_reg_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration|sh_reg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterExtConfiguration |
72 |
65 |
0 |
65 |
1 |
65 |
65 |
65 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_31 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_30 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_29 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_28 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_27 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_26 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_25 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_24 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_23 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_22 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_21 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_20 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_19 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_18 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_17 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_16 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|up_reg_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration|sh_reg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|RegisterConfiguration |
72 |
65 |
0 |
65 |
1 |
65 |
65 |
65 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|i238|lpm_add_sub_inst|auto_generated |
9 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|i238 |
9 |
5 |
0 |
5 |
4 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|DefaultEnable |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|up_reg_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|up_reg_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|up_reg_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|up_reg_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|up_reg_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|up_reg_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|up_reg_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|up_reg_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register|sh_reg_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent|control_register |
24 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL|InternalComponent |
20 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_NOS031_OB_CTLPANEL |
20 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_2_0_component_c11 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_main_component_c10 |
35 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_25_0_component_c9|U2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_25_0_component_c9|U1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_25_0_component_c9 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_9_0_component_c8|U2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_9_0_component_c8|U1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_9_0_component_c8 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_1_5_component_c7 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_2_5_component_c6 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_3_0_component_c5 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_5_0_component_c4 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_3_0_component_c3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_5_0_component_c2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_3_0_component_c1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|divisor_5_0_component_c0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|user2_register |
8 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|user1_register |
8 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|control_register |
8 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|tap1|id_reg_unit |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ|tap1 |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4|U_FREQ |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4 |
5 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_2_0_component_c11 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_main_component_c10 |
35 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_25_0_component_c9|U2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_25_0_component_c9|U1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_25_0_component_c9 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_9_0_component_c8|U2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_9_0_component_c8|U1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_9_0_component_c8 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_1_5_component_c7 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_2_5_component_c6 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_3_0_component_c5 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_5_0_component_c4 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_3_0_component_c3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_5_0_component_c2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_3_0_component_c1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_5_0_component_c0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|user2_register |
8 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|user1_register |
8 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|control_register |
8 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|tap1|id_reg_unit |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|tap1 |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3 |
5 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U2_U2|altsyncram_component|auto_generated |
45 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U2 |
45 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_BUFFREG |
38 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_TAP|id_reg_unit |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_TAP |
7 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_SELREG |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_MAGNITREG |
9 |
0 |
0 |
0 |
15 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_ECNTREG |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_CURSORREG |
9 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_TRMASKREG |
8 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_TRWORD2REG |
9 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_TRWORDREG |
8 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_CTRLREG |
10 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_CFGREG |
9 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE|U_NEXUS_CTRL_FSM |
4 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT|U_NX_MODULE |
26 |
0 |
0 |
0 |
168 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_LA16PORT |
57 |
0 |
0 |
0 |
176 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_FSM |
253 |
0 |
0 |
0 |
132 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1|U_DUMP |
83 |
0 |
0 |
0 |
76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1|U1 |
177 |
0 |
0 |
0 |
200 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2_U1 |
103 |
21 |
0 |
21 |
53 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |