Static Timing Analysis

Project : FreeSoC2blink
Build Time : 06/03/21 13:49:42
Device : CY8C5888AXI-LP096
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Async
CyBUS_CLK AB(0)_PAD
CyBUS_CLK AB(1)_PAD
CyBUS_CLK AB(2)_PAD
CyBUS_CLK AB(3)_PAD
CyBUS_CLK AB(4)_PAD
CyBUS_CLK AB(5)_PAD
CyBUS_CLK AB(6)_PAD
CyBUS_CLK AB(7)_PAD
CyBUS_CLK nIOE(0)_PAD
CyBUS_CLK nWR(0)_PAD
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
AB(0)_PAD AB(0)_PAD UNKNOWN UNKNOWN N/A
AB(1)_PAD AB(1)_PAD UNKNOWN UNKNOWN N/A
AB(2)_PAD AB(2)_PAD UNKNOWN UNKNOWN N/A
AB(3)_PAD AB(3)_PAD UNKNOWN UNKNOWN N/A
AB(4)_PAD AB(4)_PAD UNKNOWN UNKNOWN N/A
AB(5)_PAD AB(5)_PAD UNKNOWN UNKNOWN N/A
AB(6)_PAD AB(6)_PAD UNKNOWN UNKNOWN N/A
AB(7)_PAD AB(7)_PAD UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
nIOE(0)_PAD nIOE(0)_PAD UNKNOWN UNKNOWN N/A
nWR(0)_PAD nWR(0)_PAD UNKNOWN UNKNOWN N/A
phi(0)_PAD phi(0)_PAD UNKNOWN UNKNOWN 121.051 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 10000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_20/q Net_20/main_0 121.051 MHz 8.261
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,1) 1 Net_20 Net_20/clock_0 Net_20/q 1.250
macrocell7 U(2,1) 1 Net_20 Net_20/q Net_20/main_0 3.501
macrocell7 U(2,1) 1 Net_20 SETUP 3.510
Clock Skew 0.000
\APUclkDivider:count_0\/q \APUclkDivider:count_0\/main_2 132.644 MHz 7.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/clock_0 \APUclkDivider:count_0\/q 1.250
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/q \APUclkDivider:count_0\/main_2 2.779
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ SETUP 3.510
Clock Skew 0.000
\APUclkDivider:count_0\/q Net_20/main_5 132.908 MHz 7.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/clock_0 \APUclkDivider:count_0\/q 1.250
Route 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/q Net_20/main_5 2.764
macrocell7 U(2,1) 1 Net_20 SETUP 3.510
Clock Skew 0.000
\APUclkDivider:count_0\/q \APUclkDivider:count_2\/main_4 132.908 MHz 7.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/clock_0 \APUclkDivider:count_0\/q 1.250
Route 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/q \APUclkDivider:count_2\/main_4 2.764
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ SETUP 3.510
Clock Skew 0.000
\APUclkDivider:count_0\/q \APUclkDivider:count_1\/main_3 132.908 MHz 7.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/clock_0 \APUclkDivider:count_0\/q 1.250
Route 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/q \APUclkDivider:count_1\/main_3 2.764
macrocell10 U(2,1) 1 \APUclkDivider:count_1\ SETUP 3.510
Clock Skew 0.000
\APUclkDivider:not_last_reset\/q Net_20/main_2 135.980 MHz 7.354
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/clock_0 \APUclkDivider:not_last_reset\/q 1.250
Route 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/q Net_20/main_2 2.594
macrocell7 U(2,1) 1 Net_20 SETUP 3.510
Clock Skew 0.000
\APUclkDivider:not_last_reset\/q \APUclkDivider:count_2\/main_1 135.980 MHz 7.354
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/clock_0 \APUclkDivider:not_last_reset\/q 1.250
Route 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/q \APUclkDivider:count_2\/main_1 2.594
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ SETUP 3.510
Clock Skew 0.000
\APUclkDivider:not_last_reset\/q \APUclkDivider:count_1\/main_1 135.980 MHz 7.354
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/clock_0 \APUclkDivider:not_last_reset\/q 1.250
Route 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/q \APUclkDivider:count_1\/main_1 2.594
macrocell10 U(2,1) 1 \APUclkDivider:count_1\ SETUP 3.510
Clock Skew 0.000
\APUclkDivider:not_last_reset\/q \APUclkDivider:count_0\/main_1 135.999 MHz 7.353
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/clock_0 \APUclkDivider:not_last_reset\/q 1.250
Route 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/q \APUclkDivider:count_0\/main_1 2.593
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ SETUP 3.510
Clock Skew 0.000
\APUclkDivider:count_2\/q Net_20/main_3 141.623 MHz 7.061
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ \APUclkDivider:count_2\/clock_0 \APUclkDivider:count_2\/q 1.250
Route 1 \APUclkDivider:count_2\ \APUclkDivider:count_2\/q Net_20/main_3 2.301
macrocell7 U(2,1) 1 Net_20 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\APUclkDivider:count_1\/q Net_20/main_4 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \APUclkDivider:count_1\ \APUclkDivider:count_1\/clock_0 \APUclkDivider:count_1\/q 1.250
Route 1 \APUclkDivider:count_1\ \APUclkDivider:count_1\/q Net_20/main_4 2.287
macrocell7 U(2,1) 1 Net_20 HOLD 0.000
Clock Skew 0.000
\APUclkDivider:count_1\/q \APUclkDivider:count_2\/main_3 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \APUclkDivider:count_1\ \APUclkDivider:count_1\/clock_0 \APUclkDivider:count_1\/q 1.250
Route 1 \APUclkDivider:count_1\ \APUclkDivider:count_1\/q \APUclkDivider:count_2\/main_3 2.287
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ HOLD 0.000
Clock Skew 0.000
\APUclkDivider:count_1\/q \APUclkDivider:count_1\/main_2 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \APUclkDivider:count_1\ \APUclkDivider:count_1\/clock_0 \APUclkDivider:count_1\/q 1.250
macrocell10 U(2,1) 1 \APUclkDivider:count_1\ \APUclkDivider:count_1\/q \APUclkDivider:count_1\/main_2 2.287
macrocell10 U(2,1) 1 \APUclkDivider:count_1\ HOLD 0.000
Clock Skew 0.000
\APUclkDivider:count_2\/q Net_20/main_3 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ \APUclkDivider:count_2\/clock_0 \APUclkDivider:count_2\/q 1.250
Route 1 \APUclkDivider:count_2\ \APUclkDivider:count_2\/q Net_20/main_3 2.301
macrocell7 U(2,1) 1 Net_20 HOLD 0.000
Clock Skew 0.000
\APUclkDivider:count_2\/q \APUclkDivider:count_2\/main_2 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ \APUclkDivider:count_2\/clock_0 \APUclkDivider:count_2\/q 1.250
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ \APUclkDivider:count_2\/q \APUclkDivider:count_2\/main_2 2.301
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ HOLD 0.000
Clock Skew 0.000
\APUclkDivider:not_last_reset\/q \APUclkDivider:count_0\/main_1 3.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/clock_0 \APUclkDivider:not_last_reset\/q 1.250
Route 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/q \APUclkDivider:count_0\/main_1 2.593
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ HOLD 0.000
Clock Skew 0.000
\APUclkDivider:not_last_reset\/q Net_20/main_2 3.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/clock_0 \APUclkDivider:not_last_reset\/q 1.250
Route 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/q Net_20/main_2 2.594
macrocell7 U(2,1) 1 Net_20 HOLD 0.000
Clock Skew 0.000
\APUclkDivider:not_last_reset\/q \APUclkDivider:count_2\/main_1 3.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/clock_0 \APUclkDivider:not_last_reset\/q 1.250
Route 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/q \APUclkDivider:count_2\/main_1 2.594
macrocell9 U(2,1) 1 \APUclkDivider:count_2\ HOLD 0.000
Clock Skew 0.000
\APUclkDivider:not_last_reset\/q \APUclkDivider:count_1\/main_1 3.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/clock_0 \APUclkDivider:not_last_reset\/q 1.250
Route 1 \APUclkDivider:not_last_reset\ \APUclkDivider:not_last_reset\/q \APUclkDivider:count_1\/main_1 2.594
macrocell10 U(2,1) 1 \APUclkDivider:count_1\ HOLD 0.000
Clock Skew 0.000
\APUclkDivider:count_0\/q Net_20/main_5 4.014
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,1) 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/clock_0 \APUclkDivider:count_0\/q 1.250
Route 1 \APUclkDivider:count_0\ \APUclkDivider:count_0\/q Net_20/main_5 2.764
macrocell7 U(2,1) 1 Net_20 HOLD 0.000
Clock Skew 0.000
+ Asynchronous Clock Crossing Section
+ Source Clock CyBUS_CLK
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 19.584
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -21.782
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 20.825
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -20.541
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 22.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -19.225
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 21.849
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -19.517
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 21.026
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -20.340
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 21.035
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -20.331
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 21.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -19.963
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 20.656
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -20.710
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 20.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -21.329
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_0 cydff_1/main_0 20.010
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_out DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Skew -21.356
+ Input To Output Section
Source Destination Delay (ns)
AB(19)_PAD:in nRAMCS1(0)_PAD 39.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
FreeSoC2blink 1 AB(19)_PAD:in AB(19)_PAD:in AB(19)_PAD:in 0.000
Route 1 AB(19)_PAD AB(19)_PAD:in AB(19)/pad_in 0.000
iocell35 P1[5] 1 AB(19) AB(19)/pad_in AB(19)/fb 6.941
Route 1 net_AB_19 AB(19)/fb Net_102/main_0 8.308
macrocell5 U(2,2) 1 Net_102 Net_102/main_0 Net_102/q 3.350
Route 1 Net_102 Net_102/q nRAMCS1(0)/pin_input 6.091
iocell44 P0[0] 1 nRAMCS1(0) nRAMCS1(0)/pin_input nRAMCS1(0)/pad_out 15.251
Route 1 nRAMCS1(0)_PAD nRAMCS1(0)/pad_out nRAMCS1(0)_PAD 0.000
nME(0)_PAD nRAMCS1(0)_PAD 39.489
Type Location Fanout Instance/Net Source Dest Delay (ns)
FreeSoC2blink 1 nME(0)_PAD nME(0)_PAD nME(0)_PAD 0.000
Route 1 nME(0)_PAD nME(0)_PAD nME(0)/pad_in 0.000
iocell43 P1[6] 1 nME(0) nME(0)/pad_in nME(0)/fb 7.843
Route 1 net_nME nME(0)/fb Net_102/main_1 6.954
macrocell5 U(2,2) 1 Net_102 Net_102/main_1 Net_102/q 3.350
Route 1 Net_102 Net_102/q nRAMCS1(0)/pin_input 6.091
iocell44 P0[0] 1 nRAMCS1(0) nRAMCS1(0)/pin_input nRAMCS1(0)/pad_out 15.251
Route 1 nRAMCS1(0)_PAD nRAMCS1(0)/pad_out nRAMCS1(0)_PAD 0.000
AB(19)_PAD:in nRAMCS0(0)_PAD 37.802
Type Location Fanout Instance/Net Source Dest Delay (ns)
FreeSoC2blink 1 AB(19)_PAD:in AB(19)_PAD:in AB(19)_PAD:in 0.000
Route 1 AB(19)_PAD AB(19)_PAD:in AB(19)/pad_in 0.000
iocell35 P1[5] 1 AB(19) AB(19)/pad_in AB(19)/fb 6.941
Route 1 net_AB_19 AB(19)/fb Net_99/main_1 7.729
macrocell4 U(3,1) 1 Net_99 Net_99/main_1 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
nME(0)_PAD nRAMCS0(0)_PAD 37.008
Type Location Fanout Instance/Net Source Dest Delay (ns)
FreeSoC2blink 1 nME(0)_PAD nME(0)_PAD nME(0)_PAD 0.000
Route 1 nME(0)_PAD nME(0)_PAD nME(0)/pad_in 0.000
iocell43 P1[6] 1 nME(0) nME(0)/pad_in nME(0)/fb 7.843
Route 1 net_nME nME(0)/fb Net_99/main_2 6.033
macrocell4 U(3,1) 1 Net_99 Net_99/main_2 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
AB(19)_PAD:in nROMCS(0)_PAD 41.657
Type Location Fanout Instance/Net Source Dest Delay (ns)
FreeSoC2blink 1 AB(19)_PAD:in AB(19)_PAD:in AB(19)_PAD:in 0.000
Route 1 AB(19)_PAD AB(19)_PAD:in AB(19)/pad_in 0.000
iocell35 P1[5] 1 AB(19) AB(19)/pad_in AB(19)/fb 6.941
Route 1 net_AB_19 AB(19)/fb Net_94/main_1 7.729
macrocell3 U(3,1) 1 Net_94 Net_94/main_1 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
nME(0)_PAD nROMCS(0)_PAD 40.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
FreeSoC2blink 1 nME(0)_PAD nME(0)_PAD nME(0)_PAD 0.000
Route 1 nME(0)_PAD nME(0)_PAD nME(0)/pad_in 0.000
iocell43 P1[6] 1 nME(0) nME(0)/pad_in nME(0)/fb 7.843
Route 1 net_nME nME(0)/fb Net_94/main_2 6.033
macrocell3 U(3,1) 1 Net_94 Net_94/main_2 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
+ Input To Clock Section
+ AB(0)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -4.014
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -21.782
nRESET(0)_PAD cydff_1/ar_0 -5.071
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -21.782
+ AB(1)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -2.773
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -20.541
nRESET(0)_PAD cydff_1/ar_0 -3.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -20.541
+ AB(2)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -1.457
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -19.225
nRESET(0)_PAD cydff_1/ar_0 -2.514
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -19.225
+ AB(3)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -1.749
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -19.517
nRESET(0)_PAD cydff_1/ar_0 -2.806
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -19.517
+ AB(4)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -2.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -20.340
nRESET(0)_PAD cydff_1/ar_0 -3.629
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -20.340
+ AB(5)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -2.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -20.331
nRESET(0)_PAD cydff_1/ar_0 -3.620
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -20.331
+ AB(6)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -2.195
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -19.963
nRESET(0)_PAD cydff_1/ar_0 -3.252
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -19.963
+ AB(7)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -2.942
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -20.710
nRESET(0)_PAD cydff_1/ar_0 -3.999
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -20.710
+ nIOE(0)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -3.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -21.329
nRESET(0)_PAD cydff_1/ar_0 -4.618
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -21.329
+ nWR(0)_PAD
Source Destination Delay (ns)
DB0(0)_PAD:in cydff_1/main_0 -3.588
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 DB0(0)_PAD DB0(0)_PAD:in DB0(0)/pad_in 0.000
iocell42 P0[5] 1 DB0(0) DB0(0)/pad_in DB0(0)/fb 8.264
Route 1 net_DB_0 DB0(0)/fb cydff_1/main_0 5.994
macrocell12 U(3,2) 1 cydff_1 SETUP 3.510
Clock Clock path delay -21.356
nRESET(0)_PAD cydff_1/ar_0 -4.645
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb cydff_1/ar_0 8.281
macrocell12 U(3,2) 1 cydff_1 RECOVERY -0.000
Clock Clock path delay -21.356
+ phi(0)_PAD
Source Destination Delay (ns)
nRESET(0)_PAD Net_20/main_1 4.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 nRESET(0)_PAD nRESET(0)_PAD nRESET(0)/pad_in 0.000
iocell5 P12[3] 1 nRESET(0) nRESET(0)/pad_in nRESET(0)/fb 8.430
Route 1 Net_30 nRESET(0)/fb Net_20/main_1 7.529
macrocell7 U(2,1) 1 Net_20 SETUP 3.510
Clock Clock path delay -14.674
+ Clock To Output Section
+ AB(0)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 52.929
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 21.782
cydff_1/q nRAMCS0(0)_PAD 49.074
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 21.782
+ AB(1)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 51.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 20.541
cydff_1/q nRAMCS0(0)_PAD 47.833
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 20.541
+ AB(2)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 50.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 19.225
cydff_1/q nRAMCS0(0)_PAD 46.517
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 19.225
+ AB(3)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 50.664
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 19.517
cydff_1/q nRAMCS0(0)_PAD 46.809
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 19.517
+ AB(4)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 51.487
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 20.340
cydff_1/q nRAMCS0(0)_PAD 47.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 20.340
+ AB(5)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 51.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 20.331
cydff_1/q nRAMCS0(0)_PAD 47.623
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 20.331
+ AB(6)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 51.110
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 19.963
cydff_1/q nRAMCS0(0)_PAD 47.255
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 19.963
+ AB(7)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 51.857
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 20.710
cydff_1/q nRAMCS0(0)_PAD 48.002
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 20.710
+ CyBUS_CLK
Source Destination Delay (ns)
\TO_MPU_REG:Sync:ctrl_reg\/control_1 DB1(0)_PAD:out 26.435
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_324 \TO_MPU_REG:Sync:ctrl_reg\/control_1 DB1(0)/pin_input 8.165
iocell13 P12[6] 1 DB1(0) DB1(0)/pin_input DB1(0)/pad_out 16.220
Route 1 DB1(0)_PAD DB1(0)/pad_out DB1(0)_PAD:out 0.000
Clock Clock path delay 0.000
\TO_MPU_REG:Sync:ctrl_reg\/control_7 DB7(0)_PAD:out 24.960
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_7 2.050
Route 1 Net_336 \TO_MPU_REG:Sync:ctrl_reg\/control_7 DB7(0)/pin_input 7.349
iocell39 P0[6] 1 DB7(0) DB7(0)/pin_input DB7(0)/pad_out 15.561
Route 1 DB7(0)_PAD DB7(0)/pad_out DB7(0)_PAD:out 0.000
Clock Clock path delay 0.000
\TO_MPU_REG:Sync:ctrl_reg\/control_6 DB6(0)_PAD:out 24.395
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_6 2.050
Route 1 Net_320 \TO_MPU_REG:Sync:ctrl_reg\/control_6 DB6(0)/pin_input 7.294
iocell36 P4[0] 1 DB6(0) DB6(0)/pin_input DB6(0)/pad_out 15.051
Route 1 DB6(0)_PAD DB6(0)/pad_out DB6(0)_PAD:out 0.000
Clock Clock path delay 0.000
\TO_MPU_REG:Sync:ctrl_reg\/control_2 DB2(0)_PAD:out 24.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_312 \TO_MPU_REG:Sync:ctrl_reg\/control_2 DB2(0)/pin_input 6.632
iocell38 P15[3] 1 DB2(0) DB2(0)/pin_input DB2(0)/pad_out 15.486
Route 1 DB2(0)_PAD DB2(0)/pad_out DB2(0)_PAD:out 0.000
Clock Clock path delay 0.000
\TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)_PAD:out 23.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_300 \TO_MPU_REG:Sync:ctrl_reg\/control_0 DB0(0)/pin_input 6.525
iocell42 P0[5] 1 DB0(0) DB0(0)/pin_input DB0(0)/pad_out 15.023
Route 1 DB0(0)_PAD DB0(0)/pad_out DB0(0)_PAD:out 0.000
Clock Clock path delay 0.000
\TO_MPU_REG:Sync:ctrl_reg\/control_3 DB3(0)_PAD:out 23.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_328 \TO_MPU_REG:Sync:ctrl_reg\/control_3 DB3(0)/pin_input 5.986
iocell41 P0[2] 1 DB3(0) DB3(0)/pin_input DB3(0)/pad_out 15.459
Route 1 DB3(0)_PAD DB3(0)/pad_out DB3(0)_PAD:out 0.000
Clock Clock path delay 0.000
\TO_MPU_REG:Sync:ctrl_reg\/control_5 DB5(0)_PAD:out 23.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_332 \TO_MPU_REG:Sync:ctrl_reg\/control_5 DB5(0)/pin_input 5.656
iocell40 P12[2] 1 DB5(0) DB5(0)/pin_input DB5(0)/pad_out 15.666
Route 1 DB5(0)_PAD DB5(0)/pad_out DB5(0)_PAD:out 0.000
Clock Clock path delay 0.000
\TO_MPU_REG:Sync:ctrl_reg\/control_4 DB4(0)_PAD:out 23.078
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,2) 1 \TO_MPU_REG:Sync:ctrl_reg\ \TO_MPU_REG:Sync:ctrl_reg\/busclk \TO_MPU_REG:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_316 \TO_MPU_REG:Sync:ctrl_reg\/control_4 DB4(0)/pin_input 6.599
iocell37 P15[1] 1 DB4(0) DB4(0)/pin_input DB4(0)/pad_out 14.429
Route 1 DB4(0)_PAD DB4(0)/pad_out DB4(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ nIOE(0)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 52.476
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 21.329
cydff_1/q nRAMCS0(0)_PAD 48.621
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 21.329
+ nWR(0)_PAD
Source Destination Delay (ns)
cydff_1/q nROMCS(0)_PAD 52.503
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_94/main_0 2.910
macrocell3 U(3,1) 1 Net_94 Net_94/main_0 Net_94/q 3.350
Route 1 Net_94 Net_94/q nROMCS(0)/pin_input 8.142
iocell46 P0[7] 1 nROMCS(0) nROMCS(0)/pin_input nROMCS(0)/pad_out 15.495
Route 1 nROMCS(0)_PAD nROMCS(0)/pad_out nROMCS(0)_PAD 0.000
Clock Clock path delay 21.356
cydff_1/q nRAMCS0(0)_PAD 48.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q Net_99/main_0 2.910
macrocell4 U(3,1) 1 Net_99 Net_99/main_0 Net_99/q 3.350
Route 1 Net_99 Net_99/q nRAMCS0(0)/pin_input 5.527
iocell45 P15[0] 1 nRAMCS0(0) nRAMCS0(0)/pin_input nRAMCS0(0)/pad_out 14.255
Route 1 nRAMCS0(0)_PAD nRAMCS0(0)/pad_out nRAMCS0(0)_PAD 0.000
Clock Clock path delay 21.356
+ phi(0)_PAD
Source Destination Delay (ns)
Net_20/q CLK2MHZ(0)_PAD 38.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,1) 1 Net_20 Net_20/clock_0 Net_20/q 1.250
Route 1 Net_20 Net_20/q CLK2MHZ(0)/pin_input 7.527
iocell3 P1[7] 1 CLK2MHZ(0) CLK2MHZ(0)/pin_input CLK2MHZ(0)/pad_out 15.381
Route 1 CLK2MHZ(0)_PAD CLK2MHZ(0)/pad_out CLK2MHZ(0)_PAD 0.000
Clock Clock path delay 14.674