PnR Messages

Report Title PnR Report
Design File D:\File\Micky\Github\T-FPGA\example\FPGA\i2c-slave\i2c-slave\impl\gwsynthesis\i2c-slave.vg
Physical Constraints File D:\File\Micky\Github\T-FPGA\example\FPGA\i2c-slave\i2c-slave\src\i2c-slave.cst
Timing Constraints File ---
Version V1.9.8.01
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Wed Feb 22 16:34:10 2023
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s Placement Phase 1: CPU time = 0h 0m 0.059s, Elapsed time = 0h 0m 0.059s Placement Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s Placement Phase 3: CPU time = 0h 0m 0.757s, Elapsed time = 0h 0m 0.757s Total Placement: CPU time = 0h 0m 0.818s, Elapsed time = 0h 0m 0.819s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.028s, Elapsed time = 0h 0m 0.028s Routing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s Total Routing: CPU time = 0h 0m 0.059s, Elapsed time = 0h 0m 0.06s Generate output files: CPU time = 0h 0m 0.465s, Elapsed time = 0h 0m 0.465s
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 216MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 32/4608 1%
    --LUT,ALU,ROM16 32(32 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 19/3570 1%
    --Logic Register as Latch 1/3456 1%
    --Logic Register as FF 18/3456 1%
    --I/O Register as Latch 0/114 0%
    --I/O Register as FF 0/114 0%
CLS 27/2304 1%
I/O Port 4 -
I/O Buf 3 -
    --Input Buf 1 -
    --Output Buf 1 -
    --Inout Buf 1 -
IOLOGIC 0 0%
BSRAM 0 0%
DSP 00%
PLL 0/2 0%
DCS 0/4 0%
DQCE 0/12 0%
OSC 0/1 0%
CLKDIV 0/6 0%
DLLDLY 0/6 0%
DHCEN 0/12 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 0/10(0%)
bank 1 2/10(20%)
bank 2 0/9(0%)
bank 3 1/24(4%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 2/8(25%)
SECONDARY 0/8(0%)
GCLK_PIN 0/5(0%)
PLL 0/2(0%)
CLKDIV 0/6(0%)
DLLDLY 0/6(0%)

Global Clock Signals:

Signal Global Clock Location
iic_scl_d PRIMARY LEFT
n5_8 PRIMARY LEFT

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor BankVccio
clk 45/1 Y in IOT13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
iic_scl 44/1 Y in IOT17[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
led_io 15/3 Y out IOB5[A] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8
iic_sda 40/1 Y io IOT26[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
4/0 - out IOT2[B] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA -
6/0 - in IOT3[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
7/0 - in IOT3[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
8/0 - in IOT4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
9/0 - in IOT5[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
10/0 - in IOT7[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
1/0 - in IOT10[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
2/0 - in IOT10[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
48/1 - in IOT11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
47/1 - in IOT11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
45/1 clk in IOT13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
46/1 - in IOT13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
43/1 - in IOT17[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
44/1 iic_scl in IOT17[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
41/1 - in IOT20[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
42/1 - in IOT20[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
39/1 - in IOT26[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
40/1 iic_sda io IOT26[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
13/3 - in IOB4[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
14/3 - in IOB4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
15/3 led_io out IOB5[A] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8
16/3 - in IOB6[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
17/3 - in IOB6[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
18/3 - in IOB13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
19/3 - in IOB13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
20/3 - in IOB16[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
21/3 - in IOB16[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
22/3 - in IOB22[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
23/3 - in IOB22[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
35/2 - in IOR2[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
34/2 - in IOR2[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
33/2 - in IOR9[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
32/2 - in IOR11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
31/2 - in IOR11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
30/2 - in IOR15[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
29/2 - in IOR15[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
28/2 - in IOR17[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
27/2 - in IOR17[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -