Timing Messages

Report Title	Timing Analysis Report
Design File	D:\File\Micky\Github\T-FPGA\example\FPGA\i2c-slave\i2c-slave\impl\gwsynthesis\i2c-slave.vg
Physical Constraints File	D:\File\Micky\Github\T-FPGA\example\FPGA\i2c-slave\i2c-slave\src\i2c-slave.cst
Timing Constraint File	---
Version	V1.9.8.01
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Wed Feb 22 16:34:10 2023
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	42
Numbers of Endpoints Analyzed	42
Numbers of Falling Endpoints	35
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
iic_scl	Base	20.000	50.000	0.000	10.000			iic_scl_ibuf/I
slave/n5_8	Base	20.000	50.000	0.000	10.000			slave/n5_s2/F

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	iic_scl	50.000(MHz)	136.200(MHz)	3	TOP

No timing paths to get frequency of slave/n5_8!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
iic_scl	Setup	0.000	0
iic_scl	Hold	0.000	0
slave/n5_8	Setup	0.000	0
slave/n5_8	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.329	slave/iic_sdar_s0/Q	slave/adr_match_s1/CE	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	3.761
2	14.255	slave/bitcnt_3_s2/Q	slave/mem_2_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	5.701
3	7.148	slave/iic_sdar_s0/Q	slave/mem_2_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	2.585
4	7.148	slave/iic_sdar_s0/Q	slave/mem_3_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	2.585
5	7.158	slave/iic_sdar_s0/Q	slave/mem_1_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	2.575
6	7.170	slave/iic_sdar_s0/Q	slave/mem_4_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	2.563
7	7.320	slave/iic_sdar_s0/Q	slave/mem_0_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	2.414
8	7.320	slave/iic_sdar_s0/Q	slave/mem_7_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	2.414
9	14.755	slave/bitcnt_3_s2/Q	slave/mem_7_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	5.202
10	15.253	slave/bitcnt_3_s2/Q	slave/mem_5_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	4.704
11	15.253	slave/bitcnt_3_s2/Q	slave/mem_6_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	4.704
12	15.260	slave/bitcnt_3_s2/Q	slave/mem_4_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	4.697
13	15.441	slave/bitcnt_3_s2/Q	slave/mem_1_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	4.516
14	15.441	slave/bitcnt_3_s2/Q	slave/mem_3_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	4.516
15	15.489	slave/bitcnt_3_s2/Q	slave/mem_0_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	4.467
16	7.825	slave/iic_sdar_s0/Q	slave/op_read_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	1.908
17	8.221	slave/iic_sdar_s0/Q	slave/mem_5_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	1.512
18	8.221	slave/iic_sdar_s0/Q	slave/mem_6_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	1.512
19	8.224	slave/iic_sdar_s0/Q	slave/got_ACK_s1/D	iic_scl:[R]	iic_scl:[F]	10.000	-0.133	1.509
20	16.540	slave/bitcnt_0_s1/Q	slave/op_read_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	3.417
21	17.165	slave/bitcnt_0_s1/Q	slave/bitcnt_3_s2/D	iic_scl:[F]	iic_scl:[F]	20.000	0.000	2.435
22	17.524	slave/bitcnt_0_s1/Q	slave/bitcnt_1_s1/D	iic_scl:[F]	iic_scl:[F]	20.000	0.000	2.076
23	17.601	slave/bitcnt_0_s1/Q	slave/bitcnt_2_s1/D	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.999
24	17.683	slave/bitcnt_3_s2/Q	slave/bitcnt_0_s1/D	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.917
25	18.332	slave/bitcnt_3_s2/Q	slave/got_ACK_s1/CE	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.624

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.712	slave/bitcnt_3_s2/Q	slave/bitcnt_3_s2/D	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.712
2	0.714	slave/bitcnt_2_s1/Q	slave/bitcnt_2_s1/D	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.714
3	0.828	slave/bitcnt_3_s2/Q	slave/data_phase_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.843
4	0.895	slave/bitcnt_1_s1/Q	slave/bitcnt_1_s1/D	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.895
5	1.064	slave/bitcnt_0_s1/Q	slave/bitcnt_0_s1/D	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.064
6	1.162	slave/bitcnt_3_s2/Q	slave/got_ACK_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.177
7	1.191	slave/bitcnt_2_s1/Q	slave/mem_0_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.206
8	1.366	slave/bitcnt_3_s2/Q	slave/op_read_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.381
9	1.525	slave/bitcnt_0_s1/Q	slave/mem_1_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.540
10	1.525	slave/bitcnt_0_s1/Q	slave/mem_3_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.540
11	1.700	slave/bitcnt_3_s2/Q	slave/adr_match_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.715
12	1.765	slave/bitcnt_0_s1/Q	slave/mem_5_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.780
13	1.765	slave/bitcnt_0_s1/Q	slave/mem_6_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.780
14	1.931	slave/bitcnt_2_s1/Q	slave/mem_4_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.946
15	2.118	slave/bitcnt_0_s1/Q	slave/mem_7_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	2.133
16	2.387	slave/bitcnt_0_s1/Q	slave/mem_2_s1/CE	iic_scl:[F]	iic_scl:[F]	0.000	0.000	2.402
17	10.830	slave/iic_sdar_s0/Q	slave/got_ACK_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	0.950
18	10.837	slave/iic_sdar_s0/Q	slave/mem_5_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	0.957
19	10.837	slave/iic_sdar_s0/Q	slave/mem_6_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	0.957
20	11.178	slave/iic_sdar_s0/Q	slave/op_read_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	1.297
21	11.375	slave/iic_sdar_s0/Q	slave/mem_0_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	1.494
22	11.375	slave/iic_sdar_s0/Q	slave/mem_7_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	1.494
23	11.389	slave/iic_sdar_s0/Q	slave/mem_1_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	1.509
24	11.395	slave/iic_sdar_s0/Q	slave/mem_2_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	1.515
25	11.395	slave/iic_sdar_s0/Q	slave/mem_3_s1/D	iic_scl:[R]	iic_scl:[F]	-10.000	-0.120	1.515

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	8.234	slave/start_or_stop_s1/I2	slave/incycle_s2/CLEAR	iic_scl:[R]	iic_scl:[F]	10.000	-1.079	2.802
2	18.158	slave/incycle_s2/Q	slave/bitcnt_3_s2/CLEAR	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.799
3	18.185	slave/incycle_s2/Q	slave/bitcnt_2_s1/PRESET	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.772
4	18.185	slave/incycle_s2/Q	slave/bitcnt_0_s1/PRESET	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.772
5	18.662	slave/incycle_s2/Q	slave/adr_match_s1/PRESET	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.295
6	18.662	slave/incycle_s2/Q	slave/got_ACK_s1/CLEAR	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.295
7	18.669	slave/incycle_s2/Q	slave/op_read_s1/CLEAR	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.287
8	18.669	slave/incycle_s2/Q	slave/data_phase_s1/CLEAR	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.287
9	18.669	slave/incycle_s2/Q	slave/bitcnt_1_s1/PRESET	iic_scl:[F]	iic_scl:[F]	20.000	0.000	1.287

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.826	slave/incycle_s2/Q	slave/adr_match_s1/PRESET	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.841
2	0.826	slave/incycle_s2/Q	slave/got_ACK_s1/CLEAR	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.841
3	0.904	slave/incycle_s2/Q	slave/op_read_s1/CLEAR	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.919
4	0.904	slave/incycle_s2/Q	slave/data_phase_s1/CLEAR	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.919
5	0.904	slave/incycle_s2/Q	slave/bitcnt_1_s1/PRESET	iic_scl:[F]	iic_scl:[F]	0.000	0.000	0.919
6	0.974	slave/iic_sda_shadow_s0/Q	slave/incycle_s2/CLEAR	slave/n5_8:[F]	iic_scl:[F]	0.000	-0.514	1.534
7	1.102	slave/incycle_s2/Q	slave/bitcnt_3_s2/CLEAR	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.117
8	1.167	slave/incycle_s2/Q	slave/bitcnt_2_s1/PRESET	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.182
9	1.167	slave/incycle_s2/Q	slave/bitcnt_0_s1/PRESET	iic_scl:[F]	iic_scl:[F]	0.000	0.000	1.182

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/iic_sdar_s0
2	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/bitcnt_3_s2
3	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/got_ACK_s1
4	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/mem_2_s1
5	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/mem_3_s1
6	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/data_phase_s1
7	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/mem_4_s1
8	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/mem_5_s1
9	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/incycle_s2
10	8.217	9.467	1.250	Low Pulse Width	iic_scl	slave/bitcnt_0_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.329
Data Arrival Time	5.689
Data Required Time	12.018
From	slave/iic_sdar_s0
To	slave/adr_match_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.210	0.824	tNET	FF	1	R9C13[1][B]	slave/n198_s1/I3
3.836	0.626	tINS	FF	1	R9C13[1][B]	slave/n198_s1/F
3.841	0.005	tNET	FF	1	R9C13[2][B]	slave/n198_s0/I2
4.902	1.061	tINS	FR	1	R9C13[2][B]	slave/n198_s0/F
5.689	0.786	tNET	RR	1	R9C14[0][A]	slave/adr_match_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C14[0][A]	slave/adr_match_s1/CLK
12.018	-0.043	tSu		1	R9C14[0][A]	slave/adr_match_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 1.687, 44.853%; route: 1.616, 42.962%; tC2Q: 0.458, 12.186%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path2

Path Summary:

Slack	14.255
Data Arrival Time	17.762
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/mem_2_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.359	0.840	tNET	FF	1	R9C14[0][B]	slave/n223_s2/I0
14.181	0.822	tINS	FF	8	R9C14[0][B]	slave/n223_s2/F
15.179	0.998	tNET	FF	1	R9C10[1][B]	slave/n219_s0/I2
16.240	1.061	tINS	FR	1	R9C10[1][B]	slave/n219_s0/F
17.762	1.522	tNET	RR	1	R9C10[1][A]	slave/mem_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C10[1][A]	slave/mem_2_s1/CLK
32.018	-0.043	tSu		1	R9C10[1][A]	slave/mem_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.883, 33.028%; route: 3.360, 58.933%; tC2Q: 0.458, 8.039%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path3

Path Summary:

Slack	7.148
Data Arrival Time	4.513
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/mem_2_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
4.513	2.127	tNET	FF	1	R9C10[1][A]	slave/mem_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C10[1][A]	slave/mem_2_s1/CLK
11.661	-0.400	tSu		1	R9C10[1][A]	slave/mem_2_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.127, 82.271%; tC2Q: 0.458, 17.729%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path4

Path Summary:

Slack	7.148
Data Arrival Time	4.513
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/mem_3_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
4.513	2.127	tNET	FF	1	R9C10[0][A]	slave/mem_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C10[0][A]	slave/mem_3_s1/CLK
11.661	-0.400	tSu		1	R9C10[0][A]	slave/mem_3_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.127, 82.271%; tC2Q: 0.458, 17.729%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path5

Path Summary:

Slack	7.158
Data Arrival Time	4.503
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/mem_1_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
4.503	2.117	tNET	FF	1	R9C10[2][A]	slave/mem_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C10[2][A]	slave/mem_1_s1/CLK
11.661	-0.400	tSu		1	R9C10[2][A]	slave/mem_1_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.117, 82.203%; tC2Q: 0.458, 17.797%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path6

Path Summary:

Slack	7.170
Data Arrival Time	4.490
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/mem_4_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
4.490	2.105	tNET	FF	1	R9C11[1][A]	slave/mem_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C11[1][A]	slave/mem_4_s1/CLK
11.661	-0.400	tSu		1	R9C11[1][A]	slave/mem_4_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.105, 82.118%; tC2Q: 0.458, 17.882%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path7

Path Summary:

Slack	7.320
Data Arrival Time	4.341
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/mem_0_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
4.341	1.956	tNET	FF	1	R9C12[0][B]	slave/mem_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[0][B]	slave/mem_0_s1/CLK
11.661	-0.400	tSu		1	R9C12[0][B]	slave/mem_0_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.956, 81.012%; tC2Q: 0.458, 18.988%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path8

Path Summary:

Slack	7.320
Data Arrival Time	4.341
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/mem_7_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
4.341	1.956	tNET	FF	1	R9C12[2][A]	slave/mem_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[2][A]	slave/mem_7_s1/CLK
11.661	-0.400	tSu		1	R9C12[2][A]	slave/mem_7_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.956, 81.012%; tC2Q: 0.458, 18.988%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path9

Path Summary:

Slack	14.755
Data Arrival Time	17.263
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/mem_7_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.359	0.840	tNET	FF	1	R9C14[0][B]	slave/n223_s2/I0
14.181	0.822	tINS	FF	8	R9C14[0][B]	slave/n223_s2/F
15.000	0.819	tNET	FF	1	R9C17[2][B]	slave/n209_s0/I2
16.061	1.061	tINS	FR	1	R9C17[2][B]	slave/n209_s0/F
17.263	1.202	tNET	RR	1	R9C12[2][A]	slave/mem_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C12[2][A]	slave/mem_7_s1/CLK
32.018	-0.043	tSu		1	R9C12[2][A]	slave/mem_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.883, 36.197%; route: 2.861, 54.993%; tC2Q: 0.458, 8.811%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path10

Path Summary:

Slack	15.253
Data Arrival Time	16.765
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/mem_5_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.359	0.840	tNET	FF	1	R9C14[0][B]	slave/n223_s2/I0
14.181	0.822	tINS	FF	8	R9C14[0][B]	slave/n223_s2/F
15.000	0.819	tNET	FF	1	R9C17[3][B]	slave/n213_s0/I2
16.061	1.061	tINS	FR	1	R9C17[3][B]	slave/n213_s0/F
16.765	0.704	tNET	RR	1	R9C15[1][A]	slave/mem_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C15[1][A]	slave/mem_5_s1/CLK
32.018	-0.043	tSu		1	R9C15[1][A]	slave/mem_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.883, 40.029%; route: 2.363, 50.228%; tC2Q: 0.458, 9.743%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path11

Path Summary:

Slack	15.253
Data Arrival Time	16.765
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/mem_6_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.359	0.840	tNET	FF	1	R9C14[0][B]	slave/n223_s2/I0
14.181	0.822	tINS	FF	8	R9C14[0][B]	slave/n223_s2/F
15.000	0.819	tNET	FF	1	R9C17[3][A]	slave/n211_s0/I2
16.061	1.061	tINS	FR	1	R9C17[3][A]	slave/n211_s0/F
16.765	0.704	tNET	RR	1	R9C15[0][A]	slave/mem_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C15[0][A]	slave/mem_6_s1/CLK
32.018	-0.043	tSu		1	R9C15[0][A]	slave/mem_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.883, 40.029%; route: 2.363, 50.228%; tC2Q: 0.458, 9.743%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path12

Path Summary:

Slack	15.260
Data Arrival Time	16.758
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/mem_4_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.359	0.840	tNET	FF	1	R9C14[0][B]	slave/n223_s2/I0
14.181	0.822	tINS	FF	8	R9C14[0][B]	slave/n223_s2/F
15.012	0.831	tNET	FF	1	R9C12[3][A]	slave/n215_s2/I1
15.637	0.625	tINS	FR	1	R9C12[3][A]	slave/n215_s2/F
16.758	1.121	tNET	RR	1	R9C11[1][A]	slave/mem_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C11[1][A]	slave/mem_4_s1/CLK
32.018	-0.043	tSu		1	R9C11[1][A]	slave/mem_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.447, 30.807%; route: 2.792, 59.435%; tC2Q: 0.458, 9.758%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path13

Path Summary:

Slack	15.441
Data Arrival Time	16.577
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/mem_1_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.359	0.840	tNET	FF	1	R9C14[0][B]	slave/n223_s2/I0
14.181	0.822	tINS	FF	8	R9C14[0][B]	slave/n223_s2/F
15.179	0.998	tNET	FF	1	R9C10[2][B]	slave/n221_s0/I2
16.240	1.061	tINS	FR	1	R9C10[2][B]	slave/n221_s0/F
16.577	0.336	tNET	RR	1	R9C10[2][A]	slave/mem_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C10[2][A]	slave/mem_1_s1/CLK
32.018	-0.043	tSu		1	R9C10[2][A]	slave/mem_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.883, 41.697%; route: 2.175, 48.153%; tC2Q: 0.458, 10.149%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path14

Path Summary:

Slack	15.441
Data Arrival Time	16.577
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/mem_3_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.359	0.840	tNET	FF	1	R9C14[0][B]	slave/n223_s2/I0
14.181	0.822	tINS	FF	8	R9C14[0][B]	slave/n223_s2/F
15.179	0.998	tNET	FF	1	R9C10[0][B]	slave/n217_s0/I2
16.240	1.061	tINS	FR	1	R9C10[0][B]	slave/n217_s0/F
16.577	0.336	tNET	RR	1	R9C10[0][A]	slave/mem_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C10[0][A]	slave/mem_3_s1/CLK
32.018	-0.043	tSu		1	R9C10[0][A]	slave/mem_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.883, 41.697%; route: 2.175, 48.153%; tC2Q: 0.458, 10.149%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path15

Path Summary:

Slack	15.489
Data Arrival Time	16.528
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/mem_0_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.359	0.840	tNET	FF	1	R9C14[0][B]	slave/n223_s2/I0
14.181	0.822	tINS	FF	8	R9C14[0][B]	slave/n223_s2/F
15.166	0.985	tNET	FF	1	R9C12[2][B]	slave/n223_s4/I1
16.192	1.026	tINS	FR	1	R9C12[2][B]	slave/n223_s4/F
16.528	0.336	tNET	RR	1	R9C12[0][B]	slave/mem_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C12[0][B]	slave/mem_0_s1/CLK
32.018	-0.043	tSu		1	R9C12[0][B]	slave/mem_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.848, 41.368%; route: 2.161, 48.372%; tC2Q: 0.458, 10.260%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path16

Path Summary:

Slack	7.825
Data Arrival Time	3.836
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/op_read_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.836	1.450	tNET	FF	1	R9C13[0][A]	slave/op_read_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C13[0][A]	slave/op_read_s1/CLK
11.661	-0.400	tSu		1	R9C13[0][A]	slave/op_read_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.450, 75.981%; tC2Q: 0.458, 24.019%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path17

Path Summary:

Slack	8.221
Data Arrival Time	3.439
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/mem_5_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.439	1.054	tNET	RR	1	R9C15[1][A]	slave/mem_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C15[1][A]	slave/mem_5_s1/CLK
11.661	-0.400	tSu		1	R9C15[1][A]	slave/mem_5_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.054, 69.688%; tC2Q: 0.458, 30.312%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path18

Path Summary:

Slack	8.221
Data Arrival Time	3.439
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/mem_6_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.439	1.054	tNET	RR	1	R9C15[0][A]	slave/mem_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C15[0][A]	slave/mem_6_s1/CLK
11.661	-0.400	tSu		1	R9C15[0][A]	slave/mem_6_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.054, 69.688%; tC2Q: 0.458, 30.312%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path19

Path Summary:

Slack	8.224
Data Arrival Time	3.436
Data Required Time	11.661
From	slave/iic_sdar_s0
To	slave/got_ACK_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.927	0.945	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
2.386	0.458	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
2.810	0.425	tNET	RR	1	R9C17[0][A]	slave/n96_s2/I0
3.436	0.626	tINS	RF	1	R9C17[0][A]	slave/n96_s2/F
3.436	0.000	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/CLK
11.661	-0.400	tSu		1	R9C17[0][A]	slave/got_ACK_s1

Path Statistics:

Clock Skew	0.133
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 50.944%; route: 0.945, 49.056%
Arrival Data Path Delay	cell: 0.626, 41.482%; route: 0.425, 28.147%; tC2Q: 0.458, 30.371%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path20

Path Summary:

Slack	16.540
Data Arrival Time	15.478
Data Required Time	32.018
From	slave/bitcnt_0_s1
To	slave/op_read_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
12.519	0.458	tC2Q	FF	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
13.033	0.514	tNET	FF	1	R9C12[1][B]	slave/n223_s1/I0
14.094	1.061	tINS	FR	3	R9C12[1][B]	slave/n223_s1/F
14.517	0.423	tNET	RR	1	R9C13[0][B]	slave/n93_s0/I3
15.142	0.625	tINS	RR	1	R9C13[0][B]	slave/n93_s0/F
15.478	0.336	tNET	RR	1	R9C13[0][A]	slave/op_read_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C13[0][A]	slave/op_read_s1/CLK
32.018	-0.043	tSu		1	R9C13[0][A]	slave/op_read_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.686, 49.340%; route: 1.273, 37.247%; tC2Q: 0.458, 13.413%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path21

Path Summary:

Slack	17.165
Data Arrival Time	14.495
Data Required Time	31.661
From	slave/bitcnt_0_s1
To	slave/bitcnt_3_s2
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
12.519	0.458	tC2Q	FF	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
13.673	1.154	tNET	FF	1	R9C12[1][A]	slave/n27_s2/I2
14.495	0.822	tINS	FF	1	R9C12[1][A]	slave/n27_s2/F
14.495	0.000	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
31.661	-0.400	tSu		1	R9C12[1][A]	slave/bitcnt_3_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.822, 33.763%; route: 1.154, 47.411%; tC2Q: 0.458, 18.826%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path22

Path Summary:

Slack	17.524
Data Arrival Time	14.136
Data Required Time	31.661
From	slave/bitcnt_0_s1
To	slave/bitcnt_1_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
12.519	0.458	tC2Q	FF	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
13.037	0.518	tNET	FF	1	R9C13[2][A]	slave/n29_s1/I1
14.136	1.099	tINS	FF	1	R9C13[2][A]	slave/n29_s1/F
14.136	0.000	tNET	FF	1	R9C13[2][A]	slave/bitcnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C13[2][A]	slave/bitcnt_1_s1/CLK
31.661	-0.400	tSu		1	R9C13[2][A]	slave/bitcnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.099, 52.949%; route: 0.518, 24.969%; tC2Q: 0.458, 22.082%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path23

Path Summary:

Slack	17.601
Data Arrival Time	14.060
Data Required Time	31.661
From	slave/bitcnt_0_s1
To	slave/bitcnt_2_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
12.519	0.458	tC2Q	FF	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
13.028	0.509	tNET	FF	1	R9C11[0][A]	slave/n28_s2/I2
14.060	1.032	tINS	FF	1	R9C11[0][A]	slave/n28_s2/F
14.060	0.000	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/CLK
31.661	-0.400	tSu		1	R9C11[0][A]	slave/bitcnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.032, 51.614%; route: 0.509, 25.464%; tC2Q: 0.458, 22.923%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path24

Path Summary:

Slack	17.683
Data Arrival Time	13.978
Data Required Time	31.661
From	slave/bitcnt_3_s2
To	slave/bitcnt_0_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FR	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
12.946	0.426	tNET	RR	1	R9C11[0][B]	slave/n30_s1/I0
13.978	1.032	tINS	RF	1	R9C11[0][B]	slave/n30_s1/F
13.978	0.000	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
31.661	-0.400	tSu		1	R9C11[0][B]	slave/bitcnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 1.032, 53.843%; route: 0.426, 22.243%; tC2Q: 0.458, 23.913%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path25

Path Summary:

Slack	18.332
Data Arrival Time	13.685
Data Required Time	32.018
From	slave/bitcnt_3_s2
To	slave/got_ACK_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
12.519	0.458	tC2Q	FR	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
13.685	1.166	tNET	RR	1	R9C17[0][A]	slave/got_ACK_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/CLK
32.018	-0.043	tSu		1	R9C17[0][A]	slave/got_ACK_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.166, 71.785%; tC2Q: 0.458, 28.215%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.712
Data Arrival Time	12.360
Data Required Time	11.647
From	slave/bitcnt_3_s2
To	slave/bitcnt_3_s2
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
11.981	0.333	tC2Q	FR	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
11.988	0.007	tNET	RR	1	R9C12[1][A]	slave/n27_s2/I1
12.360	0.372	tINS	RF	1	R9C12[1][A]	slave/n27_s2/F
12.360	0.000	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
11.647	0.000	tHld		1	R9C12[1][A]	slave/bitcnt_3_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path2

Path Summary:

Slack	0.714
Data Arrival Time	12.361
Data Required Time	11.647
From	slave/bitcnt_2_s1
To	slave/bitcnt_2_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/CLK
11.981	0.333	tC2Q	FR	9	R9C11[0][A]	slave/bitcnt_2_s1/Q
11.989	0.008	tNET	RR	1	R9C11[0][A]	slave/n28_s2/I1
12.361	0.372	tINS	RF	1	R9C11[0][A]	slave/n28_s2/F
12.361	0.000	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/CLK
11.647	0.000	tHld		1	R9C11[0][A]	slave/bitcnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path3

Path Summary:

Slack	0.828
Data Arrival Time	12.490
Data Required Time	11.662
From	slave/bitcnt_3_s2
To	slave/data_phase_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
11.981	0.333	tC2Q	FR	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
12.490	0.510	tNET	RR	1	R9C13[1][A]	slave/data_phase_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C13[1][A]	slave/data_phase_s1/CLK
11.662	0.015	tHld		1	R9C13[1][A]	slave/data_phase_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.510, 60.465%; tC2Q: 0.333, 39.535%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path4

Path Summary:

Slack	0.895
Data Arrival Time	12.542
Data Required Time	11.647
From	slave/bitcnt_1_s1
To	slave/bitcnt_1_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C13[2][A]	slave/bitcnt_1_s1/CLK
11.981	0.333	tC2Q	FR	13	R9C13[2][A]	slave/bitcnt_1_s1/Q
11.986	0.006	tNET	RR	1	R9C13[2][A]	slave/n29_s1/I2
12.542	0.556	tINS	RR	1	R9C13[2][A]	slave/n29_s1/F
12.542	0.000	tNET	RR	1	R9C13[2][A]	slave/bitcnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C13[2][A]	slave/bitcnt_1_s1/CLK
11.647	0.000	tHld		1	R9C13[2][A]	slave/bitcnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path5

Path Summary:

Slack	1.064
Data Arrival Time	12.712
Data Required Time	11.647
From	slave/bitcnt_0_s1
To	slave/bitcnt_0_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.981	0.333	tC2Q	FR	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
11.988	0.007	tNET	RR	1	R9C11[0][B]	slave/n30_s1/I1
12.712	0.724	tINS	RR	1	R9C11[0][B]	slave/n30_s1/F
12.712	0.000	tNET	RR	1	R9C11[0][B]	slave/bitcnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.647	0.000	tHld		1	R9C11[0][B]	slave/bitcnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.724, 68.018%; route: 0.007, 0.665%; tC2Q: 0.333, 31.316%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path6

Path Summary:

Slack	1.162
Data Arrival Time	12.824
Data Required Time	11.662
From	slave/bitcnt_3_s2
To	slave/got_ACK_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
11.981	0.333	tC2Q	FR	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
12.824	0.844	tNET	RR	1	R9C17[0][A]	slave/got_ACK_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/CLK
11.662	0.015	tHld		1	R9C17[0][A]	slave/got_ACK_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.844, 71.682%; tC2Q: 0.333, 28.318%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path7

Path Summary:

Slack	1.191
Data Arrival Time	12.853
Data Required Time	11.662
From	slave/bitcnt_2_s1
To	slave/mem_0_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/CLK
11.981	0.333	tC2Q	FF	9	R9C11[0][A]	slave/bitcnt_2_s1/Q
12.231	0.251	tNET	FF	1	R9C12[2][B]	slave/n223_s4/I2
12.616	0.385	tINS	FR	1	R9C12[2][B]	slave/n223_s4/F
12.853	0.237	tNET	RR	1	R9C12[0][B]	slave/mem_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[0][B]	slave/mem_0_s1/CLK
11.662	0.015	tHld		1	R9C12[0][B]	slave/mem_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.385, 31.930%; route: 0.487, 40.425%; tC2Q: 0.333, 27.645%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path8

Path Summary:

Slack	1.366
Data Arrival Time	13.028
Data Required Time	11.662
From	slave/bitcnt_3_s2
To	slave/op_read_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
11.981	0.333	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
12.235	0.254	tNET	FF	1	R9C13[0][B]	slave/n93_s0/I1
12.791	0.556	tINS	FR	1	R9C13[0][B]	slave/n93_s0/F
13.028	0.237	tNET	RR	1	R9C13[0][A]	slave/op_read_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C13[0][A]	slave/op_read_s1/CLK
11.662	0.015	tHld		1	R9C13[0][A]	slave/op_read_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.556, 40.274%; route: 0.491, 35.581%; tC2Q: 0.333, 24.145%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path9

Path Summary:

Slack	1.525
Data Arrival Time	13.188
Data Required Time	11.662
From	slave/bitcnt_0_s1
To	slave/mem_1_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.981	0.333	tC2Q	FR	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
12.566	0.585	tNET	RR	1	R9C10[2][B]	slave/n221_s0/I1
12.951	0.385	tINS	RR	1	R9C10[2][B]	slave/n221_s0/F
13.188	0.237	tNET	RR	1	R9C10[2][A]	slave/mem_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C10[2][A]	slave/mem_1_s1/CLK
11.662	0.015	tHld		1	R9C10[2][A]	slave/mem_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.385, 24.994%; route: 0.822, 53.367%; tC2Q: 0.333, 21.640%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path10

Path Summary:

Slack	1.525
Data Arrival Time	13.188
Data Required Time	11.662
From	slave/bitcnt_0_s1
To	slave/mem_3_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.981	0.333	tC2Q	FR	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
12.566	0.585	tNET	RR	1	R9C10[0][B]	slave/n217_s0/I0
12.951	0.385	tINS	RR	1	R9C10[0][B]	slave/n217_s0/F
13.188	0.237	tNET	RR	1	R9C10[0][A]	slave/mem_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C10[0][A]	slave/mem_3_s1/CLK
11.662	0.015	tHld		1	R9C10[0][A]	slave/mem_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.385, 24.994%; route: 0.822, 53.367%; tC2Q: 0.333, 21.640%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path11

Path Summary:

Slack	1.700
Data Arrival Time	13.362
Data Required Time	11.662
From	slave/bitcnt_3_s2
To	slave/adr_match_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
11.981	0.333	tC2Q	FF	10	R9C12[1][A]	slave/bitcnt_3_s2/Q
12.235	0.254	tNET	FF	1	R9C13[2][B]	slave/n198_s0/I0
12.791	0.556	tINS	FR	1	R9C13[2][B]	slave/n198_s0/F
13.362	0.571	tNET	RR	1	R9C14[0][A]	slave/adr_match_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C14[0][A]	slave/adr_match_s1/CLK
11.662	0.015	tHld		1	R9C14[0][A]	slave/adr_match_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.556, 32.428%; route: 0.825, 48.130%; tC2Q: 0.333, 19.441%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path12

Path Summary:

Slack	1.765
Data Arrival Time	13.427
Data Required Time	11.662
From	slave/bitcnt_0_s1
To	slave/mem_5_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.981	0.333	tC2Q	FR	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
12.542	0.561	tNET	RR	1	R9C17[3][B]	slave/n213_s0/I1
12.927	0.385	tINS	RR	1	R9C17[3][B]	slave/n213_s0/F
13.427	0.501	tNET	RR	1	R9C15[1][A]	slave/mem_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C15[1][A]	slave/mem_5_s1/CLK
11.662	0.015	tHld		1	R9C15[1][A]	slave/mem_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.385, 21.629%; route: 1.062, 59.645%; tC2Q: 0.333, 18.726%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path13

Path Summary:

Slack	1.765
Data Arrival Time	13.427
Data Required Time	11.662
From	slave/bitcnt_0_s1
To	slave/mem_6_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.981	0.333	tC2Q	FR	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
12.542	0.561	tNET	RR	1	R9C17[3][A]	slave/n211_s0/I0
12.927	0.385	tINS	RR	1	R9C17[3][A]	slave/n211_s0/F
13.427	0.501	tNET	RR	1	R9C15[0][A]	slave/mem_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C15[0][A]	slave/mem_6_s1/CLK
11.662	0.015	tHld		1	R9C15[0][A]	slave/mem_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.385, 21.629%; route: 1.062, 59.645%; tC2Q: 0.333, 18.726%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path14

Path Summary:

Slack	1.931
Data Arrival Time	13.593
Data Required Time	11.662
From	slave/bitcnt_2_s1
To	slave/mem_4_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/CLK
11.981	0.333	tC2Q	FF	9	R9C11[0][A]	slave/bitcnt_2_s1/Q
12.231	0.251	tNET	FF	1	R9C12[3][A]	slave/n215_s2/I3
12.787	0.556	tINS	FR	1	R9C12[3][A]	slave/n215_s2/F
13.593	0.806	tNET	RR	1	R9C11[1][A]	slave/mem_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[1][A]	slave/mem_4_s1/CLK
11.662	0.015	tHld		1	R9C11[1][A]	slave/mem_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.556, 28.572%; route: 1.057, 54.299%; tC2Q: 0.333, 17.129%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path15

Path Summary:

Slack	2.118
Data Arrival Time	13.780
Data Required Time	11.662
From	slave/bitcnt_0_s1
To	slave/mem_7_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.981	0.333	tC2Q	FR	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
12.542	0.561	tNET	RR	1	R9C17[2][B]	slave/n209_s0/I0
12.927	0.385	tINS	RR	1	R9C17[2][B]	slave/n209_s0/F
13.780	0.854	tNET	RR	1	R9C12[2][A]	slave/mem_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[2][A]	slave/mem_7_s1/CLK
11.662	0.015	tHld		1	R9C12[2][A]	slave/mem_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.385, 18.049%; route: 1.415, 66.324%; tC2Q: 0.333, 15.627%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path16

Path Summary:

Slack	2.387
Data Arrival Time	14.049
Data Required Time	11.662
From	slave/bitcnt_0_s1
To	slave/mem_2_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.981	0.333	tC2Q	FR	16	R9C11[0][B]	slave/bitcnt_0_s1/Q
12.566	0.585	tNET	RR	1	R9C10[1][B]	slave/n219_s0/I0
12.951	0.385	tINS	RR	1	R9C10[1][B]	slave/n219_s0/F
14.049	1.098	tNET	RR	1	R9C10[1][A]	slave/mem_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C10[1][A]	slave/mem_2_s1/CLK
11.662	0.015	tHld		1	R9C10[1][A]	slave/mem_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.385, 16.029%; route: 1.684, 70.093%; tC2Q: 0.333, 13.878%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path17

Path Summary:

Slack	10.830
Data Arrival Time	2.477
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/got_ACK_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
2.105	0.244	tNET	FF	1	R9C17[0][A]	slave/n96_s2/I0
2.477	0.372	tINS	FF	1	R9C17[0][A]	slave/n96_s2/F
2.477	0.000	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/CLK
-8.353	0.000	tHld		1	R9C17[0][A]	slave/got_ACK_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.372, 39.178%; route: 0.244, 25.716%; tC2Q: 0.333, 35.106%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path18

Path Summary:

Slack	10.837
Data Arrival Time	2.484
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/mem_5_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
2.484	0.623	tNET	FF	1	R9C15[1][A]	slave/mem_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C15[1][A]	slave/mem_5_s1/CLK
-8.353	0.000	tHld		1	R9C15[1][A]	slave/mem_5_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.623, 65.152%; tC2Q: 0.333, 34.848%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path19

Path Summary:

Slack	10.837
Data Arrival Time	2.484
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/mem_6_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RF	11	R9C16[2][A]	slave/iic_sdar_s0/Q
2.484	0.623	tNET	FF	1	R9C15[0][A]	slave/mem_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C15[0][A]	slave/mem_6_s1/CLK
-8.353	0.000	tHld		1	R9C15[0][A]	slave/mem_6_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.623, 65.152%; tC2Q: 0.333, 34.848%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path20

Path Summary:

Slack	11.178
Data Arrival Time	2.825
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/op_read_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
2.825	0.964	tNET	RR	1	R9C13[0][A]	slave/op_read_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C13[0][A]	slave/op_read_s1/CLK
-8.353	0.000	tHld		1	R9C13[0][A]	slave/op_read_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.964, 74.304%; tC2Q: 0.333, 25.696%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path21

Path Summary:

Slack	11.375
Data Arrival Time	3.022
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/mem_0_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.022	1.161	tNET	RR	1	R9C12[0][B]	slave/mem_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C12[0][B]	slave/mem_0_s1/CLK
-8.353	0.000	tHld		1	R9C12[0][B]	slave/mem_0_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.161, 77.695%; tC2Q: 0.333, 22.305%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path22

Path Summary:

Slack	11.375
Data Arrival Time	3.022
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/mem_7_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.022	1.161	tNET	RR	1	R9C12[2][A]	slave/mem_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C12[2][A]	slave/mem_7_s1/CLK
-8.353	0.000	tHld		1	R9C12[2][A]	slave/mem_7_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.161, 77.695%; tC2Q: 0.333, 22.305%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path23

Path Summary:

Slack	11.389
Data Arrival Time	3.036
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/mem_1_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.036	1.175	tNET	RR	1	R9C10[2][A]	slave/mem_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C10[2][A]	slave/mem_1_s1/CLK
-8.353	0.000	tHld		1	R9C10[2][A]	slave/mem_1_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.175, 77.908%; tC2Q: 0.333, 22.092%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path24

Path Summary:

Slack	11.395
Data Arrival Time	3.043
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/mem_2_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.043	1.182	tNET	RR	1	R9C10[1][A]	slave/mem_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C10[1][A]	slave/mem_2_s1/CLK
-8.353	0.000	tHld		1	R9C10[1][A]	slave/mem_2_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.182, 77.998%; tC2Q: 0.333, 22.002%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path25

Path Summary:

Slack	11.395
Data Arrival Time	3.043
Data Required Time	-8.353
From	slave/iic_sdar_s0
To	slave/mem_3_s1
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.844	0.844	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
1.528	0.683	tNET	RR	1	R9C16[2][A]	slave/iic_sdar_s0/CLK
1.861	0.333	tC2Q	RR	11	R9C16[2][A]	slave/iic_sdar_s0/Q
3.043	1.182	tNET	RR	1	R9C10[0][A]	slave/mem_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-10.000	-10.000					active clock edge time
-10.000	0.000					iic_scl
-10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
-9.153	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
-8.353	0.800	tNET	FF	1	R9C10[0][A]	slave/mem_3_s1/CLK
-8.353	0.000	tHld		1	R9C10[0][A]	slave/mem_3_s1

Path Statistics:

Clock Skew	0.120
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 55.278%; route: 0.683, 44.722%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.182, 77.998%; tC2Q: 0.333, 22.002%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	8.234
Data Arrival Time	3.784
Data Required Time	12.018
From	slave/start_or_stop_s1
To	slave/incycle_s2
Launch Clk	iic_scl:[R]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					iic_scl
0.000	0.000	tCL	RR	1	IOT17[B]	iic_scl_ibuf/I
0.982	0.982	tINS	RR	20	IOT17[B]	iic_scl_ibuf/O
2.348	1.366	tNET	RR	1	R9C16[0][B]	slave/start_or_stop_s1/I2
3.447	1.099	tINS	RF	1	R9C16[0][B]	slave/start_or_stop_s1/F
3.784	0.336	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.018	-0.043	tSu		1	R9C16[1][A]	slave/incycle_s2

Path Statistics:

Clock Skew	1.079
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.099, 39.226%; route: 0.336, 12.003%; tC2Q: 1.366, 48.771%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path2

Path Summary:

Slack	18.158
Data Arrival Time	13.860
Data Required Time	32.018
From	slave/incycle_s2
To	slave/bitcnt_3_s2
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.519	0.458	tC2Q	FF	12	R9C16[1][A]	slave/incycle_s2/Q
13.860	1.340	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
32.018	-0.043	tSu		1	R9C12[1][A]	slave/bitcnt_3_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.340, 74.520%; tC2Q: 0.458, 25.480%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path3

Path Summary:

Slack	18.185
Data Arrival Time	13.833
Data Required Time	32.018
From	slave/incycle_s2
To	slave/bitcnt_2_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.519	0.458	tC2Q	FF	12	R9C16[1][A]	slave/incycle_s2/Q
13.833	1.313	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/CLK
32.018	-0.043	tSu		1	R9C11[0][A]	slave/bitcnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.313, 74.132%; tC2Q: 0.458, 25.868%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path4

Path Summary:

Slack	18.185
Data Arrival Time	13.833
Data Required Time	32.018
From	slave/incycle_s2
To	slave/bitcnt_0_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.519	0.458	tC2Q	FF	12	R9C16[1][A]	slave/incycle_s2/Q
13.833	1.313	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
32.018	-0.043	tSu		1	R9C11[0][B]	slave/bitcnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.313, 74.132%; tC2Q: 0.458, 25.868%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path5

Path Summary:

Slack	18.662
Data Arrival Time	13.355
Data Required Time	32.018
From	slave/incycle_s2
To	slave/adr_match_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.519	0.458	tC2Q	FF	12	R9C16[1][A]	slave/incycle_s2/Q
13.355	0.836	tNET	FF	1	R9C14[0][A]	slave/adr_match_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C14[0][A]	slave/adr_match_s1/CLK
32.018	-0.043	tSu		1	R9C14[0][A]	slave/adr_match_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.836, 64.598%; tC2Q: 0.458, 35.402%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path6

Path Summary:

Slack	18.662
Data Arrival Time	13.355
Data Required Time	32.018
From	slave/incycle_s2
To	slave/got_ACK_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.519	0.458	tC2Q	FF	12	R9C16[1][A]	slave/incycle_s2/Q
13.355	0.836	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/CLK
32.018	-0.043	tSu		1	R9C17[0][A]	slave/got_ACK_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.836, 64.598%; tC2Q: 0.458, 35.402%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path7

Path Summary:

Slack	18.669
Data Arrival Time	13.348
Data Required Time	32.018
From	slave/incycle_s2
To	slave/op_read_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.519	0.458	tC2Q	FF	12	R9C16[1][A]	slave/incycle_s2/Q
13.348	0.829	tNET	FF	1	R9C13[0][A]	slave/op_read_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C13[0][A]	slave/op_read_s1/CLK
32.018	-0.043	tSu		1	R9C13[0][A]	slave/op_read_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.829, 64.395%; tC2Q: 0.458, 35.605%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path8

Path Summary:

Slack	18.669
Data Arrival Time	13.348
Data Required Time	32.018
From	slave/incycle_s2
To	slave/data_phase_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.519	0.458	tC2Q	FF	12	R9C16[1][A]	slave/incycle_s2/Q
13.348	0.829	tNET	FF	1	R9C13[1][A]	slave/data_phase_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C13[1][A]	slave/data_phase_s1/CLK
32.018	-0.043	tSu		1	R9C13[1][A]	slave/data_phase_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.829, 64.395%; tC2Q: 0.458, 35.605%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Path9

Path Summary:

Slack	18.669
Data Arrival Time	13.348
Data Required Time	32.018
From	slave/incycle_s2
To	slave/bitcnt_1_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
12.061	1.076	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
12.519	0.458	tC2Q	FF	12	R9C16[1][A]	slave/incycle_s2/Q
13.348	0.829	tNET	FF	1	R9C13[2][A]	slave/bitcnt_1_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					iic_scl
30.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
30.984	0.984	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
32.061	1.076	tNET	FF	1	R9C13[2][A]	slave/bitcnt_1_s1/CLK
32.018	-0.043	tSu		1	R9C13[2][A]	slave/bitcnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.829, 64.395%; tC2Q: 0.458, 35.605%
Required Clock Path Delay	cell: 0.984, 47.766%; route: 1.076, 52.234%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.826
Data Arrival Time	12.488
Data Required Time	11.662
From	slave/incycle_s2
To	slave/adr_match_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.981	0.333	tC2Q	FR	12	R9C16[1][A]	slave/incycle_s2/Q
12.488	0.507	tNET	RR	1	R9C14[0][A]	slave/adr_match_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C14[0][A]	slave/adr_match_s1/CLK
11.662	0.015	tHld		1	R9C14[0][A]	slave/adr_match_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.507, 60.354%; tC2Q: 0.333, 39.646%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path2

Path Summary:

Slack	0.826
Data Arrival Time	12.488
Data Required Time	11.662
From	slave/incycle_s2
To	slave/got_ACK_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.981	0.333	tC2Q	FR	12	R9C16[1][A]	slave/incycle_s2/Q
12.488	0.507	tNET	RR	1	R9C17[0][A]	slave/got_ACK_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C17[0][A]	slave/got_ACK_s1/CLK
11.662	0.015	tHld		1	R9C17[0][A]	slave/got_ACK_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.507, 60.354%; tC2Q: 0.333, 39.646%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path3

Path Summary:

Slack	0.904
Data Arrival Time	12.566
Data Required Time	11.662
From	slave/incycle_s2
To	slave/op_read_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.981	0.333	tC2Q	FR	12	R9C16[1][A]	slave/incycle_s2/Q
12.566	0.585	tNET	RR	1	R9C13[0][A]	slave/op_read_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C13[0][A]	slave/op_read_s1/CLK
11.662	0.015	tHld		1	R9C13[0][A]	slave/op_read_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.585, 63.709%; tC2Q: 0.333, 36.291%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path4

Path Summary:

Slack	0.904
Data Arrival Time	12.566
Data Required Time	11.662
From	slave/incycle_s2
To	slave/data_phase_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.981	0.333	tC2Q	FR	12	R9C16[1][A]	slave/incycle_s2/Q
12.566	0.585	tNET	RR	1	R9C13[1][A]	slave/data_phase_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C13[1][A]	slave/data_phase_s1/CLK
11.662	0.015	tHld		1	R9C13[1][A]	slave/data_phase_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.585, 63.709%; tC2Q: 0.333, 36.291%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path5

Path Summary:

Slack	0.904
Data Arrival Time	12.566
Data Required Time	11.662
From	slave/incycle_s2
To	slave/bitcnt_1_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.981	0.333	tC2Q	FR	12	R9C16[1][A]	slave/incycle_s2/Q
12.566	0.585	tNET	RR	1	R9C13[2][A]	slave/bitcnt_1_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C13[2][A]	slave/bitcnt_1_s1/CLK
11.662	0.015	tHld		1	R9C13[2][A]	slave/bitcnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.585, 63.709%; tC2Q: 0.333, 36.291%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path6

Path Summary:

Slack	0.974
Data Arrival Time	12.667
Data Required Time	11.692
From	slave/iic_sda_shadow_s0
To	slave/incycle_s2
Launch Clk	slave/n5_8:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					slave/n5_8
10.000	0.000	tCL	FF	1	R9C16[1][B]	slave/n5_s2/F
11.133	1.133	tNET	FF	1	R9C16[0][A]	slave/iic_sda_shadow_s0/G
11.466	0.333	tC2Q	FR	2	R9C16[0][A]	slave/iic_sda_shadow_s0/Q
11.704	0.238	tNET	RR	1	R9C16[0][B]	slave/start_or_stop_s1/I1
12.430	0.726	tINS	RR	1	R9C16[0][B]	slave/start_or_stop_s1/F
12.667	0.237	tNET	RR	1	R9C16[1][A]	slave/incycle_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.677	0.030	tUnc				slave/incycle_s2
11.692	0.015	tHld		1	R9C16[1][A]	slave/incycle_s2

Path Statistics:

Clock Skew	0.514
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.133, 100.000%
Arrival Data Path Delay	cell: 0.726, 47.336%; route: 0.474, 30.930%; tC2Q: 0.333, 21.734%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path7

Path Summary:

Slack	1.102
Data Arrival Time	12.764
Data Required Time	11.662
From	slave/incycle_s2
To	slave/bitcnt_3_s2
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.981	0.333	tC2Q	FR	12	R9C16[1][A]	slave/incycle_s2/Q
12.764	0.784	tNET	RR	1	R9C12[1][A]	slave/bitcnt_3_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C12[1][A]	slave/bitcnt_3_s2/CLK
11.662	0.015	tHld		1	R9C12[1][A]	slave/bitcnt_3_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.784, 70.157%; tC2Q: 0.333, 29.843%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path8

Path Summary:

Slack	1.167
Data Arrival Time	12.829
Data Required Time	11.662
From	slave/incycle_s2
To	slave/bitcnt_2_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.981	0.333	tC2Q	FR	12	R9C16[1][A]	slave/incycle_s2/Q
12.829	0.849	tNET	RR	1	R9C11[0][A]	slave/bitcnt_2_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][A]	slave/bitcnt_2_s1/CLK
11.662	0.015	tHld		1	R9C11[0][A]	slave/bitcnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.849, 71.806%; tC2Q: 0.333, 28.194%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Path9

Path Summary:

Slack	1.167
Data Arrival Time	12.829
Data Required Time	11.662
From	slave/incycle_s2
To	slave/bitcnt_0_s1
Launch Clk	iic_scl:[F]
Latch Clk	iic_scl:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C16[1][A]	slave/incycle_s2/CLK
11.981	0.333	tC2Q	FR	12	R9C16[1][A]	slave/incycle_s2/Q
12.829	0.849	tNET	RR	1	R9C11[0][B]	slave/bitcnt_0_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					iic_scl
10.000	0.000	tCL	FF	1	IOT17[B]	iic_scl_ibuf/I
10.847	0.847	tINS	FF	20	IOT17[B]	iic_scl_ibuf/O
11.647	0.800	tNET	FF	1	R9C11[0][B]	slave/bitcnt_0_s1/CLK
11.662	0.015	tHld		1	R9C11[0][B]	slave/bitcnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.849, 71.806%; tC2Q: 0.333, 28.194%
Required Clock Path Delay	cell: 0.847, 51.414%; route: 0.800, 48.586%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/iic_sdar_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/iic_sdar_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/iic_sdar_s0/CLK

MPW2

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/bitcnt_3_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/bitcnt_3_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/bitcnt_3_s2/CLK

MPW3

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/got_ACK_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/got_ACK_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/got_ACK_s1/CLK

MPW4

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/mem_2_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/mem_2_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/mem_2_s1/CLK

MPW5

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/mem_3_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/mem_3_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/mem_3_s1/CLK

MPW6

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/data_phase_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/data_phase_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/data_phase_s1/CLK

MPW7

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/mem_4_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/mem_4_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/mem_4_s1/CLK

MPW8

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/mem_5_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/mem_5_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/mem_5_s1/CLK

MPW9

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/incycle_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/incycle_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/incycle_s2/CLK

MPW10

MPW Summary:

Slack:	8.217
Actual Width:	9.467
Required Width:	1.250
Type:	Low Pulse Width
Clock:	iic_scl
Objects:	slave/bitcnt_0_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			iic_scl
10.000	0.000	tCL	FF	iic_scl_ibuf/I
10.984	0.984	tINS	FF	iic_scl_ibuf/O
12.061	1.076	tNET	FF	slave/bitcnt_0_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			iic_scl
20.000	0.000	tCL	RR	iic_scl_ibuf/I
20.844	0.844	tINS	RR	iic_scl_ibuf/O
21.528	0.683	tNET	RR	slave/bitcnt_0_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
20	iic_scl_d	6.329	1.402
16	bitcnt[0]	15.687	1.167
13	bitcnt[1]	15.835	0.999
12	incycle	14.909	1.340
11	iic_sdar	6.329	2.127
10	bitcnt[3]	14.255	1.313
9	bitcnt[2]	15.212	1.167
8	n223_5	14.255	0.998
4	data_phase	14.390	0.807
3	n223_4	15.687	0.423

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C12	30.56%
R9C13	29.17%
R9C11	26.39%
R9C16	22.22%
R9C10	19.44%
R9C15	18.06%
R9C14	16.67%
R9C17	8.33%
R10C18	6.94%
R10C17	5.56%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command