Report Title |
Power Analysis Report |
Design File |
D:\Users\19021\Documents\fpga_project\impl\gwsynthesis\fpga_project.vg |
Physical Constraints File |
D:\Users\19021\Documents\fpga_project\src\fpga_project.cst |
Timing Constraints File |
--- |
Version |
V1.9.8.01 |
Part Number |
GW1NSR-LV4CQN48PC6/I5 |
Device |
GW1NSR-4C |
Created Time |
Tue Feb 21 14:47:52 2023
|
Legal Announcement |
Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
Total Power (mW) |
8.668 |
Quiescent Power (mW) |
8.413 |
Dynamic Power (mW) |
0.255 |
Junction Temperature |
25.094 |
Theta JA |
10.500 |
Max Allowed Ambient Temperature |
84.906 |
Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
Use Vectorless Estimation |
false |
Filter Glitches |
false |
Related Vcd File |
|
Related Saif File |
|
Use Custom Theta JA |
false |
Air Flow |
LFM_0 |
Heat Sink |
None |
Use Custom Theta SA |
false |
Board Thermal Model |
None |
Use Custom Theta JB |
false |
Ambient Temperature |
25.000
|
Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
VCC |
1.200 |
0.048 |
1.928 |
2.370 |
VCCX |
2.500 |
0.047 |
2.424 |
6.178 |
VCCO12 |
1.200 |
0.035 |
0.003 |
0.045 |
VCCO33 |
3.300 |
0.012 |
0.011 |
0.075 |
Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
Logic |
0.000 |
NA |
6.250 |
IO |
0.343
| 0.089
| 28.125
|
Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
led |
0.000 |
0.000(0.000) |
Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
clk |
50.000 |
0.001 |