Timing Messages

Report Title Timing Analysis Report
Design File D:\Users\19021\Documents\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File D:\Users\19021\Documents\fpga_project\src\fpga_project.cst
Timing Constraint File ---
Version V1.9.8.01
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Tue Feb 21 14:47:52 2023
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C
Hold Delay Model Fast 1.26V 0C
Numbers of Paths Analyzed 2
Numbers of Endpoints Analyzed 2
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 670.004(MHz) 2 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 18.507 led_s2/Q led_s2/D clk:[R] clk:[R] 20.000 0.000 1.093

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.708 led_s2/Q led_s2/D clk:[R] clk:[R] 0.000 0.000 0.708

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 7.850 9.100 1.250 Low Pulse Width clk led_s2
2 8.475 9.725 1.250 High Pulse Width clk led_s2

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 18.507
Data Arrival Time 3.435
Data Required Time 21.943
From led_s2
To led_s2
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[B] clk_ibuf/I
0.982 0.982 tINS RR 1 IOT13[B] clk_ibuf/O
2.343 1.361 tNET RR 1 R11C20[0][A] led_s2/CLK
2.801 0.458 tC2Q RF 2 R11C20[0][A] led_s2/Q
2.809 0.008 tNET FF 1 R11C20[0][A] n5_s2/I0
3.435 0.626 tINS FF 1 R11C20[0][A] n5_s2/F
3.435 0.000 tNET FF 1 R11C20[0][A] led_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[B] clk_ibuf/I
20.982 0.982 tINS RR 1 IOT13[B] clk_ibuf/O
22.343 1.361 tNET RR 1 R11C20[0][A] led_s2/CLK
21.943 -0.400 tSu 1 R11C20[0][A] led_s2

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.911%; route: 1.361, 58.089%
Arrival Data Path Delay cell: 0.626, 57.298%; route: 0.008, 0.750%; tC2Q: 0.458, 41.952%
Required Clock Path Delay cell: 0.982, 41.911%; route: 1.361, 58.089%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.708
Data Arrival Time 2.518
Data Required Time 1.810
From led_s2
To led_s2
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[B] clk_ibuf/I
0.844 0.844 tINS RR 1 IOT13[B] clk_ibuf/O
1.810 0.966 tNET RR 1 R11C20[0][A] led_s2/CLK
2.144 0.333 tC2Q RR 2 R11C20[0][A] led_s2/Q
2.146 0.002 tNET RR 1 R11C20[0][A] n5_s2/I0
2.518 0.372 tINS RF 1 R11C20[0][A] n5_s2/F
2.518 0.000 tNET FF 1 R11C20[0][A] led_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[B] clk_ibuf/I
0.844 0.844 tINS RR 1 IOT13[B] clk_ibuf/O
1.810 0.966 tNET RR 1 R11C20[0][A] led_s2/CLK
1.810 0.000 tHld 1 R11C20[0][A] led_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.642%; route: 0.966, 53.358%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 46.642%; route: 0.966, 53.358%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 7.850
Actual Width: 9.100
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: led_s2

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.984 0.984 tINS FF clk_ibuf/O
12.710 1.726 tNET FF led_s2/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.844 0.844 tINS RR clk_ibuf/O
21.810 0.966 tNET RR led_s2/CLK

MPW2

MPW Summary:

Slack: 8.475
Actual Width: 9.725
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: led_s2

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.982 0.982 tINS RR clk_ibuf/O
2.343 1.361 tNET RR led_s2/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.847 0.847 tINS FF clk_ibuf/O
12.068 1.221 tNET FF led_s2/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
2 led_d 18.507 2.584
1 clk_d 18.507 1.726
1 n5_7 18.507 0.000

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R1C2 1.39%
R1C19 1.39%
R11C20 1.39%
R19C5 1.39%
R11C13 1.39%
R11C21 1.39%
R11C5 1.39%
R1C13 1.39%
R1C21 1.39%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command