Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\File\Micky\Github\T-FPGA\example\FPGA\spi-blink\src\gowin_osc\gowin_osc.v
D:\File\Micky\Github\T-FPGA\example\FPGA\spi-blink\src\gowin_pllvr\gowin_pllvr.v
D:\File\Micky\Github\T-FPGA\example\FPGA\spi-blink\src\spi-slave.v
D:\File\Micky\Github\T-FPGA\example\FPGA\spi-blink\src\spi-top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.01
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Thu Feb 23 17:21:23 2023
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module spi_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 144.668MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 144.668MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 144.668MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 144.668MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 144.668MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 144.668MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 144.668MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 144.668MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 144.668MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 144.668MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 144.668MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.111s, Peak memory usage = 144.668MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 144.668MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 144.668MB
Total Time and Memory Usage CPU time = 0h 0m 0.249s, Elapsed time = 0h 0m 0.235s, Peak memory usage = 144.668MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 16
I/O Buf 15
    IBUF 4
    OBUF 10
    TBUF 1
Register 37
    DFFE 8
    DFFP 4
    DFFC 11
    DFFCE 14
LUT 23
    LUT2 4
    LUT3 8
    LUT4 11
ALU 7
    ALU 7
INV 4
    INV 4
CLOCK 2
    OSCZ 1
    PLLVR 1

Resource Utilization Summary

Resource Usage Utilization
Logic 34(27 LUTs, 7 ALUs) / 4608 1%
Register 37 / 3570 1%
  --Register as Latch 0 / 3570 0%
  --Register as FF 37 / 3570 1%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
rxd_flag_d Base 20.000 50.0 0.000 10.000 spi_slaver1/rxd_flag_d_s/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity

No timing path found in the netlist.