Timing Messages

Report Title	Timing Analysis Report
Design File	D:\File\Micky\Github\T-FPGA\example\FPGA\spi-blink\impl\gwsynthesis\spi-blink.vg
Physical Constraints File	D:\File\Micky\Github\T-FPGA\example\FPGA\spi-blink\src\spi-blink.cst
Timing Constraint File	D:\File\Micky\Github\T-FPGA\example\FPGA\spi-blink\src\spi-blink.sdc
Version	V1.9.8.01
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Thu Feb 23 17:21:25 2023
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	197
Numbers of Endpoints Analyzed	99
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	8
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
osc/osc_inst/OSCOUT.default_clk	Base	40.000	25.000	0.000	20.000			osc/osc_inst/OSCOUT
rxd_flag_d	Base	20.000	50.000	0.000	10.000			spi_slaver1/rxd_flag_d_s/F
pll/pllvr_inst/CLKOUT.default_gen_clk	Generated	32.000	31.250	0.000	16.000	osc/osc_inst/OSCOUT	osc/osc_inst/OSCOUT.default_clk	pll/pllvr_inst/CLKOUT
pll/pllvr_inst/CLKOUTP.default_gen_clk	Generated	32.000	31.250	0.000	16.000	osc/osc_inst/OSCOUT	osc/osc_inst/OSCOUT.default_clk	pll/pllvr_inst/CLKOUTP
pll/pllvr_inst/CLKOUTD.default_gen_clk	Generated	64.000	15.625	0.000	32.000	osc/osc_inst/OSCOUT	osc/osc_inst/OSCOUT.default_clk	pll/pllvr_inst/CLKOUTD
pll/pllvr_inst/CLKOUTD3.default_gen_clk	Generated	96.000	10.417	0.000	48.000	osc/osc_inst/OSCOUT	osc/osc_inst/OSCOUT.default_clk	pll/pllvr_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	pll/pllvr_inst/CLKOUT.default_gen_clk	31.250(MHz)	183.165(MHz)	2	TOP

No timing paths to get frequency of osc/osc_inst/OSCOUT.default_clk!

No timing paths to get frequency of rxd_flag_d!

No timing paths to get frequency of pll/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of pll/pllvr_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pll/pllvr_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
osc/osc_inst/OSCOUT.default_clk	Setup	0.000	0
osc/osc_inst/OSCOUT.default_clk	Hold	0.000	0
rxd_flag_d	Setup	0.000	0
rxd_flag_d	Hold	0.000	0
pll/pllvr_inst/CLKOUT.default_gen_clk	Setup	0.000	0
pll/pllvr_inst/CLKOUT.default_gen_clk	Hold	0.000	0
pll/pllvr_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
pll/pllvr_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
pll/pllvr_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
pll/pllvr_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
pll/pllvr_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
pll/pllvr_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.475	spi_slaver1/rxd_out_7_s0/Q	led_state_s2/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	4.335
2	-1.341	txd_dat_0_s0/Q	spi_slaver1/n112_s0/D	rxd_flag_d:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	4.000	-0.710	5.621
3	-0.463	spi_slaver1/rxd_out_1_s0/Q	txd_dat_7_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	3.323
4	-0.406	spi_slaver1/rxd_out_1_s0/Q	txd_dat_6_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	3.266
5	-0.349	spi_slaver1/rxd_out_1_s0/Q	txd_dat_5_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	3.209
6	-0.292	spi_slaver1/rxd_out_1_s0/Q	txd_dat_4_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	3.152
7	-0.235	spi_slaver1/rxd_out_1_s0/Q	txd_dat_3_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	3.095
8	-0.178	spi_slaver1/rxd_out_1_s0/Q	txd_dat_2_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	3.038
9	0.555	spi_slaver1/rxd_out_0_s0/Q	txd_dat_1_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	2.305
10	1.158	spi_slaver1/rxd_out_0_s0/Q	txd_dat_0_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	rxd_flag_d:[R]	4.000	0.710	1.702
11	26.751	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_data_5_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	5.205
12	26.751	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_data_6_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	5.205
13	26.751	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_data_7_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	5.205
14	26.877	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_data_3_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	5.079
15	27.074	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_out_0_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.882
16	27.074	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_out_1_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.882
17	27.074	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_out_2_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.882
18	27.074	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_out_3_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.882
19	27.074	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_out_4_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.882
20	27.074	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_out_5_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.882
21	27.074	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_out_6_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.882
22	27.074	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_out_7_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.882
23	27.081	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_data_1_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.876
24	27.081	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_data_2_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.876
25	27.245	spi_slaver1/sck_r0_s0/Q	spi_slaver1/rxd_data_4_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	32.000	0.000	4.712

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.709	spi_slaver1/txd_state_1_s0/Q	spi_slaver1/txd_state_1_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
2	0.710	spi_slaver1/txd_state_0_s2/Q	spi_slaver1/txd_state_0_s2/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.710
3	0.710	spi_slaver1/rxd_state_0_s2/Q	spi_slaver1/rxd_state_0_s2/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.710
4	0.711	spi_slaver1/rxd_state_2_s0/Q	spi_slaver1/rxd_state_2_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.711
5	0.937	spi_slaver1/rxd_flag_r_s0/Q	spi_slaver1/rxd_flag_r0_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.937
6	0.937	spi_slaver1/rxd_data_3_s0/Q	spi_slaver1/rxd_out_3_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.937
7	0.937	spi_slaver1/rxd_data_4_s0/Q	spi_slaver1/rxd_out_4_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.937
8	0.937	spi_slaver1/rxd_data_7_s0/Q	spi_slaver1/rxd_out_7_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.937
9	0.961	spi_slaver1/rxd_flag_r0_s0/Q	spi_slaver1/rxd_flag_r1_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.961
10	0.978	spi_slaver1/txd_state_0_s2/Q	spi_slaver1/txd_state_2_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.978
11	1.062	spi_slaver1/rxd_state_1_s0/Q	spi_slaver1/rxd_state_1_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.062
12	1.212	spi_slaver1/rxd_state_2_s0/Q	spi_slaver1/rxd_data_5_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.227
13	1.212	spi_slaver1/rxd_state_2_s0/Q	spi_slaver1/rxd_data_6_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.227
14	1.212	spi_slaver1/rxd_state_2_s0/Q	spi_slaver1/rxd_data_7_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.227
15	1.247	spi_slaver1/rxd_data_1_s0/Q	spi_slaver1/rxd_out_1_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.247
16	1.289	spi_slaver1/rxd_data_2_s0/Q	spi_slaver1/rxd_out_2_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.289
17	1.289	spi_slaver1/rxd_data_6_s0/Q	spi_slaver1/rxd_out_6_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.289
18	1.299	spi_slaver1/rxd_state_2_s0/Q	spi_slaver1/rxd_flag_r_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.299
19	1.480	spi_slaver1/rxd_state_0_s2/Q	spi_slaver1/rxd_data_4_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.495
20	1.502	spi_slaver1/rxd_state_0_s2/Q	spi_slaver1/rxd_data_1_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.517
21	1.502	spi_slaver1/rxd_state_0_s2/Q	spi_slaver1/rxd_data_2_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.517
22	1.524	spi_slaver1/rxd_data_5_s0/Q	spi_slaver1/rxd_out_5_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.524
23	1.536	spi_slaver1/sck_r0_s0/Q	spi_slaver1/sck_r1_s0/D	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.536
24	1.556	spi_slaver1/rxd_state_2_s0/Q	spi_slaver1/rxd_out_0_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.571
25	1.556	spi_slaver1/rxd_state_2_s0/Q	spi_slaver1/rxd_out_1_s0/CE	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.571

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	txd_dat_6_s0
2	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	txd_dat_5_s0
3	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	txd_dat_4_s0
4	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	txd_dat_3_s0
5	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	txd_dat_2_s0
6	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	led_state_s2
7	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	txd_dat_7_s0
8	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	txd_dat_1_s0
9	8.356	9.606	1.250	Low Pulse Width	rxd_flag_d	txd_dat_0_s0
10	8.606	9.856	1.250	High Pulse Width	rxd_flag_d	txd_dat_6_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.475
Data Arrival Time	101.991
Data Required Time	100.516
From	spi_slaver1/rxd_out_7_s0
To	led_state_s2
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C21[1][B]	spi_slaver1/rxd_out_7_s0/CLK
98.114	0.458	tC2Q	RF	3	R11C21[1][B]	spi_slaver1/rxd_out_7_s0/Q
100.560	2.446	tNET	FF	1	R17C5[0][A]	n28_s19/I0
101.186	0.626	tINS	FF	1	R17C5[0][A]	n28_s19/F
101.991	0.804	tNET	FF	1	IOB5[A]	led_state_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	IOB5[A]	led_state_s2/CLK
100.916	-0.030	tUnc				led_state_s2
100.516	-0.400	tSu		1	IOB5[A]	led_state_s2

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 14.441%; route: 3.251, 74.986%; tC2Q: 0.458, 10.573%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path2

Path Summary:

Slack	-1.341
Data Arrival Time	66.567
Data Required Time	65.226
From	txd_dat_0_s0
To	spi_slaver1/n112_s0
Launch Clk	rxd_flag_d:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					rxd_flag_d
60.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
60.946	0.946	tNET	RR	1	R11C19[0][A]	txd_dat_0_s0/CLK
61.404	0.458	tC2Q	RF	1	R11C19[0][A]	txd_dat_0_s0/Q
62.862	1.458	tNET	FF	1	R11C14[2][B]	spi_slaver1/n101_s27/I1
63.488	0.626	tINS	FF	1	R11C14[2][B]	spi_slaver1/n101_s27/F
63.488	0.000	tNET	FF	1	R11C14[2][A]	spi_slaver1/n101_s23/I1
63.637	0.149	tINS	FF	1	R11C14[2][A]	spi_slaver1/n101_s23/O
63.637	0.000	tNET	FF	1	R11C14[2][B]	spi_slaver1/n101_s21/I1
63.800	0.163	tINS	FF	1	R11C14[2][B]	spi_slaver1/n101_s21/O
66.567	2.767	tNET	FF	1	IOT26[B]	spi_slaver1/n112_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
64.000	64.000					active clock edge time
64.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
65.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
65.656	0.244	tNET	RR	1	IOT26[B]	spi_slaver1/n112_s0/CLK
65.626	-0.030	tUnc				spi_slaver1/n112_s0
65.226	-0.400	tSu		1	IOT26[B]	spi_slaver1/n112_s0

Path Statistics:

Clock Skew	0.710
Setup Relationship	4.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%
Arrival Data Path Delay	cell: 0.938, 16.687%; route: 4.225, 75.159%; tC2Q: 0.458, 8.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path3

Path Summary:

Slack	-0.463
Data Arrival Time	100.979
Data Required Time	100.516
From	spi_slaver1/rxd_out_1_s0
To	txd_dat_7_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
98.114	0.458	tC2Q	RF	2	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/Q
99.086	0.972	tNET	FF	2	R11C13[0][B]	n14_s/I0
100.131	1.045	tINS	FF	1	R11C13[0][B]	n14_s/COUT
100.131	0.000	tNET	FF	2	R11C13[1][A]	n13_s/CIN
100.188	0.057	tINS	FF	1	R11C13[1][A]	n13_s/COUT
100.188	0.000	tNET	FF	2	R11C13[1][B]	n12_s/CIN
100.245	0.057	tINS	FF	1	R11C13[1][B]	n12_s/COUT
100.245	0.000	tNET	FF	2	R11C13[2][A]	n11_s/CIN
100.302	0.057	tINS	FF	1	R11C13[2][A]	n11_s/COUT
100.302	0.000	tNET	FF	2	R11C13[2][B]	n10_s/CIN
100.359	0.057	tINS	FF	1	R11C13[2][B]	n10_s/COUT
100.359	0.000	tNET	FF	2	R11C14[0][A]	n9_s/CIN
100.416	0.057	tINS	FF	1	R11C14[0][A]	n9_s/COUT
100.416	0.000	tNET	FF	2	R11C14[0][B]	n8_s/CIN
100.979	0.563	tINS	FF	1	R11C14[0][B]	n8_s/SUM
100.979	0.000	tNET	FF	1	R11C14[0][B]	txd_dat_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	R11C14[0][B]	txd_dat_7_s0/CLK
100.916	-0.030	tUnc				txd_dat_7_s0
100.516	-0.400	tSu		1	R11C14[0][B]	txd_dat_7_s0

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.893, 56.967%; route: 0.972, 29.240%; tC2Q: 0.458, 13.793%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path4

Path Summary:

Slack	-0.406
Data Arrival Time	100.922
Data Required Time	100.516
From	spi_slaver1/rxd_out_1_s0
To	txd_dat_6_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
98.114	0.458	tC2Q	RF	2	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/Q
99.086	0.972	tNET	FF	2	R11C13[0][B]	n14_s/I0
100.131	1.045	tINS	FF	1	R11C13[0][B]	n14_s/COUT
100.131	0.000	tNET	FF	2	R11C13[1][A]	n13_s/CIN
100.188	0.057	tINS	FF	1	R11C13[1][A]	n13_s/COUT
100.188	0.000	tNET	FF	2	R11C13[1][B]	n12_s/CIN
100.245	0.057	tINS	FF	1	R11C13[1][B]	n12_s/COUT
100.245	0.000	tNET	FF	2	R11C13[2][A]	n11_s/CIN
100.302	0.057	tINS	FF	1	R11C13[2][A]	n11_s/COUT
100.302	0.000	tNET	FF	2	R11C13[2][B]	n10_s/CIN
100.359	0.057	tINS	FF	1	R11C13[2][B]	n10_s/COUT
100.359	0.000	tNET	FF	2	R11C14[0][A]	n9_s/CIN
100.922	0.563	tINS	FF	1	R11C14[0][A]	n9_s/SUM
100.922	0.000	tNET	FF	1	R11C14[0][A]	txd_dat_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	R11C14[0][A]	txd_dat_6_s0/CLK
100.916	-0.030	tUnc				txd_dat_6_s0
100.516	-0.400	tSu		1	R11C14[0][A]	txd_dat_6_s0

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.836, 56.216%; route: 0.972, 29.750%; tC2Q: 0.458, 14.034%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path5

Path Summary:

Slack	-0.349
Data Arrival Time	100.865
Data Required Time	100.516
From	spi_slaver1/rxd_out_1_s0
To	txd_dat_5_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
98.114	0.458	tC2Q	RF	2	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/Q
99.086	0.972	tNET	FF	2	R11C13[0][B]	n14_s/I0
100.131	1.045	tINS	FF	1	R11C13[0][B]	n14_s/COUT
100.131	0.000	tNET	FF	2	R11C13[1][A]	n13_s/CIN
100.188	0.057	tINS	FF	1	R11C13[1][A]	n13_s/COUT
100.188	0.000	tNET	FF	2	R11C13[1][B]	n12_s/CIN
100.245	0.057	tINS	FF	1	R11C13[1][B]	n12_s/COUT
100.245	0.000	tNET	FF	2	R11C13[2][A]	n11_s/CIN
100.302	0.057	tINS	FF	1	R11C13[2][A]	n11_s/COUT
100.302	0.000	tNET	FF	2	R11C13[2][B]	n10_s/CIN
100.865	0.563	tINS	FF	1	R11C13[2][B]	n10_s/SUM
100.865	0.000	tNET	FF	1	R11C13[2][B]	txd_dat_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	R11C13[2][B]	txd_dat_5_s0/CLK
100.916	-0.030	tUnc				txd_dat_5_s0
100.516	-0.400	tSu		1	R11C13[2][B]	txd_dat_5_s0

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.779, 55.439%; route: 0.972, 30.278%; tC2Q: 0.458, 14.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path6

Path Summary:

Slack	-0.292
Data Arrival Time	100.808
Data Required Time	100.516
From	spi_slaver1/rxd_out_1_s0
To	txd_dat_4_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
98.114	0.458	tC2Q	RF	2	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/Q
99.086	0.972	tNET	FF	2	R11C13[0][B]	n14_s/I0
100.131	1.045	tINS	FF	1	R11C13[0][B]	n14_s/COUT
100.131	0.000	tNET	FF	2	R11C13[1][A]	n13_s/CIN
100.188	0.057	tINS	FF	1	R11C13[1][A]	n13_s/COUT
100.188	0.000	tNET	FF	2	R11C13[1][B]	n12_s/CIN
100.245	0.057	tINS	FF	1	R11C13[1][B]	n12_s/COUT
100.245	0.000	tNET	FF	2	R11C13[2][A]	n11_s/CIN
100.808	0.563	tINS	FF	1	R11C13[2][A]	n11_s/SUM
100.808	0.000	tNET	FF	1	R11C13[2][A]	txd_dat_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	R11C13[2][A]	txd_dat_4_s0/CLK
100.916	-0.030	tUnc				txd_dat_4_s0
100.516	-0.400	tSu		1	R11C13[2][A]	txd_dat_4_s0

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.722, 54.633%; route: 0.972, 30.826%; tC2Q: 0.458, 14.541%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path7

Path Summary:

Slack	-0.235
Data Arrival Time	100.751
Data Required Time	100.516
From	spi_slaver1/rxd_out_1_s0
To	txd_dat_3_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
98.114	0.458	tC2Q	RF	2	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/Q
99.086	0.972	tNET	FF	2	R11C13[0][B]	n14_s/I0
100.131	1.045	tINS	FF	1	R11C13[0][B]	n14_s/COUT
100.131	0.000	tNET	FF	2	R11C13[1][A]	n13_s/CIN
100.188	0.057	tINS	FF	1	R11C13[1][A]	n13_s/COUT
100.188	0.000	tNET	FF	2	R11C13[1][B]	n12_s/CIN
100.751	0.563	tINS	FF	1	R11C13[1][B]	n12_s/SUM
100.751	0.000	tNET	FF	1	R11C13[1][B]	txd_dat_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	R11C13[1][B]	txd_dat_3_s0/CLK
100.916	-0.030	tUnc				txd_dat_3_s0
100.516	-0.400	tSu		1	R11C13[1][B]	txd_dat_3_s0

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.665, 53.797%; route: 0.972, 31.394%; tC2Q: 0.458, 14.809%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path8

Path Summary:

Slack	-0.178
Data Arrival Time	100.694
Data Required Time	100.516
From	spi_slaver1/rxd_out_1_s0
To	txd_dat_2_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
98.114	0.458	tC2Q	RF	2	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/Q
99.086	0.972	tNET	FF	2	R11C13[0][B]	n14_s/I0
100.131	1.045	tINS	FF	1	R11C13[0][B]	n14_s/COUT
100.131	0.000	tNET	FF	2	R11C13[1][A]	n13_s/CIN
100.694	0.563	tINS	FF	1	R11C13[1][A]	n13_s/SUM
100.694	0.000	tNET	FF	1	R11C13[1][A]	txd_dat_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	R11C13[1][A]	txd_dat_2_s0/CLK
100.916	-0.030	tUnc				txd_dat_2_s0
100.516	-0.400	tSu		1	R11C13[1][A]	txd_dat_2_s0

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.608, 52.930%; route: 0.972, 31.983%; tC2Q: 0.458, 15.087%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path9

Path Summary:

Slack	0.555
Data Arrival Time	99.961
Data Required Time	100.516
From	spi_slaver1/rxd_out_0_s0
To	txd_dat_1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C20[1][A]	spi_slaver1/rxd_out_0_s0/CLK
98.114	0.458	tC2Q	RF	3	R11C20[1][A]	spi_slaver1/rxd_out_0_s0/Q
99.260	1.146	tNET	FF	2	R11C13[0][B]	n14_s/I1
99.961	0.701	tINS	FR	1	R11C13[0][B]	n14_s/SUM
99.961	0.000	tNET	RR	1	R11C13[0][B]	txd_dat_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	R11C13[0][B]	txd_dat_1_s0/CLK
100.916	-0.030	tUnc				txd_dat_1_s0
100.516	-0.400	tSu		1	R11C13[0][B]	txd_dat_1_s0

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.701, 30.408%; route: 1.146, 49.710%; tC2Q: 0.458, 19.882%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path10

Path Summary:

Slack	1.158
Data Arrival Time	99.358
Data Required Time	100.516
From	spi_slaver1/rxd_out_0_s0
To	txd_dat_0_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	rxd_flag_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
96.000	96.000					active clock edge time
96.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
97.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
97.656	0.244	tNET	RR	1	R11C20[1][A]	spi_slaver1/rxd_out_0_s0/CLK
98.114	0.458	tC2Q	RR	3	R11C20[1][A]	spi_slaver1/rxd_out_0_s0/Q
98.536	0.422	tNET	RR	1	R11C19[0][A]	n15_s2/I0
99.358	0.822	tINS	RF	1	R11C19[0][A]	n15_s2/F
99.358	0.000	tNET	FF	1	R11C19[0][A]	txd_dat_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					rxd_flag_d
100.000	0.000	tCL	RR	10	R11C19[0][B]	spi_slaver1/rxd_flag_d_s/F
100.946	0.946	tNET	RR	1	R11C19[0][A]	txd_dat_0_s0/CLK
100.916	-0.030	tUnc				txd_dat_0_s0
100.516	-0.400	tSu		1	R11C19[0][A]	txd_dat_0_s0

Path Statistics:

Clock Skew	-0.710
Setup Relationship	4.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.822, 48.297%; route: 0.422, 24.774%; tC2Q: 0.458, 26.929%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path11

Path Summary:

Slack	26.751
Data Arrival Time	6.861
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_data_5_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.723	1.488	tNET	FF	1	R11C22[1][B]	spi_slaver1/n50_s2/I3
6.525	0.802	tINS	FR	1	R11C22[1][B]	spi_slaver1/n50_s2/F
6.861	0.336	tNET	RR	1	R11C22[0][A]	spi_slaver1/rxd_data_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C22[0][A]	spi_slaver1/rxd_data_5_s0/CLK
33.612	-0.043	tSu		1	R11C22[0][A]	spi_slaver1/rxd_data_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.428, 27.434%; route: 3.319, 63.761%; tC2Q: 0.458, 8.805%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path12

Path Summary:

Slack	26.751
Data Arrival Time	6.861
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_data_6_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.723	1.488	tNET	FF	1	R11C22[2][B]	spi_slaver1/n49_s2/I3
6.525	0.802	tINS	FR	1	R11C22[2][B]	spi_slaver1/n49_s2/F
6.861	0.336	tNET	RR	1	R11C22[1][A]	spi_slaver1/rxd_data_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C22[1][A]	spi_slaver1/rxd_data_6_s0/CLK
33.612	-0.043	tSu		1	R11C22[1][A]	spi_slaver1/rxd_data_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.428, 27.434%; route: 3.319, 63.761%; tC2Q: 0.458, 8.805%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path13

Path Summary:

Slack	26.751
Data Arrival Time	6.861
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_data_7_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.723	1.488	tNET	FF	1	R11C22[3][A]	spi_slaver1/n48_s2/I3
6.525	0.802	tINS	FR	1	R11C22[3][A]	spi_slaver1/n48_s2/F
6.861	0.336	tNET	RR	1	R11C22[2][A]	spi_slaver1/rxd_data_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C22[2][A]	spi_slaver1/rxd_data_7_s0/CLK
33.612	-0.043	tSu		1	R11C22[2][A]	spi_slaver1/rxd_data_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.428, 27.434%; route: 3.319, 63.761%; tC2Q: 0.458, 8.805%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path14

Path Summary:

Slack	26.877
Data Arrival Time	6.735
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_data_3_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.229	0.995	tNET	FF	1	R11C21[2][B]	spi_slaver1/n52_s2/I3
6.031	0.802	tINS	FR	1	R11C21[2][B]	spi_slaver1/n52_s2/F
6.735	0.704	tNET	RR	1	R12C21[0][A]	spi_slaver1/rxd_data_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R12C21[0][A]	spi_slaver1/rxd_data_3_s0/CLK
33.612	-0.043	tSu		1	R12C21[0][A]	spi_slaver1/rxd_data_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.428, 28.115%; route: 3.193, 62.862%; tC2Q: 0.458, 9.024%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path15

Path Summary:

Slack	27.074
Data Arrival Time	6.538
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_out_0_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.539	1.304	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I2
6.164	0.625	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
6.538	0.374	tNET	RR	1	R11C20[1][A]	spi_slaver1/rxd_out_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C20[1][A]	spi_slaver1/rxd_out_0_s0/CLK
33.612	-0.043	tSu		1	R11C20[1][A]	spi_slaver1/rxd_out_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.251, 25.624%; route: 3.173, 64.988%; tC2Q: 0.458, 9.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path16

Path Summary:

Slack	27.074
Data Arrival Time	6.538
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_out_1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.539	1.304	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I2
6.164	0.625	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
6.538	0.374	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
33.612	-0.043	tSu		1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.251, 25.624%; route: 3.173, 64.988%; tC2Q: 0.458, 9.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path17

Path Summary:

Slack	27.074
Data Arrival Time	6.538
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_out_2_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.539	1.304	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I2
6.164	0.625	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
6.538	0.374	tNET	RR	1	R11C20[2][B]	spi_slaver1/rxd_out_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C20[2][B]	spi_slaver1/rxd_out_2_s0/CLK
33.612	-0.043	tSu		1	R11C20[2][B]	spi_slaver1/rxd_out_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.251, 25.624%; route: 3.173, 64.988%; tC2Q: 0.458, 9.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path18

Path Summary:

Slack	27.074
Data Arrival Time	6.538
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_out_3_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.539	1.304	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I2
6.164	0.625	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
6.538	0.374	tNET	RR	1	R11C21[0][A]	spi_slaver1/rxd_out_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C21[0][A]	spi_slaver1/rxd_out_3_s0/CLK
33.612	-0.043	tSu		1	R11C21[0][A]	spi_slaver1/rxd_out_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.251, 25.624%; route: 3.173, 64.988%; tC2Q: 0.458, 9.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path19

Path Summary:

Slack	27.074
Data Arrival Time	6.538
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_out_4_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.539	1.304	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I2
6.164	0.625	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
6.538	0.374	tNET	RR	1	R11C20[1][B]	spi_slaver1/rxd_out_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C20[1][B]	spi_slaver1/rxd_out_4_s0/CLK
33.612	-0.043	tSu		1	R11C20[1][B]	spi_slaver1/rxd_out_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.251, 25.624%; route: 3.173, 64.988%; tC2Q: 0.458, 9.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path20

Path Summary:

Slack	27.074
Data Arrival Time	6.538
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_out_5_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.539	1.304	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I2
6.164	0.625	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
6.538	0.374	tNET	RR	1	R11C21[0][B]	spi_slaver1/rxd_out_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C21[0][B]	spi_slaver1/rxd_out_5_s0/CLK
33.612	-0.043	tSu		1	R11C21[0][B]	spi_slaver1/rxd_out_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.251, 25.624%; route: 3.173, 64.988%; tC2Q: 0.458, 9.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path21

Path Summary:

Slack	27.074
Data Arrival Time	6.538
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_out_6_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.539	1.304	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I2
6.164	0.625	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
6.538	0.374	tNET	RR	1	R11C21[1][A]	spi_slaver1/rxd_out_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C21[1][A]	spi_slaver1/rxd_out_6_s0/CLK
33.612	-0.043	tSu		1	R11C21[1][A]	spi_slaver1/rxd_out_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.251, 25.624%; route: 3.173, 64.988%; tC2Q: 0.458, 9.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path22

Path Summary:

Slack	27.074
Data Arrival Time	6.538
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_out_7_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.539	1.304	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I2
6.164	0.625	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
6.538	0.374	tNET	RR	1	R11C21[1][B]	spi_slaver1/rxd_out_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C21[1][B]	spi_slaver1/rxd_out_7_s0/CLK
33.612	-0.043	tSu		1	R11C21[1][B]	spi_slaver1/rxd_out_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.251, 25.624%; route: 3.173, 64.988%; tC2Q: 0.458, 9.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path23

Path Summary:

Slack	27.081
Data Arrival Time	6.532
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_data_1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.394	1.159	tNET	FF	1	R11C23[1][B]	spi_slaver1/n54_s2/I3
6.196	0.802	tINS	FR	1	R11C23[1][B]	spi_slaver1/n54_s2/F
6.532	0.336	tNET	RR	1	R11C23[1][A]	spi_slaver1/rxd_data_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C23[1][A]	spi_slaver1/rxd_data_1_s0/CLK
33.612	-0.043	tSu		1	R11C23[1][A]	spi_slaver1/rxd_data_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.428, 29.285%; route: 2.990, 61.315%; tC2Q: 0.458, 9.399%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path24

Path Summary:

Slack	27.081
Data Arrival Time	6.532
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_data_2_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.394	1.159	tNET	FF	1	R11C23[2][B]	spi_slaver1/n53_s2/I3
6.196	0.802	tINS	FR	1	R11C23[2][B]	spi_slaver1/n53_s2/F
6.532	0.336	tNET	RR	1	R11C23[2][A]	spi_slaver1/rxd_data_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C23[2][A]	spi_slaver1/rxd_data_2_s0/CLK
33.612	-0.043	tSu		1	R11C23[2][A]	spi_slaver1/rxd_data_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.428, 29.285%; route: 2.990, 61.315%; tC2Q: 0.458, 9.399%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path25

Path Summary:

Slack	27.245
Data Arrival Time	6.367
Data Required Time	33.612
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/rxd_data_4_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.656	0.244	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
2.114	0.458	tC2Q	RF	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.608	1.494	tNET	FF	1	R11C17[2][A]	spi_slaver1/n19_s1/I2
4.234	0.626	tINS	FF	11	R11C17[2][A]	spi_slaver1/n19_s1/F
5.229	0.995	tNET	FF	1	R11C21[3][A]	spi_slaver1/n51_s3/I1
6.031	0.802	tINS	FR	1	R11C21[3][A]	spi_slaver1/n51_s3/F
6.367	0.336	tNET	RR	1	R11C21[2][A]	spi_slaver1/rxd_data_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
33.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
33.656	0.244	tNET	RR	1	R11C21[2][A]	spi_slaver1/rxd_data_4_s0/CLK
33.612	-0.043	tSu		1	R11C21[2][A]	spi_slaver1/rxd_data_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	32.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.428, 30.308%; route: 2.825, 59.964%; tC2Q: 0.458, 9.728%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.709
Data Arrival Time	2.305
Data Required Time	1.596
From	spi_slaver1/txd_state_1_s0
To	spi_slaver1/txd_state_1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C17[1][A]	spi_slaver1/txd_state_1_s0/CLK
1.930	0.333	tC2Q	RR	4	R11C17[1][A]	spi_slaver1/txd_state_1_s0/Q
1.933	0.004	tNET	RR	1	R11C17[1][A]	spi_slaver1/n103_s5/I1
2.305	0.372	tINS	RF	1	R11C17[1][A]	spi_slaver1/n103_s5/F
2.305	0.000	tNET	FF	1	R11C17[1][A]	spi_slaver1/txd_state_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C17[1][A]	spi_slaver1/txd_state_1_s0/CLK
1.596	0.000	tHld		1	R11C17[1][A]	spi_slaver1/txd_state_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path2

Path Summary:

Slack	0.710
Data Arrival Time	2.306
Data Required Time	1.596
From	spi_slaver1/txd_state_0_s2
To	spi_slaver1/txd_state_0_s2
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C15[0][A]	spi_slaver1/txd_state_0_s2/CLK
1.930	0.333	tC2Q	RR	7	R11C15[0][A]	spi_slaver1/txd_state_0_s2/Q
1.934	0.005	tNET	RR	1	R11C15[0][A]	spi_slaver1/n108_s3/I3
2.306	0.372	tINS	RF	1	R11C15[0][A]	spi_slaver1/n108_s3/F
2.306	0.000	tNET	FF	1	R11C15[0][A]	spi_slaver1/txd_state_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C15[0][A]	spi_slaver1/txd_state_0_s2/CLK
1.596	0.000	tHld		1	R11C15[0][A]	spi_slaver1/txd_state_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path3

Path Summary:

Slack	0.710
Data Arrival Time	2.306
Data Required Time	1.596
From	spi_slaver1/rxd_state_0_s2
To	spi_slaver1/rxd_state_0_s2
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/CLK
1.930	0.333	tC2Q	RR	12	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/Q
1.934	0.005	tNET	RR	1	R11C17[0][A]	spi_slaver1/n59_s3/I0
2.306	0.372	tINS	RF	1	R11C17[0][A]	spi_slaver1/n59_s3/F
2.306	0.000	tNET	FF	1	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/CLK
1.596	0.000	tHld		1	R11C17[0][A]	spi_slaver1/rxd_state_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path4

Path Summary:

Slack	0.711
Data Arrival Time	2.308
Data Required Time	1.596
From	spi_slaver1/rxd_state_2_s0
To	spi_slaver1/rxd_state_2_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/CLK
1.930	0.333	tC2Q	RR	11	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/Q
1.936	0.006	tNET	RR	1	R11C23[0][A]	spi_slaver1/n37_s13/I0
2.308	0.372	tINS	RF	1	R11C23[0][A]	spi_slaver1/n37_s13/F
2.308	0.000	tNET	FF	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/CLK
1.596	0.000	tHld		1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path5

Path Summary:

Slack	0.937
Data Arrival Time	2.533
Data Required Time	1.596
From	spi_slaver1/rxd_flag_r_s0
To	spi_slaver1/rxd_flag_r0_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C20[0][A]	spi_slaver1/rxd_flag_r_s0/CLK
1.930	0.333	tC2Q	RF	1	R11C20[0][A]	spi_slaver1/rxd_flag_r_s0/Q
2.533	0.603	tNET	FF	1	R11C19[1][B]	spi_slaver1/rxd_flag_r0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C19[1][B]	spi_slaver1/rxd_flag_r0_s0/CLK
1.596	0.000	tHld		1	R11C19[1][B]	spi_slaver1/rxd_flag_r0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path6

Path Summary:

Slack	0.937
Data Arrival Time	2.533
Data Required Time	1.596
From	spi_slaver1/rxd_data_3_s0
To	spi_slaver1/rxd_out_3_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R12C21[0][A]	spi_slaver1/rxd_data_3_s0/CLK
1.930	0.333	tC2Q	RF	1	R12C21[0][A]	spi_slaver1/rxd_data_3_s0/Q
2.533	0.603	tNET	FF	1	R11C21[0][A]	spi_slaver1/rxd_out_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C21[0][A]	spi_slaver1/rxd_out_3_s0/CLK
1.596	0.000	tHld		1	R11C21[0][A]	spi_slaver1/rxd_out_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path7

Path Summary:

Slack	0.937
Data Arrival Time	2.533
Data Required Time	1.596
From	spi_slaver1/rxd_data_4_s0
To	spi_slaver1/rxd_out_4_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C21[2][A]	spi_slaver1/rxd_data_4_s0/CLK
1.930	0.333	tC2Q	RF	1	R11C21[2][A]	spi_slaver1/rxd_data_4_s0/Q
2.533	0.603	tNET	FF	1	R11C20[1][B]	spi_slaver1/rxd_out_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C20[1][B]	spi_slaver1/rxd_out_4_s0/CLK
1.596	0.000	tHld		1	R11C20[1][B]	spi_slaver1/rxd_out_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path8

Path Summary:

Slack	0.937
Data Arrival Time	2.533
Data Required Time	1.596
From	spi_slaver1/rxd_data_7_s0
To	spi_slaver1/rxd_out_7_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C22[2][A]	spi_slaver1/rxd_data_7_s0/CLK
1.930	0.333	tC2Q	RF	1	R11C22[2][A]	spi_slaver1/rxd_data_7_s0/Q
2.533	0.603	tNET	FF	1	R11C21[1][B]	spi_slaver1/rxd_out_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C21[1][B]	spi_slaver1/rxd_out_7_s0/CLK
1.596	0.000	tHld		1	R11C21[1][B]	spi_slaver1/rxd_out_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path9

Path Summary:

Slack	0.961
Data Arrival Time	2.557
Data Required Time	1.596
From	spi_slaver1/rxd_flag_r0_s0
To	spi_slaver1/rxd_flag_r1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C19[1][B]	spi_slaver1/rxd_flag_r0_s0/CLK
1.930	0.333	tC2Q	RR	2	R11C19[1][B]	spi_slaver1/rxd_flag_r0_s0/Q
2.557	0.628	tNET	RR	1	R11C19[1][A]	spi_slaver1/rxd_flag_r1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C19[1][A]	spi_slaver1/rxd_flag_r1_s0/CLK
1.596	0.000	tHld		1	R11C19[1][A]	spi_slaver1/rxd_flag_r1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.628, 65.312%; tC2Q: 0.333, 34.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path10

Path Summary:

Slack	0.978
Data Arrival Time	2.574
Data Required Time	1.596
From	spi_slaver1/txd_state_0_s2
To	spi_slaver1/txd_state_2_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C15[0][A]	spi_slaver1/txd_state_0_s2/CLK
1.930	0.333	tC2Q	RR	7	R11C15[0][A]	spi_slaver1/txd_state_0_s2/Q
2.202	0.272	tNET	RR	1	R11C17[1][B]	spi_slaver1/n102_s11/I0
2.574	0.372	tINS	RF	1	R11C17[1][B]	spi_slaver1/n102_s11/F
2.574	0.000	tNET	FF	1	R11C17[1][B]	spi_slaver1/txd_state_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C17[1][B]	spi_slaver1/txd_state_2_s0/CLK
1.596	0.000	tHld		1	R11C17[1][B]	spi_slaver1/txd_state_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 38.054%; route: 0.272, 27.847%; tC2Q: 0.333, 34.099%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path11

Path Summary:

Slack	1.062
Data Arrival Time	2.658
Data Required Time	1.596
From	spi_slaver1/rxd_state_1_s0
To	spi_slaver1/rxd_state_1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][B]	spi_slaver1/rxd_state_1_s0/CLK
1.930	0.333	tC2Q	RR	11	R11C23[0][B]	spi_slaver1/rxd_state_1_s0/Q
1.934	0.005	tNET	RR	1	R11C23[0][B]	spi_slaver1/n38_s5/I1
2.658	0.724	tINS	RR	1	R11C23[0][B]	spi_slaver1/n38_s5/F
2.658	0.000	tNET	RR	1	R11C23[0][B]	spi_slaver1/rxd_state_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][B]	spi_slaver1/rxd_state_1_s0/CLK
1.596	0.000	tHld		1	R11C23[0][B]	spi_slaver1/rxd_state_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path12

Path Summary:

Slack	1.212
Data Arrival Time	2.824
Data Required Time	1.611
From	spi_slaver1/rxd_state_2_s0
To	spi_slaver1/rxd_data_5_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/CLK
1.930	0.333	tC2Q	RF	11	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/Q
2.202	0.272	tNET	FF	1	R11C22[1][B]	spi_slaver1/n50_s2/I0
2.587	0.385	tINS	FR	1	R11C22[1][B]	spi_slaver1/n50_s2/F
2.824	0.237	tNET	RR	1	R11C22[0][A]	spi_slaver1/rxd_data_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C22[0][A]	spi_slaver1/rxd_data_5_s0/CLK
1.611	0.015	tHld		1	R11C22[0][A]	spi_slaver1/rxd_data_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.385, 31.367%; route: 0.509, 41.475%; tC2Q: 0.333, 27.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path13

Path Summary:

Slack	1.212
Data Arrival Time	2.824
Data Required Time	1.611
From	spi_slaver1/rxd_state_2_s0
To	spi_slaver1/rxd_data_6_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/CLK
1.930	0.333	tC2Q	RF	11	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/Q
2.202	0.272	tNET	FF	1	R11C22[2][B]	spi_slaver1/n49_s2/I0
2.587	0.385	tINS	FR	1	R11C22[2][B]	spi_slaver1/n49_s2/F
2.824	0.237	tNET	RR	1	R11C22[1][A]	spi_slaver1/rxd_data_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C22[1][A]	spi_slaver1/rxd_data_6_s0/CLK
1.611	0.015	tHld		1	R11C22[1][A]	spi_slaver1/rxd_data_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.385, 31.367%; route: 0.509, 41.475%; tC2Q: 0.333, 27.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path14

Path Summary:

Slack	1.212
Data Arrival Time	2.824
Data Required Time	1.611
From	spi_slaver1/rxd_state_2_s0
To	spi_slaver1/rxd_data_7_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/CLK
1.930	0.333	tC2Q	RF	11	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/Q
2.202	0.272	tNET	FF	1	R11C22[3][A]	spi_slaver1/n48_s2/I0
2.587	0.385	tINS	FR	1	R11C22[3][A]	spi_slaver1/n48_s2/F
2.824	0.237	tNET	RR	1	R11C22[2][A]	spi_slaver1/rxd_data_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C22[2][A]	spi_slaver1/rxd_data_7_s0/CLK
1.611	0.015	tHld		1	R11C22[2][A]	spi_slaver1/rxd_data_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.385, 31.367%; route: 0.509, 41.475%; tC2Q: 0.333, 27.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path15

Path Summary:

Slack	1.247
Data Arrival Time	2.843
Data Required Time	1.596
From	spi_slaver1/rxd_data_1_s0
To	spi_slaver1/rxd_out_1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[1][A]	spi_slaver1/rxd_data_1_s0/CLK
1.930	0.333	tC2Q	RR	1	R11C23[1][A]	spi_slaver1/rxd_data_1_s0/Q
2.843	0.914	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
1.596	0.000	tHld		1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.914, 73.269%; tC2Q: 0.333, 26.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path16

Path Summary:

Slack	1.289
Data Arrival Time	2.885
Data Required Time	1.596
From	spi_slaver1/rxd_data_2_s0
To	spi_slaver1/rxd_out_2_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[2][A]	spi_slaver1/rxd_data_2_s0/CLK
1.930	0.333	tC2Q	RR	1	R11C23[2][A]	spi_slaver1/rxd_data_2_s0/Q
2.885	0.955	tNET	RR	1	R11C20[2][B]	spi_slaver1/rxd_out_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C20[2][B]	spi_slaver1/rxd_out_2_s0/CLK
1.596	0.000	tHld		1	R11C20[2][B]	spi_slaver1/rxd_out_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.955, 74.135%; tC2Q: 0.333, 25.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path17

Path Summary:

Slack	1.289
Data Arrival Time	2.885
Data Required Time	1.596
From	spi_slaver1/rxd_data_6_s0
To	spi_slaver1/rxd_out_6_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C22[1][A]	spi_slaver1/rxd_data_6_s0/CLK
1.930	0.333	tC2Q	RR	1	R11C22[1][A]	spi_slaver1/rxd_data_6_s0/Q
2.885	0.955	tNET	RR	1	R11C21[1][A]	spi_slaver1/rxd_out_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C21[1][A]	spi_slaver1/rxd_out_6_s0/CLK
1.596	0.000	tHld		1	R11C21[1][A]	spi_slaver1/rxd_out_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.955, 74.135%; tC2Q: 0.333, 25.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path18

Path Summary:

Slack	1.299
Data Arrival Time	2.896
Data Required Time	1.596
From	spi_slaver1/rxd_state_2_s0
To	spi_slaver1/rxd_flag_r_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/CLK
1.930	0.333	tC2Q	RR	11	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/Q
2.896	0.966	tNET	RR	1	R11C20[0][A]	spi_slaver1/rxd_flag_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C20[0][A]	spi_slaver1/rxd_flag_r_s0/CLK
1.596	0.000	tHld		1	R11C20[0][A]	spi_slaver1/rxd_flag_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.966, 74.345%; tC2Q: 0.333, 25.655%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path19

Path Summary:

Slack	1.480
Data Arrival Time	3.091
Data Required Time	1.611
From	spi_slaver1/rxd_state_0_s2
To	spi_slaver1/rxd_data_4_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/CLK
1.930	0.333	tC2Q	RR	12	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/Q
2.469	0.540	tNET	RR	1	R11C21[3][A]	spi_slaver1/n51_s3/I2
2.854	0.385	tINS	RR	1	R11C21[3][A]	spi_slaver1/n51_s3/F
3.091	0.237	tNET	RR	1	R11C21[2][A]	spi_slaver1/rxd_data_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C21[2][A]	spi_slaver1/rxd_data_4_s0/CLK
1.611	0.015	tHld		1	R11C21[2][A]	spi_slaver1/rxd_data_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.385, 25.755%; route: 0.777, 51.946%; tC2Q: 0.333, 22.299%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path20

Path Summary:

Slack	1.502
Data Arrival Time	3.113
Data Required Time	1.611
From	spi_slaver1/rxd_state_0_s2
To	spi_slaver1/rxd_data_1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/CLK
1.930	0.333	tC2Q	RR	12	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/Q
2.491	0.562	tNET	RR	1	R11C23[1][B]	spi_slaver1/n54_s2/I0
2.876	0.385	tINS	RR	1	R11C23[1][B]	spi_slaver1/n54_s2/F
3.113	0.237	tNET	RR	1	R11C23[1][A]	spi_slaver1/rxd_data_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[1][A]	spi_slaver1/rxd_data_1_s0/CLK
1.611	0.015	tHld		1	R11C23[1][A]	spi_slaver1/rxd_data_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.385, 25.383%; route: 0.798, 52.640%; tC2Q: 0.333, 21.977%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path21

Path Summary:

Slack	1.502
Data Arrival Time	3.113
Data Required Time	1.611
From	spi_slaver1/rxd_state_0_s2
To	spi_slaver1/rxd_data_2_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/CLK
1.930	0.333	tC2Q	RR	12	R11C17[0][A]	spi_slaver1/rxd_state_0_s2/Q
2.491	0.562	tNET	RR	1	R11C23[2][B]	spi_slaver1/n53_s2/I1
2.876	0.385	tINS	RR	1	R11C23[2][B]	spi_slaver1/n53_s2/F
3.113	0.237	tNET	RR	1	R11C23[2][A]	spi_slaver1/rxd_data_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[2][A]	spi_slaver1/rxd_data_2_s0/CLK
1.611	0.015	tHld		1	R11C23[2][A]	spi_slaver1/rxd_data_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.385, 25.383%; route: 0.798, 52.640%; tC2Q: 0.333, 21.977%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path22

Path Summary:

Slack	1.524
Data Arrival Time	3.120
Data Required Time	1.596
From	spi_slaver1/rxd_data_5_s0
To	spi_slaver1/rxd_out_5_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C22[0][A]	spi_slaver1/rxd_data_5_s0/CLK
1.930	0.333	tC2Q	RR	1	R11C22[0][A]	spi_slaver1/rxd_data_5_s0/Q
3.120	1.191	tNET	RR	1	R11C21[0][B]	spi_slaver1/rxd_out_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C21[0][B]	spi_slaver1/rxd_out_5_s0/CLK
1.596	0.000	tHld		1	R11C21[0][B]	spi_slaver1/rxd_out_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.191, 78.127%; tC2Q: 0.333, 21.873%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path23

Path Summary:

Slack	1.536
Data Arrival Time	3.133
Data Required Time	1.596
From	spi_slaver1/sck_r0_s0
To	spi_slaver1/sck_r1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	IOT17[B]	spi_slaver1/sck_r0_s0/CLK
1.930	0.333	tC2Q	RR	5	IOT17[B]	spi_slaver1/sck_r0_s0/Q
3.133	1.203	tNET	RR	1	R11C15[0][B]	spi_slaver1/sck_r1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C15[0][B]	spi_slaver1/sck_r1_s0/CLK
1.596	0.000	tHld		1	R11C15[0][B]	spi_slaver1/sck_r1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.203, 78.304%; tC2Q: 0.333, 21.696%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path24

Path Summary:

Slack	1.556
Data Arrival Time	3.167
Data Required Time	1.611
From	spi_slaver1/rxd_state_2_s0
To	spi_slaver1/rxd_out_0_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/CLK
1.930	0.333	tC2Q	RF	11	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/Q
2.174	0.244	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I1
2.898	0.724	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
3.167	0.269	tNET	RR	1	R11C20[1][A]	spi_slaver1/rxd_out_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C20[1][A]	spi_slaver1/rxd_out_0_s0/CLK
1.611	0.015	tHld		1	R11C20[1][A]	spi_slaver1/rxd_out_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 46.097%; route: 0.513, 32.679%; tC2Q: 0.333, 21.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path25

Path Summary:

Slack	1.556
Data Arrival Time	3.167
Data Required Time	1.611
From	spi_slaver1/rxd_state_2_s0
To	spi_slaver1/rxd_out_1_s0
Launch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	pll/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/CLK
1.930	0.333	tC2Q	RF	11	R11C23[0][A]	spi_slaver1/rxd_state_2_s0/Q
2.174	0.244	tNET	FF	1	R11C22[0][B]	spi_slaver1/n80_s2/I1
2.898	0.724	tINS	FR	8	R11C22[0][B]	spi_slaver1/n80_s2/F
3.167	0.269	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll/pllvr_inst/CLKOUT.default_gen_clk
1.412	1.412	tCL	RR	28	PLL_L	pll/pllvr_inst/CLKOUT
1.596	0.185	tNET	RR	1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0/CLK
1.611	0.015	tHld		1	R11C20[2][A]	spi_slaver1/rxd_out_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 46.097%; route: 0.513, 32.679%; tC2Q: 0.333, 21.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	txd_dat_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	txd_dat_6_s0/CLK

MPW2

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	txd_dat_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	txd_dat_5_s0/CLK

MPW3

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	txd_dat_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	txd_dat_4_s0/CLK

MPW4

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	txd_dat_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	txd_dat_3_s0/CLK

MPW5

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	txd_dat_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	txd_dat_2_s0/CLK

MPW6

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	led_state_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	led_state_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	led_state_s2/CLK

MPW7

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	txd_dat_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	txd_dat_7_s0/CLK

MPW8

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	txd_dat_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	txd_dat_1_s0/CLK

MPW9

MPW Summary:

Slack:	8.356
Actual Width:	9.606
Required Width:	1.250
Type:	Low Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
11.078	1.078	tNET	FF	txd_dat_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			rxd_flag_d
20.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
20.684	0.684	tNET	RR	txd_dat_0_s0/CLK

MPW10

MPW Summary:

Slack:	8.606
Actual Width:	9.856
Required Width:	1.250
Type:	High Pulse Width
Clock:	rxd_flag_d
Objects:	txd_dat_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rxd_flag_d
0.000	0.000	tCL	RR	spi_slaver1/rxd_flag_d_s/F
0.946	0.946	tNET	RR	txd_dat_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			rxd_flag_d
10.000	0.000	tCL	FF	spi_slaver1/rxd_flag_d_s/F
10.801	0.801	tNET	FF	txd_dat_6_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
28	clk_30M	-1.475	0.262
12	rxd_state_0_6	27.501	1.493
11	rxd_state[1]	28.622	0.860
11	rxd_state[2]	28.933	1.491
11	n19_6	26.751	1.490
10	rxd_flag_d	-1.341	1.392
8	n80_5	27.074	0.495
7	txd_state_0_6	26.540	0.836
5	sck_r0	26.751	2.259
4	txd_state[1]	26.623	1.152

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C21	26.39%
R11C22	25.00%
R11C17	20.83%
R11C20	20.83%
R11C23	19.44%
R11C13	15.28%
R11C19	11.11%
R1C28	11.11%
R11C14	11.11%
R11C15	9.72%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command