| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| U3|TAP1|INST_tdoenable |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_tapstate_3 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_tapstate_2 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_tapstate_1 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_tapstate_0 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|shiftir_r |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_shiftdr |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|sh_ireg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|sh_ireg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|sh_ireg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|reset_r |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|irso |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_irout_3 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_irout_2 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_irout_1 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|INST_irout_0 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|id_reg_unit |
36 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1|byp_reg |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|TAP1 |
37 |
32 |
0 |
32 |
7 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| U3|StartUpCounter_3 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|StartUpCounter_2 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|StartUpCounter_1 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|StartUpCounter_0 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_31 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_30 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_29 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_28 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_27 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_26 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_25 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_24 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_23 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_22 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_21 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_20 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_19 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_18 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_17 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_16 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterExtConfiguration |
72 |
65 |
0 |
65 |
1 |
65 |
65 |
65 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_31 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_30 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_29 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_28 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_27 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_26 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_25 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_24 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_23 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_22 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_21 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_20 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_19 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_18 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_17 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_16 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|RegisterConfiguration |
72 |
65 |
0 |
65 |
1 |
65 |
65 |
65 |
0 |
0 |
0 |
0 |
0 |
| U3|i165|lpm_add_sub_inst|auto_generated |
7 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|i165 |
7 |
3 |
0 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|control_register |
24 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| U3 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U2|P_4 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|P_3 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|P_2 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|P_1 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|P_0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|n3n |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|n3m |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|n3g |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|LPM_COMPARE_8_8_3|auto_generated |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2|LPM_COMPARE_8_8_2|auto_generated |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2|LPM_COMPARE_8_8_1|auto_generated |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2|i254|lpm_add_sub_inst|auto_generated |
9 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2|i254 |
9 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| U2|i253|lpm_add_sub_inst|auto_generated |
15 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2|i253 |
15 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| U2|CNT_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|CNT_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|CNT_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|CNT_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|CNT_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|CNT_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|CNT_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2|CNT_0 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U2 |
25 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_tdoenable |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_tapstate_3 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_tapstate_2 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_tapstate_1 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_tapstate_0 |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|shiftir_r |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_shiftdr |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|sh_ireg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|sh_ireg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|sh_ireg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|reset_r |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|irso |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_irout_3 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_irout_2 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_irout_1 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|INST_irout_0 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|id_reg_unit |
36 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1|byp_reg |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|TAP1 |
37 |
32 |
0 |
32 |
7 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| U1|StartUpCounter_3 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|StartUpCounter_2 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|StartUpCounter_1 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|StartUpCounter_0 |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_23 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_22 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_21 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_20 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_19 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_18 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_17 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_16 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Value |
56 |
24 |
0 |
24 |
25 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterOutput_Length |
40 |
33 |
0 |
33 |
1 |
33 |
33 |
33 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_23 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_22 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_21 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_20 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_19 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_18 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_17 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_16 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Value |
56 |
25 |
0 |
25 |
1 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterInput_Length |
40 |
33 |
0 |
33 |
1 |
33 |
33 |
33 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_9 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_8 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_31 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_30 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_29 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_28 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_27 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_26 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_25 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_24 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_23 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_22 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_21 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_20 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_19 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_18 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_17 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_16 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_15 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_14 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_13 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_12 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_11 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_10 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_9 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_31 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_30 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_29 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_28 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_27 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_26 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_25 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_24 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_23 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_22 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_21 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_20 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_19 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_18 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_17 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_16 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_15 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_14 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_13 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_12 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_11 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_10 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|RegisterConfiguration |
72 |
65 |
0 |
65 |
1 |
65 |
65 |
65 |
0 |
0 |
0 |
0 |
0 |
| U1|i264|lpm_add_sub_inst|auto_generated |
7 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|i264 |
7 |
3 |
0 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| U1|DefaultEnable |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_so |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|sh_reg_7 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|sh_reg_6 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|sh_reg_5 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|sh_reg_4 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|sh_reg_3 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|sh_reg_2 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|sh_reg_1 |
5 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_regout_7 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_regout_6 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_regout_5 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_regout_4 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_regout_3 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_regout_2 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_regout_1 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register|INST_regout_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1|control_register |
24 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| U1 |
28 |
1 |
0 |
1 |
25 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |